Analog-to-Digital Converter

Abstract

The present invention provides an analog-to-digital converter, comprising: a digital-to-analog conversion module, a sampling and comparison module, and a logic control module. The digital-to-analog conversion module includes two-stage voltage division units, which are used to perform digital-to-analog conversion processing on the reference analog signal and output a target analog signal to the subsequent stage; the sampling and comparison module can process the received initial analog signal and the target analog signal into an intermediate digital signal; the logic control module performs logic processing on the intermediate digital signal to obtain a first digital signal and a second digital signal. By providing a digital-to-analog conversion module, the present application can achieve accurate digital-to-analog conversion while realizing high-precision analog-to-digital conversion, saving the layout area of the integrated circuit and improving the adaptability of the analog-to-digital converter in the aspect of the increasing integration degree of the integrated circuit.

Description

Technical Field

[0001] This application relates to the technical field of digital-to-analog conversion / analog-to-digital conversion, and particularly to an analog-to-digital converter. Background Art

[0002] Traditional high-precision successive approximation (SAR) analog-to-digital converters (ADCs) generally include: a digital-to-analog converter (DAC), a comparator, and a logic control module. The DAC in the ADC is mostly in the form of capacitors to implement the function of converting digital signals into analog signals. This structure requires a large layout area. In addition, the analog voltage on the DAC in this type of analog-to-digital converter is very sensitive and does not have driving ability itself. Even if it is changed to a current-steering DAC, the output swing of the DAC is easily limited. In addition, in traditional comparators, the common-mode input range of dynamic comparators is limited, and the comparison speed of analog comparators is slow. Summary of the Invention

[0003] This application provides an analog-to-digital converter, which can solve at least one of the problems in traditional analog-to-digital converters, such as large layout area occupation, sensitive analog voltage of the DAC module, lack of driving ability, and easy limitation of the output swing of the DAC.

[0004] On the one hand, an embodiment of this application provides an analog-to-digital converter, including:

[0005] A digital-to-analog conversion module, configured to receive an external first target control signal, a second target control signal, and a reference analog signal; perform digital-to-analog conversion processing on the reference analog signal through the first target control signal and the second target control signal and output a target analog signal to the subsequent stage; wherein, the digital-to-analog conversion module includes two-stage voltage-dividing units;

[0006] A sampling and comparison module, configured to receive an external initial analog signal and the target analog signal output by the digital-to-analog conversion module, and output an intermediate digital signal to the subsequent stage; and,

[0007] A logic control module, configured to receive the intermediate digital signal output by the sampling and comparison module, as well as an external clock signal, an enable signal, and an initial control signal, perform logic processing on the intermediate digital signal and output a first digital signal and a second digital signal to the subsequent stage, and perform logic processing on the initial control signal and output the first target control signal and the second target control signal to the digital-to-analog conversion module.

[0008] Optionally, in the analog-to-digital converter, the digital-to-analog conversion module includes: a first voltage-dividing unit and a second voltage-dividing unit connected to the first voltage-dividing unit;

[0009] The first voltage dividing unit includes: a first switching subunit, a first impedance subunit, and a second switching subunit that are connected in sequence;

[0010] The second voltage dividing unit includes: a second impedance subunit and a third switching subunit connected to the second impedance subunit;

[0011] Wherein, one end of the first impedance subunit is connected to the external reference analog signal, and the other end of the first impedance subunit is grounded; the first switching subunit and the second switching subunit are controlled by the first target control signal to perform voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage;

[0012] One end of the second impedance subunit is connected to the first intermediate voltage, and the other end of the second impedance subunit is connected to the second intermediate voltage; the third switching subunit is controlled by the second target control signal to perform voltage division processing on the difference between the first intermediate voltage and the second intermediate voltage to obtain the target analog signal.

[0013] Optionally, in the analog-to-digital converter, the first impedance subunit includes: 2 M resistors connected in series;

[0014] The second impedance subunit includes: 2 N resistors connected in series; wherein, both M and N are integers greater than or equal to 1, and M + N is an integer greater than or equal to 10.

[0015] Optionally, in the analog-to-digital converter, the first switching subunit includes: 2 M first control switches, and each of the first control switches is respectively connected to a series node between two adjacent resistors of the first impedance subunit in sequence;

[0016] The second switching subunit includes: 2 M second control switches, and each of the second control switches is respectively connected to a series node between two adjacent resistors of the first impedance subunit in sequence;

[0017] Wherein, the first control switch and the second control switch are staggered by one series node.

[0018] Optionally, in the analog-to-digital converter, the third switching subunit includes: 2 N third control switches, and each of the third control switches is respectively connected to a series node between two adjacent resistors of the second impedance subunit in sequence.

[0019] Optionally, in the analog-to-digital converter, the sampling and comparison module includes: a first selection switch, a second selection switch, a third selection switch, a capacitor, and a comparison unit, wherein the first selection switch is connected to the inverting input terminal of the comparison unit, the positive electrode of the capacitor is connected to the connection node between the first selection switch and the inverting input terminal of the comparison unit, the negative electrode of the capacitor is grounded, and both the second selection switch and the third selection switch are connected to the non-inverting input terminal of the comparison unit;

[0020] Wherein, through the third selection switch, the output terminal of the digital-to-analog conversion module is connected to the non-inverting input terminal of the comparison unit.

[0021] Optionally, in the analog-to-digital converter, when the analog-to-digital converter operates, the first selection switch and the second selection switch are closed simultaneously, so that the non-inverting input terminal and the inverting input terminal of the comparison unit receive the target analog signal.

[0022] Optionally, in the analog-to-digital converter, the switching operating state of the third selection switch is opposite to the switching operating states of the first selection switch and the second selection switch.

[0023] Optionally, in the analog-to-digital converter, the comparison unit includes: a current adder, a pre-amplifier, and a dynamic latch connected in sequence.

[0024] Optionally, in the analog-to-digital converter, the analog-to-digital converter further includes: a buffer module for buffering and adjusting the target analog signal.

[0025] The technical solution of the present application has at least the following advantages:

[0026] (1) By providing a digital-to-analog conversion module in the present application, accurate digital-to-analog conversion can be achieved while achieving high-precision analog-to-digital conversion, saving the layout area of the integrated circuit and improving the adaptability of the analog-to-digital converter in the aspect of the increasing integration degree of the integrated circuit.

[0027] (2) Further, the digital-to-analog conversion module includes two-stage voltage division units, and a target analog signal with higher precision can be obtained through the cooperation of 2 M resistors in the first stage and 2 N resistors in the second stage.

[0028] (3) In addition, the digital-to-analog conversion module provided in the present application can output a stable target analog signal (analog voltage signal) to the subsequent stage through two-stage voltage division processing. The digital-to-analog conversion module has driving ability and a large output swing. Description of the Drawings

[0029] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings required for the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0030] Figure 1 is a schematic circuit diagram of the analog-to-digital converter according to an embodiment of the present invention;

[0031] Figure 2 is a schematic circuit diagram of the digital-to-analog conversion module according to an embodiment of the present invention;

[0032] Figure 3 is a schematic circuit diagram of the comparison unit according to an embodiment of the present invention;

[0033] Among them, the reference numerals are explained as follows:

[0034] 10 - digital-to-analog conversion module, 11 - first voltage dividing unit, 111 - first switch sub-unit, 112 - first impedance sub-unit, 113 - second switch sub-unit, 12 - second voltage dividing unit, 121 - second impedance sub-unit, 122 - third switch sub-unit, 20 - sampling and comparison module, 21 - comparison unit, 211 - current adder, 212 - pre-amplifier, 213 - dynamic latch, 30 - logic control module, 40 - buffer module. Specific Embodiments

[0035] The following will clearly and completely describe the technical solutions in the present application in conjunction with the accompanying drawings. Obviously, the described embodiments are some embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0036] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0037] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may also be the communication inside two components. It may be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0038] An embodiment of the present application provides an analog-to-digital converter. Please refer to Figure 1 , Figure 1 which is a schematic circuit diagram of the analog-to-digital converter according to an embodiment of the present invention. The analog-to-digital converter includes: a digital-to-analog conversion module 10, a sampling and comparison module 20, and a logic control module 30.

[0039] Among them, the digital-to-analog conversion module 10 is configured to receive an external first target control signal CTL1 <m:0>, Second target control signal CTL2 <n:0>and a reference analog signal VREF; through the first target control signal CTL1 <m:0>and the second target control signal CTL2 <n:0>, perform digital-to-analog conversion processing on the reference analog signal VREF and output a target analog signal DAC_OUT to the subsequent stage; wherein, the digital-to-analog conversion module 10 includes two-stage voltage division units. Specifically, please refer to Figure 2 , Figure 2 is a schematic circuit diagram of the digital-to-analog conversion module according to an embodiment of the present invention. The digital-to-analog conversion module 10 includes: a first voltage division unit 11 and a second voltage division unit 12 connected to the first voltage division unit 11.

[0040] Wherein, the first voltage division unit 11 includes: a first switch sub-unit 111, a first impedance sub-unit 112, and a second switch sub-unit 113 connected in sequence; the second voltage division unit 12 includes: a second impedance sub-unit 121 and a third switch sub-unit 122 connected to the second impedance sub-unit 121.

[0041] In this embodiment, one end of the first impedance sub-unit 112 is connected to the external reference analog signal VREF, and the other end of the first impedance sub-unit 112 is grounded; through the first target control signal CTL1 <m:0>Control the first switch sub-unit 111 and the second switch sub-unit 113 to perform voltage division on the reference analog signal VREF to obtain a first intermediate voltage VOT and a second intermediate voltage VOB. In addition, one end and the other end of the first impedance sub-unit 112 can be respectively connected to two voltage signals with opposite polarities of the reference analog signal VREF, and it is only necessary to ensure that there is a voltage difference between one end and the other end of the first impedance sub-unit 112. The present invention does not make any limitation on the specific values of the voltage signals connected to one end and the other end of the first impedance sub-unit 112.

[0042] Further, one end of the second impedance sub-unit 121 is connected to the first intermediate voltage VOT, and the other end of the second impedance sub-unit 122 is connected to the second intermediate voltage VOB; through the second target control signal CTL2 <n:0>Control the third switch sub-unit 122 to perform voltage division on the difference between the first intermediate voltage VOT and the second intermediate voltage VOB to obtain the target analog signal DAC_OUT.

[0043] Preferably, the first impedance sub-unit 112 includes: 2 M resistors R1 connected in series in sequence; the second impedance sub-unit 121 includes: 2 N resistors R2 connected in series in sequence; where M and N can both be integers greater than or equal to 1, and M + N can be an integer greater than or equal to 10.

[0044] Preferably, corresponding to the first impedance sub-unit 112, the first switch sub-unit includes: 2 M first control switches S1, and each of the first control switches S1 is respectively connected to the series node between two adjacent resistors R1 of the first impedance sub-unit 112 in sequence. Similarly, still corresponding to the first impedance sub-unit 112, the second switch sub-unit 122 includes: 2 M second control switches S2, and each of the second control switches S2 is respectively connected to the series node between two adjacent resistors R1 of the first impedance sub-unit 112 in sequence; where one set of the first control switches S1 and one set of the second control switches S2 are staggered by one series node.

[0045] In this embodiment, corresponding to the second impedance sub-unit 121, the third switch sub-unit 122 includes: 2 N third control switches S3, and each of the third control switches S3 is respectively connected to the series node between two adjacent resistors R2 of the second impedance sub-unit 122 in sequence.

[0046] Further, the sampling and comparison module 20 is configured to receive an external initial analog signal VIN and the target analog signal DAC_OUT output by the digital-to-analog conversion module 10, and output an intermediate digital signal CMP_OUT to the subsequent stage. Specifically, the sampling and comparison module 20 includes: a first selection switch SHSW1, a second selection switch SHSW2, a third selection switch SHSW3, a capacitor CAP, and a comparison unit 21. Among them, the first selection switch SHSW1 is connected to the inverting input terminal of the comparison unit 21. The positive electrode of the capacitor CAP is connected to the connection node between the first selection switch SHSW1 and the inverting input terminal of the comparison unit 21, and the negative electrode of the capacitor CAP is grounded. The second selection switch SHSW2 and the third selection switch SHSW3 are both connected to the non-inverting input terminal of the comparison unit 21. Among them, through the third selection switch SHSW3, the output terminal of the digital-to-analog conversion module 10 is connected to the non-inverting input terminal of the comparison unit 21, so that the target analog signal DAC_OUT can be input to the non-inverting input terminal of the comparison unit 21. Further, the switching operating state of the third selection switch SHSW3 is opposite to the switching operating states of the first selection switch SHSW1 and the second selection switch SHSW2. Specifically, in this embodiment, it is necessary to ensure that the switching control signals for controlling the second selection switch SHSW2 and the third selection switch SHSW3 are not enabled simultaneously, that is, the second selection switch SHSW2 and the third selection switch SHSW3 will not be closed simultaneously (their switching operating states are opposite), to prevent the initial analog signal VIN and the target analog signal DAC_OUT from being short-circuited. When the analog-to-digital converter operates, the first selection switch SHSW1 and the second selection switch SHSW2 are closed simultaneously, so that the non-inverting input terminal and the inverting input terminal of the comparison unit 21 receive the initial analog signal VIN to balance the input voltage of the comparison unit 21.

[0047] Preferably, please refer to Figure 3 , Figure 3 FIG. is a schematic circuit diagram of the comparison unit according to an embodiment of the present invention. The comparison unit 21 includes: a current adder 211, a preamplifier 212, and a dynamic latch 213 connected in sequence. Specifically, the current adder 211 is composed of two current sources and multiple MOS transistors; the preamplifier 212 is a low-gain preamplifier composed of multiple resistors and multiple MOS transistors; the dynamic latch 213 is composed of multiple MOS transistors. The input signal of the comparison unit 21 has a large common-mode voltage range (GND~VDD), and the comparison speed is very fast.

[0048] Further, the logic control module 30 is configured to receive the intermediate digital signal CMP_OUT output by the sampling and comparison module 20, as well as an external clock signal ADC_CLK, an enable signal ADC_EN, a CMP_EN, and an initial control signal DAC <l:0>, perform logical processing on the intermediate digital signal CMP_OUT and output a first digital signal ADC_OUT to the subsequent stage <l:0>and a second digital signal ADC_RDY and to the initial control signal DAC <l:0>Perform logical processing and output the first target control signal CTL1 to the digital-to-analog conversion module 10 <m:0>and the second target control signal CTL2 <n:0>。

[0049] In this embodiment, the digital-to-analog conversion module 10 adopts a two-stage voltage dividing unit structure, and the first voltage dividing unit 11 and the second voltage dividing unit 12 respectively adopt 2 M , 2 N resistors in series. The first voltage dividing unit 11 evenly divides VREF into 2 M parts. Assuming that the resistance value of the resistor R1 of the first impedance sub-unit 112 is r1, the formula for the consumed current is:

[0050]

[0051] According to the first target control signal CTL1 <m:0>Select 2 M One of the two voltages (the first intermediate voltage VOT - the second intermediate voltage VOB), the first intermediate voltage VOT and the second intermediate voltage VOB are respectively connected to both ends of the second impedance sub - unit 122 through the second switch sub - unit 122. The second impedance sub - unit 122 then divides this voltage into 2 N output nodes and directly outputs them. What is output is the target analog signal DAC_OUT. The second voltage - dividing unit 12 is connected in parallel to both ends of the first voltage - dividing unit 11, which will cause a relative error. The formula for this relative error is:

[0052]

[0053] Among them, assuming that the relative error error is less than 0.05%, and both M and N are 5, then it is calculated that r2 is twice that of r1. When the first impedance sub - unit 112 outputs the last node, the resistance values of the last switch S1 and the first switch S2 in the conducting column of the first voltage - dividing unit 11 and the first resistor R2 and the last resistor R2 in the second voltage - dividing unit 12 are combined into a unit resistance value r2; when the second impedance sub - unit 121 outputs the first node, the switch controlling the second intermediate voltage VOB is turned off.

[0054] The analog - to - digital converter provided by the present invention uses the digital - to - analog conversion module 10 to achieve the conversion of digital signals to analog signals. The first selection switch SHSW1 and the capacitor CAP sample and hold the input initial analog signal VIN. The second selection switch SHSW2 is used to balance the input voltage (the initial analog signal VIN) of the comparison unit 21. The comparison unit 21 compares the initial analog signal VIN and the target analog signal DAC_OUT output by the digital - to - analog conversion module 10, and conveys the comparison result (the intermediate digital signal CMP_OUT) to the logic control module 30. The logic control module 30, according to the comparison result (the intermediate digital signal CMP_OUT), adopts the SAR logic to make the target analog signal DAC_OUT generated by the digital - to - analog conversion module 10 approach the initial analog signal VIN. After one analog - to - digital conversion is completed, the result of the analog - to - digital conversion is updated, that is, the first digital signal ADC_OUT is updated <l:0>, where L = M + N.

[0055] In this embodiment, the analog-to-digital converter further includes: a buffer module 40, the input end of the buffer module 40 is connected to the output end of the digital-to-analog conversion module 10, and is used for buffering and adjusting the target analog signal DAC_OUT.

[0056] In the analog-to-digital converter provided in this embodiment, in the reset mode, the current of all modules of the analog-to-digital converter is turned off, and the output results of the sampling and comparison module 20 and the quantization results output by the logic control module 30 are all pulled low.

[0057] In summary, the present invention provides an analog-to-digital converter, including: a digital-to-analog conversion module, a sampling and comparison module, and a logic control module. The digital-to-analog conversion module includes two-stage voltage dividing units, and uses these two-stage voltage dividing units to perform digital-to-analog conversion processing on the reference analog signal and output a target analog signal to the subsequent stage; the sampling and comparison module can process the received initial analog signal and the target analog signal into an intermediate digital signal; the logic control module performs logic processing on the intermediate digital signal to obtain a first digital signal and a second digital signal. By providing a digital-to-analog conversion module, the present application can achieve accurate digital-to-analog conversion while realizing high-precision analog-to-digital conversion, saving the layout area of the integrated circuit and improving the adaptability of the analog-to-digital converter in the aspect of the increasing integration degree of the integrated circuit. Further, the digital-to-analog conversion module includes two-stage voltage dividing units, and a target analog signal with higher precision can be obtained through the cooperation of 2 M resistors in the first stage and 2 N resistors in the second stage. In addition, the digital-to-analog conversion module provided in the present application can output a stable target analog signal (analog voltage signal) to the subsequent stage through two-stage voltage dividing processing. This digital-to-analog conversion module has driving ability and a large output swing.

[0058] Obviously, the above embodiments are only examples clearly described and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present application.

Claims

1. An analog-to-digital converter, characterized in that, Comprising: A digital-to-analog conversion module for receiving an external first target control signal, a second target control signal, and a reference analog signal; Performing digital-to-analog conversion processing on the reference analog signal through the first target control signal and the second target control signal and outputting a target analog signal to the subsequent stage; wherein, the digital-to-analog conversion module includes two-stage voltage division units; A sampling and comparison module for receiving an external initial analog signal and the target analog signal output by the digital-to-analog conversion module, and outputting an intermediate digital signal to the subsequent stage; and, A logic control module for receiving the intermediate digital signal output by the sampling and comparison module, as well as an external clock signal, an enable signal, and an initial control signal, performing logic processing on the intermediate digital signal and outputting a first digital signal and a second digital signal to the subsequent stage, and performing logic processing on the initial control signal and outputting the first target control signal and the second target control signal to the digital-to-analog conversion module; The sampling and comparison module includes: a first selection switch, a second selection switch, a third selection switch, a capacitor, and a comparison unit, wherein the first selection switch is connected to the inverting input terminal of the comparison unit, the positive electrode of the capacitor is connected to the connection node between the first selection switch and the inverting input terminal of the comparison unit, the negative electrode of the capacitor is grounded, and the second selection switch and the third selection switch are both connected to the non-inverting input terminal of the comparison unit; Wherein, through the third selection switch, the output terminal of the digital-to-analog conversion module is connected to the non-inverting input terminal of the comparison unit; The comparison unit includes: a current adder, a pre-amplifier, and a dynamic latch connected in sequence.

2. The analog-to-digital converter according to claim 1, characterized in that, The digital-to-analog conversion module includes: a first voltage division unit and a second voltage division unit connected to the first voltage division unit; The first voltage division unit includes: a first switch sub-unit, a first impedance sub-unit, and a second switch sub-unit connected in sequence; The second voltage division unit includes: a second impedance sub-unit and a third switch sub-unit connected to the second impedance sub-unit; Wherein, one end of the first impedance sub-unit is connected to the external reference analog signal, and the other end of the first impedance sub-unit is grounded; controlling the first switch sub-unit and the second switch sub-unit through the first target control signal to perform voltage division processing on the reference analog signal to obtain a first intermediate voltage and a second intermediate voltage; One end of the second impedance sub-unit is connected to the first intermediate voltage, and the other end of the second impedance sub-unit is connected to the second intermediate voltage; controlling the third switch sub-unit through the second target control signal to perform voltage division processing on the difference between the first intermediate voltage and the second intermediate voltage to obtain the target analog signal.

3. The analog-to-digital converter according to claim 2, characterized in that, The first impedance sub-unit includes: two resistors connected in series in sequence; M resistors; The second impedance sub-unit includes: 2 resistors connected in series in sequence; where M and N are both integers greater than or equal to 1, and M + N is an integer greater than or equal to 10. N ​ 4. The analog-to-digital converter according to claim 3, characterized in that The first switching sub-unit includes: 2 M first control switches, each of the first control switches is respectively and sequentially connected to a series node between two adjacent resistors of the first impedance sub-unit; The second switch sub-unit includes: 2 M second control switches, each of the second control switches is respectively and sequentially connected to a series node between two adjacent resistors of the first impedance sub-unit; Wherein, there is a stagger of one series node between the first control switch and the second control switch.

5. The analog-to-digital converter according to claim 3, wherein The third switch sub-unit includes: 2 N third control switches, and each of the third control switches is respectively and sequentially connected to a series node between two adjacent resistors of the second impedance sub-unit.

6. The analog-to-digital converter according to claim 1, characterized in that, When the analog-to-digital converter works, the first selection switch and the second selection switch are closed simultaneously, so that the non-inverting input terminal and the inverting input terminal of the comparison unit receive the target analog signal.

7. The analog-to-digital converter according to claim 1, characterized in that, The switching operating state of the third selection switch is opposite to the switching operating states of the first selection switch and the second selection switch.

8. The analog-to-digital converter according to claim 1, wherein The analog-to-digital converter further includes: a buffer module for buffering and adjusting the target analog signal.

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