Bandgap reference voltage circuit

Abstract

The present disclosure relates to a bandgap reference voltage circuit in which an output reference voltage is stable with respect to temperature and other variations. An example embodiment includes a bandgap reference voltage circuit (200) including an output voltage circuit (202) connected between first and second voltage rails (203, 204) and a plurality of offset amplifiers (201 1…n ) of an n number, each of the plurality of offset amplifiers (201 1…n ) including a transistor differential pair that together define an offset between an input voltage at an input of the amplifier (201) and an output, the offset amplifiers (201 1…n ) linked together and connected to the output voltage circuit, the output voltage circuit providing a bandgap reference voltage as a function of the offsets of the plurality of offset amplifiers.

Description

Technical Field

[0001] This disclosure relates to a bandgap reference voltage circuit in which the output reference voltage is stable relative to temperature and other variations. Background Technology

[0002] Bandgap reference voltage circuits are widely used in integrated circuits that require a fixed reference voltage that does not change with variations in power supply voltage, temperature, and other factors. Figure 1 An example bandgap reference circuit 100 is shown. Circuit 100 includes a pair of PNP transistors 101a and 101b positioned between the power supply voltage rail Vdd and the ground rail GND, and three NPN transistors Q0, Q1, and Q8. NPN transistors Q0 and Q8 are connected on either side of a resistor 102 with a total resistance R+r. Resistor r is chosen to bias NPN transistor Q1 such that the output voltage Vbg is equal to Vbe+kΔVbe, where k is the ratio (R+r) / r, and ΔVbe is the difference between the base-to-emitter voltage Vbe of NPN transistors Q1 and Q8. Typically, the resistor ratio is close to 10. The problem with this type of circuit is that the resistor ratio can change over time, causing the output voltage Vbg to drift. For example, if the ratio changes by 200ppm, the output voltage Vbg will typically change by about 100ppm. In some applications, such as in battery management systems, the lifetime drift limit may need to be less than 100ppm, which may make such circuits unsuitable. Therefore, the problem is how to manage the known drift of the resistances R and r, typically made of polysilicon in integrated circuits, to maintain a small output voltage variation with low drift over time. Another problem is... Figure 1 Circuits of this type require multiple tests at different temperatures to fine-tune the temperature-dependent output voltage Vbg, which adds considerable cost during manufacturing. Summary of the Invention

[0003] According to a first aspect, a bandgap reference voltage circuit is provided, comprising an output voltage circuit connected between a first voltage rail and a second voltage rail, and n number of offset amplifiers, the output voltage circuit comprising:

[0004] First, second, and third PNP transistors;

[0005] NPN transistors; and

[0006] A resistor is connected between the collector connection point of the first PNP transistor and the collector connection point of the NPN transistor.

[0007] The emitter connections of the first and second PNP transistors are connected together to the node; the base connections of the first and second PNP transistors are connected together to the second sensing connection point on the resistor; the collector connection of the third PNP transistor and the emitter connection of the NPN transistor are connected to the second voltage rail; the emitter connection of the third PNP transistor is connected to the collector connection of the second PNP transistor; and the base connections of the NPN transistor and the third PNP transistor are connected together to the first sensing connection point on the resistor.

[0008] The first offset amplifier of the plurality of offset amplifiers has an input connected to the emitter connection point of the third PNP transistor, the nth offset amplifier of the plurality of offset amplifiers has an output connected to the node, the output of each of the first to nth offset amplifiers is connected to the input of the subsequent offset amplifier, and each of the plurality of offset amplifiers includes a transistor differential pair that together defines the offset between the input voltage at the input of the amplifier and the output.

[0009] The size of the transistor differential pair may differ by a factor m, where m can be an integer greater than 2. The factor m can, for example, be an integer less than or equal to 10. In a specific example, the factor m can be 8.

[0010] The first and second sensing connection points are selectable along the resistor to allow adjustment of the resistance value between the sensing connection points. The first sensing connection point can be adjusted, for example, in increments different from the second sensing connection point, thereby allowing for both fine and coarse adjustments. Each sensing connection point can be connected to the resistor via a multiplexer, thereby allowing adjustment based on multiple bits of value input to each multiplexer.

[0011] The output voltage Vbg at the second sensing connection point can be determined by the following formula.

[0012]

[0013] Where V be1 It is the base-emitter voltage of the NPN transistor, and ΔV be It is the difference between the base-emitter voltages of the transistor differential pairs in each of the plurality of offset amplifiers.

[0014] According to a second aspect, a method for adjusting the output voltage of the bandgap reference voltage circuit described in the first aspect is provided, the method comprising:

[0015] Measure the output bandgap voltage at the second sensing connection point; and

[0016] Adjust the resistance value between the first sensing connection point and the second sensing connection point to adjust the output bandgap voltage to the desired value.

[0017] These and other aspects of the invention will become apparent from the embodiments described below, and these aspects will be illustrated with reference to the embodiments. Attached Figure Description

[0018] The embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0019] Figure 1 This is a schematic circuit diagram of a typical bandgap reference voltage circuit;

[0020] Figure 2 This is a schematic circuit diagram of an example bandgap reference voltage circuit;

[0021] Figure 3 yes Figure 2 A more detailed schematic circuit diagram;

[0022] Figure 4 yes Figure 3 A schematic circuit diagram of an example bipolar amplifier;

[0023] Figure 5 yes Figure 3 A schematic circuit diagram of an example implementation of a bipolar amplifier;

[0024] Figure 6 This is a schematic circuit diagram of another example of a bandgap reference voltage circuit;

[0025] Figure 7 Bandgap voltage curves as a function of temperature for both finely tuned and un-finely tuned circuits.

[0026] Figure 8 Is Figure 2 The voltage curve during circuit startup as a function of time; and

[0027] Figure 9 This is a flowchart illustrating an example method for adjusting the output voltage of a bandgap reference voltage circuit.

[0028] It should be noted that the figures are illustrative and not drawn to scale. For clarity and convenience in the figures, the relative dimensions and proportions of the parts have been shown by enlarging or reducing their size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. Detailed Implementation

[0029] Figure 2 An example bandgap reference voltage circuit 200 is shown, which is not like... Figure 1Instead of relying on a k-factor as in the conventional circuit shown, it is derived from multiple cascaded offset amplifiers 201. 1…n The sum of the ΔVbe values ​​derives the output voltage Vbg. The number n of cascaded offset amplifiers can vary depending on the required reference voltage and the value of ΔVbe in each amplifier. Each offset amplifier 201 can have Figure 2 The form shown, in Figure 4 It is shown in more detail in the middle, and has Figure 5 The example implementation shown is illustrated in the figure.

[0030] Figure 2 The bandgap reference voltage circuit 200 shown includes multiple cascaded offset amplifiers 201 connected between a first or power supply voltage rail 203 and a second or ground rail 204. 1…n Output voltage circuit 202. Offset amplifier 201. 1…n Together, current is supplied to the output voltage circuit 202 at node 205, and the voltage at node 205 is defined. The output voltage circuit 202 is connected between node 205 and ground 204. The output voltage circuit 202 includes a first PNP transistor 201a, a second PNP transistor 201b, a third PNP transistor 201c, an NPN transistor 206, and a resistor 207. The emitter connection points of the first PNP transistor 201a and the second PNP transistor 201b are connected to node 205. The base connection points of the first PNP transistor 201a and the second PNP transistor 201b are connected together. The collector connection point of the third PNP transistor 201c is connected to ground 204, and the emitter connection point of the third PNP transistor 201c is connected to the collector connection point of the second PNP transistor 201b. The emitter connection point of the NPN transistor 206 is connected to ground 204, and the base connection point of the NPN transistor 206 is connected to the base connection point of the third PNP transistor 201c. The base connection points of the third PNP transistor 201c and NPN transistor 206 are connected to a first or bottom sensing connection point 208 on resistor 207. Resistor 207 is connected between the collector connection point of the first PNP transistor 201a and the collector connection point of the NPN transistor 206. A second or top sensing connection point 209 is connected to the base connection points of the first PNP transistor 201a and the second PNP transistor 201b. The second sensing connection point 209 provides an output voltage connection point to provide the output bandgap voltage Vbg. Figure 2 In the example shown, the resistance R between the first sensing connection point 208 and the second sensing connection point 209 is 26.55 kΩ, provided by a 425 μm long polysilicon resistor segment. As described in more detail below, the points on resistor 207 where sensing connections 208 and 209 are formed can be selected to adjust the voltage output Vbg.

[0031] Multiple offset amplifiers 201 1…n A connection is made between the emitter junction of the third PNP transistor 201c and node 205, and node 205 is connected to the emitter junction of the first PNP transistor 201a and the second PNP transistor 201b. (As in...) Figure 3 The diagram shows in more detail the multiple offset amplifiers 201 1...n The first offset amplifier 2011 has an input connected to the emitter connection point of the third PNP transistor 201c. The third PNP transistor 201c requires a sufficiently high voltage at the input of the first offset amplifier 2011 to drive amplifier 2011. The nth offset amplifier 201n has an output connected to node 205. The first to (n-1)th offset amplifiers 201... n-1 The output of each offset amplifier in the array is connected to the input of the subsequent offset amplifier. Multiple offset amplifiers 201 1...n A chain is formed at node 205 to provide an output voltage equal to the base-emitter voltage difference ΔV from each offset amplifier. be The sum, that is, Adding the base-emitter voltage V from the NPN transistor and the third PNP transistor 201c be1 and V be2 The sum of .

[0032] like Figure 4 As shown, each offset amplifier 201 can be considered as including an ideal amplifier A, a voltage offset 211, an output switch 212, and a current source 213. The input voltage at the input connection point 401 of the offset amplifier 201 is offset by the voltage offset 211 and input to the non-inverting input of amplifier A. The output of amplifier A is provided to switch 212, which provides an output voltage at the output connection point 402. The voltage at the output connection point 402 differs from the voltage at the input connection point 401 by the offset provided by the voltage offset 211.

[0033] Refer again Figure 3 Offset amplifier 201 1…n The chain generates an output bandgap reference voltage Vbg, where Vbg is the base-emitter voltage V of the NPN transistor 206. be1 (It is equal to the base-collector voltage of the third PNP transistor 201c, since the base connection points of the transistors are connected), the base-emitter voltage V of the third PNP transistor 201c. be2 n offset amplifiers 201 1…n The sum minus the base-emitter voltage V of the first PNP transistor 201a and the second PNP transistor 201b be2The sum of all subsequent values. The output bandgap voltage Vbg can therefore be expressed as:

[0034]

[0035] The formula simplifies to:

[0036]

[0037] Therefore, the bandgap reference voltage is not like Figure 1 The k-factor, which previously depended primarily on resistor 207 in the bandgap reference voltage circuit, now depends primarily on multiple offset amplifiers 201. 1…n The sum of the voltage differences. This reduces the dependence on resistor changes, thus making the output voltage more stable and less prone to drift.

[0038] Figure 5 The diagram illustrates an example practical implementation of an offset amplifier 201. Amplifier 201 includes a differential pair of NPN transistors 501a and 501b, which together define an offset between the input voltage at input 401 and the output 402. The circuit also includes NFET transistors 503, 504, 506, 507, and 508, a PFET transistor 505, a pair of PNP transistors 502a and 502b, and another PNP transistor 509, and is connected between a power supply voltage rail 203 and a ground rail 204. Circuit 201 is configured to provide an output voltage at output 402 that deviates from the voltage provided at input 401 by an offset equal to the difference between the base-emitter voltages of the transistor differential pair 501a and 501b, referred to as ΔVbe. Cascading such circuitry allows voltage difference accumulation.

[0039] Figure 5 The dashed lines 510, 511, and 512 in the diagram indicate the locations where the voltage levels in the circuit are equal, namely, at the connection points between input 401 and the source connections of transistors 504 and 505, and at the collector connection points of transistor pairs 501a and 501b. It can be seen that the output voltage is thus limited by the input voltage minus the Vbe of transistor 501b plus the Vbe of transistor 501a, thereby providing the required ΔVbe offset.

[0040] The tail current, i.e., the current pulled down by the drain of transistor 507, is controlled by a closed loop formed by transistors 504, 505, 512, and 507. This closed loop forces the collectors of NPN transistor pairs 501a and 501b to be at the same voltage indicated by line 510. The tail current is driven by an NMOS mirror current, which is driven by a PMOS transistor 505 driven by an NMOS source follower 506, which is attached to the non-inverting input 401 through its gate. The source of transistor 505 is close to the same voltage as the input indicated by line 512. The gate of transistor 504 is connected to the collector of transistor 501b. The follower-stage transistor 506 provides a source voltage of Vin-Vgs, and the next follower-stage transistor 505 will perform the same operation, making the source of transistor 505 almost equal to Vin. Therefore, the collectors of differential pairs 501a and 501b have almost the same voltage. Corresponding to Figure 4 The collector of the NPN transistor 501a at the output of amplifier A has a voltage equal to Vout + Vgs, where Vout is the voltage at output 402 and Vgs is the voltage at transistor NFET 503 (corresponding to...). Figure 4 The gate-to-source voltage of transistor 212 in the transistor.

[0041] The voltage offset ΔVbe between input 401 and output 402 is determined by the size difference between transistors 501a and 501b, expressed as (kT / q)lnm, where k is the Boltzmann constant, T is the absolute temperature, and m is the size ratio between transistors 501a and 501b. Transistor 501b may, for example, be 8 times the size of transistor 501a. In general, the factor m can be an integer between 2 and 10. At room temperature, kT / q equals 25mV, so for m in the range of 2 to 10, the voltage offset will be in the range of approximately 17mV to approximately 57mV. For the bandgap reference voltage, m can be chosen to be 8, as this is a good trade-off between silicon area and the k-factor. Lower values ​​of m will require higher k-factors, while higher values ​​will require a larger increase in the size of transistor 501b.

[0042] Given that the size differences between transistors will increase in practice, a single value of m is insufficient to accurately define the required bandgap reference voltage. The solution to this is to allow adjustment of sensing connection points 208, 209 (see...). Figure 2 The resistance between ). Figure 6The diagram illustrates this situation, where the first sensing connection point 208 and the second sensing connection point 209 can each be selected among multiple locations 601, 602 along the resistor 207. This can be implemented using a multiplexer for each sensing connection point 208, 209, thereby allowing adjustment of the resistance value between the base connections of transistors 201a, 201b and transistors 206, 201c. Figure 6 Example values ​​are shown illustrating the extent to which each sensing connection point 208, 209 can be fine-tuned. For the second or top sensing connection point 209, fine-tuning may involve steps of approximately 1.71 μm along resistor 207, while for the first or bottom sensing connection point 208, larger steps of approximately 13.68 μm may be involved. In general, sensing connections 208, 209 can be adjusted incrementally along resistor 207. The increment used for the first sensing connection point may differ from the increment used for the second sensing connection point. Providing different increments allows for both coarse and fine adjustments to the resistance values ​​between sensing connections 208, 209. Using a multiplexer for each sensing connection point, if three bits are used for each connection point, a total of eight different connection points can be selected for each sensing connection point, thereby enabling the selection of resistance values ​​to finely tune the output voltage Vbg. Figure 6 In the example shown, a coarse adjustment achieves a change of + / - 880Ω, while a fine adjustment achieves a change of + / - 110Ω.

[0043] Figure 9 A flowchart is shown illustrating a method for adjusting the output bandgap reference voltage of the circuit described herein. After the circuit is started (step 901), in step 902, the output voltage Vbg is measured. The resistor is then adjusted (step 903) and a measurement is taken to determine if Vbg has reached the desired value (step 904). If not, the resistor is adjusted again. Once the desired Vbg is reached, the process ends (step 905) and the circuit is calibrated for use. The adjustment can be stored, for example, by storing a series of bits defining the positions of the sensing connection points 208, 209.

[0044] The advantage of the circuit arrangement in which the base connection points of transistors 206 and 201c are connected together with the first sensing connection point and the base connection points of transistors 201a and 201b are connected together with the second sensing connection point is that fine-tuning the resistance between the first sensing connection point 208 and the second sensing connection point 209 will fine-tune both the absolute value of Vbg and the slope of Vbg relative to temperature. Figure 7An example illustrating this is shown in the figure, which plots Vbg (in volts) as a function of temperature (in °C). The unadjusted relationship 701 of Vbg versus temperature has a slope 702, while the adjusted relationship 703 has a decreasing slope 704. The adjusted relationship 703 therefore more closely matches the typical desired curve 705. A comparison between the typical curve 705 and the adjusted curve 703 reveals a difference of 83 ppm at -40 °C and 200 ppm at 80 °C. This is achieved using only a single adjustment operation, rather than performing multiple measurements at two or three different temperatures before adjustment, as is the case with conventional techniques.

[0045] Compared to conventional bandgap voltage reference circuits, the circuit disclosed herein has the advantage of significantly less impact of changes in resistor 207 on the output voltage Vbg. For example, in a conventional circuit with a 30kΩ resistor, a 200ppm change in the k-factor, equivalent to a 6Ω difference, would shift the bandgap voltage by approximately 100ppm. In contrast, using the circuit described herein, a 1000ppm resistance change—five times the aforementioned change—would only alter the output bandgap voltage by 25ppm, a quarter of the shift. Therefore, overall, the output voltage change is approximately 20 times smaller than that of conventional circuits. This allows the circuit to be used in applications requiring lower output voltage drift, such as in battery management systems for lithium-ion batteries.

[0046] Another advantage is that no starting circuit is needed because the output does not depend on the k-multiplication factor. The circuit's output is actually the sum and difference of various Vbe values ​​across the bias resistor 207. (See the graph showing voltage versus time.) Figure 8 As shown, with the power supply voltage V DD The bandgap voltage V rises, reaching 2.1V within approximately 2.1ms after the supply voltage reaches 2.1V. BG It rises to the desired value, in this case 1.233V. Above this, the bandgap voltage remains constant.

[0047] In summary, the circuit described in this paper allows the use of the sum of ΔVbe instead of multiplying ΔVbe by a k-factor. Each ΔVbe is provided by a built-in offset amplifier configured in follower mode with a unity-gain closed-loop configuration. Due to the smaller parameter variations (without a k-factor), this provides reduced bandgap value drift and a lower correlation between the bandgap value and the slope, thus allowing for single-test adjustments to the bandgap during manufacturing and testing.

[0048] Other variations and modifications will become apparent to those skilled in the art upon reading this disclosure. Such variations and modifications may involve equivalent and other features known in the field of bandgap reference voltage circuits and used in place of or in addition to the features described herein.

[0049] Although the appended claims relate to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalized form thereof explicitly or implicitly disclosed herein, regardless of whether it relates to the same invention claimed in any claim or whether it alleviates any or all of the same technical problems as those alleviated by this invention. Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, various features described in the context of a single embodiment for brevity may also be provided individually or in any sub-combination. The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0050] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a (a or an)" does not exclude that a plurality of, a single processor or other unit may perform the functions of the several components described in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A bandgap reference voltage circuit (200), comprising a first voltage rail (203) and a second voltage rail (204), characterized in that, Includes an output voltage circuit (202) connected between a first voltage rail (203) and a second voltage rail (204) and n cascaded offset amplifiers (201). 1…n The output voltage circuit (202) includes: First, second and third PNP transistors (201a-c); NPN transistor (206); and A resistor (207) is connected between the collector connection point of the first PNP transistor (201a) and the collector connection point of the NPN transistor (206). The emitter connections of the first and second PNP transistors (201a-b) are connected together to node (205), the base connections of the first and second PNP transistors (201a-b) are connected together to the second sensing connection point (209) on resistor (207), the collector connection point of the third PNP transistor (201c) and the emitter connection point of the NPN transistor (206) are connected to the second voltage rail (204), the emitter connection point of the third PNP transistor (201c) is connected to the collector connection point of the second PNP transistor (201b), and the base connections of the NPN transistor (206) and the third PNP transistor (201c) are connected together to the first sensing connection point on resistor (207). Each of the plurality of said offset amplifiers includes: Ideal amplifier (A); The transistor differential pair (501a, 501b) together defines the offset between the input voltage at the input (401) of the ideal amplifier (A) and the non-inverting input; Output switch 212, the input switch being located between the first voltage rail (203) and the output node (402), and controlled by the output of the ideal amplifier (A); and current source 213, which is connected in series between the output node (402) and the second voltage rail (204); The output node is connected to the inverting input of the ideal amplifier; The plurality of offset amplifiers (201) 1…n The first offset amplifier (2011) in the plurality of offset amplifiers has a non-inverting input connected to the emitter connection point of the third PNP transistor (201c), the nth offset amplifier of the plurality of offset amplifiers has an output node connected to the node (205), and the output node of each of the first to (n-1)th offset amplifiers is connected to the plurality of offset amplifiers (201c). 1…n The subsequent non-inverted inputs of the first one in the series.

2. The bandgap reference voltage circuit (200) according to claim 1, characterized in that, The phase difference factor m is the size of the transistor differential pair.

3. The bandgap reference voltage circuit (200) according to claim 2, characterized in that, The factor m is an integer greater than 2.

4. The bandgap reference voltage circuit (200) according to claim 2, characterized in that, The factor m is an integer less than or equal to 10.

5. The bandgap reference voltage circuit (200) according to claim 1, characterized in that, The positions of the first and second sensing connection points (208, 209) along the resistor (207) are selectable to allow adjustment of the resistance value between the sensing connection points (208, 209).

6. The bandgap reference voltage circuit (200) according to claim 5, characterized in that, The first sensing connection point (208) can be adjusted in increments different from those of the second sensing connection point (209).

7. The bandgap reference voltage circuit (200) according to claim 5 or claim 6, characterized in that, Each sensing connection point (208, 209) is connected to the resistor (207) via a multiplexer (601, 602).

8. The bandgap reference voltage circuit (200) according to any one of claims 1-6, characterized in that, The output voltage Vbg at the second sensing connection point is determined by the following formula. Where V be1 It is the base-emitter voltage of the NPN transistor (206), and ΔV be It is the plurality of offset amplifiers (201) 1-n The difference between the base-emitter voltages of the differential pairs (501a, 501b) of the transistors in each of the transistors.

9. A method for adjusting the output voltage of the bandgap reference voltage circuit (200) according to any one of the preceding claims, characterized in that, The method includes: Measure the output bandgap voltage at the second sensing connection point (209); and Adjust the resistance value between the first sensing connection point and the second sensing connection point (208, 209) to adjust the output bandgap voltage to the desired value.

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