Optimization Method for Test Data Transmission Based on JTAG Standard

Abstract

The present invention discloses an optimization method for test data transmission based on the JTAG standard. Based on the IEEE1149.1 protocol, during the process of accessing the data register, in the Run-Test / Idle state of the FSM, the compressed test set generated on the host computer at the PC end is transmitted to the SRAM of the circuit through the TDI pin of the JTAG port, and is quickly decoded by the high-frequency clock decoding circuit. After decoding, it enters a buffer circuit and waits for the Shift-DR state of the FSM to be shifted into the scan chain. Among them, the compression coding is based on the FDR code, and a method of 0 / 1 alternating coding is given. It is a variable-length to variable-length coding method. f is an additional flag bit associated with it. The two adjacent additional flag bits of this coding are inverted with each other, and only the initial value of f needs to be remembered. After that, it remains alternating between 0 and 1, which reduces the number of test data bits and the time overhead of test set transmission. At the same time, the decoding circuit in this method is simple and independent of the circuit under test. Based on this, this method has excellent application prospects.

Description

Technical Field

[0001] The present invention relates to an integrated circuit testing method, and more particularly to an optimized method for test data transmission based on the JTAG standard. Background Art

[0002] With the rapid update of electronic circuit technology, integrated circuit chips are becoming increasingly complex, and the use of table test circuits can no longer meet the test development needs of today's very large scale integrated circuits. JTAG boundary scan based on the IEEE1149.1 international standard is a new integrated circuit testing method defined by the famous international test behavior organization, which proposes to define a standard interface for the testing of complex circuits and makes up for the traditional physical probe testing method. In the IEEE1149.1 international standard, a TAP (Test Access Port) is defined internally. Through the TAP, all data registers (DR) and instruction registers (IR) provided by the chip can be accessed. The TAP Controller controls the state transition of the 16-state FSM through the TMS signal for test operations. For chips with JTAG interfaces, the relevant JTAG pin definitions are as follows: a) TCK is the test clock input; b) TDI is the test data serial input; c) TDO is the test data serial output; d) TMS is the test mode input; e) TRST is the test reset, an optional pin. The test vector set is generally a binary sequence composed of 0 and 1, with a large amount of data and a lot of redundant parts, resulting in excessive time overhead for data transmission. Especially as time goes by, the test data grows rapidly, which increases the difficulty of data transmission, ultimately leading to lower and lower efficiency and higher and higher costs. Summary of the Invention

[0003] The problem to be solved by the present invention is to provide an optimized method for test data transmission based on the JTAG standard, which can achieve the goal of reducing data transmission time and test cost.

[0004] To solve the above technical problems, the present invention discloses an optimized method for test data transmission based on the JTAG standard, including the following steps:

[0005] S1. Establish an original test data set;

[0006] S2. Construct a code table, where the code table includes a group number represented by K, a sequence length represented by L, a prefix code, an in-group code, and a code word formed by concatenating the prefix code and the in-group code;

[0007] S3. The host computer encodes and compresses the original test data set according to the code table to obtain a compressed test data set;

[0008] S4. Transfer the compressed test set obtained in S3 to the SRAM via the TDI pin;

[0009] S5. Access the SRAM, decode the compressed test data set through the decoder, enter the TDI buffer queue, and wait for the control of TMS in the TAP Controller.

[0010] Preferably, the records in the code table are arranged in ascending order of sequence length and grouped, and the group numbers K are also arranged in ascending order.

[0011] Preferably, the method for constructing the code table in step S2 is as follows:

[0012] S2-1. When K = 1, the Kth group includes two records; if L = 1, the prefix code = 0, and the in-group code = 0; if L = 2, the prefix code = 0, and the in-group code = 1;

[0013] S2-2. When K > 1, the Kth group includes 2 K records;

[0014] S2-3. In the Kth group, the prefix code is composed of K - 1 bits of 1 and one bit of 0 concatenated, and the in-group code is composed of K-bit binary sequences, increasing from 0 to 2 K arranged in sequence.

[0015] Preferably, the method for the host computer to encode and compress the original test data set according to the code table in step S3 is as follows:

[0016] S3-1. Initialize the flag bit f, and this f corresponds to a default run type;

[0017] S3-2. Divide the test data set into sequence types, record that the first continuous sequence does not match the default continuous sequence, and f is inverted; if it matches, f remains unchanged. Place f at the first position of the compressed test set;

[0018] S3-3. Obtain the sequence length L of the current continuous sequence and look up the code word corresponding to its sequence in the code table;

[0019] S3-4. Output the code word corresponding to the current continuous sequence;

[0020] S3-5. Repeat S3-3 and S3-4 until the encoding of the entire test set is completed to obtain a continuous compressed test set.

[0021] Preferably, the decoder includes a finite state machine FSM, a K-bit counter, a log2(K + 1)-bit counter, and an adder.

[0022] Preferably, step S5 includes the following sub-steps:

[0023] S5-1. Initialize the count value cnt, where cnt = 0;

[0024] S5-2. Sequentially read the compressed test set bit by bit from the SRAM. Store the first compressed data bit read into the FSM, denoted as a, and discard it from its sequence;

[0025] S5-3. Continue to sequentially read the compressed sequence bit by bit, and increment the data bit count by 1 using a K-bit counter. Denote its value as cnt, and stop counting until a 0 is read;

[0026] S5-4. Write cnt into the log2(K + 1) counter for exponentiation. Denote its value as cod, and write it into the adder;

[0027] S5-5. Read the data bit by bit, denoted as b-in, and decrement cnt until cnt = 0, at which point the K counter stops counting. Write b-in into the adder;

[0028] S5-6. Sum cod and b-in in the adder. Denote the sum value S and write it into the K-bit counter for a decrement operation. The FSM continuously outputs one ~a and S a's; ~a is the negation of a;

[0029] S5-7. Repeat S5-3 to S5-6 until all compressed sequences are decoded;

[0030] S5-8. The decompressed sequence enters the TDI buffer queue and waits for control by TMS in the TAP Controller. The features and effects of the technical solution of the present invention are as follows:

[0031] (1) The encoding process is preprocessing of the test data in the host computer. The data in the test data set is classified into continuous 0 sequences and continuous 1 sequences, and encoded according to the sequence length. For a data set where continuous 0 / 1 sequences generally alternate, the number of bits of the encoded codeword is less than the length of the sequence itself, compressing the test data set;

[0032] (2) Use the TDI port defined in the IEEE1149.1 international standard for serial data transmission, and the compressed test data set greatly reduces the time overhead of data transmission;

[0033] (3) The decoding circuit uses a high-frequency clock to perform high-speed decoding of the compressed test data set, approximately transmitting at an extremely high bandwidth with the original test data set, which can effectively improve the transmission efficiency;

[0034] (4) According to the pre-coding table of the sequence length, the encoding process of the test data set is pre-completed in the host computer. The internal decoder of the integrated circuit only requires simple arithmetic functions such as counting, exponentiation, addition, and subtraction, further reducing the test cost. Brief Description of the Drawings

[0035] Figure 1 It is a schematic diagram of the code table of the test data transmission optimization method based on the JTAG standard of the present invention.

[0036] Figure 2 It is a flowchart for encoding the first consecutive sequence of test data using the present invention.

[0037] Figure 3 It is a flowchart for encoding consecutive sequences of test data except the first consecutive sequence using the present invention.

[0038] Figure 4 It is a flowchart for decoding compressed test data using the present invention.

[0039] Figure 5 It is a block diagram of an implementation manner of the decoder of the present invention. Specific implementation manner

[0040] The test data transmission optimization method based on the JTAG standard of the present invention includes the following steps:

[0041] S1. Establish an original test data set;

[0042] S2. Construct a code table, where the code table includes a group number represented by K, a sequence length represented by L, a prefix code, an in-group code, and a code word formed by cascading the prefix code and the in-group code;

[0043] S3. The host computer encodes and compresses the original test data set according to the code table to obtain a compressed test data set;

[0044] S4. Transmit the compressed test set obtained in S3 to the SRAM through the TDI pin;

[0045] S5. Access the SRAM, decode the compressed test data set through the decoder, enter the TDI buffer queue, and wait for the control of TMS in the TAP Controller.

[0046] A further setting of the present invention is that the method for constructing the code table in step S2 is as follows:

[0047] S2-1. When K = 1, the Kth group includes two records; if L = 1, the prefix code = 0, and the in-group code = 0; if L = 2, the prefix code = 0, and the in-group code = 1;

[0048] S2-2. When K>1, the Kth group includes 2 K records;

[0049] S2-3. In the Kth group, the prefix code is composed of K-1 bits of 1 and one bit of 0 in cascade, and the in-group code is composed of K-bit binary sequences, increasing from 0 to 2 K in sequence.

[0050] According to the above rules, the constructed code table, as Figure 1 shown, the records in the code table are arranged and grouped in ascending order of binary numbers starting from 0 with the sequence length, and the group number K is arranged in ascending order of decimal numbers starting from 1. In the code table, the prefix code is composed of K - 1 bits of 1 and one bit of 0 concatenated. During the decoding process, first read the prefix code, and then judge and read the in-group code within the group with the number of bits of the prefix code.

[0051] Specifically, when K > 1, the first half group and the second half group each include 2 K records. The prefix codes corresponding to the first half group and the second half group are different and the number of bits of the prefix code is different; the in-group code is composed of k bits of binary numbers, and there are 2 K forms of the in-group code. For different groups, the value of the group number K is different. The code word formed by concatenating the prefix code and the in-group code has a one-to-one correspondence with the sequence length L. Consecutive 0 / 1 sequences with the same sequence length adopt the same code word, and the code word corresponds to L, but does not reflect the sequence type; when K > 1, in the Kth group, the group prefix is composed of K - 1 bits of 1 and one bit of 0 concatenated, that is to say, the group prefix code contains K - 1 consecutive 1s and ends with 0. The in-group code is arranged in ascending order of K-bit binary numbers starting from 0. The smallest K-bit binary number is composed of K 0s, and the largest K-bit binary number is composed of K 1s. The number of bits of the prefix code is the same as the number of bits of the in-group code.

[0052] A further setting of the present invention, as Figure 2 and Figure 3 shown, the method for the host computer to encode and compress the original test data set in the step S3 is as follows:

[0053] S3-1. Initialize the flag bit f, and this f corresponds to a default run type;

[0054] S3-2. Divide the sequence type of the test data set, record that the first continuous sequence does not match the default continuous sequence, and f is inverted; if it matches, f remains unchanged. Place f at the first position of the compressed test set;

[0055] S3-3. Obtain the sequence length L of the current continuous sequence and look up the code table to get the code word corresponding to its sequence;

[0056] S3-4. Output the code word corresponding to the current continuous sequence;

[0057] S3-5. Repeat S3-3 and S3-4 until the encoding of the entire test set is completed to obtain a continuous compressed test set.

[0058] The following is an encoding example according to the above method:

[0059] Original test data: 0000001-1111111110-00000000000001-110-000001-11110 (45 bits);

[0060] Encoded data: 010111100101101100110101001 (27 bits), where 1011, 110010, 110110, 01, 1010, 1001 are the encoding words corresponding to the respective consecutive sequences.

[0061] Special case: For the tail of the test set, there may be cases where a consecutive 0 / 1 sequence cannot be formed, such as at least 1 consecutive 0, at least 1 consecutive 1, etc. at the tail. In this case, the corresponding encoding word is queried according to the code table. To solve this problem, a binary digit that is the inverse of the previous binary digit needs to be added after the obtained encoding to form a consecutive sequence. For example, if the final result is 11111111, then add 1 bit 0 after it to become 111111110; if the result is 0000000, then add 1 bit 1 to get 00000001. After processing, the tail of the test set can query the encoding word according to the code table. In the subsequent decoding step, the original tail data and the additional opposite binary digit are decoded. During the integrated circuit test process, there are requirements for the length of the test set data. When reading the test data, the last additional sequence end flag is not read in, so it does not affect the test result.

[0062] Further setting of the present invention, as Figure 5 shown, the decoder includes a finite state machine FSM, a K-bit counter, a log2(K + 1)-bit counter, and an adder.

[0063] Specifically, as Figure 4 shown, the step S5 includes the following sub-steps:

[0064] S5-1. Initialize the count value cnt, cnt = 0;

[0065] S5-2. Sequentially read the compressed test set bit by bit from the SRAM, store the first compressed data read into the FSM, denoted as a, and discard it from its sequence;

[0066] S5-3. Continue to sequentially read the compressed sequence bit by bit, the K-bit counter counts the number of data bits and increments by 1, and its value is denoted as cnt, until 0 is read, then stop counting;

[0067] S5-4. Write cnt into the log2(K + 1) counter for exponentiation, and its value is denoted as cod, then write it into the adder;

[0068] S5-5. Read the data bit by bit, denoted as b-in, decrement cnt until cnt = 0, stop the K counter from counting, and write b-in to the adder;

[0069] S5-6. Sum cod and b-in in the adder, write the sum value S to the K-bit counter, perform a decrement operation, and the FSM continuously outputs one ~a and S a's; ~a is the negation of a;

[0070] S5-7. Repeat S5-3 to S5-6 until all compressed sequences are decoded;

[0071] S5-8. The decompressed sequence enters the TDI buffer queue and waits for the control of TMS in the TAP Controller.

[0072] During the above decoding process, determine the sequence type according to the first bit of the compressed test data, then discard it from the sequence, read the prefix code bit by bit in turn, and the sequence length can be determined according to the prefix code; by default, only consider that the sequence types of adjacent runs are different. The above process completes the compression, transmission, and decompression of the test data set.

[0073] The following gives a specific implementation of the decoder circuit design.

[0074] From Figure 1 It can be seen that the group number (K) = the number of bits of the prefix code = the number of bits of the encoding within the group; the sequence length (L) = the encoding within the group + 2 K - 1. For example, for the codeword bit 110101, 110 is the prefix code, 101 is the encoding within the group, the group number K is 3, then the sequence length L = (encoding within the group) 10 + 2 K - 1 = (101) 10 + 2 3 - 1 = 12.

[0075] Therefore, using a K-bit counter can output the number of bits of the prefix code, and the encoding within the group can be obtained. Using a log2(K + 1) counter and an adder, calculate the run length L according to the number of bits of the prefix code and the encoding within the group, and output by the FSM.

[0076] Furthermore, in combination with Figure 4 and Figure 5 explain the decoding process of this example:

[0077] a. Initialize EN = 1, cnt = 0, t = 0;

[0078] b. Read the compressed test set bit by bit in turn, store the first compressed data read into the FSM, denoted as a, and discard the first data from its sequence;

[0079] c. Continue to sequentially read the compressed sequence bit by bit. In the K-bit counter, Inc = 1, Dec = 0, Res = 0, and increment cnt by 1 until a 0 is read, then stop counting.

[0080] d. Write k into the log2(cnt + 1) counter for exponentiation, and denote its value as cod, then write it into the adder.

[0081] e. Read the data bit by bit, denoted as b-in. In the K-bit counter, Inc = 0, Dec = 1, Res = 0, and decrement cnt by 1. When cnt = 0, the K-bit counter stops counting, and b-in is written into the adder.

[0082] f. cod and b-in are summed in the adder, and the sum value s is written into the K-bit counter. s is decremented by 1, and the FSM continuously outputs one ～ a, (cod + b-in) number of a's, and a is inverted.

[0083] g. Repeat steps c - f until all compressed sequences are decoded.

[0084] For the above technical solution, in order to cope with the pressure of the rapid growth of test data, compressed counting is used to compress the test data. In the host computer, according to the BSDL file of the internal chip in the integrated circuit structure file, a test data set is generated and encoded according to a certain encoding method. The encoded test set is transmitted to the SRAM in the circuit through the TDI pin of the JTAG port, and the decoding circuit performs decoding operations. The decoded test data is applied to the circuit under test to complete the test.

[0085] The encoding scheme based on multi-bit continuous 0 / 1 sequences has a high data compression ratio and a small decoding circuit overhead. It includes two types: continuous 0 sequences and continuous 1 sequences. Among them, continuous 0 sequences refer to binary sequences composed of at least 1 bit of continuous 0s and a 1 at the end; continuous 1 sequences refer to binary sequences composed of at least 1 bit of continuous 1s and a 0 at the end. The 1 in the continuous 0 sequence and the 0 at the end of the continuous 1 sequence can be regarded as sequence end bits and are not included in the sequence length. This reduces the time overhead of data transmission in the compressed test data set and can effectively improve the transmission efficiency.

[0086] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing test data transmission based on the JTAG standard, comprising the following steps: S1. Establish an original test data set; S2. Construct a code table, where the code table includes a group number represented by K, a sequence length represented by L, a prefix code, an intra-group code, and a code word formed by concatenating the prefix code and the intra-group code; The method for constructing the code table is as follows: S2-1. When K = 1, the Kth group includes two records; if L = 1, the prefix code = 0, and the intra-group code = 0; if L = 2, the prefix code = 0, and the intra-group code = 1; S2-2. When K > 1, the K-th group includes 2 K records; S2-3. In the Kth group, the prefix code is composed of a concatenation of K - 1 bits of 1 and one bit of 0, and the intra-group encoding is composed of a K-bit binary sequence, increasing from 0 to 2 K in sequence; S3. The host computer encodes and compresses the original test data set according to the code table to obtain a compressed test data set; The method for the host computer to encode and compress the original test data set according to the code table is as follows: S3-1. Initialize the flag bit f, and this f corresponds to a default run type; S3-2. Divide the test data set into sequence types, record that the first continuous sequence does not match the default continuous sequence, and invert f; if they match, f remains unchanged, and f is placed at the first position of the compressed test set; S3-3. Obtain the sequence length L of the current continuous sequence, look up the code table to obtain the corresponding code word of the sequence; S3-4. Output the code word corresponding to the current continuous sequence; S3-5. Repeat S3-3 and S3-4 until the encoding of the entire test set is completed to obtain a continuous compressed test set; S4. Transmit the compressed test data set obtained in S3 to the SRAM through the TDI pin of the JTAG port; S5. Access the SRAM, decode the compressed test data set through a decoder, enter the TDI buffer queue, and wait for the control of TMS in the TAP Controller.

2. The test data transmission optimization method based on the JTAG standard according to claim 1, wherein The records in the code table are arranged in ascending order according to the sequence length and grouped, and the group number K is also arranged in ascending order.

3. The test data transmission optimization method based on the JTAG standard according to claim 1, wherein The decoder includes a finite state machine FSM, a K-bit counter, a log2(K + 1)-bit counter, and an adder.

4. The test data transmission optimization method based on the JTAG standard according to claim 3, characterized in that, The step S5 includes the following sub-steps: S5-1. Initialize the count value cnt, where cnt = 0; S5-2. Read the compressed test set bit by bit from the SRAM, store the first compressed data read into the FSM, denoted as a, and discard it from its sequence; S5-3. Continue to read the compressed sequence bit by bit, and use the K-bit counter to count and increment the number of data bits by 1, and its value is denoted as cnt until 0 is read and the counting stops; S5-4. Write cnt into the log2(K + 1) counter for exponential operation, and its value is denoted as cod, and write it into the adder; S5-5. Read the data bit by bit, denoted as b-in, and decrement cnt until cnt = 0 and the K counter stops counting, and write b-in into the adder; S5-6. Perform a sum operation on cod and b-in in the adder, and write the sum value S into the K-bit counter for a decrement operation, and the FSM continuously outputs a ~a and S a's; ~a is the inverse of a; S5-7. Repeat S5-3 to S5-6 until all compressed sequences are decoded; S5-8. The decompressed sequence enters the TDI buffer queue and waits for the control of the TAP Controller.

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