A 1553B bus module and a data encryption method

Abstract

The present invention is applicable to the field of avionics bus communication and measurement and control, and in particular, relates to a 1553B bus module and a data encryption method, wherein the 1553B bus module includes a memory and an FPGA, wherein the memory is electrically connected to the FPGA, wherein the FPGA includes a 1553B Ipcore, a memory reading engine, a memory writing engine, a serial port receiving data engine, and a serial port sending data engine, wherein the memory reading engine and the memory writing engine are connected in parallel to the 1553B Ipcore and the serial port receiving data engine and the serial port sending data engine respectively. A 1553B bus module provided in an embodiment of the present invention has light weight, integration, and relative independence, can be used as an IP core to be attached to an on-chip bus protocol, has low power consumption, is relatively independent, can be migrated and reused, is conducive to the integration of multiple IP cores in the board, and can realize the realization of domestically produced related functional chips.

Description

Technical Field

[0001] The present invention belongs to the field of avionics bus communication and measurement and control, and particularly relates to a 1553B bus module and a data encryption method. Background Technique

[0002] The 1553B bus (MIL.STD.1553B) is full-named as the time-division command / response multiplex data bus inside the aircraft. Its concept is similar to that of a "local area network". Since the military data bus MIL-STD-1553 (USAF) standard was first announced in August 1973, the US military has launched improved versions many times, but the bus standard still mainly uses MIL-STD.1553B, and this standard has been in use until now. At present, the 1553B standard has been adopted by many countries and is widely used in aerospace fields such as aircraft, satellites, and the International Space Station, becoming the dominant bus standard in the aerospace field. China promulgated the corresponding national military standard in 1987 with reference to the MIL-STD-1553B standard.

[0003] In the traditional measurement and control application field, for products analyzing the 1553B bus, the composition method generally uses 1553B interface boards or circuits of various types of buses to be interconnected with a computer system or a computer module circuit, and access to the 1553B interface and resources is realized through the system bus or the local bus. The communication between the 1553B bus and the computer starts with the 1553B bus end initiating an interruption to the computer system. The system responds to the interruption and completes the read and write operations of the 1553B bus end. In the traditional technical implementation method, the data volume initiated to the computer system each time is often small, while the frequency of initiating interruptions is relatively high. Therefore, when the upper-layer application service involves relatively frequent read and write operations, it will have a greater impact on the computer system. To match higher-performance computing resources, it is necessary to improve the processing ability of the computer system, which increases the design difficulty of miniaturization and lightweight of the 1553B bus test products, and at the same time, it cannot guarantee the data analysis application in scenarios with relatively high real-time requirements. Summary of the Invention

[0004] The purpose of the embodiment of the present invention is to provide a 1553B bus module, aiming to solve the problems raised in the background technique.

[0005] The embodiment of the present invention is implemented as follows. A 1553B bus module, the 1553B bus module includes a memory and an FPGA. The memory is electrically connected to the FPGA. The FPGA includes a 1553B Ipcore, a memory reading engine, a memory writing engine, a serial port receiving data engine, and a serial port sending data engine. The memory reading engine and the memory writing engine are connected in parallel and then respectively connected to the 1553B Ipcore and the parallel-connected serial port receiving data engine and serial port sending data engine.

[0006] Preferably, the 1553B Ipcore communicates with an external 1553B bus and adopts the BM working mode to implement the functions of collecting and monitoring bus data.

[0007] Preferably, both the memory reading engine and the memory writing engine are connected to the 1553B Ipcore, and are used to read the data in the 1553B Ipcore, disassemble it, and then repackage the disassembled data according to a preset format and write it into the memory.

[0008] Preferably, the serial port data receiving engine is connected to both the memory reading engine and the memory writing engine at the same time, and is used to convert the control data received through the serial port into corresponding configuration operations to implement the setting of the 1553B data filtering format and the data access format.

[0009] Preferably, the serial port data sending engine is connected to both the memory reading engine and the memory writing engine at the same time, and is used to output the data in the set filtering format or encapsulation format and analyze the 1553B data.

[0010] Another object of the embodiment of the present invention is to provide a data encryption method, and the method includes:

[0011] Obtain the data to be encrypted, perform data segmentation on the data to be encrypted to obtain data blocks to be encrypted;

[0012] Record the time information formed by each data block to be encrypted to obtain encrypted time data;

[0013] Retrieve a corresponding data extraction scheme from a preset database according to the encrypted time data, and perform data extraction on the data to be encrypted according to the data extraction scheme to obtain random encrypted data;

[0014] Insert the random encrypted data into the data blocks to be encrypted according to a preset insertion order to obtain encrypted data, and the encrypted time data is sent separately.

[0015] Preferably, the step of obtaining the data to be encrypted, performing data segmentation on the data to be encrypted to obtain data blocks to be encrypted specifically includes:

[0016] Obtain the data to be encrypted, and determine the segmentation quantity according to the memory occupation size of the data to be encrypted;

[0017] Perform average segmentation on the data to be encrypted according to the segmentation quantity to obtain unordered data blocks;

[0018] Add a sequence code to the head of the unordered data blocks to obtain data blocks to be encrypted.

[0019] Preferably, the step of retrieving a corresponding data extraction scheme from a preset database according to the encryption time data, and extracting data to be encrypted according to the data extraction scheme to obtain random encrypted data specifically includes:

[0020] Parse the encrypted time data, extract the seconds and milliseconds, and obtain two sets of random numbers;

[0021] Retrieve the corresponding data extraction plan from the database according to the two sets of random numbers;

[0022] Parse the data extraction plan, complete data extraction according to the extraction location and data size, and obtain random encrypted data.

[0023] Preferably, the step of inserting the random encrypted data into the data block to be encrypted according to a preset insertion order to obtain the encrypted data specifically includes:

[0024] The data block to be encrypted is split according to a preset insertion order to obtain a plurality of split data blocks;

[0025] Add random encrypted data to the header of each split data block, and splice all split data blocks in the split order.

[0026] Preferably, the encrypted time data is encrypted before being sent.

[0027] A 1553B bus module provided by an embodiment of the present invention is lightweight, integrated and relatively independent, can be mounted on an on-chip bus protocol as an IP core, has low power consumption, is relatively independent, can be migrated and reused, is conducive to the integration of multiple IP cores on the board, and can realize the realization of domestically produced related functional chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 An architectural diagram of a 1553B bus module provided in an embodiment of the present invention;

[0029] Figure 2 An architecture diagram of an FPGA provided by an embodiment of the present invention;

[0030] Figure 3 The architecture diagram of the serial port data receiving engine provided by the embodiment of the present invention;

[0031] Figure 4 The architecture diagram of the serial port data transmission engine provided by the embodiment of the present invention;

[0032] Figure 5 An architectural diagram of a memory write engine provided by an embodiment of the present invention;

[0033] Figure 6 An architectural diagram of a memory reading engine provided by an embodiment of the present invention;

[0034] Figure 7 It is a flowchart of a data encryption method provided by an embodiment of the present invention;

[0035] Figure 8 It is a flowchart of the steps of obtaining data to be encrypted, performing data segmentation on the data to be encrypted, and obtaining data blocks to be encrypted provided by an embodiment of the present invention;

[0036] Figure 9 It is a flowchart of the steps of retrieving a corresponding data extraction scheme from a preset database according to encryption time data, and performing data extraction on the data to be encrypted according to the data extraction scheme to obtain random encrypted data provided by an embodiment of the present invention;

[0037] Figure 10 It is a flowchart of the steps of inserting the random encrypted data into the data blocks to be encrypted according to a preset insertion order to obtain encrypted data provided by an embodiment of the present invention.

[0038] In the drawings: 1. Memory; 2. FPGA; 3. 1553B Ipcore; 4. Memory reading engine; 5. Memory writing engine; 6. Serial port data receiving engine; 7. Serial port data sending engine. Detailed implementation manners

[0039] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0040] It can be understood that the terms "first", "second", etc. used in this application can be used to describe various elements in this text, but unless otherwise specified, these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of this application, the first xx script can be called the second xx script, and similarly, the second xx script can be called the first xx script.

[0041] As Figure 1 and 2 shown, it is an architecture diagram of a 1553B bus module provided by an embodiment of the present invention. The 1553B bus module includes a memory 1 and an FPGA 2, and the memory 1 and the FPGA 2 are connected.

[0042] The internal connection relationship of the FPGA 2 includes that the 1553B Ipcore 3 is connected to the memory reading engine 4 and the memory writing engine 5, and the memory reading engine 4 and the memory writing engine 5 are connected to the serial port data receiving engine 6 and the serial port data sending engine 7; As Figure 3 、 4, 5, and 6 are respectively the architecture diagrams of the serial port data receiving engine 6, the serial port data sending engine 7, the memory writing data engine 5, and the memory reading data engine 4.

[0043] In this embodiment, the memory 1 is connected to the FPGA 2 for data reading, writing, and storage of the FPGA 2.

[0044] In this embodiment, the 1553B Ipcore 3 is a third-party mature application and is not within the scope of protection of this patent.

[0045] The 1553B Ipcore 3 realizes communication with the external 1553B bus, adopts the BM working mode, and realizes the functions of bus data acquisition and monitoring.

[0046] In this embodiment, the memory reading data engine 4 and the memory writing data engine 5 in this invention are connected to the 1553B Ipcore 3, realizing the first reading of the data of the 1553B Ipcore 3, then disassembling and encapsulating it in a "settable" format, and finally writing it into the memory.

[0047] In this embodiment, the serial port data receiving engine 6 is connected to the memory reading data engine 4 and the memory writing data engine 5, realizing the conversion of control data received through the serial port into corresponding configuration operations to set the 1553B data filtering format and data access format.

[0048] In this embodiment, the serial port data sending engine 7 is connected to the memory reading data engine 4 and the memory writing data engine 5, realizing the output of the data in the set filtering format or encapsulation format, and realizing the function of 1553B data analysis.

[0049] This invention can realize the autonomous sending function of the underlying hardware FPGA:

[0050] 1> In the BC mode, it realizes the function of periodically sending data to a certain sub-address of the RT at a fixed time. The sending period, the interval between periodic sending and non-periodic sending messages, the frame count byte sequence number identifier, the checksum byte sequence number identifier, the check mode, and the stop periodic sending are all passed in from the API interface parameters.

[0051] 2> In the BC mode, it realizes polling data from the set sub-address of a certain rt periodically and obtaining the read-back data queue. The reading period, the rt address, all sub-addresses (which can be represented by the bit positions of a ushort), and the stop period are configured by the way of inputting through API parameters.

[0052] 3> In the RT mode, it realizes the API function of knowing when the BC reads the RT data, and returns a status and a time stamp function.

[0053] Supports five message reading application scenarios:

[0054] 1> Send a message (including command word + data word) to the RT in BC mode and obtain the RT status word;

[0055] 2> Send a message (only command word) to the RT in BC mode and read the status word + data word replied by the RT;

[0056] 3> Send the vector word mode code to the RT in BC mode and obtain the RT status word + data word

[0057] 4> In RT mode, the RT sets the vector word and sends a message to the BC or RT;

[0058] 5> In RT mode, the RT reads back a message from the BC or RT.

[0059] Implement the service functions that involve frequent read and write operations and will occupy computing resources and affect real-time performance through the FPGA (SOC) layer, thereby greatly reducing the demand for high-performance computing resources of the host computer, realizing the miniaturization and lightweight design of the 1553B bus test product, and meeting the data analysis applications in scenarios with high real-time requirements.

[0060] This invention patent design is composed of domestic FPGAs, and is divided into a 1553B data transceiver circuit, a data high-speed storage read-write circuit, and a serial port data transceiver circuit.

[0061] It is implemented by programming domestic FPGAs, and the programming language uses the general Verilog HDL hardware description language. This invention patent has the characteristics of lightweight, integration, and relative independence. It can be attached to the on-chip bus protocol as an IP core, with low power consumption, relative independence, migratability and reusability, which is conducive to integrating multiple IP cores on the board and can realize the implementation of domestic-related functional chips.

[0062] The FPGA chip adopts the domestic Fudan Micro FMQL45T900 solution to realize the intelligent 1553B bus communication technology.

[0063] As Figure 7 shown, in an embodiment of the present invention, a data encryption method is further provided, and the method includes:

[0064] S100, obtain the data to be encrypted, perform data segmentation on the data to be encrypted, and obtain the data blocks to be encrypted.

[0065] In this step, obtain the data to be encrypted. For the 1553B bus module, obtain the data that needs to be encrypted, and then split it into data blocks of the same size, that is, the data blocks to be encrypted, so that in the subsequent processing process, each data block to be encrypted can be processed.

[0066] S200, record the time information when each data block to be encrypted is formed to obtain encrypted time data.

[0067] In this step, record the time information when each data block to be encrypted is formed, that is, when splitting, the time of each data block to be encrypted is the encrypted time data. Since the formation times of different data blocks to be encrypted are different, respective encrypted time data will be obtained.

[0068] S300, retrieve the corresponding data extraction scheme from a preset database according to the encrypted time data, and perform data extraction on the data to be encrypted according to the data extraction scheme to obtain random encrypted data.

[0069] In this step, retrieve the corresponding data extraction scheme from a preset database according to the encrypted time data. A large number of data extraction schemes are stored in the database. Therefore, after obtaining the encrypted time data, the data extraction scheme corresponding to each data block to be encrypted can be obtained according to the recorded time information, thus achieving true randomness. The data extraction scheme records the position for data extraction and the size of the data to be extracted. For example, extract ten bytes of data from the middle of the data block to be encrypted to obtain random encrypted data.

[0070] S400, insert the random encrypted data into the data block to be encrypted according to the preset insertion order to obtain encrypted data, and send the encrypted time data separately.

[0071] In this step, insert the random encrypted data into the data block to be encrypted according to the preset insertion order. At this time, all data blocks to be encrypted are changed, and then all data blocks to be encrypted are re - spliced to obtain encrypted data. The encrypted time data is sent separately, which is equivalent to the decryption key and thus needs to be sent separately.

[0072] As Figure 8 shown, as a preferred embodiment of the present invention, the steps of obtaining the data to be encrypted and performing data splitting on the data to be encrypted to obtain data blocks to be encrypted specifically include:

[0073] S101, obtain the data to be encrypted and determine the splitting quantity according to the memory occupancy of the data to be encrypted.

[0074] In this step, obtain the data to be encrypted, calculate the memory occupancy of the data to be encrypted, and determine the splitting quantity according to the interval where its memory occupancy is located. For example, if the data to be encrypted is 1Mb, the splitting quantity is 3, and it is divided into three parts.

[0075] S102, perform average splitting on the data to be encrypted according to the splitting quantity to obtain unordered data blocks.

[0076] S103. Add sequential encoding to the head of the unordered data block to obtain the data block to be encrypted.

[0077] In this step, the data to be encrypted is evenly divided according to the number of divisions. After being evenly divided, the data to be encrypted becomes three unordered data blocks. To facilitate subsequent splicing, sequential encoding is added to the head of each unordered data block to obtain the data block to be encrypted.

[0078] As Figure 9 shown, as a preferred embodiment of the present invention, the step of retrieving the corresponding data extraction scheme from the preset database according to the encryption time data and extracting the data to be encrypted according to the data extraction scheme to obtain the random encrypted data specifically includes:

[0079] S301. Analyze the encryption time data, extract the seconds and milliseconds to obtain two sets of random numbers.

[0080] In this step, analyze the encryption time data, extract the contained time information to obtain the corresponding seconds and milliseconds, where the seconds are used as the first set of random numbers and the milliseconds are used as the second set of random numbers.

[0081] S302. Retrieve the corresponding data extraction scheme from the database according to the two sets of random numbers.

[0082] S303. Analyze the data extraction scheme, complete the data extraction according to the extracted position and data size to obtain the random encrypted data.

[0083] In this step, the data extraction schemes are stored in partitions in the database. It is divided into 60 large partitions, and then each large partition is divided into 10 small partitions. One data extraction scheme is stored in each small partition. Thus, the large partition is determined according to the first set of random numbers, and the small partition is determined according to the second set of random numbers, so as to determine the data extraction scheme, and then the data extraction is performed according to the content in the data extraction scheme.

[0084] As Figure 10 shown, as a preferred embodiment of the present invention, the step of inserting the random encrypted data into the data block to be encrypted in the preset insertion order to obtain the encrypted data specifically includes:

[0085] S401. Split the data block to be encrypted in the preset insertion order to obtain multiple split data blocks.

[0086] S402. Add the random encrypted data to the head of each split data block and splice all the split data blocks in the split order.

[0087] In this step, the data block to be encrypted is split to obtain split data blocks, and then random encrypted data is added to the head of each split data block, so as to disrupt the purpose of the function to be encrypted. All the split data blocks are concatenated, and finally all the data blocks to be encrypted are concatenated to obtain the encrypted data; before the encrypted time data is sent, it is encrypted.

[0088] It should be understood that although the steps in the flowcharts of the embodiments of the present invention are shown in sequence according to the arrows, these steps do not necessarily have to be executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in each embodiment may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily have to be executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages does not necessarily have to be sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0089] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0090] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0091] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several variations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

[0092] The above is only the preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A 1553B bus module, characterized in that, The 1553B bus module includes a memory and an FPGA. The memory is electrically connected to the FPGA. The FPGA includes a 1553B Ipcore, a memory read engine, a memory write engine, a serial port data receiving engine, and a serial port data sending engine. The memory read engine and the memory write engine are connected in parallel and then respectively connected to the 1553B Ipcore and the parallel-connected serial port data receiving engine and serial port data sending engine. Both the memory read engine and the memory write engine are connected to the 1553B Ipcore, and are used to read the data in the 1553B Ipcore, disassemble it, and then repackage the disassembled data according to a preset format and write it into the memory. The serial port data receiving engine is simultaneously connected to the memory read engine and the memory write engine, and is used to convert the control data received through the serial port into corresponding configuration operations to implement the setting of the 1553B data filtering format and the data access format. The serial port data sending engine is simultaneously connected to the memory read engine and the memory write engine, and is used to output the data in the set filtering format or packaging format and analyze the 1553B data. The 1553B bus module further includes a data encryption processing module, which is used to encrypt the obtained data to be encrypted. The encryption method includes: obtaining the data to be encrypted, performing data segmentation on the data to be encrypted to obtain data blocks to be encrypted; recording the time information formed by each data block to be encrypted to obtain encrypted time data; retrieving a corresponding data extraction scheme from a preset database according to the encrypted time data, and performing data extraction on the data to be encrypted according to the data extraction scheme to obtain random encrypted data; inserting the random encrypted data into the data blocks to be encrypted in a preset insertion order to obtain the encrypted data, and the encrypted time data is sent separately.

2. The 1553B bus module according to claim 1, wherein The 1553B Ipcore communicates with an external 1553B bus, and adopts the BM working mode to implement the functions of bus data acquisition and monitoring.

3. The 1553B bus module according to claim 1, characterized in that The step of obtaining the data to be encrypted and performing data segmentation on the data to be encrypted to obtain data blocks to be encrypted specifically includes: Obtaining the data to be encrypted and determining the segmentation quantity according to the memory occupancy of the data to be encrypted; Performing average segmentation on the data to be encrypted according to the segmentation quantity to obtain unordered data blocks; Adding a sequence code to the head of the unordered data blocks to obtain data blocks to be encrypted.

4. The 1553B bus module according to claim 1, characterized in that, The step of retrieving a corresponding data extraction scheme from a preset database according to the encrypted time data and performing data extraction on the data to be encrypted according to the data extraction scheme to obtain random encrypted data specifically includes: Parsing the encrypted time data, extracting the seconds and milliseconds to obtain two sets of random numbers; Retrieving the corresponding data extraction scheme from the database according to the two sets of random numbers; Parsing the data extraction scheme and completing data extraction according to the extracted position and data size to obtain random encrypted data.

5. The 1553B bus module according to claim 1, wherein The step of inserting the random encrypted data into the data blocks to be encrypted in a preset insertion order to obtain the encrypted data specifically includes: Split the encrypted data blocks according to the preset insertion order to obtain multiple split data blocks; Add random encrypted data to the head of each split data block and splice all the split data blocks according to the split order.

6. The 1553B bus module according to claim 1, characterized in that, Before sending the encrypted time data, encrypt it.

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