Storage device, memory system, and method for programming operation of storage device

Abstract

The present application provides a storage device, a memory system, and a programming operation method for a storage device. The storage device includes a plurality of memory strings, each memory string including sub-memory strings divided into multiple levels. Each sub-memory string includes a plurality of memory cells, an SSG transistor, and a DSG transistor. The method includes: in a pre-charge stage, applying a turn-on voltage to the DSG transistor, the memory cell, and the SSG transistor located in a first level among the multiple levels; after applying the turn-on voltage, applying a pre-charge voltage across both ends of each memory string; and in a programming stage, while applying a drain select voltage to the DSG transistor included in the memory string to be programmed, turning off the DSG transistors included in the remaining memory strings.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a memory device, a memory system, and a method for programming a memory device. Background Art

[0002] Recently, memory devices with vertically stacked memory cells have been widely used in electronic devices, and the storage capacity can be increased by increasing the number of stacked layers of memory cells. Memory devices with an increasing number of stacked layers can be developed to include multiple decks. For some operations of the memory device, the increase in the number of decks causes the channel current to continuously decrease. Generally, electron-rich conductive plugs can be provided between multiple decks, and the conductive plugs can electrically connect the channels of each deck, thereby improving the problem of decreasing channel current by compensating for charges.

[0003] It should be understood that this background art section is intended to partially provide useful background for understanding the technology. However, these contents are not necessarily known or understood by those skilled in the art before the filing date of this application. Summary of the Invention

[0004] One aspect of this application provides a method for programming a memory device. The memory device includes: a plurality of memory strings, each of the memory strings including a sub-memory string divided into multiple decks, each of the sub-memory strings including a plurality of memory cells, a source select gate transistor (SSG transistor), and a drain select gate transistor (DSG transistor). The method includes: in a pre-charge stage, applying a turn-on voltage to the DSG transistor, the memory cell, and the SSG transistor located in a first deck among the multiple decks; after applying the turn-on voltage, applying a pre-charge voltage across both ends of each of the memory strings; and in a programming stage, while applying a drain select voltage to the DSG transistor included in the memory string to be programmed, turning off the DSG transistors included in the remaining memory strings.

[0005] In one embodiment of this application, the pre-charge voltage is applied after the level of the turn-on voltage climbs to a peak level.

[0006] In one embodiment of this application, after the level of the turn-on voltage climbs to a peak level, the DSG transistor, the memory cell, and the SSG transistor located in the first deck are set to a floating state.

[0007] In one embodiment of this application, while applying the turn-on voltage, a ground voltage is applied to the DSG transistor, the memory cell, and the SSG transistor located in a second deck among the multiple decks.

[0008] In one embodiment of the present application, the method further includes: during the programming phase, applying a programming voltage to the memory cells to be programmed in the second level of the multiple levels, and applying a first pass voltage to the remaining memory cells.

[0009] In one embodiment of the present application, the method further includes: during the programming phase, applying a ground voltage to the SSG transistors in the second level of the multiple levels, and applying a second pass voltage to the SSG transistors in the first level.

[0010] In one embodiment of the present application, the method further includes: during the programming phase, applying a ground voltage to both ends of the memory string to be programmed, and applying a drain voltage to both ends of the remaining memory strings.

[0011] Another aspect of the present application provides a memory device, including: a plurality of memory strings, each of the memory strings including a sub-memory string divided into multiple levels, each of the sub-memory strings including a plurality of memory cells, a source select gate (SSG) transistor, and a drain select gate (DSG) transistor; and a peripheral circuit, coupled to the memory strings and configured to: during a pre-charge phase, apply a conduction voltage to the DSG transistors, memory cells, and SSG transistors in the first level of the multiple levels; after applying the conduction voltage, apply a pre-charge voltage via both ends of each memory string; and during a programming phase, turn off the DSG transistors included in the remaining memory strings while applying a drain select voltage to the DSG transistors included in the memory string to be programmed.

[0012] In one embodiment of the present application, the memory device further includes: a stacked layer, including sub-stacked layers located in each level, the sub-stacked layers including alternately stacked gate layers and dielectric layers, and the sub-memory strings passing through the sub-stacked layers corresponding to each level; conductive plugs, located between the respective sub-stacked layers and electrically connecting the respective sub-memory strings included in the same memory string; and a top select gate cut line, passing through the gate layers corresponding to the DSG transistors in each level and located between adjacent sub-memory strings.

[0013] In one embodiment of the present application, the peripheral circuit is further configured to: after the level of the conduction voltage climbs to a peak level, apply the pre-charge voltage.

[0014] In one embodiment of the present application, the peripheral circuit is further configured to: after the level of the conduction voltage climbs to a peak level, set the DSG transistors, memory cells, and SSG transistors in the first level to a floating state.

[0015] In one embodiment of the present application, the peripheral circuit is further configured to: while applying the conduction voltage, apply a ground voltage to the DSG transistor, the memory cell, and the SSG transistor located in the second level among the multiple levels.

[0016] In one embodiment of the present application, the peripheral circuit is further configured to: in the programming stage, apply a programming voltage to the memory cell to be programmed located in the second level among the multiple levels, and apply a first pass voltage to the remaining memory cells.

[0017] In one embodiment of the present application, the peripheral circuit is further configured to: in the programming stage, apply a ground voltage to the SSG transistor located in the second level among the multiple levels, and apply a second pass voltage to the SSG transistor located in the first level.

[0018] In one embodiment of the present application, the peripheral circuit is further configured to: in the programming stage, apply a ground voltage to both ends of the memory string to be programmed, and apply a drain voltage to both ends of the remaining memory strings.

[0019] Another aspect of the present application provides a memory system, including: a storage device configured to store data, and including: a plurality of memory strings, each of the memory strings including sub-memory strings divided into multiple levels, each of the sub-memory strings including a plurality of memory cells, a source select gate (SSG) transistor, and a drain select gate (DSG) transistor; and a peripheral circuit coupled to the memory strings and configured to: in a pre-charge stage, apply a conduction voltage to the DSG transistor, the memory cell, and the SSG transistor located in the first level among the multiple levels; after applying the conduction voltage, apply a pre-charge voltage through both ends of each of the memory strings; and in the programming stage, turn off the DSG transistors included in the remaining memory strings while applying a drain select voltage to the DSG transistors included in the memory string to be programmed; and a memory controller coupled to the storage device and configured to control the storage device.

[0020] In one embodiment of the present application, the storage device further includes: a stacked layer including sub-stacked layers located in each level, the sub-stacked layers including alternately stacked gate layers and dielectric layers, and the sub-memory strings passing through the sub-stacked layers corresponding to each level; conductive plugs located between the respective sub-stacked layers and electrically connecting the respective sub-memory strings included in the same memory string; and a top select gate tangent passing through the gate layers corresponding to the DSG transistors in each level and located between adjacent sub-memory strings.

[0021] In one embodiment of the present application, the memory system includes: a solid state drive or a memory card. Description of the Drawings

[0022] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non - limiting embodiments read in conjunction with the accompanying drawings. In the drawings:

[0023] Figure 1 FIG. is a block diagram of an exemplary system including a memory according to some embodiments of the present application;

[0024] Figure 2 FIG. is a schematic diagram of an exemplary memory card having a memory according to some embodiments of the present application;

[0025] Figure 3 FIG. is a schematic diagram of an exemplary solid - state drive (SSD) having a memory according to some embodiments of the present application;

[0026] Figure 4 FIG. is a schematic diagram of a memory device including a memory array and peripheral circuits according to some embodiments of the present application;

[0027] Figure 5 FIG. is a partial top - down view of a memory array included in a memory device according to some embodiments of the present application;

[0028] Figure 6 FIG. is Figure 5 a partial cross - sectional view along line A - A in FIG.;

[0029] Figure 7 FIG. is a partial equivalent circuit diagram of a memory array included in a memory device according to some embodiments of the present application;

[0030] Figure 8 FIG. is a schematic flow chart of a programming operation method of a memory device according to some embodiments of the present application;

[0031] Figure 9 FIG. is a voltage waveform timing diagram of a programming operation performed on a top stacked layer in a programming operation method of a memory device according to some embodiments of the present application;

[0032] Figure 10 FIG. is a voltage waveform timing diagram of a programming operation performed on a middle stacked layer in a programming operation method of a memory device according to some embodiments of the present application.

[0033] Figure 11 FIG. is a voltage waveform timing diagram of a programming operation performed on a bottom stacked layer in a programming operation method of a memory device according to some embodiments of the present application. Detailed Description of the Embodiments

[0034] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0035] Note that references in the specification to "one embodiment", "some embodiments", "an example", "some examples", "exemplarily", etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Moreover, these phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not explicitly described, implementing such feature, structure, or characteristic in connection with other embodiments will be within the knowledge of those skilled in the relevant art.

[0036] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey a singular usage or a plural usage, at least in part depending on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors and can alternatively allow for the existence of additional factors that are not necessarily explicitly described, again at least in part depending on the context.

[0037] It should be readily understood that the meanings of "on", "above", and "over" in the present disclosure should be interpreted in the broadest possible manner such that "on" not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above" or "over" not only means the meaning of "above" or "over" something, but can also include the meaning of "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0038] In addition, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. are used herein for convenience of description to describe the relationship of one element or feature to another (one or more) element or (one or more) feature as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein can be interpreted similarly.

[0039] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire upper or lower structure, or may have a scope less than that of the lower or upper structure. In addition, the layer may be a region of a continuous structure that is uniform or non-uniform, and its thickness is less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it, and / or below it. A layer may include multiple layers.

[0040] In the drawings, for ease of illustration, the thickness, dimensions, and shape of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. For example, as used herein, terms such as "substantially", "about", and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0041] It should also be understood that the terms "comprises", "comprising", "has", "including", and / or "containing", when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of listed features, rather than individual elements in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplarily" is intended to refer to an example or illustration.

[0042] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0043] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments may be combined with each other. In addition, unless clearly defined or in conflict with the context, the specific steps included in the methods described in this application do not have to be limited to the recorded order, but may be executed in any order or executed in parallel. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0044] Figure 1FIG. 0 shows a block diagram of an exemplary system 400 including a memory according to some embodiments of the present application. System 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As Figure 1 shown, system 400 may include a host 408 and a memory system 402 having one or more memories 404 and a memory controller 406. Host 408 may be a processor of the electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). Host 408 may be configured to send or receive data stored in memory 404.

[0045] According to some embodiments, the memory controller 406 is coupled to the memory 404 and the host 408, and is configured to control the memory 404. The memory controller 406 can manage the data stored in the memory 404 and communicate with the host 408. In some embodiments, the memory controller 406 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 406 is designed to operate in a high-duty-cycle environment such as a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), which is used as data storage for mobile devices (such as smart phones, tablets, laptop computers, etc.) and enterprise storage arrays. The memory controller 406 can be configured to control the operations of the memory 404, such as read, erase, and program operations. The memory controller 406 can also be configured to manage various functions regarding the data stored in or to be stored in the memory 404, including bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to process an Error Correction Code (ECC) for data read from or written to the memory 404. Any other suitable functions can also be performed by the memory controller 406, for example, formatting the memory 404. The memory controller 406 can communicate with external devices (e.g., the host 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the High-Speed PCI (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the FireWire protocol, etc.

[0046] The memory controller 406 and one or more memories 404 can be integrated into various types of storage devices, for example, including in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 402 can be implemented as different types of end-user electronic products and packaged into the end-user electronic products. In Figure 2In one example shown, the memory controller 406 and a single memory 404 can be integrated into a memory card 502. The memory card 502 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 502 can further include a memory card connector 504 that electrically couples the memory card 502 to a host (e.g., the host 408 in Figure 1 ). In another example shown in Figure 3 , the memory controller 406 and multiple memories 404 can be integrated into an SSD 506. The SSD 506 can further include an SSD connector 508 that electrically couples the SSD 506 to a host (e.g., the host 408 in Figure 1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 506 is greater than that of the memory card 502.

[0047] Figure 4 A block diagram of a storage device 100 according to some embodiments of the present application is shown. The storage device 100 can be an example of the memory 404 shown in Figure 1 . The memory 100 can be, for example, a 3D NAND memory. As shown in Figure 4 , the storage device 100 includes a storage array 102 and a peripheral circuit 101 coupled together. In some embodiments, the storage array 102 and the peripheral circuit 101 can be arranged on the same chip. In some other embodiments, the storage array 102 can be arranged on an array chip, and the peripheral circuit 101 can be arranged on a different chip (e.g., implemented using complementary metal oxide semiconductor (CMOS) technology and referred to as a CMOS chip). The array chip and the CMOS chip can be electrically coupled together through a process such as bonding. In some embodiments, the storage device 100 is an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0048] Optionally, the storage device 100 can be configured to store data in the storage array 102 and perform operations in response to received commands (CMDs). In some embodiments, the storage device 100 can receive write commands, read commands, erase commands, etc., and can perform operations accordingly.

[0049] Generally, the storage array 102 can include one or more storage planes 160, and each storage plane in the storage plane 160 can include a plurality of storage blocks (e.g., block-1 to block-N shown in Figure 4 ). Each storage block can further include a plurality of vertically stacked levels (e.g.,Figure 4 (levels 1 to M included in block-1 as shown). In some examples, concurrent operations may occur at different storage planes 160. It should be understood that Figure 4 block-2 to block-N as shown may have multiple levels similar to or the same as those of block-1, which is not limited in this application.

[0050] In some embodiments, the storage array 102 may be a flash memory array, for example, and may be implemented using 3D NAND flash technology. In some embodiments, the peripheral circuit 101 includes a row decoder circuit 110, a page buffer circuit 120, a data input / output (I / O) circuit 130, a voltage generator 140, and a control circuit 150 that are coupled together. The row decoder circuit 110 may receive an address referred to as a row address (R-ADDR), generate a word line (WL) signal and select line signals (such as a drain select line (DSL) signal, a source select line (SSL) signal, etc.) based on the row address, and provide the WL signal and the select line signals to the storage array 102. Further, during a programming operation, the row decoder circuit 110 provided in this application may provide appropriate WL signals and select signals.

[0051] The page buffer circuit 120 is coupled to the bit lines (BL) of the storage array 102 and is configured to buffer data during read and write operations. The data I / O circuit 130 is coupled to the page buffer circuit 120 via a data line DL. In one example (e.g., during a write operation), the data I / O circuit 130 is configured to receive data from an external circuit of the storage device 100 and provide the received data to the storage array 102 via the page buffer circuit 120.

[0052] The voltage generator 140 is configured to generate appropriate voltages for the proper operation of the storage device 100. In some embodiments of this application, the voltage generator 140 may generate various programming voltages, various turn-on voltages, various pass voltages, precharge voltages, drain select voltages, ground voltages, etc. suitable for programming operations. For example, during a programming operation, a first turn-on voltage is provided to the row decoder 110 to drive the WL. In some examples, during a programming operation, the voltage generator 140 may provide a precharge voltage to the page buffer circuit 120 to drive the bit lines (BL). In some examples, the precharge voltage may also be provided to the Array Common Source (ACS) through the source line.

[0053] The control circuit 150 is configured to receive a command (CMD) and an address (ADDR), and based on the command and the address, provide control signals to circuits such as the row decoder circuit 110, the page buffer circuit 120, the data I / O circuit 130, the voltage generator 140, etc. For example, the control circuit 150 may generate a row address R-ADDR and a column address C-ADDR based on the address ADDR, and provide the row address R-ADDR to the row decoder 110, and provide the column address to the data I / O circuit 130. In another embodiment, the control circuit 150 may control the voltage generator 140 to generate an appropriate voltage based on the received CMD. The control circuit 150 may coordinate other circuits to provide signals to the memory array 102 at an appropriate time and with an appropriate voltage.

[0054] As Figure 5 shown, in some examples, some types of gate line gap structures (not shown) may divide the memory array 102 into multiple memory blocks (e.g., Figure 4 the shown block-1 to block-n). As Figure 6 shown, in some examples, the memory blocks of the memory array 102 may include multiple stacked layers

[0055] , and each stacked layer may include sub-stacked layers located at respective levels (e.g., the top sub-stacked layer 452 at the top level, the middle sub-stacked layer 454 at the middle level, and the bottom sub-stacked layer 450 at the bottom level. Optionally, the bottom sub-stacked layer 450 may be located on the semiconductor layer 401. Exemplarily, the sub-stacked layers at each level include alternately stacked gate layers 415 and dielectric layers 417. Optionally, the gate layer 415 and the dielectric layer 417 may be alternately stacked on the semiconductor layer 401. Optionally, the gate layer 415 includes a conductive material such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. Optionally, the semiconductor layer 401 may include silicon (e.g., single-crystalline silicon, polysilicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0056] Returning to Figure 5 , optionally, some other types of gate line gap structures 106 may divide each memory block into multiple memory fingers 105, and the memory fingers 105 may include multiple channel structures 412 passing through the sub-stacked layers at respective levels and dummy channel structures 413. The dummy channel structures 413 may have the same configuration as the channel structures 412 and are formed by the same process. During the operation of the memory device 100, the dummy channel structures 413 will not be electrically connected.

[0057] Continuing to refer to Figure 6, the channel structure 412 can extend vertically or substantially vertically through the gate layer 415 and the dielectric layer 417 and extend into the semiconductor layer 401. In some examples, the channel structure 412 includes a barrier layer 422, a storage layer 424, a tunneling layer 426, and a channel layer 420 arranged in sequence from the outside to the inside. Optionally, the channel layer 420 may include polysilicon. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may include silicon oxide, silicon oxynitride, a high-k (high dielectric constant) dielectric, or any combination thereof. Optionally, the channel layer 420 is, for example, lightly P-doped or intrinsically doped.

[0058] Referring again to Figure 6 , a memory cell 340 may be formed at the intersection of the channel structure 412 and the gate layer 415. A plurality of memory cells 340 are connected in series in the direction of the channel structure 412 to form a memory string (such as memory string 212 and memory string 213), and the memory string may be, for example, a NAND string. Optionally, a dummy memory cell may be formed at the intersection of the dummy channel structure 413 and the gate layer 415, and the dummy memory cells are connected in series to form a dummy memory string 214.

[0059] Exemplarily, the memory block may further include a top select gate cut (TSG-CUT) 335. Optionally, the dummy channel structure 413 may be used as the process landing point for the TSG-CUT 335, and the TSG-CUT 335 may, for example, pass through a part of the dummy channel structure 413.

[0060] Referring again to Figure 6 , in some examples, the TSG-CUT 335 may, for example, include: a CUT passing through some of the gate layer 415 and the dielectric layer 417 away from the top of the semiconductor layer 401 of the top sub-stack layer 452 335-2 , a CUT passing through some of the gate layer 415 and the dielectric layer 417 away from the top of the semiconductor layer 401 of the middle sub-stack layer 454 335-3 and a CUT passing through some of the gate layer 415 and the dielectric layer 417 away from the top of the semiconductor layer 401 of the bottom sub-stack layer 450 335-1 .

[0061] As Figure 6As shown, in some examples where the storage capacity is increased by increasing the number of stacked layers of the gate layer 415 and the dielectric layer 417, the problem of the current flowing through the channel layer 420 decreasing becomes particularly prominent. Generally, conductive plugs (such as conductive plugs 460, 470, 480, 490) electrically connected to the channel layer (such as channel layer 420) are provided between each sub-stacked layer (for example, between the top sub-stacked layer 452 and the middle sub-stacked layer 454, and between the middle sub-stacked layer 454 and the bottom sub-stacked layer 450). Optionally, the above-mentioned conductive plugs can be heavily N-doped, so that during the programming operation of the memory device 100, the conductive plugs can act as an "electron reservoir" to compensate for the charge flowing through the channel layer 420, thereby improving the problem of current reduction.

[0062] However, although heavily N-doping the above-mentioned conductive plugs can increase the channel current, for a programmed-inhibited memory string (Inhibit String, such as memory string 213), when a programming voltage is applied to the word line (WL) corresponding to the memory cell 340 to be programmed ( Figure 7 ) included in the selected memory string (SelectedString, such as memory string 212), the electrons in the conductive plugs 480 and 490 will move along the channel of the memory string 213 towards a memory cell with a higher potential (not shown), so that the channel potential of the memory string 213 is difficult to effectively rise, causing a programming interference problem.

[0063] In some embodiments, the memory strings 212 and 213 further include electrode plugs 416 at their respective drain terminals. The electrode plugs 416 are, for example, heavily N-doped. Optionally, the electrode plugs 416 can be electrically connected to the channel layer 420 of the memory strings 212 and 213. For example, the electrode plugs 416 can be electrically connected to the channel layer 420 of the sub-memory strings 212-2 and 213-2. Optionally, the electrode plugs 416 can be part of the drain 341 of the memory string 212 and the drain of the memory string 213, and the electrode plugs 416 can be used as the landing point where the BL can be coupled to the drain terminals of each memory string.

[0064] Continuing to refer to Figure 6 , in some examples, the semiconductor layer 401 can be heavily N-doped, so that the semiconductor layer 401 forms an N-doped well region (NW). The channel layer 420 can be in direct contact with the NW. Therefore, the NW can act as an array common source (Array Common Source, ACS), as Figure 7 shown, the ACS 464 can be led out from the source line for electrical signal interaction.

[0065] As Figure 6 and Figure 7As shown, taking the storage string 212 as an example, the storage string 212 further includes sub - storage strings located in each level. The sub - storage strings pass through the sub - stack layers corresponding to each level. For example, the sub - storage string 212 - 2 passes through the top sub - stack layer 452, the sub - storage string 212 - 3 passes through the middle sub - stack layer 454, and the sub - storage string 212 - 1 passes through the bottom sub - stack layer 450. Optionally, as Figure 6 shown, the channels of the memory cells (e.g., the channel layer 420) that make up the same sub - storage string are physically connected in a direction perpendicular or substantially perpendicular to the semiconductor layer 401. The conductive plug 460 can be used to electrically connect the channel layers 420 of the sub - storage strings 212 - 2 and 212 - 3, and the conductive plug 470 can be used to electrically connect the channel layers 420 of the sub - storage strings 212 - 3 and 212 - 1.

[0066] Similarly, the storage string 213 can include sub - storage strings 213 - 2, 213 - 3, and 213 - 1 corresponding to each level.

[0067] Exemplarily, in combination with Figure 7 , during the storage operation of the storage device 100, the gate layer 415 that the CUT 335-2 passes through can serve as the top - select gate (TSG) 334 - 2 of the sub - storage string 212 - 2. The TSG 334 - 2 can be led out by the DSL to interact with the peripheral circuit 101 for electrical signals.

[0068] Similarly, in combination with Figure 7 , the gate layer 415 that the CUT 335-3 passes through can serve as the TSG 334 - 3 of the sub - storage string 212 - 3, and the gate layer 415 that the CUT 335-1 passes through can serve as the TSG 334 - 1 of the sub - storage string 212 - 1.

[0069] In some examples of the present application, the TSG - CUT located in each level can classify and partition the gate layers 415 of each level, so that inter - level programming operations can be achieved through the TSGs of each level.

[0070] Exemplarily, in combination with Figure 7 , some gate layers 415 located at the end near the semiconductor layer 401 in the top sub - stack layer 452 can serve as the bottom - select gate (BSG) 332 - 2 of the sub - storage string 212 - 2. The BSGs 332 - 2 located in the same row can be led out by the source - select line SSL to interact for electrical signals. Similarly, as Figure 7As shown, the sub - storage string 212 - 3 may include the corresponding BSG 332 - 3, and the sub - storage string 212 - 1 may include the corresponding BSG 332 - 1. Optionally, each sub - storage string as described above may include a drain DSG transistor (e.g., a top - select gate transistor) and a source - select gate SSG transistor (e.g., a bottom - select gate transistor). The top - select gate transistors of each sub - storage string may be controlled by the corresponding TSG. Similarly, the bottom - select gate transistors of each sub - storage string may be controlled by the corresponding BSG. Optionally, the TSG - CUT 335 located at each level as described above may pass through the gate layer 415 corresponding to the DSG transistor of the corresponding level. Therefore, the TSG - CUT 335 can not only electrically separate adjacent storage strings (e.g., the storage string 212 to be programmed and the remaining storage string 213), but also separate adjacent sub - storage strings within adjacent storage strings, so that the DSGs of different sub - storage strings can be controlled independently of each other.

[0071] In some examples, some gate layers 415 between the TSG and the BSG located at each level may serve as control gates 333. The storage cells 340 as described above may be formed at the intersection of the control gate 333 and the channel structure 412. The control gates located in the same row may be led out through the WL to perform operations such as reading and erasing on the above - mentioned storage cells. Optionally, the sub - storage string 212 - 2 may include the storage cell 340 - 2, the sub - storage string 212 - 3 may include the storage cell 340 - 3, and the sub - storage string 212 - 1 may include the storage cell 340 - 1. It should be understood that the "row" described above may have substantially the same height with respect to the semiconductor layer 401( Figure 6 )

[0072] In some embodiments, each storage cell 460 is a single - level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some embodiments, each storage cell 460 is a multi - level cell (MLC) that is capable of storing more than a single bit of data in more than four memory states. For example, the MLC may store two bits per cell, three bits per cell (also known as a triple - level cell (TLC)), or four bits per cell (also known as a quad - level cell (QLC)).

[0073] In some examples, each sub - storage string (e.g., sub - storage string 212 - 2, sub - storage string 212 - 3, sub - storage string 212 - 1) may also include dummy storage cells (not shown) for process and electrical buffering. These dummy storage cells may be located between the respective storage cells (e.g., storage cell 340 - 2, storage cell 340 - 3, storage cell 340 - 1) described above. In some options, these dummy storage cells may be located in a partial area near the top select gate transistor. In other options, these dummy storage cells may also be located in another partial area near the bottom select gate transistor.

[0074] In the memory device 100, the storage cells in each row of each level (e.g., the storage cells in the same row as storage cell 340) may be connected to the same WL (not shown), and multiple sub - storage strings in each column (e.g., Figure 7 the sub - storage strings 212 - 1, 212 - 2, and 212 - 3 shown) may be connected to the same BL (not shown). Each WL may correspond to a page, and a memory block is composed of multiple pages (e.g., Figure 4 the blocks - 1 to blocks - n shown). Further, in the memory device 100 with multiple levels, each level can be processed separately for efficient reading, writing, and erasing. For example, each level in the memory device 100 can perform an erase operation independently of other levels. In addition, read and write operations can also be performed on the pages including the storage cells sharing the same WL.

[0075] It should be noted that the description of the memory device 100 with a stacked layer including three sub - stacked layers above is only an example. In other examples, the stacked layer may include two sub - stacked layers or more than three sub - stacked layers, and the present application does not limit this.

[0076] In other examples, the memory device 100 also includes the peripheral circuit described above (e.g., Figure 4 the peripheral circuit 101 shown). The peripheral circuit 101 can be used, for example, to receive commands such as a turn - on command, a pre - charge command, and a programming command.

[0077] Although an exemplary structure of the memory device 100 is described herein, it can be understood that one or more features can be omitted, substituted, or added to the structure of the memory device 100. Additionally, the exemplified layers and their materials are only exemplary.

[0078] Figure 8 A programming operation method 300 for the above - mentioned memory device 100 according to some embodiments of the present application is shown. The programming operation method 300 will be described in detail below in combination with Figures 6 - 11 and will be described in detail.

[0079] In some examples, the programming operation includes a pre-charge phase and a programming phase after the pre-charge phase. During the programming or erasing of selected memory cells, charges will inevitably be generated in the channels of the remaining memory cells, resulting in a programming interference phenomenon. Usually, before the programming operation proceeds to the programming phase, for example, before applying a programming voltage to the memory cell to be programmed, a pre-charge phase can be executed first. For example, the channel can be pre-charged to reduce the charge density in the channel. The pre-charge method includes, for example: providing a large positive bias voltage through the bit line or the source terminal to attract electrons in the channel to move outwards, so as to reduce the charge density in the channel and thus reduce the programming interference phenomenon.

[0080] As Figure 8 shown, the programming operation method 300 starts at operation S301, where, in the pre-charge phase, a conduction voltage is applied to the DSG transistor, the memory cell, and the SSG transistor in the first level among multiple levels.

[0081] In some examples, the sub-memory string where the memory cell to be programmed (for example, Figure 7 the memory cell 340 shown) is located is the sub-memory string to be programmed, and the memory string where the memory cell to be programmed (the selected memory cell) is located is the memory string to be programmed. Similarly, the level where the memory cell to be programmed is located is the level to be programmed (for example, the second level described herein), and the remaining levels can be the first level.

[0082] Taking the programming operation performed on the top level where the top sub-stack layer 452 shown in Figure 6 is located as an example, the top level can be the second level, while the middle level where the middle sub-stack layer 454 is located and the bottom level where the bottom sub-stack layer 450 is located are the first levels. Among them, the sub-memory string 212-2 where the memory cell 340 to be programmed is located is the sub-memory string to be programmed, and the memory string 212 where the memory cell 340 to be programmed is located is the memory string to be programmed. In an example where the stack layer includes sub-stack layers of multiple levels, the programming operation can be performed by sequentially selecting the sub-stack layers of the level to be programmed, so as to achieve level programming.

[0083] As Figure 9 shown, t0 to t4 are the pre-charge phase, where t0 to t1 are the pre-conduction phase. At time t0, the word lines (for example, the unselected word line Usel_WL) corresponding to the memory cells included in the sub-memory strings of the middle level and the bottom level (for example, sub-memory strings 212-3, 213-3, 212-1, 213-1) can be addressed through the WL and a conduction voltage V _b , V _b can be greater than the threshold voltage V _th of the corresponding memory cell. Exemplarily, the conduction voltage V _bFor example, it can be 5V to 7V, corresponding to the threshold voltage V of the memory cell _th It can be 2V to 3V.

[0084] Continue to refer to Figure 9 , optionally, while applying the conduction voltage V to the unselected word line Usel_WL _b , the conduction voltage V can be applied to the M_TSG in the middle level, for example, the M_TSG controlling the sub memory strings 212-3 and 213-3 _b , and the value of the conduction voltage V _b can be greater than the threshold voltage of the top select gate transistors controlled by these M_TSGs.

[0085] Continue to refer to Figure 9 , similarly, while applying the conduction voltage V to the unselected word line Usel_WL _b , the conduction voltage V can be applied to the L_TSG in the bottom level, for example, the L_TSG controlling the sub memory strings 212-1 and 213-1 _b , and the value of the conduction voltage V _b can be greater than the threshold voltage of the top select gate transistors controlled by these L_TSGs.

[0086] Exemplarily, while applying the conduction voltage V _b , the conduction voltage V can also be applied to the M_BSG in the middle level and the L_BSG in the bottom level _b .

[0087] The level of the above conduction voltage can climb to its peak level at time t1, so as to be able to conduct the channels of the sub memory strings 212-3, 212-1, 213-3, and 213-1. For example, the channels can be inverted into N-type channels, so as to form a path for electron transfer.

[0088] Continue to refer to Figure 9 , in some other embodiments, in the t0-t1 stage, the U_TSG included in the sub memory strings 212-2 and 213-2 in the top level can be kept off, for example, by applying a ground voltage. Optionally, the U_BSG included in the sub memory strings 212-2 and 213-2 can also be kept off, for example, by applying a ground voltage.

[0089] In some other examples, in the t0-t1 stage, a ground voltage (such as 0V) is applied to the selected word line Sel_WL and the unselected word line Usel_WL corresponding to the memory cells included in the sub memory strings 212-2 and 213-2 in the top level, so as to keep the channels in the top level off.

[0090] In some examples, during the t0 - t1 stage, a ground voltage can be applied to the memory string to be programmed (e.g., memory string 212) and the remaining memory strings (e.g., memory string 213) via BL and ACS respectively.

[0091] Returning to Figure 8 As shown, the programming operation method 300 proceeds to operation S302, where, after applying the on - voltage, a pre - charge voltage is applied across both ends of each of the memory strings.

[0092] Continuing to refer to Figure 9 , optionally, during the t1 - t2 stage, after the channels of the sub - memory strings (e.g., sub - memory strings 212 - 3, 212 - 1, 213 - 3, 213 - 1) located in the middle and bottom levels are turned on and inverted, for example, at time t1, a pre - charge voltage V_ per , V _per which can be, for example, 4V to 6V, can be applied across both ends (e.g., source terminal and drain terminal) of the memory string to be programmed (e.g., memory string 212) and the remaining memory strings (e.g., memory string 213) via ACS and BL respectively. In some examples, the level (e.g., positive potential) of the pre - charge voltage V_ per applied via ACS can conduct along the channels of the memory string 212 to be programmed and the remaining memory strings 213 of the memory string to be programmed towards the sub - memory strings 212 - 2 and 213 - 2 in the top level.

[0093] Continuing to refer to Figure 9 , in some examples, at time t1, the unselected word lines Usel_WL corresponding to the memory cells located in the middle and bottom levels can be set to a floating state. Setting to a floating state includes, for example: after the channels of the sub - memory strings located in the middle and bottom levels are turned on and inverted, removing the on - voltage V _b applied to the unselected word lines Usel_WL corresponding to the memory cells located in the middle and bottom levels, and these unselected word lines Usel_WL can couple out a voltage in response to the rise of the channel potential.

[0094] Optionally, M_TSG and M_BSG located in the middle level and L_TSG and L_BSG located in the bottom level can also be set to a floating state. During the process of the level of the pre - charge voltage V _per climbing to its peak level, these memory cells, M_TSG, M_BSG, L_TSG, and L_BSG can couple out a voltage higher than V _per , for example, the peak level of the coupling is V _per +V _b .

[0095] As Figure 9As shown, during the t2 - t3 stage, the pre - charge voltage V_ applied via the ACS per is conducted to the conductive plugs between the middle level and the top level (e.g., Figure 6 the conductive plugs 460 and 480 shown). Since the channels of the sub - memory strings 212 - 2 and 213 - 2 located in the top level remain off, the pre - charge voltage V _per can induce electron - hole pairs at the interfaces between the conductive plugs 460 and 480 and the channel layer 420 of the corresponding sub - memory strings 212 - 2 and 213 - 2, causing holes to move along the channel layer 420 towards the middle of the corresponding sub - memory strings 212 - 2 and 213 - 2, while electrons return to the conductive plugs 460 and 480, thereby generating a Gate - Induced Drain Leaking (GIDL) current to perform GILD pre - charge on the channels of the sub - memory strings 212 - 2 and 213 - 2. Optionally, the channel potentials of the sub - memory strings 212 - 2 and 213 - 2 are correspondingly raised, for example, by 2V to 3V.

[0096] Optionally, the V applied via the BL _per can induce electron - hole pairs at the interface where the electrode plug 416 ( Figure 6 ) contacts the channel layer 420 of the sub - memory strings 212 - 2 and 213 - 2, thereby generating a GILD current to perform GILD pre - charge on the sub - memory strings 212 - 2 and 213 - 2.

[0097] As Figure 9 shown, t3 - t4 is the pre - charge recovery stage. In some examples, after GILD pre - charge, the pre - charge voltage V applied to the BL and ACS _er can be turned off, so that the voltages applied in the middle level and the bottom level return to the reference voltage.

[0098] Return to Figure 8 , and the programming operation method 300 continues to operation S303, where, during the programming stage, while applying a drain selection voltage to the DSG transistors included in the memory string to be programmed, the DSG transistors included in the remaining memory strings are turned off.

[0099] Continue to refer to Figure 9 , t4 - t5 is the programming stage. In some examples of the programming stage, a programming voltage V _pgm can be applied to the selected word line Sel_WL corresponding to the memory cell 340 to be programmed included in the sub - memory string 212 - 2, and V_ pgm can be a pulse voltage. In some examples, V_ pgmThe value can be, for example, 15V to 21V. Optionally, while applying the above programming voltage V_ pgm a first pass voltage V_ pass , V_ pass can be applied to the unselected word lines Usel_WL corresponding to the remaining memory cells in each level, and the value of V_

[0100] is, for example, 8V to 12V. In some examples, while applying the above programming voltage V_ pgm a second pass voltage can be applied to the M_BSG included in the sub-bit strings 212-3 and 213-3 and the L_BSG included in the sub-bit strings 212-1 and 213-1, and the second pass voltage is, for example, V_ pass , V_ pass and the value of V_

[0101] is, for example, 8V to 12V. In some examples, while applying the above programming voltage V_ pgm a drain select voltage V_ sel can be applied to each DSG transistor in the memory string 212 to be programmed. For example, a drain select voltage V_ sel can be applied to the DSL corresponding to each TSG included in the sub-bit strings 212-2, 212-3, and 212-1 to turn on the channels of the memory string 212 to be programmed.

[0102] Optionally, while applying the above programming voltage V _pgm a ground voltage can be applied to the drain and source terminals of the memory string 212 to be programmed via the BL and ACS respectively. The ground voltage is, for example, 0V. Applying the ground voltage can cause the potential obtained by the channel of the sub-bit string 212-2 to drop to 0 at a relatively fast speed during the GIDL pre-charge phase, so that the programming of the memory cells 420 that do not need to be programmed is hardly interfered.

[0103] Optionally, while applying the above programming voltage V_pgm, a ground voltage can also be applied to each DSG transistor in the remaining memory strings 213. For example, a ground voltage is applied to the DSL corresponding to each TSG included in the sub-bit strings 213-2, 213-3, and 213-1 to turn off the channels of the remaining memory strings 213 to be programmed.

[0104] In some embodiments of the present application, on the one hand, since the channel potential of the sub - memory string 213 - 2 has been lifted during the GIDL pre - charge stage, the V_pass applied to the unselected word line Usel_WL will further boost the channel potential of the sub - memory string 213 - 2, reducing the programming interference. On the other hand, thanks to the U_TSG of each sub - memory string in the remaining memory strings 213 of the memory string to be programmed being turned off, it can prevent the electrons rich in the conductive plugs 480 and 490 from being transmitted to the sub - memory string 213 - 2, further reducing the programming interference.

[0105] Optionally, a drain voltage can be applied to the drain of the remaining memory strings 213 of the memory string to be programmed. The drain voltage can be, for example, the bit - line voltage V_bl applied through the BL, and V_bl is, for example, 1V - 3V.

[0106] In some examples, the sub - memory string groups located in the middle level and the bottom level may further include dummy memory cells. Operations similar to those of Usel_WL in the middle level and the bottom level as described above can be performed on the dummy word lines coupled to these dummy memory cells, and this application will not elaborate further on this.

[0107] It should be understood that in the example of performing a programming operation on the middle level where the middle sub - stack layer 454 as shown in Figure 6 is located, the middle level can be the second level, while the top level where the top sub - stack layer 452 is located and the bottom level where the bottom sub - stack layer 450 is located are the first level. Among them, the sub - memory string 212 - 3 where the memory cell 340 to be programmed is located is the sub - memory string to be programmed, and the memory string 212 where the memory cell 340 to be programmed is located is the memory string to be programmed.

[0108] As Figure 10 shown, programming operations similar to those of the top level can be performed on the middle level. Exemplarily, during the pre - conduction stage from t0 to t1, a conduction voltage V _b can be applied to the U_TSG and L_TSG located in the first level (for example, the top level and the bottom level), the word lines corresponding to each memory cell (for example, the unselected word line Usel_WL), and the U_BSG and L_BSG. _b Optionally, the value of the conduction voltage V

[0109] In some examples, after applying the conduction voltage V _b , for example, when the level of the conduction voltage V _b climbs to the peak level at time t1, it can conduct as Figure 6The channels of the sub - memory strings 212 - 2, 212 - 1, 213 - 2, 213 - 1 shown, for example, can invert the channels into N - type channels, thereby forming a path for electron transfer.

[0110] In some examples, during the t0 - t1 stage, the channels of the sub - memory strings 212 - 3 and 213 - 3 in the middle level can be kept off. For example, a ground voltage can be applied to the M_TSG and M_BSG included in the sub - memory strings 212 - 3 and 213 - 3 and each word line.

[0111] In some examples, during the t0 - t1 stage, a ground voltage can be applied to the memory string 212 to be programmed and the remaining memory strings 213 via the BL and ACS respectively.

[0112] In some embodiments, during the t1 - t2 stage, for example, at the moment t1, a pre - charge voltage V_ can be applied to both ends (e.g., drain terminal and source terminal) of the memory string 212 to be programmed and the remaining memory strings 213 via the BL and ACS respectively. per to conduct the pre - charge voltage to the sub - memory strings 212 - 3 and 213 - 3 in the middle level. Optionally, at the moment t1, the U_TSG and L_TSG in the top and bottom levels, the unselected word line Usel_WL corresponding to the memory cell, and the U_BSG and L_BSG can be set to a floating state.

[0113] In some examples, during the t2 - t3 stage, the pre - charge voltage V_ applied via the BL and ACS per conducts to Figure 6 the conductive plugs 460, 470, 480, and 490 shown, and causes a GIDL current to be generated in the sub - memory strings 212 - 3 and 213 - 3, so as to be able to perform GILD pre - charging on the channels of the sub - memory strings 212 - 3 and 213 - 3 to obtain a rise in the channel potential.

[0114] In some examples, during the programming stage of t4 - t5, a drain selection voltage V_ can be applied to each DSG transistor in the memory string 212 to be programmed. sel For example, V_ can be applied to the DSL corresponding to the U_TSG of the sub - memory string 212 - 2, the DSL corresponding to the L_TSG of the sub - memory string 212 - 1, and the DSL corresponding to the M_TSG of the sub - memory string 212 - 3. sel .

[0115] Optionally, when applying the above - mentioned drain selection voltage V_ selMeanwhile, a ground voltage can also be applied to each DSG transistor in the remaining memory strings 213. For example, a ground voltage can be applied to the DSL corresponding to U_TSG of the sub-memory string 213-2, the DSL corresponding to M_TSG of the sub-memory string 213-3, and the DSL corresponding to L_TSG of the sub-memory string 213-1, for turning off the channels of the remaining memory strings 213.

[0116] It should also be understood that, in an example of performing a programming operation on the bottom level where the bottom sub-stack layer 450 shown Figure 6 is located, the bottom level can be the second level, while the top level where the top sub-stack layer 452 is located and the middle level where the middle sub-stack layer 454 is located are the first levels. Among them, the sub-memory string 212-1 where the memory cell 340 to be programmed is located is the sub-memory string to be programmed, and the memory string 212 where the memory cell 340 to be programmed is located is the memory string to be programmed.

[0117] As Figure 11 shown, a programming operation similar to that of the top level can be performed on the bottom level. Exemplarily, in the pre-conduction stage from t0 to t1, a conduction voltage V _b can be applied to U_TSG and M_TSG located in the first level (e.g., the top level and the middle level), the word lines corresponding to each memory cell (e.g., the unselected word line Usel_WL), and U_BSG and M_BSG. _b Optionally, the value of the conduction voltage V

[0118] can be greater than the threshold voltages of the corresponding transistors and memory cells. _b After applying the conduction voltage V _b , for example, when the level of the conduction voltage V Figure 6 rises to the peak level at the moment t1, the channels of the sub-memory strings 212-2, 212-3, 213-2, and 213-3 shown

[0119] can be turned on, for example, the channels can be inverted into N-type channels, so as to form a path for electron transfer.

[0120] In some examples, during the stage from t0 to t1, the channels of the sub-memory strings 212-1 and 213-1 located in the bottom level can be kept off. For example, a ground voltage can be applied to L_TSG and L_BSG included in the sub-memory strings 212-1 and 213-1 and each word line.

[0121] In some embodiments, during the t1 - t2 stage, for example, at the moment of t1, via the BL and ACS, a pre - charge voltage V_ can be applied to both ends (e.g., the drain terminal and the source terminal) of the memory string 212 to be programmed and the remaining memory strings 213 respectively. per The pre - charge voltage V_ applied via the BL per can be conducted to the sub - memory strings 212 - 1 and 213 - 1 of the bottom level. Optionally, at the moment of t1, the U_TSG and M_TSG in the top level and the middle level, the word lines corresponding to each memory cell (e.g., the unselected word line Usel_WL), and the U_BSG and M_BSG can be set to the floating state.

[0122] In some examples, during the t2 - t3 stage, the pre - charge voltage V_ applied via the BL per is conducted to Figure 6 the conductive plugs 470 and 490 shown, and enables the generation of GIDL current in the sub - memory strings 212 - 1 and 213 - 1, so as to be able to perform GILD pre - charge on the channels of the sub - memory strings 212 - 1 and 213 - 1 to obtain a rise in the channel potential.

[0123] In some examples, during the programming stage of t4 - t5, a drain select voltage V_ can be applied to each DSG transistor in the memory string 212 to be programmed. sel For example, V_ can be applied to the DSL corresponding to the U_TSG of the sub - memory string 212 - 2, the DSL corresponding to the M_TSG of the sub - memory string 212 - 3, and the DSL corresponding to the L_TSG of the sub - memory string 212 - 1. sel .

[0124] Optionally, while applying the above - mentioned drain select voltage V_ sel , a ground voltage can also be applied to each DSG transistor in the remaining memory strings 213. For example, a ground voltage can be applied to the DSL corresponding to the U_TSG of the sub - memory string 213 - 2, the DSL corresponding to the M_TSG of the sub - memory string 213 - 3, and the DSL corresponding to the L_TSG of the sub - memory string 213 - 1, for turning off the channels of the remaining memory strings 213.

[0125] It should be understood that the above - mentioned programming operations performed on the top sub - stack layer 452 can be partially or fully applicable to the programming operations on the middle sub - stack layer 454 and the bottom sub - stack layer 450, which will not be elaborated in this application.

[0126] As can be seen from the foregoing, in some embodiments of the present application, by separately controlling the top select gate transistors of the sub - memory strings at each level, on the one hand, inter - level programming operations can be achieved, and on the other hand, pre - charging of the channels of the sub - memory string 213 - 2 can be implemented separately. During the programming stage, the channel potential of the sub - memory string 213 - 2 is greatly increased, thereby improving programming interference. Further, during the programming stage, by controlling the turn - off of the top select gate transistors of the sub - memory string 213 - 2, it is difficult for electrons in the conductive plugs connected to the sub - memory string 213 - 2 to enter the channel, further reducing programming interference.

[0127] Some embodiments of the present application also provide a memory system (e.g., Figure 1 the memory system 402 shown), the memory system 402 includes a storage device (e.g., Figure 4 the storage device 100 shown) and a memory controller (e.g., Figure 1 the memory controller 406 shown), the memory controller 406 is configured to control the peripheral circuit in the storage device 100 (e.g., Figure 4 the peripheral circuit 101 shown). Optionally, the memory controller 406 may be configured to issue a conduction command, a pre - charging command, and a programming command to the peripheral circuit 101. Optionally, the peripheral circuit 101 may respond to the conduction command, the pre - charging command, and the programming command to execute the above - mentioned programming operation method 300.

[0128] The specific embodiments described above further elaborate on the object, technical solution, and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not used to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for programming an electronic storage device, wherein, The storage device includes a plurality of memory strings, each of the memory strings including sub-memory strings divided into a plurality of levels, each of the sub-memory strings including a plurality of memory cells, an SSG transistor, and a DSG transistor, characterized in that the method includes: In a pre-charge phase, applying a conduction voltage to the DSG transistor, the memory cell, and the SSG transistor located in a first level of the plurality of levels; After applying the conduction voltage, applying a pre-charge voltage across both ends of each of the memory strings; and In a programming phase, while applying a drain select voltage to the DSG transistor included in the memory string to be programmed, turning off the DSG transistors included in the remaining memory strings.

2. The method according to claim 1, wherein, After the level of the conduction voltage climbs to a peak level, applying the pre-charge voltage.

3. The method according to claim 1, wherein, After the level of the conduction voltage climbs to a peak level, setting the DSG transistor, the memory cell, and the SSG transistor located in the first level to a floating state.

4. The method according to claim 1, wherein, While applying the conduction voltage, applying a ground voltage to the DSG transistor, the memory cell, and the SSG transistor located in a second level of the plurality of levels.

5. The method according to claim 1, further comprising: In the programming phase, applying a programming voltage to the memory cells to be programmed located in a second level of the plurality of levels, and applying a first pass voltage to the remaining memory cells.

6. The method according to claim 1, further comprising: In the programming phase, applying a ground voltage to the SSG transistor located in a second level of the plurality of levels, and applying a second pass voltage to the SSG transistor located in the first level.

7. The method according to claim 1, further comprising: In the programming phase, applying a ground voltage across both ends of the memory string to be programmed, and applying a drain voltage across both ends of the remaining memory strings.

8. A storage device, comprising: A plurality of memory strings, each of the memory strings including sub-memory strings divided into a plurality of levels, each of the sub-memory strings including a plurality of memory cells, an SSG transistor, and a DSG transistor; And A peripheral circuit, coupled to the memory strings and configured to: In a pre-charge phase, applying a conduction voltage to the DSG transistor, the memory cell, and the SSG transistor located in a first level of the plurality of levels; After applying the conduction voltage, applying a pre-charge voltage across both ends of each of the memory strings; And In a programming phase, while applying a drain select voltage to the DSG transistor included in the memory string to be programmed, turning off the DSG transistors included in the remaining memory strings.

9. The storage device according to claim 8, further comprising: A stacked layer, including sub-stacked layers located in respective levels, the sub-stacked layers including alternately stacked gate layers and dielectric layers, the sub-memory strings passing through the sub-stacked layers corresponding to the respective levels; Conductive plugs, located between the respective sub-stacked layers and electrically connecting the respective sub-memory strings included in the same memory string; and The top select gate line passes through the gate layers corresponding to the DSG transistors in each level and is located between adjacent sub - memory strings.

10. The memory device according to claim 8, wherein, The peripheral circuit is further configured to: Apply the pre - charge voltage after the level of the conduction voltage climbs to the peak level.

11. The storage device according to claim 8, wherein, The peripheral circuit is further configured to: After the level of the conduction voltage climbs to the peak level, set the DSG transistors, the memory cells, and the SSG transistors in the first level to a floating state.

12. The memory device according to claim 8, wherein the peripheral circuit is further configured to: Apply a ground voltage to the DSG transistors, the memory cells, and the SSG transistors in the second level among the multiple levels while applying the conduction voltage.

13. The memory device according to claim 8, wherein the peripheral circuit is further configured to: During the programming phase, apply a programming voltage to the memory cells to be programmed in the second level among the multiple levels, and apply a first pass voltage to the remaining memory cells.

14. The memory device according to claim 8, wherein the peripheral circuit is further configured to: During the programming phase, apply a ground voltage to the SSG transistors in the second level among the multiple levels, and apply a second pass voltage to the SSG transistors in the first level.

15. The memory device according to claim 8, wherein the peripheral circuit is further configured to: During the programming phase, apply a ground voltage to both ends of the memory string to be programmed, and apply a drain voltage to both ends of the remaining memory strings.

16. A memory system, comprising: A memory device configured to store data and comprising: Multiple memory strings, each memory string including sub - memory strings divided into multiple levels, each sub - memory string including multiple memory cells, SSG transistors, and DSG transistors; and A peripheral circuit coupled to the memory strings and configured to: During the pre - charge phase, apply a conduction voltage to the DSG transistors, the memory cells, and the SSG transistors in the first level among the multiple levels; After applying the conduction voltage, apply a pre - charge voltage through both ends of each memory string; and During the programming phase, while applying a drain select voltage to the DSG transistors included in the memory string to be programmed, turn off the DSG transistors included in the remaining memory strings; and A memory controller coupled to the memory device and configured to control the memory device.

17. The storage system according to claim 16, wherein, The memory device further comprises: A stacked layer including sub - stacked layers in each level, the sub - stacked layers including alternately stacked gate layers and dielectric layers, and the sub - memory strings passing through the sub - stacked layers corresponding to the respective levels; Conductive plugs located between the respective sub - stacked layers and electrically connecting the respective sub - memory strings included in the same memory string; and The top select gate line passes through the gate layers corresponding to the DSG transistors in each level and is located between adjacent sub - memory strings.

18. The memory system according to claim 16, comprising: A solid - state drive or a memory card.

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