Memory devices

Abstract

The present application relates to a memory device. A memory device includes: a contact opening region located between memory blocks; and a row decoder disposed between a global line and a local line to which an operating voltage is supplied, and configured to transmit the operating voltage to one of the memory blocks in response to a row address. A plurality of contacts are formed in the contact opening region and configured to transmit a voltage between a bit line and a peripheral circuit. A dummy region is included in the row decoder and spaced apart from the contact opening region in a second direction. A discharge switch is included in the dummy region and configured to discharge the global line in response to a discharge signal.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices, and more particularly, to a memory device including a memory block and a row decoder. Background Art

[0002] The memory device may include a volatile memory device in which stored data disappears when power supply is interrupted and a nonvolatile memory device in which stored data remains even when power supply is interrupted.

[0003] Volatile memory devices may include dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory devices may include read-only memory (ROM), programmable read-only memory (PROM), erasable programm ...

[0004] A memory device may include a memory cell array, peripheral circuits, and logic circuits.

[0005] A memory cell array may include a memory block comprising a plurality of memory cells. The memory block may be formed in a two-dimensional or three-dimensional structure. For example, a memory block having a two-dimensional structure may include memory cells arranged parallel to a substrate. A memory block having a three-dimensional structure may include memory cells stacked perpendicular to a substrate.

[0006] The use of three-dimensional memory blocks capable of increasing the degree of integration has recently increased.

[0007] Since the memory cells are stacked in three-dimensional memory blocks on the substrate, the word lines connected to the memory cells can also be stacked. Since a large number of metal lines in addition to word lines are used in the memory device, the memory device may include multiple contacts for transmitting voltage between these lines. Summary of the Invention

[0008] Various embodiments of the present disclosure provide a memory device in which transistors are formed in an unused dummy region in the memory device, thereby enabling reduction in the size of peripheral circuits.

[0009] According to one aspect of the present disclosure, a memory device is provided, comprising: memory blocks spaced apart from each other in a first direction and connected to bit lines spaced apart from each other in a second direction perpendicular to the first direction and local lines spaced apart from each other in the first direction; a contact opening region located between the memory blocks; and a row decoder disposed between a global line and the local line to which an operating voltage is supplied, and configured to transmit an operating voltage to one of the memory blocks in response to a row address, wherein a plurality of contacts are formed in the contact opening region and configured to transmit a voltage between the bit line and a peripheral circuit, wherein a dummy region is included in the row decoder and spaced apart from the contact opening region in the second direction, and wherein a discharge switch is included in the dummy region and configured to discharge the global line in response to a discharge signal.

[0010] According to another aspect of the present disclosure, a memory device is provided, which includes: a plurality of memory blocks; a global line to which an operating voltage is applied; a local line connected to each memory block; a plurality of high-voltage switches and a plurality of path switch groups, which are configured to connect the local lines connected to a selected memory block among the memory blocks to the global line in response to a row address; and a discharge switch, which is located between the path switch groups and is configured to discharge the global line in response to a discharge signal.

[0011] According to another aspect of the present disclosure, a memory device is provided, comprising: a memory block configured to store data and connected to a local line and a bit line; a page buffer connected to the bit line through a contact and located between the memory block and a substrate; a voltage generator configured to generate an operating voltage and output the operating voltage to a global line; a path switch group configured to transmit the operating voltage to a selected memory block among the memory blocks; and a discharge switch located between the path switch groups and configured to discharge the global line in response to a discharge signal.

[0012] According to another aspect of the present disclosure, a memory device is provided, comprising: a memory block disposed on a substrate, connected to bit lines spaced apart from each other in a second direction, and connected to local lines spaced apart in a first direction perpendicular to the second direction; a contact disposed adjacent to the memory block in the first direction and configured to electrically couple the bit lines to a page buffer disposed between the memory block and the substrate; a path switch group disposed adjacent to the memory block in the second direction and configured to electrically couple the local lines to a global line; and a discharge switch disposed adjacent to the contact in the second direction and adjacent to the path switch group in the first direction and configured to discharge the global line. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0014] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Like reference numerals refer to like elements throughout.

[0015] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0016] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0017] Figure 3 is a circuit diagram illustrating a memory block.

[0018] Figure 4 is a perspective view illustrating a memory block.

[0019] Figure 5 FIG. 1 is a diagram illustrating a contact opening region according to an embodiment of the present disclosure.

[0020] Figure 6 FIG. 1 is a diagram illustrating a contact opening region in more detail according to an embodiment of the present disclosure.

[0021] Figure 7 is a diagram illustrating a peripheral circuit including a dummy region according to an embodiment of the present disclosure.

[0022] Figure 8 is a diagram illustrating a layout of a via switch group according to an embodiment of the present disclosure.

[0023] Figure 9A and Figure 9B is a diagram illustrating a discharge switch according to a first embodiment of the present disclosure.

[0024] Figure 10A is a diagram illustrating a discharge switch according to a second embodiment of the present disclosure.

[0025] Figure 10B is a diagram illustrating a discharge switch according to a third embodiment of the present disclosure.

[0026] Figure 11 is a diagram illustrating a connection configuration of a discharge switch according to an embodiment of the present disclosure.

[0027] Figure 12 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0028] Figure 13 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0029] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments of the concepts of the present disclosure. Embodiments of the concepts of the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0030] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0031] Reference Figure 1 , the memory system 1000 may include a storage device 1100 and a controller 1200. The storage device 1100 may include a plurality of memory devices MD, and the memory devices MD may be connected to the controller 1200 through input / output lines.

[0032] The controller 1200 may communicate between the host 1500 and the storage device 1100. The controller 1200 may generate a command CMD for controlling the memory device MD included in the storage device 1100 according to a request RQ of the host 1500, and perform background operations for improving the performance of the memory system 1000 even when the request RQ of the host 1500 does not exist.

[0033] The host 1500 may generate request RQs for various operations and output the generated request RQs to the memory system 1000. For example, the request RQs may include a program request capable of controlling a program operation, a read request capable of controlling a read operation, an erase request capable of controlling an erase operation, and the like.

[0034] The host 1500 can communicate with the memory system 1000 through various interfaces such as: Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS) or Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0035] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0036] Reference Figure 2 , the memory device MD may include a memory cell array 110 in which data is stored, a peripheral circuit 200 configured to perform a program operation, a read operation, or an erase operation, and a logic circuit 300 for controlling the peripheral circuit 200 .

[0037] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKi in which data is stored. Each of the memory blocks BLK1 to BLKi may include a plurality of memory cells, and the memory cells may be implemented in a three-dimensional structure in which the memory cells are vertically stacked over a substrate.

[0038] The peripheral circuit 200 may include a voltage generator 120 , a row decoder 130 , a page buffer group 140 , and an input / output circuit 150 .

[0039] The voltage generator 120 can generate operating voltages required for various operations in response to the voltage code VCD and output the operating voltages through the global line GL. For example, the voltage generator 120 can generate and output program voltages, verification voltages, read voltages, pass voltages, erase voltages, etc. having various levels.

[0040] The row decoder 130 may select a memory block from the memory blocks BLK1 to BLKi included in the memory cell array 110 according to the row address RADD and transmit an operating voltage to the selected memory block via the local line LL. The row decoder 130 may discharge the global line GL in response to the discharge signal DIS. For example, when the global line GL is discharged, the voltage of the global line GL may become 0V or a negative voltage.

[0041] The page buffer group 140 can be connected to the memory cell array 110 through the bit lines BL. For example, the page buffer group 140 may include page buffers connected to the respective bit lines BL. The page buffers can operate simultaneously in response to the page buffer control signal PBSIG and temporarily store data during a programming operation or a read operation. The verification operation performed in the programming operation and the verification operation performed in the erase operation can be performed in the same manner as the read operation. The page buffer can sense the voltage of the bit line that changes according to the threshold voltage of the memory cell during the read operation or the verification operation. That is, it can be determined based on the result of the sensing operation performed by the page buffer whether the threshold voltage of the memory cell is lower than the read voltage or the verification voltage, or higher than the read voltage or the verification voltage.

[0042] The input / output circuit 150 can be connected to the controller ( Figure 11200 shown in FIG. 1200). The input / output circuit 150 can input / output commands CMD, addresses ADD, and data DATA through the input / output lines. For example, the input / output circuit 150 can transmit commands CMD and addresses ADD received through the input / output lines to the logic circuit 300, and transmit data received through the input / output lines to the page buffer group 140. The input / output circuit 150 can output data DATA received from the page buffer group 140 to the controller 1200 through the input / output lines.

[0043] The logic circuit 300 can output a voltage code VCD, a row address RADD, a discharge signal DIS, and a page buffer control signal PBSIG in response to a command CMD and an address ADD. For example, the logic circuit 300 may include software for executing an algorithm in response to the command CMD and hardware configured to output various signals based on the address ADD and the algorithm. After a select operation is performed in a selected memory block, the logic circuit 300 can output a discharge signal DIS to discharge the global line GL. Alternatively, after a select operation is performed in a selected memory block, the logic circuit 300 can output a discharge signal DIS to discharge the global line GL and the local line LL.

[0044] Figure 3 is a circuit diagram illustrating a memory block, and illustrates Figure 2 An i-th memory block BLKi among the plurality of memory blocks BLK1 to BLKi is shown as an example.

[0045] Reference Figure 3 , the i-th memory block BLKi may include a plurality of strings ST1 to ST4. Figure 3 1 to 4 strings ST1 to ST4 are illustrated in FIG, but a greater number of strings than the first to fourth strings ST1 to ST4 may be included in the i-th memory block BLKi.

[0046] The first to fourth strings ST1 to ST4 may be connected between the bit lines BL1 to BL4 and the source line SL. For example, the first string ST1 may be connected between the first bit line BL1 and the source line SL, and the second string ST2 may be connected between the second bit line BL2 and the source line SL.

[0047] Each of the first to fourth strings ST1 to ST4 may include a source select transistor SST, a plurality of memory cells C1 to Cn, and a drain select transistor DST. Although not shown in the figure, a dummy cell may be further included between the memory cells C1 to Cn and the source select transistor SST or the drain select transistor DST. To describe the configuration of the string, the fourth string ST4 will be described as an example.

[0048] The source select transistor SST included in the fourth string ST4 can electrically connect the source line SL and the first memory cell C1 to each other or block the connection between the source line SL and the first memory cell C1 according to the voltage applied to the source select line SSL. The gates of the first memory cell C1 to the nth memory cell Cn can be connected to the first word line WL1 to the nth word line WLn, respectively. The drain select transistor DST included in the fourth string ST4 can electrically connect the fourth bit line BL14 and the nth memory cell Cn to each other or block the connection between the fourth bit line BL14 and the nth memory cell Cn according to the voltage applied to the drain select line DSL. The gates of the source select transistors SST included in different strings ST1 to ST4 can be commonly connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings ST1 to ST4 can be commonly connected to the drain select line DSL. A group of memory cells connected to the same word line is called a page PG, and programming operations and read operations can be performed in units of page PG.

[0049] The programming operation will be described as an example. A programming voltage can be applied to the selected word line connected to the selected page, and a pass voltage can be applied to other unselected word lines. The programming voltage is a voltage used to increase the threshold voltage of the selected memory cell, and the pass voltage is used to form a channel in the string by turning on the unselected memory cells included in the string. For example, when the sixth word line WL6 is the selected word line, the first word line WL1 to the fifth word line WL5 and the seventh word line WL7 to the nth word line WLn can become unselected word lines. The programming operation can be performed in the direction from the source select line SSL to the drain select line DSL, or in the direction from the drain select line DSL to the source select line SSL.

[0050] Figure 4 is a perspective view illustrating a storage block and illustrating Figure 2 An i-th memory block BLKi among the plurality of memory blocks BLK1 to BLKi is shown as an example.

[0051] Reference Figure 4 In the i-th memory block BLKi formed in a three-dimensional structure, a source line SL may be formed on top of a lower structure UST, and a stacked structure STC including memory cells may be formed on the source line SL. The lower structure UST may be a substrate or include a substrate and peripheral circuits. For example, a portion of the peripheral circuits may be formed on the substrate, and the source line SL may be formed on top of the portion of the peripheral circuits.

[0052] The stacked structure STC may include a source select line SSL, first to nth word lines WL1 to WLn, and a drain select line DSL stacked in sequence. A channel plug CHP may be formed to penetrate the source select line SSL, the first to nth word lines WL1 to WLn, and the drain select line DSL in a vertical direction Z. The channel plug CHP may include a memory layer capable of trapping electrons and a channel layer capable of forming a channel. For example, the channel plug CHP may include a channel layer, a tunnel insulating layer surrounding the channel layer, a memory layer, and a barrier layer.

[0053] A source select transistor may be formed in a region where the channel plug CHP and the source select line SSL overlap, a memory cell may be formed in a region where the channel plug CHP and the first to nth word lines WL1 to WLn overlap, and a drain select transistor may be formed in a region where the channel plug CHP and the drain select line DSL overlap. The first to nth word lines WL1 to WLn may be formed on a plane XY parallel to the lower structure UST and extend in the X direction. A bit line BL may be formed on top of the channel plug CHP. The bit line BL may extend in the Y direction while contacting the channel plug CHP and be spaced apart from each other in the X direction.

[0054] like Figure 4 As shown, the i-th memory block BLKi can be formed in a three-dimensional structure, and the other memory blocks included in the memory cell array can be formed in the same structure as the i-th memory block BLKi. When the memory blocks included in the memory cell array are formed in a three-dimensional structure, contacts for providing voltage to the bit lines BL, the source select lines SSL, the first word lines WL1 to the n-th word lines WLn, and the drain select lines DSL can be formed in local areas of the memory cell array. No memory cells are formed in the areas where the contacts are formed. In this embodiment, these areas are defined as contact opening regions.

[0055] Figure 5 FIG. 1 is a diagram illustrating a contact opening region according to an embodiment of the present disclosure. Figure 6 FIG. 1 is a diagram illustrating a contact opening region in more detail according to an embodiment of the present disclosure.

[0056] Reference Figure 5 and Figure 6 , a plurality of memory blocks may be included in the memory cell array 110. Figure 5 , first to third memory blocks BLK1 to BLK3 among a plurality of memory blocks are illustrated as examples.

[0057] In one embodiment, each of the first to third memory blocks BLK1 to BLK3 may be configured similarly to Figure 4Therefore, some of the memory blocks among the first to third memory blocks BLK1 to BLK3 may include contact opening areas OFC. To help understand this embodiment, Figure 5 1 and 2 , respectively, illustrate a case where the contact opening region OFC is located between the first memory block BLK1 and the second memory block BLK2 . However, the number and positions of the contact opening regions OFC may be changed depending on the memory cell array 110 .

[0058] Since the contact is formed in the contact opening area OFC included in the memory cell array 110, no memory cell is formed in the contact opening area OFC. For example, an insulating material is filled in the contact opening area OFC, and a plurality of contacts CT may be formed to penetrate the contact opening area OFC in the vertical direction Z. The contact CT may be connected to a voltage supply line (not shown) included in the lower structure UST. For example, in a unit lower peripheral (PUC) structure in which a portion of the peripheral circuit is formed in the lower structure UST, a portion of the peripheral circuit may be formed between the substrate and the memory block. For example, a page buffer group included in the peripheral circuit may be located between the substrate and the memory block, and the bottom of the contact CT may be connected to the page buffer group. The bit lines BL may be connected to the tops of the contacts CT, respectively. For example, the bit lines BL may extend in the Y direction and may be formed spaced apart from each other in the X direction.

[0059] During the manufacturing process of the memory device, when the contact opening region OFC is formed in the memory cell array 110, no memory cells are formed in the contact opening region OFC. Therefore, a dummy region may be formed in the peripheral circuit. The dummy region corresponds to the contact opening region OFC. The peripheral circuit including the dummy region will be described below.

[0060] Figure 7 is a diagram illustrating a peripheral circuit including a dummy region according to an embodiment of the present disclosure.

[0061] Reference Figure 7 , the voltage generator 120 may generate an operating voltage, and the generated operating voltage may be output to the global line GL. The row decoder 130 may be connected between the voltage generator 120 and the memory blocks BLK1 to BLK3. To help understand this embodiment, in Figure 7 1 to 3 storage blocks BLK1 to BLK3 are illustrated in FIG. However, this embodiment is not limited to Figure 7The number of memory blocks shown. The row decoder 130 can be connected to the voltage generator 120 through the global line GL, and connected to the first to third memory blocks BLK1 to BLK3 through the first to third local lines LL1 to LL3. The row decoder 130 is commonly connected to the voltage generator 120 through the global line GL, but can be connected to the first to third memory blocks BLK1 to BLK3 separately through the first to third local lines LL1 to LL3. The row decoder 130 will be described in more detail below.

[0062] The row decoder 130 may include first to third pass switch groups 1PSG to 3PSG and first to third high-voltage switches 1HVSW to 3HVSW corresponding to the first to third memory blocks BLK1 to BLK3, respectively. For example, the first pass switch group 1PSG and the first high-voltage switch 1HVSW may correspond to the first memory block BLK1, the second pass switch group 2PSG and the second high-voltage switch 2HVSW may correspond to the second memory block BLK2, and the third pass switch group 3PSG and the third high-voltage switch 3HVSW may correspond to the third memory block BLK3.

[0063] The first pass switch group 1PSG may include pass switches PS connected between the global line GL and the first local line LL1. The pass switches PS may be implemented using high-voltage NMOS transistors capable of transmitting high voltages. For example, the drain of the high-voltage NMOS transistor may be connected to the global line GL, and the source of the high-voltage NMOS transistor may be connected to the first local line LL1. The gates of the high-voltage NMOS transistors may be commonly connected to a first block select line 1BLKSL, and the first block select line 1BLKSL may be connected to the first high-voltage switch 1HVSW.

[0064] The first high-voltage switch 1HVSW can selectively output a high voltage to the first block select line 1BLKSL in response to an input row address to turn the pass switches PS on or off at the same time. For example, when the first memory block BLK1 is selected in a program operation, a read operation, or an erase operation, the first high-voltage switch 1HVSW can generate a high voltage in response to the row address used to select the first memory block BLK1 and output the generated high voltage through the first block select line 1BLKSL. When a high voltage is applied to the first block select line 1BLKSL, the pass switches PS included in the first pass switch group 1PSG can be turned on at the same time. Therefore, the global line GL can be electrically connected to the first local line LL1, and the operating voltage can be applied to the selected first memory block BLK1. The other second high-voltage switches 2HVSW and the third high-voltage switches 3HVSW do not output a high voltage in response to the row address. Therefore, the second memory block BLK2 and the third memory block BLK3 may not be selected.

[0065] The first memory block BLK1, the first local line LL1, and the first pass switch group 1PSG are connected to each other in the X direction. The second and third memory blocks BLK2 and BLK3, the second and third local lines LL2 and LL3, and the second and third pass switch groups 2PSG and 3PSG are also connected to each other in the X direction. In this structure, a dummy region DMR can be formed in a portion of the region extending in the X direction relative to the contact opening region OFC. For example, the dummy region DMR can be formed between the first pass switch group 1PSG and the second pass switch group 2PSG.

[0066] The dummy region DMR is an unused area created by the contact opening region OFC during the manufacturing process of a memory device. It can be formed in an area extending in the X, Y, or Z directions relative to the contact opening region OFC. For example, the contacts CT formed in the contact opening region OFC can be connected to the bit lines BL. When the bit lines BL are spaced apart from each other in the X direction, the dummy region DMR can also be spaced apart from the contact opening region OFC in the X direction. Since no memory cells are formed in the contact opening region OFC, the local lines are not connected to the contact opening region OFC. Therefore, the local lines are not connected to the dummy region DMR.

[0067] When the dummy regions DMR are maintained as unused regions in the memory device, the number and size of the dummy regions DMR increase as the number and size of the contact opening regions OFC increase. Therefore, the size of the memory device can be increased.

[0068] Therefore, in this embodiment, some switches that are part of the peripheral circuits are formed in the dummy region DMR, thereby preventing the size of the memory device from increasing. In this embodiment, the dummy region DMR is formed in the row decoder 130, and the switches that are part of the row decoder 130 are formed in the dummy region DMR. For example, the row decoder 130 includes a discharge switch DISW for discharging the global line GL. Therefore, the discharge switch DISW is formed in the dummy region DMR, which enables the size of the row decoder 130 to be reduced. Therefore, the size of the memory device including the row decoder 130 can be reduced. That is, in a memory device including the contact opening region OFC, a portion of the row decoder 130 (e.g., the discharge switch DISW) can be formed in the dummy region DMR, which occupies space within the memory device that is not used due to the contact opening region OFC. Therefore, due to the dummy region DMR, the space occupied by the row decoder 130 can be reduced within the memory device. Depending on the embodiment, the unused space of the dummy region DMR can be occupied by a portion of the row decoder 130, thereby preserving the size of the memory device even with the contact opening region OFC. According to this embodiment, when the discharge switch DISW is formed in the dummy region DMR, a discharge signal DIS for turning the discharge switch DISW on or off can be applied to the dummy region DMR, and a negative voltage VNEG for discharging the global line GL can be applied to the dummy region DMR. In this embodiment, the discharge switch DISW used in the row decoder 130 is formed in the dummy region DMR. However, if the layout is changed, some switches used in the row decoder 130 may also be formed in the dummy region DMR.

[0069] Figure 8 is a diagram illustrating a layout of a via switch group according to an embodiment of the present disclosure.

[0070] Reference Figure 8 , a first pass switch group 1PSG is illustrated as an example to compare the layout of the switch group with the layout of the dummy area according to this embodiment. The first pass switch group 1PSG may include a plurality of pass switches PS, which are connected between the global line GL and the first local line LL1 and are commonly connected to the first block select line 1BLKSL. For example, the pass switches PS may be implemented using NMOS transistors that electrically connect the global line GL and the first local line LL1 in response to a first block select signal.

[0071] Figure 9A and Figure 9B is a diagram illustrating a discharge switch according to a first embodiment of the present disclosure.

[0072] Reference Figure 9A, the discharge switch DISW may be implemented with an NMOS transistor having a drain DR, a source SC, and a gate GT. For example, the drain DR of the discharge switch DISW may be connected to a global line, a negative voltage VNEG may be supplied to the source SC of the discharge switch DISW, and a discharge signal DIS may be applied to the gate GT of the discharge switch DISW. That is, even though Figure 8 The pass switches PS included in the first pass switch group 1PSG are shown connected to the first local line LL1, but the discharge switch DISW may be connected to the source SC instead of the local line, as shown in FIG. Figure 9A shown.

[0073] The structure of the discharge switch DISW will be described in more detail below.

[0074] Reference Figure 9B , the drain DR and source SC of the discharge switch DISW can be a junction region JC formed in the active portion AC. The global line GL can be connected to the junction region JC of the drain DR and can provide a negative voltage VNEG to the junction region JC of the source SC. The active portion AC can be formed of a semiconductor material, and the junction region JC can be a region where ions are doped into the semiconductor material. Therefore, when the discharge signal DIS is not applied to the gate GT of the discharge switch DISW, the drain DR and the source SC can be electrically disconnected from each other. When the discharge signal DIS is applied to the gate GT of the discharge switch DISW, a channel can be formed in the active portion AC below the gate GT, so that the drain DR and the source SC are electrically connected to each other. Therefore, when the discharge signal DIS is applied to the gate GT of the discharge switch DISW, the voltage of the global line GL is extracted to the terminal provided with the negative voltage VNEG, thereby discharging the global line GL.

[0075] In addition to the layout of the first embodiment, the discharge switch DISW may be formed with various layouts, and will be referred to as Figure 10A and Figure 10B Describes various layouts.

[0076] Figure 10A is a diagram illustrating a discharge switch according to a second embodiment of the present disclosure. Figure 10B is a diagram illustrating a discharge switch according to a third embodiment of the present disclosure.

[0077] Reference Figure 10AAccording to the second embodiment, the global line GL can be connected to the drain DR of the discharge switch DISW and can supply a negative voltage VNEG to the source SC of the discharge switch DISW. The active portion where the drain DR is formed can extend through the gate GT of the discharge switch DISW to the region where the source SC is formed. The active portion where the source SC is formed can be in common contact with the terminal TM to which the negative voltage VNEG is supplied. The width (Y direction) of the terminal TM can be formed to be narrower than the width (Y direction) of the region where the drain DR is formed.

[0078] Reference Figure 10B According to the third embodiment, the global line GL can be connected to the drain DR of the discharge switch DISW and can provide a negative voltage VNEG to the source SC of the discharge switch DISW. The active portion where the drain DR is formed can be in contact with one active portion, and the one active portion can extend to the source SC through the gate GT of the discharge switch DISW. The width (Y direction) of the region where the source SC is formed can be formed to be narrower than the width (Y direction) of the region where the drain DR is formed.

[0079] Figure 11 is a diagram illustrating a connection configuration of a discharge switch according to an embodiment of the present disclosure.

[0080] Reference Figure 11 The discharge switch DISW may be formed in the dummy region DMR. The drains DR of the discharge switches DISW may be commonly connected to the global line GL, and a negative voltage VNEG may be supplied to the source of the discharge switches DISW. When a discharge signal DIS having a positive voltage level is applied to the gate GT of the discharge switch DISW, the discharge switch DISW is turned on, thereby discharging the global line GL.

[0081] Figure 12 is a diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0082] Reference Figure 12 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0083] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control the programming operation, reading operation or erasing operation of the memory device 2200, or control the background operation of the memory device 2200. The memory controller 2100 provides an interface between the memory device 2200 and the host. The memory controller 2100 drives the firmware for controlling the memory device 2200. The memory device 2200 can communicate with the reference Figure 1 The described storage device 1100 is similarly configured.

[0084] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication protocol. The memory controller 2100 can communicate with an external device through at least one of the following communication protocols: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. The connector 2300 can be defined according to at least one of the above-mentioned various communication protocols.

[0085] The memory device 2200 may be implemented using various nonvolatile memory devices such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0086] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may form memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), Compact Flash (CF) cards, Smart Media Cards (SM and SMC), Memory Sticks, MultiMedia Cards (MMC, RS-MMC, MicroMMC, and eMMC), SD cards (SD, MiniSD, MicroSD, and SDHC), and Universal Flash Storage (UFS).

[0087] Figure 13 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to an embodiment of the present disclosure is applied.

[0088] Reference Figure 13 , SSD system 3000 includes a host 3100 and an SSD 3200. SSD 3200 exchanges signals with host 3100 via a signal connector 3001 and receives a power supply voltage via a power connector 3002. SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0089] According to an embodiment of the present disclosure, the flash memories 3221 to 322n may be configured similarly to the reference Figure 2 A memory device MD is described.

[0090] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100. The signal may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal may be a signal defined according to at least one of the following interfaces: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0091] The auxiliary power supply 3230 is connected to the host 3100 via the power connector 3002. The auxiliary power supply 3230 can receive power input from the host 3100 and charge itself. When the power supply from the host 3100 is not smooth, the auxiliary power supply 3230 can supply power to the SSD 3200. The auxiliary power supply 3230 can be located within the SSD 3200 or external to the SSD 3200. For example, the auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to the SSD 3200.

[0092] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0093] According to the present disclosure, the size of a memory device can be reduced.

[0094] Various embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, they are only used to describe the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments and many variations are possible within the spirit and scope of the present disclosure. It should be clear to those skilled in the art that in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

[0095] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the meanings commonly understood by those skilled in the art to which this disclosure belongs. Terms with dictionary definitions should be understood as having meanings consistent with the context of the relevant technology. For terms not explicitly defined in this application, the terms should not be understood in an ideal or overly formal manner.

[0096] It will be appreciated from the foregoing that although specific embodiments of the present invention have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the present invention should not be limited except in accordance with the appended claims.

[0097] CROSS-REFERENCE TO RELATED APPLICATIONS

[0098] This application claims priority to Korean Patent Application No. 10-2020-0167788, filed on December 3, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A memory device, comprising: memory blocks arranged spaced apart from each other in a first direction and connected to bit lines arranged spaced apart from each other in a second direction perpendicular to the first direction and local lines arranged spaced apart from each other in the first direction; a contact opening region, the contact opening region being located between the memory blocks; as well as a row decoder provided between a global line supplied with an operating voltage and the local line and transmitting the operating voltage to one of the memory blocks in response to a row address, wherein a plurality of contacts are formed in the contact opening region and transmit voltage between the bit line and a peripheral circuit, wherein the dummy region is included in the row decoder and is provided spaced apart from the contact opening region in the second direction, and A discharge switch is included in the dummy region and discharges the global line in response to a discharge signal.

2. The memory device according to claim 1, wherein The row decoder further includes a high-voltage switch and a pass switch group corresponding to each memory block.

3. The memory device according to claim 2, in, The high voltage switch outputs a block selection signal in response to the row address, and The path switch group connects the global line and the selected local line to each other in response to the block selection signal.

4. The memory device according to claim 3, wherein The discharge switch is located between the path switch groups.

5. The memory device according to claim 4, in, The discharge switch is implemented with a transistor, and Wherein, the transistor includes: drains, the drains being commonly connected to the global line; a source to which a negative voltage is supplied; and A gate is located between the drain and the source and electrically connects the drain and the source to each other in response to the discharge signal.

6. The memory device according to claim 5, in, The drain and the source are formed as a set of active parts, and The active portions are arranged spaced apart from each other in the first direction.

7. The memory device according to claim 6, wherein: The gate is formed on a top of the active portion.

8. A memory device, comprising: a plurality of memory blocks arranged along a first direction and respectively connected to the local lines; a global line to which an operating voltage is applied; a plurality of pass switch groups arranged along the first direction, wherein each of the plurality of pass switch groups connects a local line connected to a memory block located at a position of each pass switch group in a second direction perpendicular to the first direction among the plurality of memory blocks to the global line in response to a row address; and a contact opening region, wherein the contact opening region is located between two memory blocks among the plurality of memory blocks; A discharge switch is located at a position of the contact opening region in the second direction and discharges the global line in response to a discharge signal. 9 . The memory device according to claim 8 , further comprising a plurality of high-voltage switches, the plurality of high-voltage switches being respectively connected to the plurality of pass switch groups.

10. The memory device according to claim 8, wherein The discharge switch is provided between a first path switch group and a second path switch group among the plurality of path switch groups, and The first path switch group is connected to a local line of a first memory block among the two memory blocks, and the second path switch group is connected to a local line of a second memory block among the two memory blocks.

11. The memory device according to claim 8, wherein The discharge switches are commonly connected to the global line.

12. The memory device according to claim 8, in, The discharge switch is implemented with a transistor, and Wherein, the transistor comprises: drains, the drains being commonly connected to the global line; a source to which a negative voltage is supplied; and A gate electrically connects the drain and the source to each other in response to the discharge signal. 13 . The memory device of claim 8 , further comprising a logic circuit that outputs the discharge signal after performing a selection operation on the memory block.

14. A memory device, comprising: a plurality of memory blocks storing data and connected to local lines and bit lines; a contact opening region, the contact opening region being located between two memory blocks among the plurality of memory blocks and including a contact connected to the bit line; a page buffer connected to the bit line through the contact; a voltage generator that generates an operating voltage and outputs the operating voltage to a global line; a plurality of pass switch groups, the plurality of pass switch groups transmitting the operating voltage of the global line to a selected memory block among the plurality of memory blocks; as well as a discharge switch located between two pass switch groups among the plurality of pass switch groups and discharging the global line in response to a discharge signal, The two path switch groups are respectively connected to the two storage blocks.

15. The memory device according to claim 14, wherein Each of the plurality of pass switch groups and the discharge switch are commonly connected to the global line.

16. The memory device according to claim 14, wherein The plurality of pass switch groups include pass switches respectively connected between the global lines and the local lines.

17. The memory device according to claim 14, in, The discharge switch is implemented with a transistor, and Wherein, the transistor comprises: drains, the drains being commonly connected to the global line; a source to which a negative voltage is supplied; and A gate electrically connects the drain and the source to each other in response to the discharge signal.

18. The memory device according to claim 17, in, The drain and the source are formed as a set of active parts, and Wherein, the gate is formed on the top of the active portion.

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