Semiconductor storage device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor storage device and a method for manufacturing the same. The manufacturing method includes the following steps. First, a substrate is provided, a plurality of active areas are formed on the substrate, and shallow trench isolations are formed in the substrate, surrounding all the active areas. Next, a plurality of gate trenches are formed in the substrate, passing through the shallow trench isolations and the active areas. Then, a semiconductor layer is formed on the substrate, covering the surface of each gate trench, and the semiconductor layer is oxidized into an oxide layer. Thereafter, a plurality of gate structures are formed in the substrate, each gate structure fills each gate trench respectively, and is staggered with the shallow trench isolations and the active areas. In this way, the joint problem caused by the large gaps between the active areas can be improved, thereby improving the reliability of the manufactured semiconductor storage device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor storage device and a manufacturing method thereof. Background Art

[0002] With the miniaturization of semiconductor devices and the increasing complexity of integrated circuits, the size of components continues to decrease and the structure continues to change. Therefore, maintaining the performance of small-sized semiconductor components is currently the main goal of the industry. In the semiconductor manufacturing process, multiple active areas are usually defined on the substrate as a basis, and then the required components are formed on the active areas. Generally speaking, in a semiconductor memory device with a buried gate, the current leakage caused by the capacitor is reduced or avoided due to the relatively long length of the channel under the buried gate. The semiconductor memory device with a buried gate includes a transistor device and a charge storage device, which are connected in series to form a memory cell capable of receiving signals from the bit line and word line during operation. However, due to the limitations of manufacturing technology, many defects are formed in the memory cell with a buried gate. Therefore, the existing technology needs to be further improved to effectively improve the performance and reliability of the relevant semiconductor memory devices. Summary of the Invention

[0003] One purpose of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, wherein an oxide layer is formed in a gate trench through an additional deposition process and an oxidation process when forming a word line, so as to improve the seam problem derived from the large gap between active areas, thereby effectively improving the reliability of the manufactured semiconductor memory device.

[0004] To achieve the above-mentioned purpose, one embodiment of the present invention provides a method for manufacturing a semiconductor memory device, comprising the following steps. First, a substrate is provided, on which a plurality of active areas are formed, and the active areas extend parallel to each other and alternately along a first direction. Shallow trench isolations are formed in the substrate, surrounding all the active areas. A plurality of gate trenches are formed in the substrate, and each of the gate trenches extends parallel to each other along a second direction and passes through the shallow trench isolations and the active areas. A semiconductor layer is formed on the substrate, and the semiconductor layer covers each of the gate trenches and the surface of the substrate. Then, the semiconductor layer is oxidized into an oxide layer, and the oxide layer covers the surface of each of the gate trenches. Finally, a plurality of gate structures are formed in the substrate, and each of the gate structures fills each of the gate trenches respectively and is staggered with the shallow trench isolations and the active areas.

[0005] To achieve the above-mentioned purpose, one embodiment of the present invention provides a semiconductor memory device, comprising a substrate, shallow trench isolation, a plurality of gate structures and an oxide layer. The substrate comprises a plurality of active areas extending parallel to each other and alternately along a first direction. The shallow trench isolation is arranged in the substrate and surrounds all the active areas. The gate structure is arranged in the substrate, and each of the gate structures extends parallel to each other along a second direction and is interlaced with the shallow trench isolation and the active area. Each of the gate structures comprises a gate dielectric layer, a gate electrode layer and a cap layer stacked in sequence, and the thickness of the portion of the gate dielectric layer contacting the active area is greater than the thickness of the portion of the gate dielectric layer contacting the shallow trench isolation. The oxide layer is arranged between each of the gate structures and each of the active areas, and between each of the gate structures and the shallow trench isolation. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings provide a deeper understanding of these embodiments and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all figures are schematic and relative sizes and proportions have been adjusted for ease of illustration and drawing. The same symbols in different embodiments represent corresponding or similar features.

[0007] Figures 1 to 6 FIG2 is a schematic diagram of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention, wherein:

[0008] Figure 1 is a schematic top view of a semiconductor memory device after gate trenches are formed;

[0009] Figure 2 for Figure 1 A schematic cross-sectional view along the tangent line AA'; and

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor memory device after forming a semiconductor layer;

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor memory device after an oxide material layer is formed;

[0012] Figure 5 is a schematic cross-sectional view of a semiconductor memory device after an oxide layer is formed; and

[0013] Figure 6 It is a cross-sectional schematic diagram of the semiconductor memory device after the gate structure is formed.

[0014] Figures 7 and 8 FIG2 is a schematic diagram of a method for manufacturing a semiconductor memory device according to another embodiment of the present invention, wherein:

[0015] Figure 7 is a schematic cross-sectional view of a semiconductor memory device after an oxide layer is formed; and

[0016] Figure 8 It is a cross-sectional schematic diagram of the semiconductor memory device after the gate structure is formed.

[0017] Figure 9 FIG2 is a schematic diagram of a method for manufacturing a semiconductor memory device according to another embodiment of the present invention.

[0018] The description of the accompanying drawings is as follows:

[0019] 100 substrate

[0020] 101 active area

[0021] 110 Shallow Trench Isolation

[0022] 120 gate trench

[0023] 130 dielectric layer

[0024] 131 silicon oxide layer

[0025] 133 silicon nitride layer

[0026] 135 silicon oxide layer

[0027] 140 semiconductor layer

[0028] 150 Oxidation material layer

[0029] 155, 355 oxide layer

[0030] 160, 360 gate structure

[0031] 161, 361, 461 dielectric layer

[0032] 163, 363 gate insulation layer

[0033] 165, 365 gate electrode layer

[0034] 167, 367 cap layer

[0035] 200, 400, 500 semiconductor storage devices

[0036] 461a bottom

[0037] d1, d2 depth

[0038] D1, D2 directions

[0039] g1, g2 interval

[0040] T1, T2, T3 thickness

[0041] T4, T5 thickness

[0042] P1 Oxidation Process

[0043] P2 back etching process

[0044] w1, w2 width DETAILED DESCRIPTION

[0045] To help those skilled in the art further understand the present invention, several preferred embodiments of the present invention are listed below, along with the accompanying drawings, to provide a detailed description of the present invention's components and intended functions. Those skilled in the art can, without departing from the spirit of the present invention, refer to the following embodiments and replace, reorganize, or combine features from the various embodiments to create other embodiments.

[0046] Please refer to Figures 1 to 6 , which is a schematic diagram of the steps of a method for manufacturing a semiconductor memory device 200 according to an embodiment of the present invention, wherein Figure 1 is a top view of the semiconductor memory device 200 during the manufacturing stage. Figures 2 to 6 FIG is a cross-sectional view of the semiconductor memory device 200 during the manufacturing stage. Figure 1 and Figure 2 As shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate. At least one insulating region, such as shallow trench isolation (STI) 110, is formed in the substrate 100. A plurality of active areas (AA) 101 are defined on the substrate 100, and the STI 110 surrounds all of the active areas 101. The STI 110 is formed, for example, by first forming a plurality of trenches (not shown) in the substrate 100 by etching, and then filling the trenches with an insulating material (e.g., silicon oxide or silicon oxynitride, etc.), but the present invention is not limited thereto. In this embodiment, the active regions 101 extend in parallel along the same direction D1, and are alternately arranged in sequence in the direction D2 (x direction). The direction D1 intersects and is not perpendicular to the y direction or the x direction (direction D2), and preferably forms an angle θ with the direction D2 (x direction) of about 30 degrees to 80 degrees. Figure 1In addition, the active regions 101 preferably have the same gap, wherein the adjacent parts of the active regions 101 (body-to-body) in the direction D2 have a relatively small gap g1, while the adjacent parts of the active regions 101 (tip-to-tip) in the direction D1 have a relatively large gap g2, as shown in FIG. Figure 1 shown.

[0047] The substrate 100 is further covered with a dielectric layer 130, which may include a composite layer structure, such as, but not limited to, a silicon oxide layer 131-silicon nitride layer 133-silicon oxide layer 135 (oxide-nitride-oxide, ONO) structure. Next, an etching process is performed to form a plurality of gate trenches 120 in the substrate 100. Each gate trench 120 extends parallel to each other along a direction D2 and simultaneously crosses a plurality of active regions 101 and shallow trench isolations 110, such as Figure 1 As shown. It should be noted that due to the material difference between the substrate 100 and the shallow trench isolation 110, the etching process may have different etching rates when etching the substrate 100 and the shallow trench isolation 110. As a result, the portion of each gate trench 120 falling on the substrate 100 (i.e., the active area 101) may have a relatively small depth d1 and / or width w1, while the portion of each gate trench 120 falling on the shallow trench isolation 110 may have a relatively large depth d2 and / or width w2, as shown in FIG. Figure 2 As shown, but not limited to.

[0048] like Figure 3 As shown, a deposition process is performed to form a semiconductor layer 140 on the substrate 100, conformally covering the surfaces of the substrate 100 and each gate trench 120, and having a uniform thickness T1. In one embodiment, the semiconductor layer 140 includes a material such as silicon, polysilicon, doped silicon, silicon germanium, or silicon carbide, and preferably includes the same material as the substrate 100. For example, when the substrate 100 includes a silicon substrate, the semiconductor layer 140 may also include silicon, but is not limited thereto.

[0049] like Figure 4 As shown, another deposition process is performed to form an oxide material layer 150 on the substrate 100. The oxide material layer 150 is also conformally formed on the surfaces of the substrate 100 and each gate trench 120, and covers the semiconductor layer 140. In one embodiment, the oxide material layer 150 includes, for example, an insulating material, preferably the same material as the shallow trench isolation 110, such as silicon oxide, and has a uniform thickness T2, but is not limited thereto.

[0050] Then, if Figure 5As shown, an oxidation process P1, such as a thermal oxidation process, is performed to oxidize the semiconductor layer 140, thereby forming an oxide layer 155 together with the oxide material layer 150 thereon. In one embodiment, the oxide layer 155 comprises, for example, the same material as the shallow trench isolation 110 and the oxide material layer 150, such as silicon oxide, but is not limited thereto. Furthermore, because the oxide layer 155 is formed by the semiconductor layer 140 and the oxide material layer 150 reacting together through the oxidation process P1, the oxide layer 155 can have an overall uniform and relatively large thickness T3, which is significantly greater than the thickness T1 of the semiconductor layer 140 or the thickness T2 of the oxide material layer 150.

[0051] Subsequent, such as Figure 6As shown, after the oxide layer 155 is formed, a plurality of gate structures 160 are formed in the substrate 100 to fill the remaining space of each gate trench 120. Specifically, the method for manufacturing the gate structure 160 includes, but is not limited to, the following steps: first, a dielectric material layer (not shown) and a gate insulating material layer (not shown) are sequentially formed in each gate trench 120 to cover at least the entire surface of the gate trench 120, and the gate material layer (not shown) is formed to fill at least the remaining space of the gate trench 120. Next, an etch-back process is performed to remove the gate material layer and the gate insulating material layer located in the upper half of the gate trench 120, and then a covering material layer (not shown) is formed to fill at least the upper half of the gate trench 120. Afterwards, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove the covering material layer, the dielectric material layer, and the oxide layer 155 outside each gate trench 120. In this way, a dielectric layer 161 covering the entire surface of the gate trench 120, a gate insulation layer 163 covering the lower half of the gate trench 120, a gate electrode layer 165 filling the lower half of the gate trench 120, and a cap layer 167 filling the upper half of the gate trench 120 can be formed to form the gate structure 160. In one embodiment, the dielectric layer 161 includes a dielectric material such as silicon oxide or silicon oxynitride; the gate insulation layer 163 includes a high-k dielectric material different from the oxide layer 155, the dielectric layer 161, and the shallow trench isolation 110, and is selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2), and zirconium oxide-aluminum oxide-zirconium oxide (ZAZ), but is not limited thereto. In this embodiment, the dielectric layer 161 and the gate insulation layer 163 may together constitute the gate dielectric layer of each gate structure 160. Thus, the lower half of the gate dielectric layer (including the dielectric layer 161 and the gate insulation layer 163) is a composite layer structure having a relatively large thickness, while the upper half of the gate dielectric layer (including only the dielectric layer 161) is a single layer structure having a relatively small thickness. Therefore, the gate dielectric layer can effectively prevent current from leaking from the bottom of the gate structure 160. However, in another embodiment, the dielectric layer 161 may be omitted, so that each gate structure only includes the gate insulation layer 163 covering the surface of the lower half of the gate trench 120, the gate electrode layer 165 filling the lower half of the gate trench 120, and the cap layer 167 filling the upper half of the gate trench 120.In this way, the gate dielectric layer in the other embodiment only includes a single-layer structure (gate insulation layer 163) and has a relatively small thickness as a whole, wherein the gate dielectric layer includes, for example, dielectric materials such as silicon oxide or silicon oxynitride, or includes high dielectric constant dielectric materials such as hafnium oxide and hafnium silicon oxide, but is not limited to this.

[0052] It should be noted that, in this embodiment, the oxide layer 155 may entirely cover the surface of each gate trench 120 (including two opposite sidewalls and the bottom surface). Figure 6 The cross-sectional view shows a U-shaped structure, allowing each gate structure 160 to directly contact the underlying oxide layer 155. Thus, the oxide layer 155 can be disposed between each gate structure 160 and the active area 101, or between each gate structure 160 and the shallow trench isolation 110. This can further mitigate the STI seam problem that may arise between each gate structure 160 and the shallow trench isolation 110 when each gate trench 120 is located on the shallow trench isolation 110 and has a relatively large depth d2 and / or width w2, but the invention is not limited thereto.

[0053] Subsequently, bit lines (BL), storage node contacts (SNc), and storage nodes (SN) may be formed on the substrate 100 to complete the fabrication of the semiconductor memory device 200. It should be noted that in this embodiment, the surface of the cap layer 167 may be flush with the top surface of the substrate 100, so that each gate structure 160 within the substrate 100 is a buried gate and can serve as a wordline (WL) of the semiconductor memory device 200. Thus, each wordline (i.e., each gate structure 160) extends parallel to each other along a direction D2, thereby intersecting with multiple active regions 101 and shallow trench isolations 110. The semiconductor memory device 200 of this embodiment is, for example, a dynamic random access memory (DRAM) device, which includes at least one transistor element (not shown) and at least one capacitor element (not shown) to serve as the smallest component unit (memory cell) in the dynamic random access memory array and receive voltage information from the bit line and the word line.

[0054] Furthermore, it should be noted that during the fabrication of the semiconductor memory device 200 of this embodiment, an oxide layer 155 is formed within the gate trenches 120 through additional deposition and oxidation processes, covering the opposing sidewalls and bottom surface of each gate trench 120. Consequently, each gate structure 160 formed subsequently is formed on and in direct contact with the oxide layer 155. In this manner, even if the portion of each gate trench 120 that falls within the shallow trench isolation 110 has a relatively large depth d2 and / or width w2, the additionally formed oxide layer 155 can fill the gap, thereby preventing the aforementioned seam problem between each gate structure 160 and the shallow trench isolation 110, particularly when each gate structure 160 passes through a location with a large gap g2 between active regions 101. Thus, the fabrication method of this embodiment can effectively improve the device reliability and operational performance of the fabricated semiconductor memory device 200.

[0055] Furthermore, those skilled in the art will readily appreciate that, to meet actual product requirements, the semiconductor memory device fabrication method of the present invention may also have other aspects, not limited to the aforementioned. The following further describes other embodiments or variations of the semiconductor memory device method of the present invention. To simplify the description, the following description primarily details the differences between the various embodiments, without reiterating the similarities. Furthermore, identical components in the various embodiments of the present invention are designated with identical reference numerals to facilitate cross-reference between the various embodiments.

[0056] Please refer to Figures 7 and 8 FIG2 is a schematic diagram illustrating a method for manufacturing a semiconductor memory device 400 according to another embodiment of the present invention. The front-end manufacturing method of the semiconductor memory device 400 in this embodiment is substantially the same as the manufacturing method of the semiconductor memory device 200 in the aforementioned embodiment. Figures 1 to 5 The main difference between this embodiment and the previous embodiment is that the manufacturing method of this embodiment performs an additional etching process P2 after the oxidation process P1.

[0057] In detail, Figure 7 As shown, the oxide layer 155 covering the surface of the substrate 100 and the bottom surface of each gate trench 120 is removed by an additional etch-back process P2, forming an oxide layer 355 covering only two opposite sidewalls of each gate trench 120. Figure 8As shown, after the oxide layer 355 is formed, a plurality of gate structures 360 are formed in the substrate 100, filling the remaining space of each gate trench 120. Each gate structure 360 ​​sequentially includes a dielectric layer 361 covering the entire surface of the gate trench 120, a gate insulation layer 363 covering the lower half of the gate trench 120, a gate electrode layer 365 filling the lower half of the gate trench 120, and a cap layer 367 filling the upper half of the gate trench 120. The dielectric layer 361 and the gate insulation layer 363 can together constitute the gate dielectric layer of each gate structure 360. The specific manufacturing method and material selection of the gate structure 360 ​​are generally the same as those in the previous embodiment and will not be repeated here.

[0058] It should be noted that, in this embodiment, the oxide layer 355 only covers two opposite sidewalls of each gate trench 120 and exposes the bottom surface of each gate trench 120, so that the bottom of each gate structure 360 ​​can directly contact the shallow trench isolation 110 or each active area 101 below. Figure 8 As shown. Thus, the oxide layer 355 can also fill any gaps that may form between each gate structure 360 ​​and the shallow trench isolation 110. Furthermore, the oxide layer 355 is not disposed at the bottom of each gate structure 360, shortening the distance between each gate structure 360 ​​and the gate channel (not shown), thereby improving the degree of control each gate structure 360 ​​has over the gate channel. Subsequently, the bit lines, storage node plugs, and storage nodes can be formed on the substrate 100, completing the fabrication of the semiconductor memory device 400 to form a dynamic random access memory device.

[0059] In the manufacture of the semiconductor memory device 400 of the present embodiment, the oxide layer 155 is partially removed by an additional etch-back process P2, forming an oxide layer 355 that only covers the two opposite sidewalls of each gate trench 120. Under this operation, each gate structure 360 ​​formed subsequently will be directly formed on the shallow trench isolation 110 or each active area 101 and directly contact therewith. Under this operation, the oxide layer 355 can also be used to fill the seams that may be generated between each gate structure 160 and the shallow trench isolation 110. At the same time, the control degree of the gate structure 360 ​​over the gate channel can be improved. In this way, the manufacturing method of the semiconductor memory device 400 of the present embodiment can further improve the reliability and operating performance of the manufactured semiconductor memory device 400.

[0060] Please refer to Figure 9 , which depicts a schematic diagram of the steps of a method for manufacturing a semiconductor memory device 500 according to another embodiment of the present invention. The method for manufacturing the semiconductor memory device 500 in this embodiment is substantially the same as the method for manufacturing the semiconductor memory device 400 in the aforementioned embodiment. Figure 7The main difference between this embodiment and the above-mentioned embodiment is that the manufacturing method of this embodiment forms at least a portion of the gate dielectric layer through another thermal oxidation process after the etch-back process P2.

[0061] Specifically, the manufacturing method of this embodiment is to form a dielectric layer 461 covering the entire surface of the gate trench 120 through the other thermal oxidation process, and then sequentially form a gate insulation layer 363 covering the surface of the lower half of the gate trench 120, a gate electrode layer 365 filling the lower half of the gate trench 120, and a cap layer 367 filling the upper half of the gate trench 120 to form a gate structure 460, wherein the dielectric layer 461 and the gate insulation layer 363 can together constitute the gate dielectric layer of each gate structure 460. The specific manufacturing method and material selection of the gate structure 460 are generally the same as those of the aforementioned embodiment and will not be repeated here. Thereafter, the bit line, the storage node plug, and the storage node can be formed on the substrate 100 to complete the manufacturing of the semiconductor memory device 500 to constitute a dynamic random access memory device.

[0062] It should be noted that in this embodiment, since the dielectric layer 461 is formed through the thermal oxidation process, the portion of the dielectric layer 461 that directly contacts the shallow trench isolation 110 (including silicon oxide material) or the oxide layer 355 (including silicon oxide material) may have a relatively small thickness T4, while the portion of the dielectric layer 461 that directly contacts the active area 101 (including materials such as silicon, polysilicon, doped silicon, silicon germanium or silicon carbide) may have a relatively large thickness T5, so that the gate dielectric layer may have a relatively large bottom 460a (dielectric layer 461 with a thickness of T5 and gate insulation layer 363) and a relatively small sidewall thickness (dielectric layer 461 with a thickness of T4 and gate insulation layer 363) at the portion where each gate structure 460 intersects with each active area 101. In addition, the thickness of the bottom 460a of the gate dielectric layer is also greater than the thickness of the gate dielectric layer at the portion where each gate structure 460 intersects with the shallow trench isolation 110, as shown in FIG. Figure 9 As shown. In this way, the gate dielectric layer can have a more uniform and flat thickness, and the bottom 460a that is locally thickened through the dielectric layer 461 can further prevent current from leaking from the bottom of each gate structure 460 (especially the corner of each gate trench 120). In addition, in this embodiment, the oxide layer 355 also only covers the two opposite sidewalls of each gate trench 120 and exposes the bottom surface of each gate trench 120, so that the bottom of each gate structure 460 can also directly contact the shallow trench isolation 110 or substrate 100 below, as shown. Figure 9As shown, this helps improve the control of each gate structure 460 over the gate channel. However, in another embodiment, the dielectric layer 461 can be omitted, and a gate insulation layer (including silicon oxide, not shown) can be formed through the thermal oxidation process to cover the lower half of the gate trench 120. This allows the gate insulation layer to have a relatively large thickness at the bottom directly contacting the active area 101. In this way, the locally thickened bottom of the gate insulation layer can maintain a certain degree of control over the gate channel by the gate structure while preventing bottom leakage.

[0063] In the manufacture of the semiconductor memory device 500 of the present embodiment, the gate dielectric layer or at least a portion of the gate dielectric layer is formed by the thermal oxidation process. In this way, the bottom thickness of the portion where the gate dielectric layer intersects with each active area 101 can be greater than the bottom thickness of the portion where the gate dielectric layer intersects with the shallow trench isolation 110. In this operation, the oxide layer 355 can also be used to fill the joints that may be generated between each gate structure 460 and the shallow trench isolation 110, thereby maintaining the control of each gate structure 460 over the gate channel and, at the same time, preventing current from leaking from the bottom 460a of each gate structure 460 (especially the corners of each gate trench 120). In this way, the manufacturing method of the present embodiment can also improve the reliability and operating performance of the manufactured semiconductor memory device 500.

[0064] In general, the present invention forms an oxide layer covering the entire surface of the gate trench through additional deposition and oxidation processes before forming the word lines, or forms an oxide layer covering only two opposing sidewalls of the gate trench through additional deposition, oxidation, and etch-back processes. This additional oxide layer can fill the gaps that may arise between the word lines and the shallow trench isolation (STI), while also preventing excessive resistance increases. Thus, the semiconductor memory device fabrication method of the present invention is beneficial for improving the reliability and operational performance of the resulting semiconductor memory device.

[0065] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor memory device, characterized in that include: Providing a substrate, on which a plurality of active regions are formed, wherein the active regions are parallel to each other and extend alternately along a first direction; forming shallow trench isolation in the substrate, surrounding all the active areas; forming a plurality of gate trenches in the substrate, wherein the gate trenches extend parallel to each other along the second direction and pass through the shallow trench isolation and the active area; forming a semiconductor layer on the substrate, wherein the semiconductor layer covers each of the gate trenches and the surface of the substrate; Oxidizing the semiconductor layer into an oxide layer, wherein the oxide layer covers the surface of each gate trench; as well as A plurality of gate structures are formed in the substrate, each of the gate structures fills each of the gate trenches and is isolated from the shallow trenches and interlaced with the active area.

2. The method for manufacturing a semiconductor memory device according to claim 1, wherein: The thickness of the oxide layer is greater than the thickness of the semiconductor layer.

3. The method for manufacturing a semiconductor memory device according to claim 1, wherein: Also includes: forming an oxide material layer on the semiconductor layer, wherein the oxide material layer and the shallow trench isolation are made of the same material; as well as A thermal oxidation process is performed to oxidize the semiconductor layer and the oxidation material layer together to form the oxide layer.

4. The method for manufacturing a semiconductor memory device according to claim 3, wherein: The gate structure is formed after the oxide layer is formed.

5. The method for manufacturing a semiconductor memory device according to claim 3, wherein: The oxide layer covers the surfaces of two opposite side walls and the bottom surface of each gate trench.

6. The method for manufacturing a semiconductor memory device according to claim 5, wherein: The bottom of each gate structure directly contacts the oxide layer.

7. The method for manufacturing a semiconductor memory device according to claim 5, wherein: Also includes: After the thermal oxidation process, an etch-back process is performed to remove the oxide layer covering the bottom surface of each gate trench.

8. The method for manufacturing a semiconductor memory device according to claim 7, wherein: The bottom of each gate structure directly contacts the shallow trench isolation.

9. The method for manufacturing a semiconductor memory device according to claim 7, wherein: Also includes: After the etch-back process, another thermal oxidation process is performed to form a gate dielectric layer, wherein the thickness of the portion of the gate dielectric layer contacting the active area is greater than the thickness of the portion of the gate dielectric layer contacting the shallow trench isolation.

10. The method for manufacturing a semiconductor memory device according to claim 9, wherein: The gate dielectric layer comprises a composite layer structure including a dielectric layer and a gate insulating layer stacked in sequence. The dielectric layer has a locally thickened bottom. The gate insulating layer is made of a high-k dielectric material.

11. The method for manufacturing a semiconductor memory device according to claim 9, wherein: The gate dielectric layer comprises a single-layer structure including a gate insulating layer with a locally thickened bottom.

12. A semiconductor memory device, characterized in that: include: A substrate comprising a plurality of active regions extending parallel to each other and alternately along a first direction; Shallow trench isolation, disposed in the substrate and surrounding all the active areas; a plurality of gate structures disposed in the substrate, each of the gate structures extending parallel to one another along a second direction and intersecting the shallow trench isolation and the active area, wherein each of the gate structures comprises a gate dielectric layer, a gate electrode layer, and a cap layer stacked in sequence, wherein a thickness of a portion of the gate dielectric layer contacting the active area is greater than a thickness of a portion of the gate dielectric layer contacting the shallow trench isolation; and a depth of a portion of the gate structure located above the active area is less than a depth of a portion of the gate structure located above the shallow trench isolation; as well as, An oxide layer is disposed between each gate structure and each active area, and between each gate structure and the shallow trench isolation.

13. The semiconductor memory device according to claim 12, wherein The gate dielectric layer comprises a composite layer structure including a dielectric layer and a gate insulating layer stacked in sequence, and the dielectric layer has a locally thickened bottom.

14. The semiconductor memory device according to claim 12, wherein The gate dielectric layer comprises a single-layer structure including a gate insulating layer with a locally thickened bottom.

15. The semiconductor memory device according to claim 12, wherein The oxide layer is disposed on two opposite side walls of each gate structure.

16. The semiconductor memory device according to claim 13, wherein The oxide layer and the shallow trench isolation include the same material, which is different from the material of the gate insulation layer.

17. The semiconductor memory device according to claim 13, wherein The gate insulating layer is made of a high-k dielectric material.

18. The semiconductor memory device according to claim 14, wherein The gate dielectric layer includes silicon oxide.

Images