Chip module, use of a chip module, test arrangement and test method

Abstract

A chip module comprises a chip (1) having a front side (11) and a back side (12), a chip carrier (2) having an upper side (21) facing the chip (1), a contact layer (3) formed of an electrically conductive material and arranged on the upper side (21) of the chip carrier (2) between the back side (12) of the chip (1) and the upper side (21) of the chip carrier (2), and an electrically conductive adhesive (4) arranged on an upper side (321) of the contact layer (3) facing the chip (1). The electrically conductive adhesive (4) connects the upper side (321) of the contact layer (3) and the back side (12) of the chip (1). The contact layer (3) has a plurality of regions (3A, 3B) which are electrically isolated from each other and each electrically connected to the chip (1) by the electrically conductive adhesive (4).

Description

TECHNICAL FIELD

[0001] The present application relates to a chip module, a use of such a chip module, a test arrangement for testing contacts of a chip module, and a test method for testing contacts of a chip module. BACKGROUND

[0002] Semiconductor components usually use the front side of a wafer or chip for arranging electrically conductive active elements. These semiconductor components are mounted on a chip carrier and electrically contact the chip carrier. Many of these semiconductor components require electrically conductive contacts to be made on the back side of the chip. To ensure good electrical contact, the wafer back is usually metallized, typically by means of a metal interlayer with a final gold surface.

[0003] The connection between chip and chip carrier has to fulfill two basic functions. In this context, on the one hand, a sufficient mechanical connection has to be established to ensure strength, in particular adhesive strength, under the conditions of use of the component. Furthermore, this connection should ensure a stable electrical connection under the conditions of use. The combination of these two functions puts high demands on adhesive connections or soldered or sintered connections. SUMMARY

[0004] A chip module comprises a chip having a front side and a back side, a chip carrier having an upper side facing the chip, a contact layer formed of an electrically conductive material and arranged on the upper side of the chip carrier between the back side of the chip and the upper side of the chip carrier, and an electrically conductive adhesive arranged on the upper side of the contact layer facing the chip. The electrically conductive adhesive connects the upper side of the contact layer and the back side of the chip. The contact layer has a plurality of regions which are electrically isolated from each other and each electrically connected to the chip by the electrically conductive adhesive. BRIEF DESCRIPTION OF DRAWINGS

[0005] The application will now be described by way of example with reference to the accompanying drawings, in which:

[0006] Figure 1 is a schematic plan view of a chip module according to an embodiment;

[0007] Figure 2 is a schematic plan view of a chip module without a chip Figure 1 is a sectional side view of the chip module of

[0008] Figure 3 is a sectional side view of the chip module of Figure 2 with an electrically conductive adhesive;

[0009] Figure 4 is a sectional side view of the chip module of Figure 3 with a chip;

[0010] Figure 5 is a sectional side view of the chip module of Figure 4 with a housing;

[0011] Figure 6 is a cross-sectional side view of a chip module with solder balls Figure 5

[0012] Figure 7 is a schematic plan view of a chip module according to another embodiment

[0013] Figure 8 is a cross-sectional side view of a chip module without a chip Figure 7

[0014] is a cross-sectional side view of a chip module with a conductive adhesive Figure 9 Figure 8

[0015] Figure 10 is a cross-sectional side view of a chip module with a chip Figure 9

[0016] Figure 11 is a cross-sectional side view of a chip module with a housing Figure 11

[0017] is a cross-sectional side view of a chip module with solder balls Figure 12 Figure 12

[0018] Figure 13 is a schematic plan view of a chip module according to another embodiment

[0019] Figure 14 is a cross-sectional side view of a chip module without a chip Figure 13

[0020] Figure 15 is a cross-sectional side view of a chip module with a non-conductive adhesive Figure 14

[0021] is a cross-sectional side view of a chip module with a chip Figure 16 Figure 15 is a cross-sectional side view of a chip module with a conductive adhesive

[0022] Figure 17 Figure 16

[0023] Figure 18 is a cross-sectional side view of a chip module with a housing Figure 17

[0024] is a schematic cross-sectional side view of a test arrangement with a chip module according to an embodiment Figure 19

[0025] ​​​​​​​​​​​Figure 20 is a schematic cross-sectional side view of a test arrangement with a chip module according to another embodiment;

[0026] Figure 21 is a schematic cross-sectional side view of a test arrangement with a chip module according to another embodiment; and

[0027] Figure 22 is a schematic cross-sectional side view of a test arrangement with a chip module according to another embodiment. DETAILED DESCRIPTION

[0028] The application will be explained in more detail below with reference to the drawings. Identical parts have identical reference signs and identical part names. Furthermore, some features or combinations of features from the different embodiments shown and described can represent independent solutions according to the application themselves. Repetitively occurring features have identical reference signs.

[0029] Figure 1 A schematic view of the chip module is shown in a plan view. The chip module comprises a chip 1, which is outlined in a dashed line and shown transparently in Figure 1 order to reveal the underlying structure. In addition, the chip module comprises a chip carrier 2, on an upper side 21 of which a contact layer 3 is arranged. The contact layer 3 is electrically conductive.

[0030] The contact layer 3 comprises at least three, and in the embodiment shown four, regions 3A, 3B, 3C, 3D, which in the embodiment shown are electrically isolated from one another. In the present example, the regions 3A to 3D, which are electrically isolated from one another, are rectangular. In other examples, these regions 3A to 3D can also have other shapes, for example square, circular, elliptical or a combination of these shapes. The regions 3A to 3D each protrude beyond the chip 1. In other embodiments, the contact layer 3 can have more than four mutually isolated regions. Regions which are isolated from one another can also be referred to as contact regions.

[0031] In one embodiment, the length of the chip 1 can be at least 1 mm, at least 1.5 mm, or at least 2 mm. Additionally or alternatively, the length of the chip 1 can be at most 200 mm, at most 100 mm, or at most 50 mm. However, chips 1 having larger dimensions can also be processed. In one embodiment, the width of the chip 1 can be at least 1 mm, at least 1.5 mm, or at least 2 mm. Additionally or alternatively, the width of the chip 1 can be at most 200 mm, at most 100 mm, or at most 50 mm.

[0032] In Figure 1In the embodiment shown, the chip 1 has a width B1 of 8 mm and a length L1 of 15 mm. The contact layer 3 has a length L3 of 17 mm and a width B3 of 10 mm. The individual regions 3A-3D, which are isolated from one another, have the same dimensions. Each region 3A to 3D has a length L3A of 7.5 mm and a width B3A of 4 mm.

[0033] In the present case, the chip 1 is to be understood to mean a microelectronic component, in particular a semiconductor chip or a microsystem. The chip 1 has a front side 11 and a back side 12. The front side 11 usually carries an active semiconductor structure. The chip 1 can have electrical contact pieces on its back side, for example for supplying voltage to electrical components or microsystems integrated in the chip and / or for communication with the electrical components and / or microsystems. Additionally or alternatively, the chip 1 can have further electrical contact pieces on its front side.

[0034] In the present example, the chip carrier 2 comprises FR4 or a derivative thereof. FR4 is a printed circuit board substrate, for example a glass fiber reinforced epoxy resin laminate. Embodiments consisting of or comprising ceramic are also possible. Through-holes, which allow the plated-through holes 31, are provided in the chip carrier 2. In each of the mutually insulated regions 3A to 3D, the contact layer 3 has a plated-through hole 31, which connects a contact surface 32 arranged on the upper side 21 of the chip carrier 2 to the bottom side 22 of the chip carrier 2. This can have the advantage that each of the regions 3A to 3D, which are isolated from one another, can be electrically controlled independently of one another via the plated-through holes 31. On the bottom side of the chip 2, the contact layer 3 has a solder surface 33 at the lower end of the plated-through hole 31, as is shown in Figure 2

[0035] In one embodiment, the chip 1 and the contact layer 3 are arranged centrally to one another such that a surface center point of the upper side of the contact layer 3 is at a minimum distance from a surface center point of the back side 12 of the chip 1. The contact layer 3 comprises regions 3A-3D, which are electrically isolated from one another, such that a surface of the contact layer 3 is defined by the outer edges of the regions, which are electrically isolated from one another. The center point of the surface of the contact layer 3, which is defined in this way, is thus located in one of the regions 3A-3D, which are isolated from one another, but can also be located in a region between the regions 3A-3D, which are isolated from one another.

[0036] The electrically conductive adhesive 4 is arranged on the upper side of the contact layer 3 - more precisely, on each of the upper sides 321 of the respective contact surfaces 32. This is shown in Figure 3 , which corresponds essentially to Figure 2 , but also shows the arrangement of the adhesive 4. In Figure 3 ​As can be seen, the adhesive 4 is arranged on the upper side 321 of the contact surface 32 such that the areas isolated from each other are not in contact with the adhesive. In embodiments, a conductive silver adhesive is chosen as the conductive adhesive 4. In this case, the conductive adhesive 4 can comprise a solder connection or a sinter layer or can be designed as a solder connection or a sinter connection.

[0037] The contact layer 4 can comprise, for example, gold and / or other noble metals and / or other metals. The conductive adhesive 4 can comprise, for example, one or several polymers, such as, for example, epoxy resins, acrylates, silicones, polyurethanes and / or esters. The conductive adhesive 4 can comprise silver particles and / or one or more other conductive substances, such as, for example, graphite. The conductive substance can be embedded in the polymer(s), in particular.

[0038] Figure 4 A cross-sectional view of the chip module of Figure 2 and Figure 3 is shown, the chip 1 also being shown. The back side 12 of the chip 1 rests on the conductive adhesive layer 4. In this way, the areas isolated from each other can contact different areas of the back side 12 of the chip. The contacts of the chip 1 arranged on the back side 12 can thus be electrically connected to the contact surface 32, the plated through hole 31 and the solder surface 33 via the conductive adhesive 4.

[0039] Figure 5 A cross-sectional view of the chip module of Figure 4 is shown, the housing 5 also being shown in the form of a potting housing. In the example shown, the housing 5 comprises an epoxy resin-based potting. In other examples, the housing 5 can comprise other materials, such as, for example, injection-molded materials, paints and coatings, and molding compounds. The molding compound can be a composite of plastic injection-molding compounds. The housing 5 at least partially, and in embodiments completely, encloses the chip 1 and the contact layer 3, in particular the areas of the contact layer 3 that are electrically isolated from each other. The housing 5 can be arranged, in particular, on the upper side of the chip carrier. The housing 5 can comprise a cover and / or a frame and / or a window and / or a window pane. The housing 5 can protect the chip 1 and the contact layer 3 from contamination and / or impacts.

[0040] The housing 5 as shown in Figure 5 has an optical window 51. The optical window 51 is arranged on the front side 11 of the chip 1 such that it can be used, for example, in a LIDAR sensor. LIDAR sensors are used for light detection and ranging, in which distances are determined by means of light. The housing 5 can comprise, for example, one or more window panes. In addition, the housing 5 can comprise light sources, such as, for example, emitters, laser chips and / or further chips, such as, for example, temperature sensors. The light sources, such as, for example, in the form of emitters, laser chips and / or further chips, such as, for example, temperature sensors, can additionally or alternatively be mounted on the housing 5.

[0041] In Figure 6In a further embodiment, the solder balls 34 can be arranged as a replacement for the solder surfaces 33. An advantage is that the chip module can be arranged on a circuit board with correspondingly arranged contacts and connected to these in a simple manner, for example by fusing the solder surfaces 33 and / or the solder balls 34 with the contacts, for example to form a so-called ball grid array. With larger chip or housing edge lengths, different thermal expansions can have a greater effect. Solder balls or ball grid arrays (BGA) arranged in a matrix can be used to reduce thermal mechanical stress.

[0042] The chip module can comprise one or more further chips 1. The features of the present application described in relation to one of the chips 2 can be applied analogously to at least one further chip, or to a plurality of further chips. In an embodiment in which the chip module comprises a plurality of chips 1, the chips 1 can have different properties. For example, one or more sensor chips, an ASIC for signal evaluation, one or more temperature sensors, and / or one or more LEDs as light sources can be provided. Chips of the same type can also be built into the chip module.

[0043] In an embodiment, the chip module can comprise a passivation. The chip module can be protected from the environment by the passivation. The passivation can be, for example, a lacquer, a conformal coating, a potting, a glob top, an underfill or a molding compound applied over the entire surface or a portion thereof. A conformal coating adapts to the surface structure underneath, a glob top covers or completely encloses the bond connections or the chip and can be formed from a plastic material. An underfill is a polymer that flows between the chip 1 and the chip carrier and binds them together; the underfill can serve as an additional mechanical fixation and / or for filling cavities.

[0044] Figure 7 A chip module is shown which substantially corresponds to Figures 1 to 5 The lateral dimension of the chip 1 is greater than the lateral dimension of the contact layer 3. The chip 1 therefore protrudes beyond the outer edges of the contact surface 3. Figures 7-10 A cross-sectional view is shown of Figure 6 The structure of the chip module corresponds to the structure of the chip module in Figures 1-5 The embodiment in Figures 7-12 corresponds substantially to the example embodiment in Figures 2-5 , in which the lateral dimensions of the chip 1 and the contact surface 32 differ from the lateral dimensions in the example in Figures 1-5 . The lateral dimensions of the chip 1 and the contact area 32 are designed such that the chip 1 protrudes beyond the edges of the contact area 3 and covers them.

[0045] Figures 7-12The chip 1 shown has a width B1 of 20 mm and a length L1 of 40 mm. The contact layer 3 has a length L3 of 20 mm and a width B3 of 10 mm. The individual regions 3A-3D, which are isolated from one another, have the same dimensions. Each region 3A to 3D has a length L3A of 8 mm and a width B3A of 4 mm. With regard to Figures 8 to 12 further features, reference is therefore made to the description of Figures 2-6 with reference to the drawings, in which the same reference signs denote the same elements.

[0046] In the case of very small chips 1, in particular chips with an edge length of less than 2 mm, it can be technically more advantageous to make the contact layer 3 larger than the chip 2. On the other hand, in the case of very large chips, it can be advantageous to select the contact layer edge length to be smaller than the chip edge length, so that the influence of the different expansion behavior is less.

[0047] Figures 13 to 18 Further embodiments are shown in schematic illustrations. In Figure 13 the chip module is shown in plan view. Figures 14 to 18 The chip module is shown in cross-sectional view along the section line A-A, wherein Figure 14 only the chip carrier 2 and the contact layer 3' with plated vias 31' and solder surfaces 33' are shown. Figures 13 to 18 The chip module of Figures 1 to 5 corresponds essentially to the chip module of the features that occur repeatedly have the same reference signs.

[0048] Figures 13 to 18 The contact layer 3' of the regions 3A to 3D, the plated vias 31' and the solder surfaces 33' differ from the contact layer 3 of the previously described embodiments in the presence of channels 35, in particular in the form of through-holes that extend from the upper side of the contact layer 3' to the underside of the solder surfaces 33'.

[0049] Figure 15 Corresponding to Figure 14 a non-conductive adhesive 6 is also shown. The non-conductive adhesive 6 is arranged in sub-areas on the upper side of the mutually isolated regions 3A to 3D. The non-conductive adhesive 6 forms a substantially rectangular layer, which is centered with respect to the chip 1 and the contact layer 3'. The non-conductive adhesive 6 is arranged between the chip 1 and the contact layer 3. The contours of the screen-printed pattern of the non-conductive adhesive 6 are designed in such a way that the concentric channels 35 are not covered and not electrically connected to one another. The non-conductive adhesive 6 can consist, for example, of an unfilled or filled polymer, the filler being non-conductive. These fillers can be inorganic, for example silicon oxide or aluminum oxide, or further polymer. The non-conductive adhesive 6 can in particular be bubble-free, i.e. without air inclusions.

[0050] The chip 1 is also shown in Figure 16 In Figure 17In the middle, the electrically conductive adhesive 4 is arranged in the area on the contact layer 3' and in the channel 35. The bottom side of the chip module, in particular the bottom side 22 of the chip carrier 2, is thus electrically connected to the chip back side 12 via the solder surface 33' and via the electric adhesive 4. Figure 18 A sectional view is shown Figure 17 of a chip module according to the preceding embodiment. The chip module also has a housing 5. The housing 5 corresponds to the housing 5 of the preceding embodiment.

[0051] The sensor can comprise a chip module according to the above-described embodiments. The chip module according to the preceding embodiments can in particular be used for optical sensors, in particular LIDAR sensors. These can be used, for example, in vehicle information or safety systems, for example distance warning systems, and in the field of autonomous driving.

[0052] Figure 19 A test arrangement is shown, which has a contact area 3 arranged on the upper side of the chip carrier 2. The test arrangement serves for monitoring the chip 1 contacts and / or for locating defects in the chip 1 contacts. The test arrangement is shown schematically in a sectional view. The electrically conductive adhesive 4 is arranged on the upper side of the contact surface 3. The chip 1 is arranged on the upper side of the electrically conductive adhesive layer 4 and its lateral dimensions are smaller than the contact surface 3 which projects beyond the chip 1. The contact layer 3 is divided into four areas 3A, 3B, 3C, 3D which are electrically isolated from one another. The electrical connection elements 7 - in the example shown first and second contact pins 71, 72 - each make contact with the areas 3A and 3B, respectively. The contact pins 71 and 72 are connected to a current meter A or current measuring device for measuring a test current 8 between the first and second contact pins 71, 72. The flow of the test current 8 is shown.

[0053] Figure 20 Another possibility for measuring a test current between the electrical connection elements 7 is shown. Figure 20 The test arrangement according to Figure 5 comprises a chip module according to the preceding embodiment. The electrical connection elements 7 are each electrically connected to the solder surface 33, so that the test current 8 can be sent and measured by the current meter A.

[0054] Figure 21 A test arrangement according to the preceding figures is shown, which test arrangement comprises a chip module according to the preceding embodiment. The electrical connection elements 7 are electrically connected to the solder balls 3. Figure 6

[0055] Figure 22 ​The test arrangement is shown, substantially corresponding to the previous figures. The chip carrier 2 also has electrical contact elements 10, which include an upper contact surface 101, a plated through-hole 102, and a lower solder surface 103. The upper contact surface 101 is disposed on the upper side 21 of the chip carrier 2. The lower solder surface 22 is disposed on the bottom side 22 of the chip carrier 2. The plated through-hole 102 is disposed in a channel 35, specifically in a through-hole in the chip carrier 2, and electrically connects the contact surface 101 to the solder surface 103. On the upper side of the chip 1, the front contact of the chip 1 is electrically connected to the upper contact surface 101 via bonding wires 9. Electrical connection elements 7 are electrically connected to the solder surface 33 or the solder surface 103 via solder balls 34 and 104, respectively, so that a test current 8 can be transmitted and measured by a galvanometer A. In this case, the current to the rear side 12 of the chip is measured via the bonding wires 9 through the chip 1 and via the front contact.

[0056] It should be noted that, Figures 20 to 22 The test setup shows the chip module, whose plated vias 31 do not have corresponding... Figures 13 to 18 Channel 35 is shown as channel 35. Of course, the test arrangement described can alternatively include, according to... Figures 13-18 The chip module. Figures 19 to 22 The illustrations of the chip modules should not be interpreted as restrictive, but rather as examples.

[0057] Figures 19-22 Each test setup includes a voltage source U. Of course, any test setup in the previous figures may also include this voltage source U. The test setups shown are suitable for testing methods to monitor chip contacts and / or for locating defects in chip contacts, particularly defective areas of the chip contacts.

[0058] First, a test current 8 is measured between the first and second connecting elements 7, such as the test current 8 of the first and second contact pins 71, 72. The measured test current 8 can then be compared with a predefined threshold. If the measured value is greater than the threshold, a defect is indicated. Additional test currents 8 can be measured before other connecting elements 7. The test currents 8 can be compared individually with thresholds or with each other. Defects are located by assigning the measured values ​​to the positions of the contact layer 3.

[0059] A tolerance range can be defined around a predetermined average value. It can be specified that a test current 8 outside the tolerance range indicates a defect. A localized area of ​​chip 1 can be assigned to these predetermined test currents 8. A warning signal can indicate a defective contact in a localized area of ​​chip 1.

[0060] The resistance can first be calculated from the measured test current 8. The calculated resistance can be compared to a threshold value. A deviation from the threshold value can indicate a defect in the respective contact. A warning signal can be output to a higher-level system or a user. For example, a limit of 100 Ω.

[0061] The electrically conductive adhesive 4 can in particular have a threshold value in the low ohm range. In the event of a fault, the threshold value of the electrical contact can be in the mega-ohm or giga-ohm range. The electrical resistance of the electrical contacts on the back side of the chip 1 is usually in the lower ohm range. Depending on the chip area on the back side, these are usually less than 1 ohm.

[0062] If the connection to the back side of the chip fails, the electrical resistance can increase by a factor of 1000 to 1,000,000 or more. This increase can be easily detected electronically. When graphite or aluminum-filled adhesives are used, they are usually less conductive. They are then mostly in the range of kilo-ohms to mega-ohms. The threshold value can also depend on environmental influences, such as humidity.

[0063] The threshold value can thus be product-specific. In particular, the threshold value can be at least 0.1 Ω, at least 0.5 Ω, or at least 1 Ω. The threshold value can be less than 100 MΩ, less than 100 kΩ, or less than 100 Ω.

[0064] Errors can be predicted by repeating and comparing measurements. To this end, for example, the test current of a first measurement can be compared to a second test current measured at a later point in time. The first and second test currents are measured between the same insulating regions or between the same insulating regions and the electrical contact elements of the chip carrier.

[0065] The test method is particularly suitable for contact testing during and / or after the manufacturing process of a chip module. In this case, the contact resistances of at least two or more contact areas 3A to 3D insulated from one another can be compared to one another or to a good / bad value by means of current-voltage measurements. Such measurements can be integrated as sample measurements into the manufacturing process. It can also be provided that, during the manufacturing process of a chip module, all or almost all contacts are checked in accordance with the test method.

[0066] The test procedure can be carried out as part of the quality control of a chip module. After the module has been completed, in the so-called final test, the contact resistances of at least two or more insulated contact surfaces can be compared to one another or to at least one threshold value, for example in the form of a good / bad value, by means of current-voltage measurements using suitable contact and measurement devices, for example the test arrangement described. Such measurements can be integrated as sample measurements into the quality control process. It can also be provided that, during the quality control of a chip module, all or almost all contacts are checked in accordance with the test method.

[0067] The test procedure can be carried out as part of a reliability test for the development, modification, qualification and quality assurance of the chip module. Using suitable contact and measurement means, in particular the test arrangement described above, the contact resistance of at least two or more insulating contact surfaces can be detected by means of current-voltage measurements. This can take place as a function of various parameters, such as time, temperature, humidity, etc. The measurement value detection can take place continuously.

[0068] In an embodiment, the described test method can be applied while using the chip module, for example in a LIDAR sensor. The measurement value detection can take place continuously. If a specified threshold value is exceeded or undershot, a warning can be sent to a higher-level system. This is particularly advantageous for safety-relevant systems, for example in a vehicle safety system. For example, a malfunction of individual contacts of the chip module can be detected and localized, preferably in real time, and a warning signal can be used to signal to a user or system a malfunction or loss of quality of certain contacts. Thus, in addition to sudden malfunctions of the chip module, the test method can also detect early malfunctions of the chip module.

[0069] The invention improves the stability and reliability of the connection between the chip 1 and the chip carrier and / or creates the possibility of checking the state of this electrical and mechanical connection, in particular permanently monitoring it.

[0070] The basic function of the secure backside contacts of the chip 1 can not only be tested in the manufacturing process itself, but also this test can be permanently carried out in the application - i.e. while the chip module is being used, for example in a motor vehicle or a drone, and again, for example in a LIDAR sensor. This can provide the possibility of detecting malfunctions early and reacting accordingly, in particular in the case of safety-critical applications.

Claims

1. A chip module, comprising: a chip (1) having a front side (11) and a back side (12); a chip carrier (2) having an upper side (21) facing the chip (1); a contact layer (3) formed of an electrically conductive material and arranged on the upper side (21) of the chip carrier (2) between the back side (12) of the chip (1) and the upper side (21) of the chip carrier (2); and an electrically conductive adhesive (4) arranged on an upper side (321) of the contact layer (3) facing the chip (1), the electrically conductive adhesive (4) connecting the upper side (321) of the contact layer (3) and the back side (12) of the chip (1), the contact layer (3) having a plurality of areas (3A, 3B) which are electrically isolated from each other and each electrically connected to the chip (1) by the electrically conductive adhesive (4); wherein at least two of the plurality of areas (3A, 3B) have a plated through hole (31) extending from the upper side (21) of the chip carrier (2) to a bottom side (22) of the chip carrier (2), the plated through hole (31) having a passage (35) extending through the plated through hole (31), the contact layer (3) being arranged in the passage (35) and between the plated through hole (31) and the chip (1); a non-conductive adhesive (6) arranged between the chip carrier (2) and the chip (1) and connecting the upper side (21) of the chip carrier (2) to the back side (12) of the chip (1), the non-conductive adhesive (6) being arranged on the contact layer (3) and in sub-areas on the upper sides of mutually isolated areas, the non-conductive adhesive (6) covering two adjacent mutually isolated areas. The plurality of areas (3A, 3B, 3C) is at least three areas.

2. The chip module of claim 1, wherein, The chip (1) has a length (LI) and / or a width (BI) which is smaller than a length (L3) and / or a width (B3) of the contact layer (3), and the contact layer (3) protrudes beyond the chip (1).

3. The chip module of claim 1, wherein, The chip (1) has a length (LI) and / or a width (BI) which is larger than a length (L3) and / or a width (B3) of the contact layer (3), and the chip (1) covers the contact layer (3).

4. The chip module of claim 1, wherein, The chip (1) is centered with the contact layer (3) in that a surface center point of the upper side (321) of the contact layer (3) is at a minimum distance from a surface center point of the back side (12) of the chip (1), the surface of the contact layer (3) being defined by a plurality of outer edges of the plurality of areas (3A, 3B).

5. The chip module of claim 1, wherein, The plated through hole (31) has a solder surface (33) and / or a solder ball (34) on the bottom side (22) of the chip carrier (2).

6. The chip module of claim 1, wherein, ​ 7. The chip module of claim 1, wherein, The electrically conductive adhesive (4) is arranged in the passage (35) and / or between the plated through hole (31) and the back side (12) of the chip (1).

8. The chip module of claim 1, further comprising a housing (5) arranged on the upper side (21) of the chip carrier (2), the housing (5) enclosing the chip (1) and the contact layer (3).

9. The chip module of claim 8, wherein, The housing (5) has an optical window (51) at the front side (11) of the chip (1).

10. A test arrangement, comprising: a chip module comprising a chip (1) having a front side (11) and a back side (12); a chip carrier (2) having an upper side (21) facing the chip (1); a contact layer (3) formed of an electrically conductive material and arranged on the upper side (21) of the chip carrier (2) between the back side (12) of the chip (1) and the upper side (21) of the chip carrier (2); an electrically conductive adhesive (4) arranged on an upper side (321) of the contact layer (3) facing the chip (1), the electrically conductive adhesive (4) connecting the upper side (321) of the contact layer (3) and the back side (12) of the chip (1), the contact layer (3) having a plurality of regions (3A, 3B) electrically isolated from each other and each electrically connected to the chip (1) by the electrically conductive adhesive (4), wherein at least two of the plurality of regions (3A, 3B) have a plated through hole (31) extending from the upper side (21) of the chip carrier (2) to a bottom side (22) of the chip carrier (2), the plated through hole (31) having a passage (35) extending through the plated through hole (31), the contact layer (3) being arranged in the passage (35) and between the plated through hole (31) and the chip (1); and a non-conductive adhesive (6) arranged between the chip carrier (2) and the chip (1) and connecting the upper side (21) of the chip carrier (2) to the back side (12) of the chip (1), the non-conductive adhesive (6) being arranged on the contact layer (3) and in sub-regions on the upper sides of mutually isolated regions, the non-conductive adhesive (6) covering two adjacent mutually isolated regions; a first electrical connection element (71) in electrical contact with a first region (3A) of the plurality of regions (3A, 3B); a second electrical connection element (72) in electrical contact with a second region (3B) of the plurality of regions (3A, 3B) or in electrical contact with an electrical contact element (10) of the chip carrier (2); and a current measuring device (A) electrically connected to the first electrical connection element (71) and the second electrical connection element (72), the current measuring device (A) measuring a test current (8) between the first electrical connection element (71) and the second electrical connection element (72).

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