Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate including a first device region for forming a first device and a second device region for forming a second device, wherein the channel length of the first device is greater than that of the second device; a polysilicon gate layer located on the substrate in the first device region, including a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer enclosing a groove, and both the top gate layer and the bottom gate layer are doped with conductive ions; a metal gate layer located on the substrate in the second device region; and an interlayer dielectric layer located on the substrate on the sides of the polysilicon gate layer and the metal gate layer and filling the groove. In the present invention, the top gate layer is used to improve the problem of the top surface depression of the polysilicon gate layer, and by doping both the top gate layer and the bottom gate layer with conductive ions, the gate resistance of the polysilicon gate layer is reduced. In summary, the performance of the polysilicon gate layer is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In existing semiconductor devices, devices with different operating voltages are usually formed on a substrate. For example, low-voltage (LV) devices, high-voltage devices (HV), and medium-voltage (MV) devices.

[0003] With the development of semiconductor manufacturing technology, the critical dimensions of semiconductor devices are continuously reduced, resulting in a more and more serious gate depletion effect. In order to better overcome problems such as the gate depletion effect, the high-k gate dielectric layer followed by the formation of the gate electrode layer (high k last metal gate last) process and the replacement gate process have become commonly used processes.

[0004] Among them, compared with low-voltage devices, high-voltage devices and medium-voltage devices have higher operating voltages, and the sizes of high-voltage devices and medium-voltage devices are correspondingly larger. Therefore, polysilicon gates are still used for high-voltage devices and medium-voltage devices, while metal gates are used for low-voltage devices. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, embodiments of the present invention provide a semiconductor structure, including: a substrate, including a first device region for forming a first device and a second device region for forming a second device, the channel length of the first device being greater than the channel length of the second device; a polysilicon gate layer located on the substrate of the first device region, the polysilicon gate layer including a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer enclosing a groove, and both the top gate layer and the bottom gate layer being doped with conductive ions; a metal gate layer located on the substrate of the second device region; and an interlayer dielectric layer located on the substrate on the sides of the polysilicon gate layer and the metal gate layer and filling the groove.

[0007] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, including a first device region for forming a first device and a second device region for forming a second device, wherein a channel length of the first device is greater than a channel length of the second device; forming discrete polysilicon gate layers on the substrate in the first device region and the second device region, in the first device region, the polysilicon gate layer includes a bottom gate layer and a top gate layer protruding from the bottom gate layer, and the top gate layer and the bottom gate layer enclose a groove; injecting conductive ions into the polysilicon gate layer exposed by the groove, and an injection direction of the conductive ions has an acute angle with a normal direction of the bottom surface of the groove; after injecting the conductive ions into the polysilicon gate layer exposed by the groove, forming an interlayer dielectric layer on the substrate at a side portion of the polysilicon gate layer and in the groove, and the interlayer dielectric layer exposes a top of the polysilicon gate layer in the second device region; removing the polysilicon gate layer in the second device region, and forming a gate opening in the interlayer dielectric layer; and forming a metal gate layer in the gate opening.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present invention, the polysilicon gate layer in the first device region includes a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer enclose a groove, and both the top gate layer and the bottom gate layer are doped with conductive ions. Among them, compared with a polysilicon gate layer without a groove, a line width dimension of the top gate layer and a spacing between adjacent top gate layers (i.e., a line width dimension of the groove) in this embodiment are both smaller, thereby improving a problem of top surface depression (dishing) generated when forming the metal gate layer. Moreover, both the top gate layer and the bottom gate layer are doped with conductive ions, reducing the resistance of the polysilicon gate layer and correspondingly reducing the gate resistance of the first device. In addition, by providing the groove, the bottom of the groove exposes the bottom gate layer, and the side wall of the groove exposes the top gate layer. Therefore, conductive ions can be injected into the polysilicon gate layer through the bottom and side walls of the groove, so that both the top gate layer and the bottom gate layer have the conductive ions, which is beneficial to improving the ion concentration uniformity of the conductive ions in the polysilicon gate layer; in summary, the performance of the semiconductor structure can be improved; in addition, the injection process of the conductive ions and the process of forming the groove can share a photomask and a lithography process, thereby reducing costs.

[0010] In the formation method provided by the embodiment of the present invention, the polysilicon gate layer in the first device region includes a bottom gate layer and a top gate layer protruding from the bottom gate layer. A groove is formed between the top gate layer and the bottom gate layer. Subsequently, conductive ions are implanted into the polysilicon gate layer exposed by the groove, and the implantation direction of the conductive ions has an acute angle with the normal direction of the bottom surface of the groove. Since the polysilicon gate layer in the second device region will be removed subsequently to form a gate opening, and a metal gate layer is formed in the gate opening, and the process of forming the metal gate layer usually includes a planarization step. By forming a groove in the polysilicon gate layer in the first device region, the line width dimension of the top gate layer and the spacing between adjacent top gate layers (i.e., the line width dimension of the groove) are both small. Therefore, during the planarization process of forming the metal gate layer, it is beneficial to improve the problem of the top surface depression of the polysilicon gate layer in the first device region. In addition, the implantation direction of the conductive ions has an acute angle with the normal direction of the bottom surface of the groove, which enables the conductive ions to be implanted into the polysilicon gate layer through the bottom and side walls of the groove, so that both the top gate layer and the bottom gate layer contain the conductive ions, which is beneficial to improving the ion concentration uniformity of the conductive ions in the polysilicon gate layer and reducing the resistance of the polysilicon gate layer in the first device region, and correspondingly reducing the gate resistance of the first device. In summary, by forming a groove in the polysilicon gate layer in the first device region and making the implantation direction of the conductive ions have an acute angle with the normal direction of the bottom surface of the groove, the structural integrity and electrical performance of the polysilicon gate layer in the first device region are improved, which is beneficial to improving the performance of the semiconductor structure. Description of the Drawings

[0011] Figures 1 to 4 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

[0012] Figure 5 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention;

[0013] Figure 6 is a top view of the polysilicon gate layer in the first device region in an embodiment of the semiconductor structure of the present invention;

[0014] Figures 7 to 19 are schematic structural diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention;

[0015] Figure 20 is a schematic structural diagram of another embodiment of the method for forming a semiconductor structure of the present invention. Detailed Description of the Invention

[0016] As known from the background art, currently, polysilicon gates are used for high-voltage devices and medium-voltage devices, while metal gates are used for low-voltage devices. However, the performance of the current semiconductor structure is not good.

[0017] Now, in combination with a method for forming a semiconductor structure, the reasons for the performance to be improved are analyzed. Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0018] Refer to Figure 1 , a substrate 10 is provided, including a first device region 10M for forming a first device and a second device region 10L for forming a second device, and the channel length of the first device is greater than that of the second device.

[0019] Specifically, the operating voltage of the first device is greater than that of the second device. The first device includes one or both of a high-voltage device and a medium-voltage device, and the second device is a low-voltage device. Among them, the operating voltages of the low-voltage device, the medium-voltage device, and the high-voltage device increase in sequence.

[0020] Continue to refer to Figure 1 , a gate oxide material layer 20 is formed on the surface of the substrate 10 in the first device region 10M; a high-k gate dielectric material layer 21 covering the gate oxide material layer 20 and the substrate 10, a metal barrier material layer 22 covering the high-k gate dielectric material layer 21, and a polysilicon material layer 23 covering the metal barrier material layer 22 are formed.

[0021] It should be noted that according to process requirements, before forming the high-k gate dielectric material layer 21, another gate oxide material layer (not shown in the figure) can also be formed on the surface of the substrate 10 in the second device region 10L, and compared with the gate oxide material layer 20 in the first device region 10M, the thickness of the gate oxide material layer in the second device region 10L is smaller.

[0022] Continue to refer to Figure 1 , conductive ions are implanted into the polysilicon material layer 23 in the first device region 10M, and the conductive ions are used to reduce the resistance of the polysilicon material layer 23.

[0023] Refer to Figure 2 , after implanting conductive ions into the polysilicon material layer 23 in the first device region 10M, the polysilicon material layer 23, the metal barrier material layer 22, the high-k gate dielectric material layer 21, and the gate oxide material layer 20 are etched. A gate oxide layer 33 is formed on the substrate 10 in the first device region 10M, a high-k gate dielectric layer 34 is formed on the gate oxide layer 33 and on the substrate 10 in the second device region 10L, a metal barrier layer 35 is formed on the high-k gate dielectric layer 34, and a polysilicon gate layer 36 is formed on the metal barrier layer 35.

[0024] In the first device region 10M, the stacked gate oxide layer 33, high-k gate dielectric layer 34, metal barrier layer 35, and polysilicon gate layer 36 form a polysilicon gate structure 31.

[0025] It should be noted that when another layer of gate oxide material layer is formed on the surface of the substrate 10 in the second device region 10L, the gate oxide material layer in the second device region 10L is correspondingly etched to form a gate oxide layer at the bottom of the high-k gate dielectric layer 34 in the second device region 10L.

[0026] Reference Figure 3 , an interlayer dielectric layer 40 is formed on the substrate 10 on the side of the polysilicon gate layer 36, and the top of the polysilicon gate layer 36 in the second device region 10L is exposed by the interlayer dielectric layer 40.

[0027] Reference Figure 4 , the polysilicon gate layer 36 in the second device region 10L is removed to form a gate opening (not shown in the figure) exposing the metal barrier layer 35 in the interlayer dielectric layer 40; a metal gate layer 37 is formed in the gate opening.

[0028] In the second device region 10L, the stacked high-k gate dielectric layer 34, metal barrier layer 35, and metal gate layer 37 form a metal gate structure 32.

[0029] By forming the high-k gate dielectric layer 34 in the first device region 10M and the second device region 10L, and forming the polysilicon gate structure 31 in the first device region 10M and the metal gate structure 32 in the second device region 10L, the performance of the second device can be maintained while the critical dimensions of the semiconductor device are continuously reduced. At the same time, the formation process of the first device still uses polysilicon gate technology.

[0030] Specifically, the step of forming the metal gate layer 37 in the gate opening includes: filling the gate opening with a metal gate material, and the metal gate material also covers the interlayer dielectric layer 40; performing a planarization process on the metal gate material to remove the metal gate material higher than the top of the interlayer dielectric layer 40, and retaining the remaining metal gate material in the gate opening as the metal gate layer 37.

[0031] However, since the channel length of the first device is greater than the channel length of the second device, the line width dimension of the polysilicon gate layer 36 in the first device region 10M is correspondingly larger. Therefore, as Figure 4As shown, during the planarization process of the metal gate material, it is easy to cause the problem of over polish to the polysilicon gate layer 36 in the first device region 10M, resulting in a serious problem of the top surface depression of the polysilicon gate layer 36 in the first device region 10M. Even in severe cases, the metal barrier layer 35 may be exposed.

[0032] In particular, a gate oxide layer 33 is further formed on the substrate 10 in the first device region 10M. Since the operating voltage of the first device is greater than that of the second device, compared with the gate oxide layer at the bottom of the high-k gate dielectric layer 34 in the second device region 10L, the thickness of the gate oxide layer 33 in the first device region 10M is greater. This makes the top surface of the polysilicon gate layer 36 in the first device region 10M higher than the top surface of the polysilicon gate layer 36 in the second device region 10L. Therefore, the probability of the top surface depression problem of the polysilicon gate layer 36 in the first device region 10M is higher.

[0033] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate including a first device region for forming a first device and a second device region for forming a second device, the channel length of the first device being greater than that of the second device; a polysilicon gate layer located on the substrate in the first device region, the polysilicon gate layer including a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer enclosing a groove, and both the top gate layer and the bottom gate layer being doped with conductive ions; a metal gate layer located on the substrate in the second device region; and an interlayer dielectric layer located on the substrate on the sides of the polysilicon gate layer and the metal gate layer and filling the groove.

[0034] In the semiconductor structure provided by the embodiment of the present invention, the polysilicon gate layer in the first device region includes a bottom gate layer and a top gate layer protruding from the bottom gate layer. The top gate layer and the bottom gate layer enclose a groove, and both the top gate layer and the bottom gate layer are doped with conductive ions. Among them, compared with the polysilicon gate layer without a groove, the line width dimension of the top gate layer and the spacing between adjacent top gate layers (i.e., the line width dimension of the groove) in this embodiment are both smaller, thereby improving the problem of top surface depression generated when forming the metal gate layer. Moreover, both the top gate layer and the bottom gate layer are doped with conductive ions, reducing the resistance of the polysilicon gate layer and correspondingly reducing the gate resistance of the first device. In addition, by providing the groove, the bottom of the groove exposes the bottom gate layer, and the side wall of the groove exposes the top gate layer. Therefore, conductive ions can be injected into the polysilicon gate layer through the bottom and side walls of the groove, so that both the top gate layer and the bottom gate layer have the conductive ions, which is beneficial to improving the ion concentration uniformity of the conductive ions in the polysilicon gate layer. In summary, the performance of the semiconductor structure can be improved. In addition, the process of injecting conductive ions and the process of forming the groove can share a photomask and a lithography process, thereby reducing costs.

[0035] In order to make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the drawings.

[0036] With reference to Figure 5 and Figure 6 , Figure 5 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention, Figure 6 and

[0037] is a top view of the polysilicon gate layer in the first device region of an embodiment of the semiconductor structure of the present invention. Figure 6 Among them, for the convenience of illustration,

[0038] The semiconductor structure includes: a substrate 400, including a first device region 400M for forming a first device and a second device region 400L for forming a second device, wherein the channel length of the first device is greater than that of the second device; a polysilicon gate layer 630 located on the substrate 400 of the first device region 400M, the polysilicon gate layer 630 includes a bottom gate layer 632 and a top gate layer 631 protruding from the bottom gate layer 632, the top gate layer 631 and the bottom gate layer 632 enclose a groove 633, and both the top gate layer 631 and the bottom gate layer 632 are doped with conductive ions 651; a metal gate layer 680 located on the substrate 400 of the second device region 400L; an interlayer dielectric layer 670 located on the substrate 400 on the sides of the polysilicon gate layer 630 and the metal gate layer 680 and filling the groove 633.

[0039] In the semiconductor structure provided in this embodiment, the polysilicon gate layer 630 includes a bottom gate layer 632 and a top gate layer 631 protruding from the bottom gate layer 632, and the top gate layer 631 and the bottom gate layer 632 enclose a groove 633. Compared with the polysilicon gate layer without a groove, the line width dimension of the top gate layer 631 and the spacing between adjacent top gate layers 631 (i.e., the line width dimension of the groove 633) in this embodiment are both smaller, thereby improving the problem of top surface depression generated when forming the metal gate layer 680 for the polysilicon gate layer 630. And by doping both the top gate layer 631 and the bottom gate layer 632 with conductive ions 651, the gate resistance of the polysilicon gate layer 630 is reduced, and correspondingly the gate resistance of the first device is reduced. In summary, the structural integrity and electrical performance of the polysilicon gate layer 630 in the first device region 400M are improved, which is beneficial to improving the performance of the semiconductor structure.

[0040] Wherein, the bottom of the groove 633 exposes the bottom gate layer 632, and the side wall of the groove 633 exposes the top gate layer 631. Therefore, during the formation process of the semiconductor structure, the conductive ions 651 can be implanted into the polysilicon gate layer 630 through the bottom and side walls of the groove 633, so that both the top gate layer 631 and the bottom gate layer 632 have the conductive ions 651, which is beneficial to improving the ion concentration uniformity of the conductive ions 651 in the polysilicon gate layer 630.

[0041] In addition, the process of implanting the conductive ions 651 and the process of forming the groove 633 can share a photomask and a photolithography process, thereby reducing costs.

[0042] In this embodiment, taking the semiconductor structure as a planar field-effect transistor as an example, the substrate 400 is a planar substrate. In other embodiments, the semiconductor structure is a fin field-effect transistor (FinFET), and correspondingly, the substrate includes a substrate and fin portions protruding from the substrate.

[0043] In this embodiment, the substrate 400 is a silicon substrate. In some other embodiments, the substrate can also be a substrate of other material types. For example, the material of the substrate can be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as silicon-on-insulator or germanium-on-insulator.

[0044] In this embodiment, the substrate is a P-type substrate (Psub), that is, the substrate is doped with P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0045] The substrate 400 includes a first device region 400M for forming a first device and a second device region 400L for forming a second device, and the channel length of the first device is greater than the channel length of the second device.

[0046] As an example, the operating voltage of the first device is greater than the operating voltage of the second device, such that the channel length of the first device is greater than the channel length of the second device.

[0047] In this embodiment, the first device includes one or both of a medium-voltage device and a high-voltage device, and the second device is a low-voltage device. Among them, the operating voltages of the low-voltage device, the medium-voltage device, and the high-voltage device increase in sequence. As an example, the operating voltage of the low-voltage device is less than 1V, the operating voltage of the medium-voltage device is 1V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0048] It should be noted that when the first device includes a medium-voltage device and a high-voltage device, the first device region 400M for forming the medium-voltage device and the first device region 400M for forming the high-voltage device are isolated from each other.

[0049] The first device can be an NMOS device or a PMOS device. Similarly, the second device can also be an NMOS device or a PMOS device.

[0050] As an example, the first device region 400M includes a first sub-region 400MN and a second sub-region 400MP, and the first sub-region 400MN and the second sub-region 400MP are used to form the first device with different channel conduction types. For example, the first device formed in the first sub-region 400MN is an NMOS device, and the first device formed in the second sub-region 400MP is a PMOS device.

[0051] In this embodiment, taking the first device region 100M for forming medium-voltage devices and the second device region 100L for forming low-voltage devices as an example, a deep N-type well (DNW) region (not shown in the figure) is further formed in the substrate 400. A first well region (not labeled) is formed in the deep N-type well region of the first device region 400M, and a second well region (not labeled) is formed in the deep N-type well region of the second device region 400L.

[0052] The deep N-type well region is used to isolate the first well region from the P-type substrate and also to isolate the second well region from the P-type substrate, thereby reducing substrate coupling noise.

[0053] The doping ion type in the first well region is opposite to the channel conduction type of the first device located above it. When the first device is an NMOS device, the doping ions in the first well region are P-type ions; when the first device is a PMOS device, the doping ions in the first well region are N-type ions. Similarly, the doping ion type in the second well region is opposite to the channel conduction type of the second device located above it.

[0054] In other embodiments, when the first device region is used to form high-voltage devices, a high-voltage well region is formed in the substrate. Correspondingly, no deep N-type well region is formed in the substrate. Similarly, the doping ion type in the high-voltage well region is opposite to the channel conduction type of the first device formed above it.

[0055] In this embodiment, the semiconductor structure further includes an isolation structure 401 located in the substrate 400. Specifically, the isolation structure 401 is located in the substrate 400 at the junction of the first device region 400M and the second device region 400L.

[0056] Wherein, the first device region 400M includes a first sub-region 400MN and a second sub-region 400MP. Therefore, the isolation structure 401 is also formed in the substrate 400 at the junction of the first sub-region 400MN and the second sub-region 400MP.

[0057] The isolation structure 401 is used to achieve isolation between adjacent devices. In this embodiment, the isolation structure 401 is a shallow trench isolation (STI), so that the isolation structure 401 has a good isolation effect. In this embodiment, the material of the isolation structure 401 is an insulating material, and the insulating material includes silicon oxide.

[0058] The polysilicon gate layer 630 is used as the device gate structure of the first device, thereby controlling the opening or closing of the channel of the first device.

[0059] During the formation of the semiconductor structure, a metal gate layer 680 is formed in a gate opening in an interlayer dielectric layer 670. The process of forming the metal gate layer 680 usually includes a step of planarizing the metal gate material. Moreover, the larger the size of the metal gate layer 680, the higher the probability that the top surface of the metal gate layer 680 will have a depression problem during the planarization of the metal gate material. Since the first device region 400M is used to form a first device and the channel length of the first device is relatively large, by using a polysilicon gate layer 630 for the first device, the step of planarizing the metal gate material is omitted in the first device region 400M, thereby avoiding the depression problem on the top surface of the metal gate layer caused by the relatively large linewidth size.

[0060] Furthermore, by forming a groove 633 in the polysilicon gate layer 630 of the first device region 400M, the probability of over-polishing the polysilicon gate layer 630 in the first device region 400M during the planarization process of forming the metal gate layer 680 is relatively low, which is beneficial to improving the depression problem on the top surface of the polysilicon gate layer 630 in the first device region 400M, making the top surface flatness of the polysilicon gate layer 630 in the first device region 400M relatively high, correspondingly improving the structural integrity of the polysilicon gate layer 630 in the first device region 400M, and further being beneficial to improving the performance of the semiconductor structure.

[0061] In addition, since the conductive ions 651 are used to reduce the resistance of the polysilicon gate layer 630, compared with the scheme where the conductive ions are only located in the bottom gate layer, by doping the top gate layer 631 and the bottom gate layer 632 with the conductive ions 651, the gate resistance of the polysilicon gate layer 630 is reduced.

[0062] It should be noted that by providing the groove 633 in the polysilicon gate layer 630, during the formation of the semiconductor structure, the top gate layer 631 and the bottom gate layer 632 can be doped with the conductive ions 651 by injecting the conductive ions 651 into the polysilicon gate layer 630 exposed by the groove 633. For example, by injecting the conductive ions 651 into the polysilicon gate layer 630 in such a way that the injection direction of the conductive ions 651 has an acute angle with the normal direction of the bottom surface of the groove 633, when injecting the conductive ions 651, the side walls and the bottom of the groove 633 expose the material of the polysilicon gate layer 630. Therefore, it is easy to dope both the top gate layer 631 and the bottom gate layer 632 with the conductive ions 651, which is beneficial to making the concentration of the conductive ions 651 in both the top gate layer 631 and the bottom gate layer 632 meet the performance requirements, and is beneficial to improving the uniformity of the concentration of the conductive ions 651 in the top gate layer 631 and the bottom gate layer 632.

[0063] In addition, since the sidewalls and the bottom of the groove 633 expose the material of the polysilicon gate layer 630, it is beneficial to inject the conductive ions 651 into the top gate layer 631 and the bottom gate layer 632 with a relatively small injection energy, thereby reducing the probability of injecting the conductive ions 651 into the substrate 400 under the polysilicon gate layer 630, and further improving the performance of the semiconductor structure.

[0064] In this embodiment, the material of the polysilicon gate layer 630 is correspondingly polysilicon.

[0065] It should be noted that the ratio of the thickness of the top gate layer 631 to the total thickness of the polysilicon gate layer 630 should neither be too small nor too large. If the ratio is too small, during the planarization process of forming the metal gate layer 680, the top gate layer 631 is likely to be completely removed, increasing the probability of over-polishing the bottom gate layer 632, and further increasing the probability of the top surface depression problem of the polysilicon gate layer 630 in the first device region 400M. If the ratio is too large, the thickness of the bottom gate layer 632 is likely to be too small. Considering the influence of etching uniformity and loading effect, during the process of forming the groove 633, the probability of etching through the bottom gate layer 632 exposed by the top gate layer 631 is relatively high, that is, the groove 633 is likely to penetrate through the entire polysilicon gate layer 630, thus affecting the performance of the polysilicon gate layer 630 in the first device region 400M. And the conductive ions 651 are injected into the polysilicon gate layer 630 through the polysilicon gate layer 630 exposed by the groove 633. Correspondingly, if the ratio is too large, the conductive ions 651 may pass through the bottom gate layer 632 and be injected into the gate oxide layer or the substrate 400. Therefore, in this embodiment, the thickness of the top gate layer 631 accounts for 1 / 5 to 1 / 3 of the total thickness of the polysilicon gate layer 630, that is, the depth of the groove 633 accounts for 1 / 5 to 1 / 3 of the total thickness of the polysilicon gate layer 630.

[0066] It should also be noted that the line width dimension of the top gate layer 631 should not be too small or too large. If the line width dimension of the top gate layer 631 is too small, the line width dimension of the groove 633 will be correspondingly too large. When forming the metal gate layer 680, the interlayer dielectric layer 670 in the groove 633 is prone to serious top surface depression problems. If the line width dimension of the top gate layer 631 is too large, when forming the metal gate layer 680, the probability of the top surface of the top gate layer 631 being depressed is relatively high. Moreover, it is likely to cause the line width dimension of the groove 633 to be too small, thus having an adverse effect on the filling effect of the subsequent interlayer dielectric layer 670 in the groove 633. In addition, it is also likely to increase the process difficulty of the photolithography process used to form the groove 633. Therefore, in this embodiment, the line width dimension of the top gate layer 631 is 0.15 micrometers to 2 micrometers. For example, the line width dimension of the top gate layer 631 is 0.5 micrometers, 1 micrometer, or 1.5 micrometers.

[0067] Similarly, the line width dimension of the groove 633 is 0.15 micrometers to 2 micrometers. For example, the line width dimension of the groove 633 is 0.5 micrometers, 1 micrometer, or 1.5 micrometers.

[0068] Among them, the line width dimension of the groove 633 is the spacing (space) between adjacent top gate layers 631.

[0069] In this embodiment, the semiconductor structure further includes: a gate oxide layer 510, located between the polysilicon gate layer 630 and the substrate 400. The gate oxide layer 510 serves as the gate dielectric of the first device, and the gate oxide layer 510 is used to electrically isolate the polysilicon gate layer 630 from the channel of the first device.

[0070] In this embodiment, the material of the gate oxide layer 210 is silicon oxide.

[0071] It should be noted that according to process requirements, in the second device region 400L, a gate oxide layer (not shown in the figure) may also be formed between the high-k gate dielectric layer 610 and the substrate 400, and compared with the gate oxide layer 510 in the first device region 400M, the thickness of the gate oxide layer in the second device region 400L is smaller.

[0072] The metal gate layer 680 is used to form a metal gate structure. Since the operating voltage of the second device is relatively small, therefore, as the critical dimensions of the device continue to shrink, by adopting a metal gate structure, it is beneficial to improve the short-channel effect. Among them, the metal gate layer 680 is used to lead out the electrical properties of the metal gate structure.

[0073] The material of the metal gate layer 680 is Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In this embodiment, the material of the metal gate layer 680 is Al.

[0074] It should be noted that the semiconductor structure further includes a work function layer covering the sidewalls and the bottom of the metal gate layer 680, which will not be elaborated herein in this embodiment.

[0075] In this embodiment, the semiconductor structure further includes a stacked structure (not labeled), which is located between the polysilicon gate layer 630 and the substrate 400, and between the metal gate layer 680 and the substrate 400. The stacked structure includes a high-k gate dielectric layer 610 and a metal barrier layer 620 stacked in sequence from bottom to top.

[0076] In the second device region 400L, the stacked high-k gate dielectric layer 610, metal barrier layer 620, and metal gate layer 380 form a metal gate structure.

[0077] In this embodiment, the metal gate structure is formed by using the high-K first process in the gate last process. Therefore, the stacked structure is also located in the first device region 400M. Specifically, the stacked structure in the first device region 400M is located between the polysilicon gate layer 630 and the gate oxide layer 510.

[0078] The high-k gate dielectric layer 610 is used to form the gate dielectric layer of the second device, that is, the gate dielectric layer of the second device includes the high-k gate dielectric layer 610. The material of the high-k gate dielectric layer 610 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 610 can be selected from HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al 2 O 3 etc. As an example, the material of the high-k gate dielectric layer 610 is HfO 2 .

[0079] The metal barrier layer 620 is used to isolate the high-k gate dielectric layer 610 and the metal gate layer 680 to protect the high-k gate dielectric layer 610. Moreover, the metal barrier layer 620 is also used to block the diffusion of easily diffused ions (such as: Al ions) in the metal gate layer 680 into the high-k gate dielectric layer 610.

[0080] Specifically, the material of the metal barrier layer 620 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 620 is titanium nitride.

[0081] Among them, the metal barrier layer 620 also has a certain influence on the gate work function of the second device. In the actual process, by reasonably setting the thickness of the metal barrier layer 620, the blocking effect of the metal barrier layer 620 on the easily diffused ions in the metal gate layer 680 can be better ensured.

[0082] It should be noted that in the second device region 400L, a gate oxide layer (not shown in the figure) is also formed between the high-k gate dielectric layer 610 and the substrate 400. Therefore, the gate oxide layer of the second device region 400L also serves as a part of the metal gate structure, and the gate oxide layer and the high-k gate dielectric layer 610 of the second device region 400L together serve as the gate dielectric layer of the second device.

[0083] Both the top gate layer 631 and the bottom gate layer 632 are doped with conductive ions 651, and the conductive ions 651 are used to reduce the resistance of the polysilicon gate layer 630 in the first device region 400M, thereby reducing the gate resistance of the first device and the contact resistance between the polysilicon gate layer 630 and the gate silicide layer, which is correspondingly beneficial to improving the performance of the semiconductor structure.

[0084] Moreover, during the formation of the semiconductor structure, the conductive ions 651 can be implanted into the polysilicon gate layer 630 through the bottom and side walls of the groove 633, so that both the top gate layer 631 and the bottom gate layer 632 have the conductive ions 651, and the implanted conductive ions 651 are activated by heat treatment (for example, thermal annealing treatment) to diffuse the conductive ions 651, thereby reducing the resistance of the polysilicon gate layer 630 in the first device region 400M and correspondingly reducing the gate resistance of the first device.

[0085] In this embodiment, the conductive ions 651 can be N-type ions or P-type ions. Specifically, the conductive ions 651 include B ions, Ga ions, In ions, P ions, As ions or Sb ions.

[0086] Among them, a high-k gate dielectric layer 610 and a metal barrier layer 620 are formed under the polysilicon gate layer 630. Therefore, the conductivity type of the conductive ions 651 can be the same as or different from the channel conductivity type of the corresponding device.

[0087] For example, the first device region 400M includes a first sub-region 400MN and a second sub-region 400MP. Therefore, in the first device region 400M, the conductive ions 651 in the polysilicon gate layer 630 of each sub-region can have the same conductivity type or different conductivity types.

[0088] In this embodiment, the semiconductor structure further includes: sidewalls 690 located on the sidewalls of the polysilicon gate layer 630, the sidewalls of the grooves 633, and the sidewalls of the metal gate layer 680.

[0089] The sidewalls 690 are used to protect the sidewalls of the polysilicon gate layer 630 and also to define the positions of the source / drain doping regions.

[0090] Moreover, the sidewalls 690 also cover the sidewalls of the grooves 633. During the planarization process performed after the formation of the sidewalls 690 in the process of forming the semiconductor structure, the sidewalls 690 are conducive to further reducing the probability of over-polishing the top surface of the polysilicon gate layer 630, thereby further improving the problem of the top surface depression of the polysilicon gate layer 630.

[0091] The material of the sidewalls 690 is selected such that the hardness and density of the material are relatively high and the polishing rate of the planarization process for the sidewalls 690 is relatively small, which is conducive to further improving the problem of the top surface depression of the polysilicon gate layer 630 in the first device region 400M.

[0092] Therefore, the material of the sidewalls 690 includes silicon nitride or silicon oxynitride.

[0093] In this embodiment, the material of the sidewalls 690 includes silicon nitride. Silicon nitride has relatively high hardness and density.

[0094] As an example, the sidewalls 690 are a stacked structure, and the sidewalls 690 include: a silicon oxide layer located on the sidewalls of the polysilicon gate layer 630, the sidewalls of the grooves 633, and the sidewalls of the metal gate layer 680; a silicon nitride layer covering the sidewalls of the silicon oxide layer.

[0095] In other embodiments, the sidewalls can also be a single-layer structure or a four-layer structure. For example, the four-layer structure can be an ONON (Oxide - SiN - Oxide - SiN) structure.

[0096] In this embodiment, the sidewalls 690 also cover the sidewalls of the gate oxide layer 510.

[0097] In this embodiment, the semiconductor structure further includes: source / drain doping regions 650 respectively located in the substrate 400 on both sides of the polysilicon gate layer 630 and in the substrate 400 on both sides of the metal gate layer 680.

[0098] The source / drain doping regions 650 serve as the source regions or drain regions of the formed devices.

[0099] The conduction type of the doped ions in the source-drain doped region 650 is the same as that of the channel of the corresponding device. When the formed device is an NMOS device, the doped ions in the source-drain doped region 650 are N-type ions, and the N-type ions include P ions, As ions or Sb ions. When the formed device is a PMOS device, the doped ions in the source-drain doped region 650 are P-type ions, and the P-type ions include B ions, Ga ions or In ions.

[0100] In this embodiment, the semiconductor structure further includes: a gate silicide layer 661 located on the bottom surface of the groove 633. Specifically, the gate silicide layer 661 is located on the bottom surface of the groove 633 exposed by the sidewall 690.

[0101] Through the gate silicide layer 661 located on the bottom surface of the groove 633, when the first device operates, current can flow through the gate silicide layer 661, thereby reducing the gate resistance.

[0102] In this embodiment, the material of the gate silicide layer 661 can be nickel silicide, cobalt silicide or titanium silicide.

[0103] In this embodiment, the semiconductor structure further includes: a source-drain silicide layer 660 located on the surface of the source-drain doped region 650.

[0104] Subsequently, a source-drain contact plug is formed on the top of the source-drain doped region 650, and the source-drain silicide layer 660 is used to reduce the contact resistance between the source-drain doped region 650 and the source-drain contact plug.

[0105] In this embodiment, the material of the source-drain silicide layer 660 can be nickel silicide, cobalt silicide or titanium silicide.

[0106] The interlayer dielectric layer 670 is used to isolate adjacent devices. In this embodiment, the interlayer dielectric layer 670 covers the sidewalls of the metal gate layer 680 and the polysilicon gate layer 630, and fills the groove 633.

[0107] The material of the interlayer dielectric layer 670 is an insulating material, and the material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 670 is silicon oxide.

[0108] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure. Figures 7 to 19 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0109] Refer to Figure 7, a substrate 100 is provided, which includes a first device region 100M for forming a first device and a second device region 100L for forming a second device, and the channel length of the first device is greater than that of the second device.

[0110] The substrate 100 is used to provide a process platform for subsequent process steps.

[0111] In this embodiment, taking the substrate 100 being used to form a planar field-effect transistor as an example, the substrate 100 is a planar substrate. In other embodiments, the substrate is used to form a fin field-effect transistor (FinFET). Correspondingly, the substrate includes a substrate and fin portions protruding from the substrate.

[0112] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other material types. For example, the material of the substrate can be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as silicon-on-insulator or germanium-on-insulator substrates.

[0113] In this embodiment, the substrate is a P-type substrate (Psub), that is, the substrate is doped with P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0114] The substrate 100 includes a first device region 100M for forming a first device and a second device region 100L for forming a second device, and the channel length of the first device is greater than that of the second device.

[0115] As an example, the operating voltage of the first device is greater than that of the second device, such that the channel length of the first device is greater than that of the second device.

[0116] In this embodiment, the first device includes one or both of a medium-voltage device and a high-voltage device, and the second device is a low-voltage device. Among them, the operating voltages of the low-voltage device, the medium-voltage device, and the high-voltage device increase in sequence. As an example, the operating voltage of the low-voltage device is less than 1V, the operating voltage of the medium-voltage device is 1V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

[0117] It should be noted that when the first device includes a medium-voltage device and a high-voltage device, the first device region 100M for forming the medium-voltage device and the first device region 100M for forming the high-voltage device are isolated from each other.

[0118] The first device can be an NMOS device or a PMOS device. Similarly, the second device can also be an NMOS device or a PMOS device.

[0119] As an example, the first device region 100M includes a first sub-region 100MN and a second sub-region 100MP. The first sub-region 100MN and the second sub-region 100MP are used to form a first device of different channel conduction types. For example, the first device formed in the first sub-region 100MN is an NMOS device, and the first device formed in the second sub-region 100MP is a PMOS device.

[0120] In this embodiment, taking the first device region 100M being used to form medium-voltage devices and the second device region 100L being used to form low-voltage devices as an example, a deep N-type well (DNW) region (not shown in the figure) is further formed in the substrate 100. A first well region (not labeled) is formed in the deep N-type well region of the first device region 100M, and a second well region (not labeled) is formed in the deep N-type well region of the second device region 100L.

[0121] The deep N-type well region is used to isolate the first well region from the P-type substrate and is also used to isolate the second well region from the P-type substrate, thereby reducing substrate coupling noise.

[0122] The doping ion type in the first well region is opposite to the channel conduction type of the first device formed above it. When the first device is an NMOS device, the doping ions in the first well region are P-type ions. When the first device is a PMOS device, the doping ions in the first well region are N-type ions. Similarly, the doping ion type in the second well region is opposite to the channel conduction type of the second device formed above it.

[0123] In other embodiments, when the first device region is used to form high-voltage devices, a high-voltage well region is formed in the substrate. Correspondingly, no deep N-type well region is formed in the substrate. Similarly, the doping ion type in the high-voltage well region is opposite to the channel conduction type of the first device formed above it.

[0124] In this embodiment, an isolation structure 101 is further formed in the substrate 100. Specifically, the isolation structure 101 is formed in the substrate 100 at the junction of the first device region 100M and the second device region 100L.

[0125] Wherein, the first device region 100M includes a first sub-region 100MN and a second sub-region 100MP. Therefore, the isolation structure 101 is also formed in the substrate 100 at the junction of the first sub-region 100MN and the second sub-region 100MP.

[0126] The isolation structure 101 is used to achieve isolation between adjacent devices. In this embodiment, the isolation structure 101 is a shallow trench isolation, so that the isolation structure 101 has a good isolation effect. In this embodiment, the material of the isolation structure 101 is an insulating material, and the insulating material includes silicon oxide.

[0127] Continuing to refer to Figure 7 , the forming method further includes: forming a gate oxide layer 210 on the substrate 100 of the first device region 100M.

[0128] Subsequently, a polysilicon gate layer is formed on the gate oxide layer 210 of the first device region 100M. The polysilicon gate layer is used to control the opening or closing of the channel of the first device. The gate oxide layer 210 serves as the gate dielectric of the first device and is used to electrically isolate the polysilicon gate layer from the channel of the first device.

[0129] In this embodiment, the gate oxide layer 210 exposes the substrate 100 of the second device region 100L, so as to prepare for forming a high-k gate dielectric layer on the substrate 100 of the second device region 100L subsequently.

[0130] In this embodiment, the material of the gate oxide layer 210 is silicon oxide.

[0131] It should be noted that according to process requirements, the forming method may further include: forming another layer of gate oxide layer (not shown in the figure) on the surface of the substrate 100 of the second device region 100L, and the thickness of the gate oxide layer located in the second device region 100L is smaller than that of the gate oxide layer 210 in the first device region 100M.

[0132] With reference to Figures 8 to 11 , discrete polysilicon gate layers 330 are formed on the substrates 100 of the first device region 100M and the second device region 100L (as Figure 10 shown). In the first device region 100M, the polysilicon gate layer 330 includes a bottom gate layer 332 and a top gate layer 331 protruding from the bottom gate layer 332. The top gate layer 331 and the bottom gate layer 332 enclose a groove 333.

[0133] Among them, Figure 11 is a top view of the polysilicon gate layer 330 in the first device region 100M in an embodiment of the present invention. For the convenience of illustration, Figure 11 different shades of colors are used in

[0134] The polysilicon gate layer 330 of the first device region 100M is used as the device gate structure of the first device, thereby controlling the opening or closing of the channel of the first device. The polysilicon gate layer 330 of the second device region 100L is used to occupy a spatial position for the subsequent formation of the metal gate layer.

[0135] Wherein, after the interlayer dielectric layer is formed on the substrate 100 on the side of the polysilicon gate layer 330, the polysilicon gate layer 330 of the second device region 100L is removed to form a gate opening. Subsequently, a metal gate layer is formed in the gate opening. The process of forming the metal gate layer usually includes a step of planarizing the metal gate material. Moreover, the larger the linewidth dimension of the metal gate layer, the higher the probability of the occurrence of the dishing problem on the top surface of the metal gate layer during the planarization of the metal gate material. Since the first device region 100M is used to form the first device and the channel length of the first device is longer, therefore, by using the polysilicon gate layer 330 for the first device, the step of planarizing the metal gate material is omitted in the first device region 100M, thereby avoiding the dishing problem on the top surface of the metal gate layer caused by the larger size.

[0136] Moreover, by forming the groove 333 in the polysilicon gate layer 330 of the first device region 100M, the linewidth dimension of the top gate layer 331 and the interval between adjacent top gate layers 331 (i.e., the linewidth dimension of the groove 333) are both small. Therefore, during the planarization process of forming the metal gate layer, the probability of over-polishing the polysilicon gate layer 330 of the first device region 100M is low, which is beneficial to improving the dishing problem on the top surface of the polysilicon gate layer 330 of the first device region 100M, making the top surface flatness of the polysilicon gate layer 330 of the first device region 100M high, correspondingly improving the structural integrity of the polysilicon gate layer 330 of the first device region 100M, and further being beneficial to improving the performance of the semiconductor structure.

[0137] In this embodiment, the material of the polysilicon gate layer 330 is polysilicon accordingly.

[0138] It should be noted that the depth H of the groove 333 (such as Figure 10The ratio of the depth H of the groove 333 to the total thickness of the polysilicon gate layer 330 (as shown) should not be too small or too large. If the ratio is too small, correspondingly, the thickness of the top gate layer 331 is too small, then during the subsequent planarization process of forming the metal gate layer, it is easy to cause the complete removal of the top gate layer 331, thereby causing over-grinding of the bottom gate layer 332, and further increasing the probability of the top surface depression problem of the polysilicon gate layer 330 in the first device region 100M; if the ratio is too large, it is easy to cause the thickness of the bottom gate layer 332 to be too small. Considering the influence of etching uniformity and loading effect, during the process of forming the groove 333, the probability of etching through the bottom gate layer 332 exposed by the top gate layer 331 is relatively high, that is, the groove 333 is likely to penetrate the entire polysilicon gate layer 330, thus affecting the performance of the polysilicon gate layer 330 in the first device region 100M. And since conductive ions will be injected into the polysilicon gate layer 330 exposed by the groove 333 subsequently, correspondingly, the conductive ions may pass through the bottom gate layer 332 and be injected into the gate oxide layer 210. Therefore, in this embodiment, the depth H of the groove 333 accounts for 1 / 5 to 1 / 3 of the total thickness of the polysilicon gate layer 330. That is to say, the thickness of the top gate layer 331 accounts for 1 / 5 to 1 / 3 of the total thickness of the polysilicon gate layer 330.

[0139] It should also be noted that the line width dimension of the top gate layer 331 should not be too small or too large. If the line width dimension of the top gate layer 331 is too small, then the line width dimension of the groove 333 is correspondingly too large, and when forming the metal gate layer subsequently, the interlayer dielectric layer in the groove 333 is prone to serious top surface depression problems; if the line width dimension of the top gate layer 331 is too large, then when forming the metal gate layer subsequently, the probability of the top surface depression problem of the top gate layer 331 is relatively high. Moreover, it is easy to cause the line width dimension of the groove 333 to be too small, thereby having an adverse effect on the filling effect of the subsequent interlayer dielectric layer in the groove 333. In addition, it is also easy to increase the process difficulty of the lithography process used to form the groove 333. Therefore, in this embodiment, the line width dimension of the top gate layer 331 is 0.15 micrometers to 2 micrometers. For example, the line width dimension of the top gate layer 331 is 0.5 micrometers, 1 micrometer or 1.5 micrometers.

[0140] Similarly, the line width dimension of the groove 333 is 0.15 micrometers to 2 micrometers. For example, the line width dimension of the groove 333 is 0.5 micrometers, 1 micrometer or 1.5 micrometers.

[0141] In this embodiment, after forming the polysilicon gate layer 330, the groove 333 is formed in the polysilicon gate layer 330 of the first device region 100M, thereby reducing the modification to the existing process and having high process compatibility.

[0142] The following describes in detail the steps of forming the polysilicon gate layer 330 and the groove 333 in conjunction with the accompanying drawings.

[0143] Refer to Figure 8 , a polysilicon material layer 240 covering the substrate 100 of the first device region 100M and the second device region 100L is formed.

[0144] The polysilicon material layer 240 is used to prepare for the subsequent formation of the polysilicon gate layer. In this embodiment, the thickness of the polysilicon material layer 240 is equal to the target thickness of the polysilicon gate layer.

[0145] In this embodiment, a furnace tube process or a chemical vapor deposition process is used to form the polysilicon material layer 240.

[0146] Specifically, the polysilicon material layer 240 covers the substrate 100 of the second device region 100L and extends to cover the gate oxide layer 210.

[0147] It should be noted that when another gate oxide layer (not shown in the figure) is formed on the surface of the substrate 100 of the second device region 100L, in the second device region 100L, the polysilicon material layer 240 correspondingly covers the gate oxide layer.

[0148] Refer to Figure 9 , the polysilicon material layer 240 is etched (as shown in Figure 8 ), to form discrete polysilicon gate layers 330.

[0149] In this embodiment, an anisotropic dry etching process is used to etch the polysilicon material layer 240. The anisotropic etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate is much greater than the lateral etching rate, so as to obtain a better etching profile, thereby improving the morphology quality and dimensional accuracy of the polysilicon gate layer 330.

[0150] It should be noted that before etching the polysilicon material layer 240, the forming method further includes: forming a gate mask layer 340 on the polysilicon material layer 240 (as shown in Figure 9 ).

[0151] The gate mask layer 340 is used as a mask when etching the polysilicon material layer 240, that is, the polysilicon material layer 240 is etched with the gate mask layer 340 as a mask.

[0152] Specifically, a deposition process, a photolithography process, and an etching process are sequentially performed to form the gate mask layer 340.

[0153] Therefore, in this embodiment, after forming the polysilicon gate layer 330, a gate mask layer 340 is formed on the top of the polysilicon gate layer 330.

[0154] As an example, the material of the gate mask layer 340 is silicon nitride.

[0155] Continue to refer to Figure 8 , in this embodiment, before forming the polysilicon material layer 240, it further includes: forming a high-k gate dielectric material layer 220 and a metal barrier material layer 230 stacked in sequence from bottom to top on the substrate 100 of the first device region 100M and the second device region 100L.

[0156] Specifically, the high-k gate dielectric material layer 220 covers the substrate 100 of the second device region 100L and extends to cover the gate oxide layer 210.

[0157] It should be noted that when another gate oxide layer (not shown in the figure) is formed on the surface of the substrate 100 of the second device region 100L, in the second device region 100L, the high-k gate dielectric material layer 220 correspondingly covers the gate oxide layer.

[0158] In this embodiment, a metal gate structure is formed by using the high-K first process in the gate last process. Therefore, a stacked high-k gate dielectric layer and a metal barrier layer are first formed on the substrate 100.

[0159] The high-k gate dielectric material layer 220 is used to form a high-k gate dielectric layer, and the high-k gate dielectric layer is used to form the gate dielectric layer of the second device, that is, the gate dielectric layer of the second device includes a high-k gate dielectric layer. The material of the high-k gate dielectric material layer 220 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric material layer 220 can be selected from HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 etc. As an example, the material of the high-k gate dielectric material layer 220 is HfO 2 .

[0160] The metal barrier material layer 230 is used to form a metal barrier layer, which is used to isolate the high-k gate dielectric layer and the metal gate layer to protect the high-k gate dielectric layer. Meanwhile, during the subsequent etching process of removing the polysilicon gate layer 330 in the second device region 100L, the metal barrier layer serves as an etch stop layer, thereby reducing the probability of damage to the high-k gate dielectric layer. Moreover, after the metal gate layer is formed subsequently, the metal barrier layer is also used to prevent the diffusion of easily diffused ions (e.g., Al ions) in the metal gate layer into the high-k gate dielectric layer.

[0161] Specifically, the material of the metal barrier material layer 230 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier material layer 230 is titanium nitride.

[0162] Among them, the metal barrier layer also has a certain influence on the gate work function of the second device.

[0163] In the actual process, by reasonably setting the thickness of the metal barrier material layer 230, it is ensured that the metal barrier layer can serve as an etch stop layer during the subsequent etching process of removing the polysilicon gate layer 330 in the second device region 100L. Meanwhile, the metal barrier layer has a better blocking effect on the easily diffused ions in the metal gate layer.

[0164] In this embodiment, the high-k gate dielectric material layer 220 and the metal barrier material layer 230 are formed by a deposition process.

[0165] Specifically, the deposition process is an atomic layer deposition process. By using the atomic layer deposition process, the step coverage and thickness uniformity of the high-k gate dielectric material layer 220 and the metal barrier material layer 230 are improved. In other embodiments, the deposition process can also be a physical vapor deposition process.

[0166] Correspondingly, as Figure 9 shown, after etching the polysilicon material layer 243, it further includes: etching the high-k gate dielectric material layer 220 and the metal barrier material layer 230 exposed by the polysilicon gate layer 330 to respectively form a stacked high-k gate dielectric layer 310 and a metal barrier layer 320.

[0167] Therefore, a stacked structure is also formed between the polysilicon gate layer 330 and the substrate 100, and the stacked structure includes a high-k gate dielectric layer 310 and a metal barrier layer 320 stacked in sequence from bottom to top.

[0168] In this embodiment, the forming method further includes: etching the gate oxide layer 210 exposed by the polysilicon gate layer 330 to expose the substrate 100 on both sides of the polysilicon gate layer 330.

[0169] By exposing the substrate 100 on both sides of the polysilicon gate layer 330, the influence on the subsequent process of forming the source / drain doping regions is reduced, and preparations are made for the subsequent formation of the source / drain silicide layer.

[0170] Wherein, when another gate oxide layer (not shown in the figure) is formed on the surface of the substrate 100 in the second device region 100L, the forming method further includes: in the second device region 100L, etching and removing the gate oxide layer exposed by the polysilicon gate layer 330.

[0171] It should be noted that in other embodiments, in the first device region, a part of the thickness of the gate oxide layer exposed by the polysilicon gate layer can also be removed. For example, when another gate oxide layer (not shown in the figure) is formed on the surface of the substrate in the second device region, and compared with the gate oxide layer in the first device region, the thickness of the gate oxide layer in the second device region is smaller, and the time required to remove the gate oxide layer in the second device region is correspondingly shorter. Therefore, in the second device region, after successively etching the stacked polysilicon material layer, metal barrier material layer, high-k gate dielectric material layer and gate oxide layer (not shown in the figure) from top to bottom, the gate oxide layer in the first device region may not be completely removed, so that in the first device region, a part of the thickness of the gate oxide layer exposed by the polysilicon gate layer is removed.

[0172] Reference Figure 10 , a first mask layer 334 covering the substrate 100 and the polysilicon gate layer 330 is formed. A first mask opening (not labeled) is formed in the first mask layer 334 of the first device region 100M, and the first mask opening is located above a part of the top of the polysilicon gate layer 330.

[0173] The first mask layer 334 is used as a mask for subsequent etching of the polysilicon gate layer 330 in the first device region 100M to form a groove, and the first mask opening is used to define the position and line width dimension of the groove.

[0174] In this embodiment, the material of the first mask layer 334 is photoresist. By means of the processes of coating, exposing and developing the photoresist, the first mask opening is formed, and the processes of forming the first mask layer 334 and the first mask opening are simple.

[0175] With reference to Figure 10 and Figure 11 , Figure 11 is Figure 10 a top view of the polysilicon gate layer 330 in the first device region 100M in . Using the first mask layer 334 as a mask, a part of the thickness of the polysilicon gate layer 330 is etched along the first mask opening, and a groove 333 is formed in the polysilicon gate layer 330.

[0176] In the first device region 100M, after etching a polysilicon gate layer 330 with a partial thickness along a first mask opening, the groove 333 is formed, so that the remaining polysilicon gate layer 330 includes a bottom gate layer 332 and a top gate layer 331 protruding from the bottom gate layer 332. That is, the top gate layer 331 and the bottom gate layer 332 enclose the groove 333.

[0177] It should be noted that a gate mask layer 340 is formed on the top of the polysilicon gate layer 330. Therefore, before etching the polysilicon gate layer 330 with a partial thickness, it further includes: etching the gate mask layer 340 along the first mask opening to expose the top of the polysilicon gate layer 330. Correspondingly, after etching the gate mask layer 340, continue to etch the polysilicon gate layer 330 with a partial thickness.

[0178] In this embodiment, an anisotropic dry etching process is used to etch the polysilicon gate layer 330 with a partial thickness. The anisotropic etching process has the characteristics of anisotropic etching, that is, the longitudinal etching rate is much greater than the lateral etching rate, so that a better etching profile can be obtained to improve the morphology quality and dimensional accuracy of the groove 333. Moreover, it is beneficial to accurately control the longitudinal etching amount of the polysilicon gate layer 330. In addition, by using a dry etching process, the gate mask layer 340 and the polysilicon gate layer 330 can be etched in sequence in the same etching chamber by changing the etching gas, and the etching process is simple.

[0179] It should also be noted that the line width dimension of the groove 333 is 0.15 micrometers to 2 micrometers. The line width dimension of the groove 333 is not too small, thereby reducing the process difficulty of forming the first mask opening and increasing the process window of the lithography process.

[0180] In this embodiment, after forming the groove 333, the first mask layer 334 is retained.

[0181] Subsequently, conductive ions are implanted into the polysilicon gate layer 330 exposed by the groove 333. By retaining the first mask layer 334, during the process of implanting conductive ions into the polysilicon gate layer 330, the first mask layer 334 can continue to be used as a mask, so that the first mask layer 334 plays a protective role for the substrate 100 and the polysilicon gate layer 330 in the second device region 100L.

[0182] Moreover, in this embodiment, the process of forming the groove 333 and the process of subsequently implanting conductive ions into the polysilicon gate layer 330 exposed by the groove 333 can share one photomask and one lithography process, thereby saving the photomask and reducing the manufacturing cost.

[0183] Continue to refer toFigure 10 , conductive ions 351 are implanted into the polysilicon gate layer 330 exposed to the groove 333, and the implantation direction of the conductive ions 351 has an acute angle with the normal direction of the bottom surface of the groove 333.

[0184] By implanting the conductive ions 351 into the polysilicon gate layer 330 of the first device region 100M, the resistance of the polysilicon gate layer 330 in the first device region 100M is reduced, thereby reducing the gate resistance of the first device and the contact resistance between the polysilicon gate layer 330 and the gate silicide layer, which is correspondingly beneficial to improving the performance of the semiconductor structure.

[0185] Moreover, the implantation direction of the conductive ions 351 has an acute angle with the normal direction of the bottom surface of the groove 333, which enables the conductive ions 351 to be implanted into the polysilicon gate layer 330 through the bottom and side walls of the groove 333, so that both the top gate layer 331 and the bottom gate layer 332 have the conductive ions 351, and it is easy to activate the conductive ions through subsequent heat treatment (for example, thermal annealing treatment), diffuse the conductive ions 351, which is beneficial to improving the ion concentration uniformity of the conductive ions 351 in the polysilicon gate layer 330, thereby reducing the resistance of the polysilicon gate layer 330 in the first device region 100M and correspondingly reducing the gate resistance of the first device.

[0186] In summary, in this embodiment, by forming the groove 333 in the polysilicon gate layer 330 of the first device region 100M and making the implantation direction of the conductive ions 351 have an acute angle with the normal direction of the bottom surface of the groove 333, it is easy for the conductive ions 351 to be implanted into the top gate layer 331 from the side wall of the groove 333 and into the bottom gate layer 332 from the bottom of the groove 333, thereby improving the electrical performance of the polysilicon gate layer 330 in the first device region 100M, and correspondingly being beneficial to improving the performance of the semiconductor structure.

[0187] In this embodiment, the conductive ions 351 can be N-type ions or P-type ions. Specifically, the conductive ions 351 include B ions, Ga ions, In ions, P ions, As ions or Sb ions.

[0188] Wherein, a high-k gate dielectric layer 310 and a metal barrier layer 320 are formed under the polysilicon gate layer 330. Therefore, the conductivity type of the conductive ions 351 can be the same as or different from the channel conductivity type of the corresponding device.

[0189] For example, the first device region 100M includes a first sub-region 100MN and a second sub-region 100MP. Therefore, in the first device region 100M, the conductive ions 215 in the polysilicon material layer 220 of each sub-region may have the same conductivity type or different conductivity types.

[0190] Specifically, using the first mask layer 334 as a mask, conductive ions 351 are implanted into the polysilicon gate layer 330 exposed in the groove 333.

[0191] In this embodiment, the conductive ions 351 are implanted into the polysilicon gate layer 330 exposed in the groove 333 by means of ion implantation 335. The process of ion implantation is relatively simple.

[0192] It should be noted that the angle of the included angle should not be too small or too large. If the angle of the included angle is too small, it is difficult for the conductive ions 351 to be implanted into the top gate layer 331, which is not conducive to reducing the resistance of the polysilicon gate layer 330 in the first device region 100M; if the angle of the included angle is too large, it is easily affected by the shadow effect, resulting in the difficulty of implanting the conductive ions 351 into the groove 333, which is also not conducive to reducing the resistance of the polysilicon gate layer 330 in the first device region 100M. Therefore, in this embodiment, the angle of the included angle is 5 degrees to 30 degrees. For example, the angle of the included angle is 10 degrees, 15 degrees, 20 degrees or 25 degrees. Herein, the included angle refers to the included angle between the implantation direction of the conductive ions 351 and the normal direction of the bottom surface of the groove 333.

[0193] In other embodiments, during the actual process, the angle of the included angle can be adjusted according to the line width dimension of the groove. For example, when the line width dimension of the groove is relatively large, the angle of the included angle can be greater than 30 degrees.

[0194] It should also be noted that the implantation energy of the ion implantation process should not be too small or too large. If the implantation energy is too small, it is difficult to ensure that both the top gate layer 331 and the bottom gate layer 332 within the entire thickness range can be implanted with the conductive ions 351, and the conductivity uniformity of the conductive ions 351 in the polysilicon gate layer 330 is relatively low. Correspondingly, it is not conducive to reducing the resistance of the polysilicon gate layer 330 in the first device region 100M; if the implantation energy is too large, the conductive ions 351 are easily implanted into the substrate 100 below the polysilicon gate layer 330 through the bottom of the groove 333, thus having an adverse effect on the performance of the second device. Therefore, in this embodiment, the implantation energy of the ion implantation process is 1 KeV to 10 KeV. For example, the implantation energy of the ion implantation process is 3 KeV, 5 KeV, 7 KeV or 9 KeV.

[0195] In this embodiment, after injecting conductive ions 351 into the polysilicon gate layer 330 exposed by the groove 333, it further includes: removing the first mask layer 334.

[0196] In this embodiment, the material of the first mask layer 334 is photoresist, and accordingly, an ashing process is used to remove the first mask layer 334. The ashing process is simple and causes little damage to other film layers.

[0197] Reference Figure 13 , after injecting conductive ions 351 into the polysilicon gate layer 330 exposed by the groove 333, it further includes: forming a sidewall 390 on the sidewalls of the polysilicon gate layer 330 and the groove 333.

[0198] The sidewall 390 is used to protect the sidewalls of the polysilicon gate layer 330 and also to define the positions of subsequent source and drain doping regions.

[0199] In this embodiment, the sidewall 390 is formed after injecting conductive ions 351 into the polysilicon gate layer 330. That is, when injecting conductive ions 351 into the polysilicon gate layer 330, the polysilicon gate layer 330 is exposed by the sidewalls of the groove 333, so that the conductive ions 351 can be injected into the polysilicon gate layer 330 through the sidewalls of the groove 333.

[0200] Moreover, the sidewall 390 is also formed on the sidewalls of the groove 333. During the subsequent planarization process, it is beneficial to further reduce the probability of over-grinding the top surface of the polysilicon gate layer 330, thereby further improving the problem of top surface depression of the polysilicon gate layer 330.

[0201] The material of the sidewall 390 is selected as follows: the material has high hardness and density, and the planarization process has a small grinding rate for the sidewall 390, which is beneficial to further improving the problem of top surface depression of the polysilicon gate layer 330 in the first device region 100M.

[0202] Therefore, the material of the sidewall 390 includes silicon nitride or silicon oxynitride.

[0203] In this embodiment, the material of the sidewall 390 includes silicon nitride. Silicon nitride has high hardness and density.

[0204] As an example, the sidewall 390 is a stacked structure, and the sidewall 390 includes a silicon oxide layer covering the sidewalls of the polysilicon gate layer 330 and the groove 333 and a silicon nitride layer covering the sidewalls of the silicon oxide layer.

[0205] In other embodiments, the sidewall can also be a single-layer structure or a four-layer structure. For example, the four-layer structure can be an ONON (Oxide - SiN - Oxide - SiN) structure.

[0206] In this embodiment, the sidewall 390 also covers the sidewalls of the gate oxide layer 210.

[0207] It should be noted that in other embodiments, according to process requirements, after etching the polysilicon material layer to form discrete polysilicon gate layers and etching the high - k gate dielectric material layer, metal barrier material layer, and gate oxide layer exposed by the polysilicon gate layer, before etching the polysilicon gate layer to form a groove, the sidewall can be formed on the sidewalls of the polysilicon gate layer. Among them, after etching the high - k gate dielectric material layer, metal barrier material layer, and gate oxide layer exposed by the polysilicon gate layer, the sidewalls of the high - k gate dielectric layer, metal barrier layer, and gate oxide layer below the polysilicon gate layer are exposed. Therefore, by forming the sidewall first, the sidewall plays a protective role for the high - k gate dielectric layer, metal barrier layer, and gate oxide layer, thereby reducing the probability of pollution problems caused by long - term exposure of the high - k gate dielectric layer or metal barrier layer and reducing the probability of adverse effects on the quality of the gate oxide layer.

[0208] With reference to Figure 14 and Figure 15 , after forming the sidewall 390, the forming method further includes: forming source - drain doping regions 350 in the substrate 100 on both sides of the polysilicon gate layer 330.

[0209] The source - drain doping regions 350 serve as the source region or drain region of the formed device.

[0210] The conduction type of the doping ions in the source - drain doping regions 350 is the same as the channel conduction type of the corresponding device. When the formed device is an NMOS device, the doping ions in the source - drain doping regions 350 are N - type ions, and the N - type ions include P ions, As ions, or Sb ions. When the formed device is a PMOS device, the doping ions in the source - drain doping regions 350 are P - type ions, and the P - type ions include B ions, Ga ions, or In ions.

[0211] In this embodiment, an ion implantation process is used to implant ions into the substrate 100 on both sides of the polysilicon gate layer 330 to form the source - drain doping regions 350.

[0212] Specifically, the source - drain doping process is respectively performed on the first device region 100M and the second device region 100L to form the source - drain doping regions 350.

[0213] As Figure 14As shown, in this embodiment, taking the formation of source / drain doping regions 350 in the substrate 100 of the first sub-region 100MN as an example, the source / drain doping process includes: forming a second mask layer 351 on the substrate 100, the second mask layer 351 also covering the bottom of the groove 333, and in the first sub-region 100MN, second mask openings 352 penetrating through the second mask layer 351 are formed in the second mask layer 351 on both sides of the polysilicon gate layer 330; performing source / drain doping on the substrate 100 exposed by the second mask openings 352 to form source / drain doping regions 350 in the substrate 100.

[0214] In this embodiment, after forming the source / drain doping regions 350, the source / drain doping process further includes: removing the second mask layer 351.

[0215] Correspondingly, source / drain doping region processes are respectively performed on the first sub-region 100MP and the second device region 100L, so as to form source / drain doping regions 350 in the substrate 100 on both sides of the polysilicon gate layer 330 in the first sub-region 100MP and in the substrate 100 on both sides of the polysilicon gate layer 330 in the second device region 100L respectively. The specific steps can refer to the description when forming the source / drain doping regions 350 in the substrate 100 of the first sub-region 100MN, and will not be elaborated here.

[0216] It should be noted that when forming the source / drain doping regions 350, due to the relatively large implantation energy of the ion implantation process, therefore, using different processes, conductive ions 351 are respectively implanted into the polysilicon gate layer 330 exposed by the groove 333, and the source / drain doping regions 350 are formed, and the second mask layer 351 also covers the bottom of the groove 333, thereby reducing the probability that ions are implanted into the substrate 100 at the bottom of the polysilicon gate layer 330 through the bottom of the groove 333.

[0217] Reference Figure 16 , after implanting conductive ions 351 into the polysilicon gate layer 330 exposed by the groove 333, the forming method further includes: forming a gate silicide layer 361 on the bottom surface of the groove 333.

[0218] Specifically, a gate silicide layer 361 is formed on the bottom surface of the groove 333 exposed by the sidewall 390.

[0219] By forming a gate silicide layer 361 on the bottom surface of the groove 333, when the first device operates, current can flow through the gate silicide layer 361, thereby playing a role in reducing the gate resistance.

[0220] In this embodiment, the material of the gate silicide layer 361 can be nickel silicide, cobalt silicide or titanium silicide.

[0221] It should be noted that a gate mask layer 340 is formed on the top of the polysilicon gate layer 330. Therefore, during the formation of the gate silicide layer 361, the gate mask layer 340 is used as a protective layer to prevent the formation of the gate silicide layer 361 on the top surface of the polysilicon gate layer 330. Thus, during the subsequent planarization process of forming the metal gate layer, the gate silicide layer 361 will not be polished, thereby avoiding metal contamination of the polishing machine.

[0222] In this embodiment, the forming method further includes: forming a source / drain silicide layer 360 on the surface of the source / drain doped region 350, and forming the gate silicide layer 361 during the formation of the source / drain silicide layer 360.

[0223] Subsequently, a source / drain contact plug is formed on the top of the source / drain doped region 350. By forming the source / drain silicide layer 360, the contact resistance between the source / drain doped region 350 and the source / drain contact plug is reduced.

[0224] Moreover, in this embodiment, the source / drain silicide layer 360 and the gate silicide layer 361 are formed in the same step, thus simplifying the process steps.

[0225] Specifically, a metal layer is formed on the surface of the source / drain doped region 350 and the bottom surface of the groove 333, and an annealing treatment is performed to cause the metal layer to react with the materials of the source / drain doped region 350 and the bottom gate layer 332, thereby converting the metal layer on the surface of the source / drain doped region 350 into the source / drain silicide layer 360, and converting the metal layer on the bottom surface of the groove 333 into the gate silicide layer 361. After the formation of the source / drain silicide layer 360 and the gate silicide layer 361, the unreacted remaining metal layer is removed.

[0226] It should be noted that before the formation of the source / drain silicide layer 360 and the gate silicide layer 361, there is also a step of forming a silicide block (SAB) layer (not shown in the figure). By forming the silicide blocking layer, the regions for forming the source / drain silicide layer 360 and the gate silicide layer 361 are exposed, and the regions where silicide layers are not expected to be formed are protected.

[0227] It should also be noted that before the formation of the source / drain silicide layer 360 and the gate silicide layer 361, it further includes: removing the oxide layer (e.g., natural oxide layer) on the surface of the substrate 100 exposed by the silicide blocking layer or the remaining gate oxide layer 210 in the first device region 100M, and removing the natural oxide layer on the bottom surface of the groove 333, thereby exposing the surface of the source / drain doped region 350 and the surface of the bottom gate layer 332, and further preparing for the formation of the source / drain silicide layer 360 and the gate silicide layer 361.

[0228] Reference Figure 17 On the substrate 100 on the side of the polysilicon gate layer 330 and in the groove 333, an Inter Layer Dielectric (ILD) layer 370 is formed, and the top of the polysilicon gate layer 330 in the second device region 100L is exposed by the interlayer dielectric layer 370.

[0229] The interlayer dielectric layer 370 is used to isolate adjacent devices.

[0230] Moreover, the top of the polysilicon gate layer 330 in the second device region 100L is exposed by the interlayer dielectric layer 370, so as to prepare for removing the polysilicon gate layer 330 in the second device region 100L subsequently.

[0231] The material of the interlayer dielectric layer 370 is an insulating material, and the material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 370 is silicon oxide.

[0232] Specifically, the interlayer dielectric layer 370 is formed by a deposition and planarization process (for example, a chemical mechanical polishing process), so that the top of the polysilicon gate layer 330 in the second device region 100L is exposed by the interlayer dielectric layer 370.

[0233] It should be noted that the operating voltage of the first device is relatively high. Therefore, the thickness of the gate oxide layer 210 is usually relatively large. Correspondingly, the top of the polysilicon gate layer 330 in the first device region 100M is usually higher than the top of the polysilicon gate layer 330 in the second device region 100L. Therefore, after the interlayer dielectric layer 370 is formed, the top of the polysilicon gate layer 330 in the first device region 100M is usually also exposed by the interlayer dielectric layer 370.

[0234] In this embodiment, during the formation of the interlayer dielectric layer 370, the gate mask layer 340 located on the top of the polysilicon gate layer 330 and the sidewall 390 higher than the top of the polysilicon gate layer 330 are removed.

[0235] In this embodiment, the interlayer dielectric layer 370 fills the groove 333.

[0236] Reference Figure 18 The polysilicon gate layer 330 in the second device region 100L is removed, and a gate opening 381 is formed in the interlayer dielectric layer 370, and the gate opening 381 exposes the metal barrier layer 320.

[0237] The gate opening 381 is used to provide a spatial position for forming the metal gate layer.

[0238] In this embodiment, one or both of a dry etching process and a wet etching process are used to remove the polysilicon gate layer 330 in the second device region 100L.

[0239] Reference Figure 19 , a metal gate layer 380 is formed in the gate opening 381 (as Figure 18 shown).

[0240] The high-k gate dielectric layer 310, the metal barrier layer 320, and the metal gate layer 380 in the second device region 100L are used to form a metal gate structure.

[0241] Since the operating voltage of the second device is small, therefore, as the critical dimensions of the device continue to shrink, by adopting a metal gate structure, it is beneficial to improve the short-channel effect.

[0242] The metal gate layer 380 is used to lead out the electrical property of the metal gate structure.

[0243] Specifically, the step of forming the metal gate layer 380 in the gate opening 381 includes: filling the gate opening 381 with a metal gate material, and the metal gate material also covers the top of the interlayer dielectric layer 370; performing a planarization process (for example, chemical mechanical polishing) on the metal gate material to remove the metal gate material higher than the top of the interlayer dielectric layer 370, and retaining the remaining metal gate material in the gate opening 381 as the metal gate layer 380.

[0244] The material of the metal gate layer 380 is Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In this embodiment, the material of the metal gate layer 380 is Al.

[0245] It should be noted that in the second device region 100L, when a gate oxide layer is further formed between the high-k gate dielectric layer 310 and the substrate 100, the metal gate structure further includes the gate oxide layer.

[0246] It should also be noted that before filling the gate opening 381 with the metal gate material, there is also a step of forming a work function layer in the gate opening 381, which is not elaborated in this embodiment.

[0247] Figure 20 Schematic diagram of the structure of another embodiment of the method for forming the semiconductor structure of the present invention.

[0248] The same parts of the embodiments of the present invention and the foregoing embodiments will not be described herein again. The differences between the embodiments of the present invention and the foregoing embodiments are as follows: In the step of forming the silicide blocking layer 800, the silicide blocking layer 800 is located on a part of the substrate, and the silicide blocking layer 800 also covers the top of the top gate layer 731 of the first device region (not labeled).

[0249] In this embodiment, the material of the silicide blocking layer 800 includes silicon nitride. The hardness and density of silicon nitride are relatively high, and the polishing rate of the silicide blocking layer 800 by the planarization process is small. By making the silicide blocking layer 800 also cover the top of the top gate layer 731 of the first device region, the probability of over-polishing the top of the top gate layer 731 is further reduced during the subsequent planarization process of forming the interlayer dielectric layer, thereby further improving the problem of the top surface depression of the polysilicon gate layer (not labeled) of the first device region (not labeled).

[0250] In this embodiment, a gate mask layer 740 is formed on the top of the top gate layer 731. Therefore, in the step of forming the silicide blocking layer 800, the silicide blocking layer 800 covers a part of the substrate 100 and the gate mask layer 740, and exposes the source-drain doping region (not labeled) and the bottom surface of the groove 733.

[0251] Correspondingly, a source-drain silicide layer 760 is formed on the surface of the source-drain doping region exposed by the silicide blocking layer 800, and a gate silicide layer 761 is formed on the bottom surface of the groove 733 exposed by the silicide blocking layer 800.

[0252] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, it includes: a substrate, including a first device region for forming a first device and a second device region for forming a second device, wherein the channel length of the first device is greater than that of the second device; a polysilicon gate layer located on the substrate of the first device region, the polysilicon gate layer including a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer enclosing a groove, and both the top gate layer and the bottom gate layer are doped with conductive ions; a metal gate layer located on the substrate of the second device region; an interlayer dielectric layer located on the substrate on the sides of the polysilicon gate layer and the metal gate layer and filling the groove.

2. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure further includes: sidewalls located on the sidewalls of the polysilicon gate layer, the sidewalls of the groove, and the sidewalls of the metal gate layer.

3. The semiconductor structure according to claim 2, characterized in that, the material of the sidewalls includes silicon nitride or silicon oxynitride.

4. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure further includes: a gate silicide layer located on the bottom surface of the groove.

5. The semiconductor structure according to claim 1, characterized in that, the conductive ions include B ions, Ga ions, In ions, P ions, As ions or Sb ions.

6. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure further includes: a stacked structure located between the polysilicon gate layer and the substrate and between the metal gate layer and the substrate, the stacked structure including a high-k gate dielectric layer and a metal barrier layer stacked in sequence from bottom to top.

7. The semiconductor structure according to claim 1, characterized in that, the line width dimension of the top gate layer is from 0.15 micrometers to 2 micrometers, and the line width dimension of the groove is from 0.15 micrometers to 2 micrometers.

8. The semiconductor structure according to claim 1, characterized in that, the thickness of the top gate layer accounts for 1 / 5 to 1 / 3 of the total thickness of the polysilicon gate layer.

9. A method for forming a semiconductor structure, characterized in that, it includes: providing a substrate, including a first device region for forming a first device and a second device region for forming a second device, wherein the channel length of the first device is greater than that of the second device; forming a discrete polysilicon gate layer on the substrates of the first device region and the second device region. In the first device region, the polysilicon gate layer includes a bottom gate layer and a top gate layer protruding from the bottom gate layer, and the top gate layer and the bottom gate layer enclose a groove; injecting conductive ions into the polysilicon gate layer exposed by the groove, and the injection direction of the conductive ions has an acute angle with the normal direction of the bottom surface of the groove; after injecting conductive ions into the polysilicon gate layer exposed by the groove, forming an interlayer dielectric layer on the substrate on the side of the polysilicon gate layer and in the groove, and the interlayer dielectric layer exposes the top of the polysilicon gate layer in the second device region; Remove the polysilicon gate layer in the second device region and form a gate opening in the interlayer dielectric layer; Form a metal gate layer in the gate opening.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, After forming the polysilicon gate layer, form the groove in the polysilicon gate layer in the first device region; Before forming the groove, the forming method further includes: forming a first mask layer covering the substrate and the polysilicon gate layer, a first mask opening is formed in the first mask layer in the first device region, and the first mask opening is located above a part of the top of the polysilicon gate layer; The step of forming the groove includes: using the first mask layer as a mask to etch a part of the thickness of the polysilicon gate layer along the first mask opening; In the step of implanting conductive ions into the polysilicon gate layer exposed by the groove, use the first mask layer as a mask; After implanting conductive ions into the polysilicon gate layer exposed by the groove and before forming the interlayer dielectric layer, the forming method further includes: removing the first mask layer.

11. The method for forming a semiconductor structure according to claim 9, characterized in that, The angle of the included angle is 5 degrees to 30 degrees.

12. The method for forming a semiconductor structure according to claim 9, characterized in that, Use an ion implantation process to dope conductive ions into the polysilicon gate layer exposed by the groove, and the implantation energy of the ion implantation process is 1 KeV to 10 KeV.

13. The method for forming a semiconductor structure according to claim 9, characterized in that, The step of forming the polysilicon gate layer includes: forming a polysilicon material layer covering the substrates in the first device region and the second device region; etching the polysilicon material layer to form discrete polysilicon gate layers.

14. The method for forming a semiconductor structure according to claim 9, characterized in that, After implanting conductive ions into the polysilicon gate layer exposed by the groove and before forming the interlayer dielectric layer, the forming method further includes: forming sidewalls on the sidewalls of the polysilicon gate layer and the sidewalls of the groove.

15. The method for forming a semiconductor structure according to claim 9, characterized in that, After implanting conductive ions into the polysilicon gate layer exposed by the groove and before forming the interlayer dielectric layer, the forming method further includes: forming a gate silicide layer on the bottom surface of the groove.

16. The method for forming a semiconductor structure according to claim 15, characterized in that, In the step of forming the polysilicon gate layer, a gate mask layer is further formed on the top of the top gate layer; Using the gate mask layer as a protection layer, form a gate silicide layer on the bottom surface of the groove.

17. The method for forming a semiconductor structure according to claim 15, characterized in that, Before forming the gate silicide layer on the bottom surface of the groove, the forming method further includes: forming a silicide blocking layer on a part of the substrate, and the silicide blocking layer also covers the top of the top gate layer.

18. The method for forming a semiconductor structure according to claim 15, characterized in that, Before forming the interlayer dielectric layer after injecting conductive ions into the polysilicon gate layer exposed in the groove, the forming method further includes: forming source / drain doping regions in the substrate on both sides of the polysilicon gate layer; forming source / drain silicide layers on the surfaces of the source / drain doping regions, and forming the gate silicide layer during the process of forming the source / drain silicide layers.

19. The forming method of the semiconductor structure according to claim 9, wherein, before forming the interlayer dielectric layer after injecting conductive ions into the polysilicon gate layer exposed in the groove, the forming method further includes: performing source / drain doping processes on the first device region and the second device region respectively; wherein, the source / drain doping process includes: forming a second mask layer on the substrate, the second mask layer further covering the bottom of the groove, and second mask openings penetrating through the second mask layer are formed in the second mask layer on both sides of the polysilicon gate layer; performing source / drain doping on the substrate exposed by the second mask openings to form source / drain doping regions in the substrate; removing the second mask layer.

20. The forming method of the semiconductor structure according to claim 9, wherein, the step of forming a metal gate layer in the gate opening includes: filling a metal gate material into the gate opening, and the metal gate material further covers the interlayer dielectric layer; performing a planarization process on the metal gate material to remove the metal gate material higher than the top of the interlayer dielectric layer, and retaining the remaining metal gate material in the gate opening as the metal gate layer.

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