Ferroelectric field effect transistor memory and its manufacturing method, operation method, and read / write circuit

Abstract

The present invention relates to a ferroelectric field effect transistor memory, a manufacturing method thereof, an operation method thereof, and a read / write circuit. The memory includes: a substrate; a first insulating layer disposed on the substrate; a fin body disposed on the first insulating layer; a first gate disposed on a first side, including a first gate electrode and a first dielectric layer disposed between the first gate electrode and the fin body; a second gate disposed on a second side, including a second gate electrode, a ferroelectric layer, and a second dielectric layer, the ferroelectric layer and the second dielectric layer being disposed between the second gate electrode and the fin body, and the ferroelectric layer being disposed between the second gate electrode and the second dielectric layer; a source electrode disposed at a first end and connected to the fin body; and a drain electrode disposed at a second end and connected to the fin body. By applying a polarization reversal voltage to the ferroelectric layer on the double gate electrodes in the present invention, it is equivalent to directly applying a polarization reversal voltage to the ferroelectric layer and the semiconductor fin body, which can to a certain extent alleviate the problem of voltage division between the dielectric layer and the long channel of the field effect transistor, and further improve the write operation speed of the ferroelectric memory.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to a ferroelectric field effect transistor memory, a manufacturing method of a ferroelectric field effect transistor memory, an operating method of a ferroelectric field effect transistor memory, and a read / write circuit of a ferroelectric field effect transistor memory. Background Art

[0002] Ferroelectric materials generally refer to materials that have spontaneous polarization in the state without applying an external electric field. Specifically, a ferroelectric material can maintain either of two stable remanent polarization states. These characteristics can be used in a storage device to store logical information "0" or "1" in a non-volatile manner.

[0003] In an exemplary ferroelectric field effect transistor memory technology, there is a problem of voltage division between a dielectric layer and a long channel of a field effect transistor, and the write operation speed of the ferroelectric field effect transistor memory is relatively slow. Summary of the Invention

[0004] Based on this, it is necessary to provide a ferroelectric field effect transistor memory, a manufacturing method thereof, an operating method thereof, and a read / write circuit thereof.

[0005] A ferroelectric field effect transistor memory includes: a substrate; a first insulating layer disposed on the substrate; a fin body disposed on the first insulating layer, made of semiconductor and serving as a channel region, the fin body having opposite first and second sides and opposite first and second ends in the horizontal direction of the ferroelectric field effect transistor memory; a first gate disposed on the first side, including a first gate electrode and a first dielectric layer disposed between the first gate electrode and the fin body; a second gate disposed on the second side, including a second gate electrode, a ferroelectric layer, and a second dielectric layer, the ferroelectric layer and the second dielectric layer being disposed between the second gate electrode and the fin body, the ferroelectric layer being disposed between the second gate electrode and the second dielectric layer; a source electrode disposed at the first end and connected to the fin body; a drain electrode disposed at the second end and connected to the fin body; wherein, the first gate, the fin body, the source electrode, and the drain electrode serve as a fin field effect transistor, and the second gate, the fin body, the source electrode, and the drain electrode serve as a fin ferroelectric field effect transistor.

[0006] In one embodiment, the second gate further includes an electrode layer disposed between the second gate electrode and the ferroelectric layer.

[0007] In one embodiment, it further includes a second insulating layer disposed on the top of the fin body.

[0008] A manufacturing method of a ferroelectric field effect transistor memory, comprising: obtaining a substrate, the substrate including a substrate and a first insulating layer on the substrate; forming a fin body and a second insulating layer on the first insulating layer; the second insulating layer is formed on the fin body, the material of the fin body is semiconductor, the fin body has opposite first and second sides and opposite first and second ends in the horizontal direction of the ferroelectric field effect transistor memory, and the first end and the second end of the fin body are exposed by the second insulating layer; forming a first dielectric layer on the first side and a second dielectric layer on the second side; forming a ferroelectric layer on a side of the second dielectric layer opposite to the fin body; forming a first gate and a second gate, the first gate is formed on a side of the first dielectric layer opposite to the fin body, and the second gate is formed on a side of the ferroelectric layer opposite to the fin body; doping the fin body to form a source electrode at the first end and a drain electrode at the second end.

[0009] In one embodiment, after the step of forming the ferroelectric layer on the side of the second dielectric layer opposite to the fin body and before the step of forming the first gate and the second gate, the method further includes a step of forming an electrode layer on the side of the ferroelectric layer opposite to the fin body.

[0010] In one embodiment, after the step of forming the electrode layer on the side of the ferroelectric layer opposite to the fin body and before the step of forming the first gate and the second gate, the method further includes a step of performing ion implantation on the ferroelectric layer and the electrode layer to eliminate interface defects.

[0011] In one embodiment, the first gate and the second gate are polysilicon gates, and the material of the electrode layer includes at least one of TiN, TaN, and AlTiN.

[0012] In one embodiment, the method further includes a step of forming sidewalls on the outer sides of the first gate and the second gate.

[0013] In one embodiment, the method further includes a step of forming a source elevation portion on the source electrode and a drain elevation portion on the drain electrode.

[0014] An operation method of a ferroelectric field-effect transistor memory according to any one of the foregoing embodiments, the operation including a read operation or a write operation; the read operation includes: applying a read voltage to the second gate, floating the first gate, and applying a first voltage between the source and the drain; detecting the magnitude of the current between the source and the drain, and if the current is greater than a preset current value, determining that the ferroelectric memory is in an erased state; if the current is less than the preset current value, determining that the ferroelectric memory is in a programmed state; the write operation includes an erase operation or a programming operation, the erase operation includes applying a second voltage to the second gate and a third voltage to the first gate, floating the source and the drain, and the difference between the second voltage and the third voltage is not less than the threshold voltage of the erase operation or not less than the coercive field voltage of the ferroelectric layer; the programming operation includes applying a fourth voltage to the first gate and a fifth voltage to the second gate, floating the source and the drain, and the difference between the fourth voltage and the fifth voltage is not less than the threshold voltage of the programming operation or not less than the coercive field voltage of the ferroelectric layer.

[0015] A read / write circuit of a ferroelectric field-effect transistor memory, including at least one ferroelectric field-effect transistor memory according to any one of the foregoing embodiments, further including a word line pair, a bit line pair, a first switch unit, and a second switch unit, the word line pair including a first word line and a second word line, the bit line pair including a first bit line and a second bit line; the second gate of at least one ferroelectric field-effect transistor memory is connected to the first word line, the first gate is connected to the second word line, the drain is connected to the first bit line, and the source is connected to the second bit line; the first switch unit is connected to the first bit line and is used to control the first bit line to be open when closed and conduct when open; the second switch unit is connected to the first bit line and the second bit line and is used to short-circuit the first bit line and the second bit line when open.

[0016] For the above ferroelectric field-effect transistor memory, when working, applying a polarization reversal voltage to the ferroelectric layer on the double gate is equivalent to directly applying a polarization reversal voltage to the ferroelectric layer and the semiconductor fin body, which can, to a certain extent, alleviate the problem of voltage division between the dielectric layer and the long channel of the field-effect transistor, and further improve the write operation speed of the ferroelectric memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the inventions disclosed, the embodiments and / or examples currently described, and the best mode of these inventions currently understood.

[0018] Figure 1 is a schematic structural diagram of a ferroelectric field-effect transistor memory in an embodiment;

[0019] Figure 2 is a top view of the structure of a ferroelectric field-effect transistor memory in one embodiment;

[0020] Figure 3 is a flowchart of a manufacturing method of a ferroelectric field-effect transistor memory in one embodiment;

[0021] Figure 4 is a schematic structural diagram of a device after step S120 is completed in one embodiment;

[0022] Figure 5 is a schematic structural diagram of a device after step S130 is completed in one embodiment;

[0023] Figure 6 is a schematic structural diagram of a device in which a ferroelectric layer and an electrode layer are formed on both the first side and the second side of a fin body after step S140 in one embodiment;

[0024] Figure 7 is in one embodiment Figure 6 is a schematic structural diagram after removing the ferroelectric layer and the electrode layer on the second side in the shown structure;

[0025] Figure 8 is a schematic structural diagram of a device after depositing polysilicon in step S150 in one embodiment;

[0026] Figure 9 is a schematic diagram after performing CMP and etching processes on the deposited polysilicon in step S150 in one embodiment;

[0027] Figure 10 is a top view of the structure of a ferroelectric field-effect transistor memory after step S150 is completed in one embodiment;

[0028] Figure 11 is Figure 10 is a cross-sectional view along BB' of the shown structure;

[0029] Figure 12 is a schematic structural diagram of a device after forming sidewalls in one embodiment;

[0030] Figure 13 is a schematic structural diagram of a device after forming a source electrode and a drain electrode in step S160 in one embodiment;

[0031] Figure 14 is a schematic structural diagram of a device after forming a source electrode elevation portion and a drain electrode elevation portion in one embodiment;

[0032] Figure 15 is a schematic structural diagram of a device after forming an interlayer dielectric layer and tungsten plugs in one embodiment;

[0033] Figure 16 is a flowchart of a read operation in one embodiment;

[0034] Figure 17 is Figure 1 The power-on schematic diagram when the shown structure performs a read operation in an embodiment;

[0035] Figure 18 is Figure 1 The power-on schematic diagram when the shown structure performs an erase operation in an embodiment;

[0036] Figure 19 is Figure 1 The power-on schematic diagram when the shown structure performs a programming operation in an embodiment;

[0037] Figure 20 It is the circuit schematic diagram of the read / write circuit of the ferroelectric field-effect transistor memory in an embodiment;

[0038] Figure 21 It is the structural schematic diagram of an exemplary ferroelectric field-effect transistor memory. Detailed implementation manners

[0039] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0041] It should be noted that when an element is referred to as "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this article are only for the purpose of illustration. When an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to other elements or layers, or there can be intermediate elements or layers. On the contrary, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" other elements or layers, there are no intermediate elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part.

[0042] When the terms "comprise" and / or "include" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof. The singular forms of "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise.

[0043] Since the remanent polarization can be switched by the application of an external electric field, research on the application of ferroelectric materials in non-volatile memory devices has been actively carried out. As an application example, in a cell structure with a single transistor, a non-volatile memory device can use a ferroelectric material in the gate dielectric layer of the transistor. According to the magnitude or polarity of the voltage applied from the outside, the gate dielectric layer including the ferroelectric material can store remanent polarizations with different polarization directions. Additionally, different potential polarization directions can induce different types of charges into the channel region of the transistor. As a result, the channel resistance of the transistor can be measured to identify the stored remanent polarization. Currently, due to the breakthrough in the research on ferroelectricity in doped hafnium-based materials, ferroelectric transistors as non-volatile memories have attracted extensive research by researchers. Among them, hafnium-based ferroelectric memories have advantages such as easy miniaturization and compatibility with traditional CMOS processes. However, during the erasing and writing processes of traditional hafnium-based ferroelectric memories, a large number of carriers are injected into the ferroelectric thin film layer due to the high switching electric field, resulting in a large number of charged defects in the ferroelectric thin film. This has a shielding effect on the spontaneous polarization intensity of the ferroelectric thin film body and a pinning effect on the domain inversion, resulting in a decrease in the spontaneous polarization intensity of the ferroelectric thin film with the number of read / write switching times; thus reducing its storage window and further decreasing the durability. At the same time, the release process of the charges trapped in the ferroelectric layer also affects the read operation after erasing and writing, thus limiting the read speed. And the distribution of the electric field in the ferroelectric layer and the dielectric layer is unreasonable. On the one hand, it reduces the electric field between the two sides of the ferroelectric layer, resulting in the device operating in the ferroelectric non-saturated region, thus reducing the storage window; on the other hand, it makes the electric field on both sides of the dielectric layer too large, resulting in an increase in its leakage current.

[0044] Figure 21is a schematic structural diagram of an exemplary planar MFIS ferroelectric field effect transistor memory, including: a substrate, a source region, a drain region, and a gate stack structure; the gate stack structure includes a dielectric layer, a ferroelectric thin film layer, and a gate arranged in sequence. The endurance performance of this ferroelectric field effect transistor memory is poor, and the main reason is that: due to the relatively large reverse electric field of the ferroelectric thin film applied between the gate and the source or the drain, charge injection effects occur at the ferroelectric thin film / dielectric layer (i.e., the oxide layer) / semiconductor interface of the source or the drain. Specifically: when a positive voltage Vdd is applied to the gate and the source / drain is grounded (G) simultaneously, the positive polarization intensity of the ferroelectric thin film reverses towards the channel or the semiconductor direction. Under the action of the positive voltage between the source / drain and the gate, negative electrons or other negatively charged defects can be injected into the doped ferroelectric thin film in large quantities through the ferroelectric thin film dielectric layer / semiconductor interface, resulting in poor fatigue / endurance performance of the ferroelectric thin film. To solve this problem, a ferroelectric field effect transistor memory with an MFMIS structure has been proposed, where a voltage is applied between the main gate and the secondary gate of the conductor when the polarization intensity of the ferroelectric thin film reverses. However, the leakage current of the ferroelectric field effect transistor memory with the MFMIS structure is very poor and does not meet the usage requirements.

[0045] Figure 1 is a schematic structural diagram of a ferroelectric field effect transistor memory in an embodiment, including a substrate 110, a first insulating layer 120, a fin body 130, a source 140, a drain 160, a first gate, and a second gate. The first insulating layer 120 is disposed on the substrate 110. The fin body 130 made of semiconductor material is disposed on the first insulating layer 120 and serves as the channel region. The fin body 130 has opposite first and second sides (i.e., Figure 1 the left and right sides of the fin body 130 in the figure) and opposite first and second ends in the horizontal direction of the ferroelectric field effect transistor memory.

[0046] The first gate includes a first gate electrode 150 and a first dielectric layer 131 disposed between the first gate electrode 150 and the fin body 130, and the first gate is disposed Figure 1 on the left side of the fin body 130 in the figure. The second gate includes a second gate electrode 151, a ferroelectric layer 133, and a second dielectric layer 132. The ferroelectric layer 133 and the second dielectric layer 132 are disposed between the second gate electrode 151 and the fin body 130, and the ferroelectric layer 133 is disposed between the second gate electrode 151 and the second dielectric layer 132. The second gate is disposed Figure 1 on the right side of the fin body 130 in the figure. In Figure 1In the illustrated embodiment, the second gate further includes an electrode layer 134 disposed between the second gate electrode 151 and the ferroelectric layer 133. That is, the second gate, starting from the second side of the fin body 130, includes, in sequence, a second dielectric layer 132, a ferroelectric layer 133, an electrode layer 134, and a second gate electrode 151. The first dielectric layer 131 and the second dielectric layer 132 serve as the gate oxide layers of the first gate electrode 150 and the second gate electrode 151, respectively.

[0047] The source electrode 140 is disposed at the first end of the fin body 130 and is connected to the fin body 130. The drain electrode 160 is disposed at the second end of the fin body 130 and is connected to the fin body 130.

[0048] Among them, the first gate, the fin body 130, the source electrode 140, and the drain electrode 160 serve as a fin field-effect transistor, and the second gate, the fin body 130, the source electrode 140, and the drain electrode 160 serve as a fin ferroelectric field-effect transistor. Thus, in a single FinFET unit, a storage element (fin ferroelectric field-effect transistor) and a logic element (fin field-effect transistor) are integrated simultaneously. Therefore, the dual-gate ferroelectric field-effect transistor can have two application operation modes: 1) ferroelectric field-effect transistor memory; 2) negative capacitance field-effect transistor. The channel current in the fin body 130 can be controlled separately through the dual gate electrodes, and device parameters such as the threshold voltage and sub-threshold swing (SS) can be adjusted by controlling the channel current to suit different applications. In particular, since one side of the dual-gate ferroelectric field-effect transistor is a fin ferroelectric field-effect transistor, the sub-threshold swing of the dual-gate FinFET can be significantly lower than 60 mV / dec. The dual-gate ferroelectric field-effect transistor can dynamically modulate the performance of the FinFET. For example, a control signal sent from an integrated circuit can be transmitted to one of the gate electrodes to modulate the performance of the dual-gate ferroelectric field-effect transistor. Based on the above characteristics, the dual-gate ferroelectric field-effect transistor can be used in core logic circuits that require low leakage current.

[0049] The above ferroelectric field effect transistor memory uses a polarization inversion voltage applied to the ferroelectric layer 133 on the double gate electrodes, which is equivalent to directly applying a polarization inversion voltage to the ferroelectric layer 133 and the fin body 130 of the semiconductor. This can, to a certain extent, alleviate the problem of voltage division between the dielectric layer and the long channel of the field effect transistor, further improve the read operation and write operation speeds of the ferroelectric memory, and reduce the voltage for the write operation (writing 0 or writing 1). On the other hand, the erase operation / programming operation unit structure of the above ferroelectric field effect transistor memory is: a capacitor structure of conductor / ferroelectric layer / dielectric layer / semiconductor / dielectric layer / ferroelectric layer / conductor, or a capacitor structure of conductor / ferroelectric layer / dielectric layer / semiconductor / dielectric layer / conductor. By controlling the conductor / ferroelectric layer interface and reducing the amount of electrons injected into the ferroelectric layer through the interface between the electrode and the ferroelectric layer, the electron injection at the interface between the ferroelectric layer and the semiconductor layer and the charge trapping effect of the ferroelectric layer are effectively eliminated, increasing the storage window, thereby improving the endurance performance and retention characteristics of the device. The above ferroelectric field effect transistor memory can be mainly used for high-performance and low-power ferroelectric field effect transistor memories.

[0050] In one embodiment, the substrate 110 is a semiconductor substrate, and its material can be undoped single-crystalline silicon, doped single-crystalline silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc. In Figure 1 the illustrated embodiment, the material of the substrate 110 is selected as single-crystalline silicon.

[0051] In one embodiment, the material of the first insulating layer 120 can be an oxide of silicon (such as silicon dioxide) or a nitride of silicon (such as silicon nitride).

[0052] In one embodiment, the material of the fin body 130 is silicon; in another embodiment, the material of the fin body 130 is silicon germanide.

[0053] In one embodiment, the materials of the first dielectric layer 131 and the second dielectric layer 132 can be an oxide of silicon (such as silicon dioxide) or a nitride of silicon (such as silicon nitride) or a oxynitride of silicon (such as silicon oxynitride).

[0054] In Figure 1 the illustrated embodiment, the ferroelectric field effect transistor memory further includes a second insulating layer 155 disposed on the top of the fin body 130. The second insulating layer 155 is an insulating capping layer for isolating the first gate electrode 150 and the second gate electrode 151. The material of the insulating capping layer 155 can be silicon nitride or silicon oxide.

[0055] In one embodiment, the material of the ferroelectric layer 133 includes a host material and a dopant, where the host material can be at least one of HfZrO2, HfO2 (hafnium oxide), ZrO2 (zirconium oxide), Hf 0.5 Zr 0.5 O2 (hafnium zirconium oxide); the dopant can be at least one of carbon C, silicon Si, magnesium Mg, aluminum Al, yttrium Y, nitrogen N, germanium Ge, tin Sn, strontium Sr, lead Pb, calcium Ca, barium Ba, titanium Ti, zirconium Zr, gadolinium Gd, lanthanum La. The dopant can help stabilize the ferroelectricity of the ferroelectric layer.

[0056] In one embodiment, the materials of the first gate 150 and the second gate 151 are at least one of polysilicon, polysilicon silicide, tungsten metal, TaN, TiN, and metal nitride.

[0057] In one embodiment, the material of the electrode layer 134 includes at least one of TiN, TaN, and AlTiN. For example, it can be a composite layer of AlTiN and TaN.

[0058] In one embodiment, the fin body 710 can be doped or undoped. The thickness of the fin body 710 can be very thin (5 - 15 nm). In this case, the material of the fin body 710 can be undoped silicon, and such a fin body 710 can also form a fully depleted fin Si structure, which can ensure that the ferroelectric field effect transistor memory cell only requires a relatively small inversion voltage because the voltage drop in the depleted region is minimized.

[0059] Figure 2 is a top view of the structure of a ferroelectric field effect transistor memory in an embodiment, including: a fin body 230, a first gate 250, a second gate 251, a source 240, a drain 260, and a second insulating layer 255. The first gate 250 and the second gate 251 are located on the opposite lateral sides of the fin body 230 Figure 2 i.e., the first side and the second side. The source 240 and the drain 260 are located at the two longitudinal ends of the fin body 230 Figure 2 i.e., the first end and the second end. The second insulating layer 255 is located on top of the fin body 230, between the first gate 250 and the second gate 251. The isolation between the gates 250 and 251 is achieved through the second insulating layer 255.

[0060] The present application correspondingly provides a manufacturing method for a ferroelectric field effect transistor memory for manufacturing the ferroelectric field effect transistor memory described in any of the above embodiments. Figure 3 is a flowchart of a manufacturing method for a ferroelectric field effect transistor memory in an embodiment, including:

[0061] S110, obtaining a substrate.

[0062] The substrate includes a base substrate and a first insulating layer on the base substrate.

[0063] In one embodiment, the substrate is a semiconductor substrate, and its material can be undoped single-crystalline silicon, doped single-crystalline silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanide-on-insulator (S-SiGeOI), silicon germanide-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.

[0064] In one embodiment, the material of the first insulating layer can be an oxide of silicon (such as silicon dioxide) or a nitride of silicon (such as silicon nitride).

[0065] S120: Form a fin body and a second insulating layer on the first insulating layer.

[0066] Figure 4 is a schematic structural diagram of the device after step S120. From bottom to top, it is the base substrate 410, the first insulating layer 420, the fin body 710, and the second insulating layer 610. The material of the fin body 710 is a semiconductor, that is, the fin body 710 is formed by etching a semiconductor layer. The fin body 710 has opposite first and second sides and opposite first and second ends in the horizontal direction of the ferroelectric field-effect transistor memory, and the first end and the second end of the fin body 710 are exposed. In one embodiment, the second insulating layer 610 can be formed on SOI (SOI is short for Silicon-On-Insulator, that is, silicon on an insulating substrate) to obtain Figure 4 the structure shown. The second insulating layer 610 can adopt a deposition process, and part of the second insulating layer 610 is selectively etched, and the remaining second insulating layer 610 serves as an insulating capping layer. In another embodiment, a sidewall transfer (SWT) process can be used, and the specific method will not be elaborated. After the etching of the second insulating layer 610 is completed, the semiconductor layer is continuously etched downward to form the fin body 710. In this embodiment, the fin body 710 is formed by etching the semiconductor layer twice using a photomask.

[0067] In one embodiment, forming the fin body 710 further includes an annealing step. The annealing is carried out in a mixed gas environment of hydrogen and nitrogen, and the annealing temperature is 800 - 1000 degrees Celsius.

[0068] In Figure 4 the shown embodiment, the fin body 710 serves as the active region of the FinFET and will be used to form the source, channel, and drain in subsequent steps. Specifically, the fin body 710 is in the shape of a cuboid, divided into two ends and a middle region. The two ends are used to form the source and drain in the subsequent steps, and the middle region serves as the channel region. The second insulating layer 610 covers the middle region, exposing the first end and the second end of the fin body 710.

[0069] S130 forms a first dielectric layer on the first side and a second dielectric layer on the second side.

[0070] Figure 5 is a schematic structural diagram of the device after step S130 is completed. In one embodiment, the materials of the first dielectric layer 811 and the second dielectric layer 812 can be oxides of silicon (such as silicon dioxide), nitrides of silicon (such as silicon nitride), or oxynitrides of silicon (such as silicon oxynitride).

[0071] In one embodiment, step S130 specifically includes:

[0072] 1. Form a base oxide layer through a situ stream-generated (ISSG) process or a rapid thermal annealing (RTO) process. The process temperature range is 700 - 900 °C, and the thickness of the formed base oxide layer is 0.1 nm - 3 nm.

[0073] 2. Perform decoupled plasma nitridation (DPN) on the wafer in a nitrogen environment.

[0074] 3. Perform a post-annealing process on the wafer to form the first dielectric layer 812 and the second dielectric layer 811 as the gate oxide layer.

[0075] S140 forms a ferroelectric layer on the side of the second dielectric layer opposite to the fin body.

[0076] In one embodiment, an atomic layer deposition (ALD) process is used to form a ferroelectric layer 813 surrounding the first dielectric layer 812 and the second dielectric layer 811. In one embodiment, the material of the ferroelectric layer 813 includes a main material and a dopant. The main material can be at least one of HfZrO2, HfO2 (hafnium oxide), ZrO2 (zirconium oxide), Hf 0.5 Zr 0.5 O2 (hafnium zirconium oxide); the dopant can be at least one of carbon C, silicon Si, magnesium Mg, aluminum Al, yttrium Y, nitrogen N, germanium Ge, tin Sn, strontium Sr, lead Pb, calcium Ca, barium Ba, titanium Ti, zirconium Zr, gadolinium Gd, lanthanum La. The dopant can help stabilize the ferroelectricity of the ferroelectric layer.

[0077] In one embodiment, step S140 further includes forming an electrode layer 815 on the side of the ferroelectric layer 813 opposite to the fin body 710.

[0078] In one embodiment, the material of the electrode layer 815 includes at least one of TiN, TaN, and AlTiN. For example, it can be a composite layer of AlTiN and TaN.

[0079] In Figure 6 In the illustrated embodiment, a ferroelectric layer 813 is first formed on both the first side and the second side, and then an electrode layer 815 surrounding the ferroelectric layer 813 is formed (the electrode layer 815 is formed on both the first side and the second side). Then, the electrode layer 815 and the ferroelectric layer 813 on the second side are removed by etching, as shown in Figure 7 shown. In one embodiment, the etching may employ a reactive ion etching (RIE) method at a small angle.

[0080] In one embodiment, before the step of etching away the electrode layer 815 and the ferroelectric layer 813 on the second side, there is further a step of performing ion implantation on the ferroelectric layer 813 and the electrode layer 815 on both the first side and the second side to eliminate interface defects. In one embodiment, the ion implantation may be a low-energy Al ion implantation; in other embodiments, the ion implantation may include at least one of Al, B, Mg, Ru, and Ga ions.

[0081] S150, form a first gate and a second gate.

[0082] The first gate 1031 is formed on a side of the first dielectric layer 812 opposite to the fin body 710, and the second gate 1030 is formed on a side of the ferroelectric layer 813 opposite to the fin body 710. In Figure 8 and Figure 9 In the illustrated embodiment, a polysilicon layer 910 is first deposited on the fin body 710 to cover the fin body 710; then the polysilicon layer 910 is planarized by chemical mechanical polishing (CMP), and the second insulating layer 610 serves as a polishing stop layer. After chemical mechanical polishing and planarization, the polysilicon layer 910 has an upper surface 1020. The second insulating layer 610 located on the fin body 710 isolates the polysilicon layer 910 into two parts, and then the polysilicon layer 910 is selectively etched to form the first gate 1031 and the second gate 1030. The process of etching the polysilicon layer 910 includes: depositing a hard mask layer on the polysilicon surface 1020 and patterning the hard mask layer, the hard mask layer being a dielectric layer, such as silicon dioxide or silicon nitride; then etching the polysilicon layer 910, and only the polysilicon located on the sides of the first dielectric layer 812 and the second dielectric layer 811 is retained as the first gate 1031 / second gate 1030, and finally the hard mask layer is removed. In one embodiment, the etching may employ a reactive ion etching (RIE) method.

[0083] S160, dope the fin body to form a source at the first end and a drain at the second end.

[0084] Figure 10is a top view of the structure of the ferroelectric field-effect transistor memory after step S150 in an embodiment, and its cross-section along AA' can be Figure 9 the structure shown, and its cross-section along BB' can be Figure 11 the structure shown. In one embodiment, before step S160, there is also a step of forming spacers on the outer sides of the first gate 1031 and the second gate 1031; further, sidewalls 1210 are also formed at the first and second ends of the fin body 710, and both ends of the insulating layer 610, as Figure 12 shown. In one embodiment, the sidewall 1210 is an ONO structure, that is, an oxide layer - nitride layer - oxide layer. In one embodiment, the method of forming the sidewall 1210 is: first, a first oxide layer is formed by high-temperature oxidation (HTO); then, gate nitridation is carried out to form a nitride layer; then, a second oxide layer is formed by high-temperature oxidation (HTO); finally, the sidewall 1210 is formed by reactive ion etching (RIE).

[0085] In one embodiment, step S160 is, after forming the sidewall 1210, performing ion implantation at both ends of the fin body 710 not covered by the second insulating layer 610 to form the source electrode 1310 and the drain electrode 1320, as Figure 13 shown. In one embodiment, the ferroelectric field-effect transistor memory is an N-channel FinFET, and the doped ions implanted into the source electrode 1310 and the drain electrode 1320 are N-type ions, such as arsenic ions, and the implantation dose of arsenic ions is 1×10 15 / cm 2 ~5×10 15 / cm 2 , the implantation ion energy is not less than 1.0 Kev, and the implantation angle can be from 1° to 30°. In another embodiment, the ferroelectric field-effect transistor memory is a P-channel FinFET, and the doped ions implanted into the source electrode 1310 and the drain electrode 1320 are P-type ions, such as boron ions, and the implantation dose of boron ions is 1×10 15 / cm 2 ~5×10 15 / cm 2 , the implantation ion energy is not less than 1.0 Kev, and the implantation angle can be from 1° to 30°. After ion implantation, spike annealing can also be carried out in the temperature range of 1000 - 1100 °C.

[0086] See Figure 14 , in Figure 14In the illustrated embodiment, after step S160, there are further steps of forming a source elevation portion 1410 on the source electrode 1310 and a drain elevation portion 1420 on the drain electrode 1320. This step can increase the effective length of the conductive channel between the source and the drain. In one embodiment, the materials of the source elevation portion 1410 and the drain elevation portion 1420 are SiGe; SiGe has a higher carrier mobility than silicon material. In other embodiments, other semiconductor materials can also be used as the source elevation portion 1410 and the drain elevation portion 1420, such as silicon material (epitaxial silicon layer).

[0087] In one embodiment, the method of forming the source elevation portion 1410 and the drain elevation portion 1420 is as follows: in an environment containing SiH2Cl2, HCl, and GeH4 gases, epitaxial growth is performed on the source electrode 1310 and the drain electrode 1320 to form a SiGe layer. The environmental temperature range for epitaxial growth is 700 - 800 °C, the thickness of the grown SiGe layer is 100 - 500 nm, and the proportion of Ge is 10 - 30%. Further, after growing the SiGe layer, there is a step of ion implantation into the SiGe layer, and after implantation, the source elevation portion 1410 and the drain elevation portion 1420 are obtained. In one embodiment, the ions for ion implantation are boron, and the concentration of implanted boron is 1×10 20 / cm -3 ~5×10 20 / cm -3 。

[0088] After forming the source elevation portion 1410 and the drain elevation portion 1420, relevant back-end processes are also carried out. Refer to Figure 15 。This includes: forming an interlayer dielectric layer 1500, an interconnect structure 1510, and an interconnect structure 1520. In the embodiment illustrated in Figure 15 , the interconnect structure 1510 and the interconnect structure 1520 are tungsten plugs, which are used to lead out the source elevation portion 1410 and the drain elevation portion 1420 and connect them to subsequent interconnect structures.

[0089] The present application correspondingly provides an operation method for a ferroelectric field-effect transistor memory, which is applied to the read operation / write operation of any of the above ferroelectric field-effect transistor memories. Figure 16 is a flowchart of the read operation in an embodiment. Refer to Figure 16 and Figure 17 , the read operation includes:

[0090] S210, applying a read voltage to the second gate, floating the first gate, and applying a first voltage between the source and the drain.

[0091] Figure 17 is Figure 1Power-on schematic diagram during a read operation in an embodiment of the shown structure. When performing a read operation on the ferroelectric field-effect transistor memory, a read voltage Vread is applied to the second gate 151, the first gate 150 is floating, and a first voltage is applied between the source 140 and the drain 160. The purpose of applying the first voltage is to generate a current between the source 140 and the drain 160. When the ferroelectric field-effect transistor memory is in the erased state (i.e., the stored information is "0"), the magnitude of this current will be different from that in the programmed state (i.e., the stored information is "1"). Subsequently, it is determined whether the ferroelectric field-effect transistor memory is in the erased state or the programmed state based on the magnitude of this current. Therefore, the value of the first voltage is not limited, as long as it can generate an appropriate such current. In one embodiment, the read voltage Vread can be 0. In Figure 18 In the shown embodiment, the drain 160 is grounded, and a source voltage Vd is applied to the source 140.

[0092] S220, detect the magnitude of the current between the source and the drain.

[0093] S230, determine whether the current is greater than a preset current value. If so, determine that the ferroelectric memory is in the erased state; otherwise, determine that the ferroelectric memory is in the programmed state.

[0094] The write operation can be an erase (i.e., write 0) operation or a program (i.e., write 1) operation. In this embodiment, a gate-to-gate (i.e., from the first gate 150 to the second gate 151 or from the second gate 151 to the first gate 150) write operation is adopted. Figure 18 is Figure 1 Power-on schematic diagram during an erase operation in an embodiment of the shown structure. When performing an erase operation on the ferroelectric field-effect transistor memory, a second voltage is applied to the second gate 151, a third voltage is applied to the first gate 150, and the source 140 and the drain 160 are floating. Among them, the difference between the second voltage and the third voltage is not less than the threshold voltage required for the erase operation, or not less than the coercive field voltage of the ferroelectric layer 133. In Figure 18 In the shown embodiment, the first gate 150 is grounded (V = G), and the second voltage is Vdd.

[0095] Figure 19 is Figure 1 Power-on schematic diagram during a program operation in an embodiment of the shown structure. When performing a program operation on the ferroelectric field-effect transistor memory, a fifth voltage is applied to the second gate 151, a fourth voltage is applied to the first gate 150, and the source 140 and the drain 160 are floating. Among them, the difference between the fourth voltage and the fifth voltage is not less than the threshold voltage required for the program operation, or not less than the coercive field voltage of the ferroelectric layer 133. In Figure 19 In the shown embodiment, the second gate 151 is grounded (V = G), and the fourth voltage is Vdd.

[0096] This application separates the read and write units of the ferroelectric field effect transistor: its read operation unit is a conventional MFMIS structure, while its write operation unit is an MFMISIM structure. The read operation voltage of the former is applied between the second gate, the source, and the drain, while the write operation voltage of the latter is applied between the first gate and the second gate, thereby reducing the electrons injected into the ferroelectric layer through the channel at the interface between the semiconductor and the ferroelectric layer.

[0097] This application correspondingly provides a read and write circuit for a ferroelectric field effect transistor memory, including the ferroelectric field effect transistor memory described in any of the foregoing embodiments, and further including a word line pair, a bit line pair, a first switch unit, and a second switch unit. The word line pair includes a first word line and a second word line, and the bit line pair includes a first bit line and a second bit line; the second gate of at least one of the ferroelectric field effect transistor memories is connected to the first word line, the first gate is connected to the second word line, the drain is connected to the first bit line, and the source is connected to the second bit line; the first switch unit is connected to the first bit line and is used to control the first bit line to be open when closed and to be conductive when open; the second switch unit is connected to the first bit line and the second bit line and is used to short-circuit the first bit line and the second bit line when open.

[0098] Referring to Figure 20 , in one embodiment, a plurality of ferroelectric field effect transistor memories are arranged in a matrix. Each ferroelectric field effect transistor memory (i.e., a FinFET unit) is connected to two word lines (i.e., WLka and WLkb, k = 1, 2, 3,..., m) and two bit lines (i.e., BLi and BLib, i = 1, 2, 3,..., n). Among them, the word line WLka is connected to the second gate, and the word line WLkb is connected to the first gate. The bit line BLi is connected to the drain, and the bit line BLib is connected to the source. At the same time, for each pair of bit lines BLi and BLib, top transistor M1 and bottom transistor M2 are used for access control. During the write operation, the top transistor M1 is turned off, and at the same time, the bottom transistor M2 is turned on, and the source and the drain are short-circuited and floating. During the read operation, the bottom transistor M2 is turned off, and at the same time, the top transistor M1 is turned on, and there is a voltage difference between the source and the drain.

[0099] It should be understood that although Figure 3 and Figure 16 the steps in the flowcharts of Figure 3 and Figure 16At least a part of the steps therein may include multiple steps or multiple stages, and these steps or stages are not necessarily executed and completed at the same moment, but may be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but may be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0100] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0101] The above-described embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A method for operating a ferroelectric field effect transistor memory, characterized in that, The ferroelectric field effect transistor memory device includes: A substrate; A first insulating layer disposed on the substrate; A fin body disposed on the first insulating layer, made of semiconductor and serving as a channel region, the fin body having opposite first and second sides and opposite first and second ends in the horizontal direction of the ferroelectric field effect transistor memory device; A first gate disposed on the first side, including a first gate electrode and a first dielectric layer disposed between the first gate electrode and the fin body; A second gate disposed on the second side, including a second gate electrode, a ferroelectric layer, an electrode layer, and a second dielectric layer, the ferroelectric layer and the second dielectric layer being disposed between the second gate electrode and the fin body, the ferroelectric layer being disposed between the second gate electrode and the second dielectric layer, and the electrode layer being disposed between the second gate electrode and the ferroelectric layer; A source electrode disposed at the first end and connected to the fin body; A drain electrode disposed at the second end and connected to the fin body; Wherein, the first gate, the fin body, the source electrode, and the drain electrode serve as a fin field effect transistor, and the second gate, the fin body, the source electrode, and the drain electrode serve as a fin ferroelectric field effect transistor; The operation includes a read operation or a write operation; The read operation includes: Applying a read voltage to the second gate electrode, floating the first gate electrode, and applying a first voltage between the source electrode and the drain electrode; Detecting the magnitude of the current between the source electrode and the drain electrode, if the current is greater than a preset current value, it is determined that the ferroelectric field effect transistor memory device is in an erased state; if the current is less than the preset current value, it is determined that the ferroelectric field effect transistor memory device is in a programmed state; The write operation includes an erase operation or a program operation, the erase operation includes applying a second voltage to the second gate electrode, applying a third voltage to the first gate electrode, floating the source electrode and the drain electrode, and the difference between the second voltage and the third voltage is not less than the threshold voltage of the erase operation or not less than the coercive field voltage of the ferroelectric layer; the program operation includes applying a fourth voltage to the first gate electrode, applying a fifth voltage to the second gate electrode, floating the source electrode and the drain electrode, and the difference between the fourth voltage and the fifth voltage is not less than the threshold voltage of the program operation or not less than the coercive field voltage of the ferroelectric layer.

2. The operating method of the ferroelectric field effect transistor memory according to claim 1, characterized in that, The ferroelectric field effect transistor memory device further includes a second insulating layer disposed on top of the fin body.

3. The operation method of the ferroelectric field effect transistor memory according to claim 1, characterized in that, The first gate electrode and the second gate electrode are polysilicon gate electrodes, and the material of the electrode layer includes at least one of TiN, TaN, and AlTiN.

4. The operation method of the ferroelectric field effect transistor memory according to claim 1, wherein The second gate electrode of the ferroelectric field effect transistor memory device is connected to a first word line, the first gate electrode is connected to a second word line, the drain electrode is connected to a first bit line, and the source electrode is connected to a second bit line; the first bit line is connected to a first switch unit, and the first switch unit is used to control the first bit line to be open when closed and to be conductive when open; the first bit line and the second bit line are connected to a second switch unit, and the second switch unit is used to short-circuit the first bit line and the second bit line when open; the first word line and the second word line form a word line pair, and the first bit line and the second bit line form a bit line pair.

5. The operating method of the ferroelectric field effect transistor memory according to claim 1, characterized in that, The source electrode and the drain electrode are disposed on the first insulating layer.

6. The operation method of the ferroelectric field effect transistor memory according to claim 1, characterized in that, Sidewalls are formed on the outer sides of the first gate electrode and the second gate electrode of the ferroelectric field effect transistor memory device.

7. The operating method of the ferroelectric field effect transistor memory according to claim 1, characterized in that, A source elevation portion is formed on the source, and a drain elevation portion is formed on the drain.

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