latch architecture and latch circuit

Abstract

This document discloses a latch architecture and latch circuit. The latch architecture includes an input circuit that receives input data; a combinational network that provides first intermediate data, a first intermediate control signal, and a second intermediate control signal based on the latched input data from the input circuit; one or more first latches that provide latched first intermediate data; a second latch that provides latched first intermediate control signal; a third latch that provides latched second intermediate control signal; at least one fourth latch that provides output data; and a decoder connected to the first latches that receives the latched first intermediate data and provides second intermediate data. At least one fourth latch receives an input signal modified based on the latched first intermediate control signal, the latched second intermediate control signal, and the second intermediate data. The first to third latches operate with an inverted clock signal, and at least one fourth latch operates with a non-inverted clock signal.

Description

Technical Field

[0001] This disclosure relates to a latch architecture. Background Technology

[0002] As is well known, low power consumption has become an important parameter to consider when designing integrated circuits, mainly due to the widespread use of portable and handheld applications. Similarly, the area footprint of integrated circuits is also extremely important.

[0003] Integrated circuits typically consist of flip-flops and latching circuits (e.g., for exchanging data) organized in a suitable architecture.

[0004] For example in Figure 1 The diagram illustrates a traditional architecture for outputting data from a microcontroller.

[0005] Architecture 100 includes an input unit 110, which is a delay flip-flop (DFF) and receives input data ROMDATA and a clock signal OUT_CLK, for example, from the microcontroller's ROM memory. Input unit 110 provides latched data ROMDATA_L to decoder logic 120, which in turn connects to output unit 130. Similarly, output unit 130 is a delay flip-flop (DFF) connected to the clock signal OUT_CLK and providing output data MC_OUT.

[0006] Because it uses flip-flop units and a common clock signal OUT_CLK, architecture 100 exhibits synchronous behavior. Unfortunately, this known architecture typically shows a non-negligible area footprint, especially when large amounts of data must be transmitted.

[0007] US Patent No. 10,429,443 describes a scan trigger architecture including an input unit and a trigger. The input unit is configured to select a signal from a data input signal and a scan input signal and provide the selected signal as an internal signal according to an operating mode. The trigger is configured to latch the internal signal according to a clock signal. US Patent No. 7,391,250 also discloses a data holding unit for preserving output data signals in a power-saving mode. This data holding unit includes input control circuitry in the form of master-slave triggers and delay triggers (DFFs), with the master-slave triggers further including a master latch unit and a slave latch unit. Summary of the Invention

[0008] Embodiments of the present invention relate to a latch architecture for outputting data from a microcontroller that is appropriately designed to reduce its footprint.

[0009] The proposed latch architecture aims to reduce footprint and increase the speed of data transfer from the microcontroller.

[0010] In one embodiment of the present invention, a latch architecture has an input terminal for receiving input data and an output terminal for providing output data. The latch architecture includes: an input circuit connected to the input terminal of the latch architecture, receiving input data from the input terminal and providing latched input data; a combination network connected to the input circuit, receiving the latched input data from the input circuit, and providing first intermediate data, a first intermediate control signal, and a second intermediate control signal; wherein the latch architecture further includes: one or more first latches connected to the combination network, receiving the first intermediate data and providing latched first intermediate data; a second latch connected to the combination network, receiving the first intermediate control signal and providing latched first intermediate control signal; a third latch connected to the combination network, receiving the second intermediate control signal and providing latched second intermediate control signal; and at least one fourth latch. At least one fourth latch is connected to the output of the latch architecture and provides output data; a decoder is connected to the first latch and receives latched first intermediate data; at least one first AND gate is connected to the decoder, receives second intermediate data from the decoder and a latched first intermediate control signal from the second latch, and provides set-enabled second intermediate data to the first input of the fourth latch; and at least one second AND gate is connected to the decoder, receives second intermediate data from the decoder and a latched second intermediate control signal from the third latch, and provides reset-enabled second intermediate data to the second input of the fourth latch, wherein the first AND gate and the second AND gate provide their respective input signals to the fourth latch; wherein one or more first latches, second latches, and third latches receive clock signals at an inverting clock input, and the fourth latch receives clock signals at a clock input.

[0011] In one embodiment of the present invention, a latching circuit includes: an input terminal and an output terminal; an input circuit connected to the input terminal and configured to receive input data from the input terminal and generate latched input data; a combination network connected to the input circuit and configured to receive the latched input data from the input circuit and use the latched input data to generate first intermediate data, a first intermediate control signal, and a second intermediate control signal; a first register connected to the combination network and configured to receive the first intermediate data, the first intermediate control signal, and the second intermediate control signal, and use a clock signal and an asynchronous low-level active reset signal to generate the latched first intermediate data, the latched first intermediate control signal, and the latched second intermediate control signal; and a decoder connected to the first register and configured to receive the latched first intermediate data and generate... The system comprises: a second intermediate data; one or more logic gates connected to the decoder and the first register, configured to receive the second intermediate data, a latched first intermediate control signal, and a latched second intermediate control signal, and to use a combination of the second intermediate data, the latched first intermediate control signal, and the latched second intermediate control signal to generate set-enabled second intermediate data and reset-enabled second intermediate data; and a second register connected to the logic gates, configured to receive the set-enabled second intermediate data and the reset-enabled second intermediate data, to use a combination of the set-enabled second intermediate data, the reset-enabled second intermediate data, a clock signal, and an asynchronous low-level active reset signal to generate output data, and to output the output data to an output terminal, wherein the first register includes a D-latch and the second register includes an SR latch.

[0012] According to another embodiment of the present invention, a first latch has an input terminal for receiving first intermediate data from a combination network and an output terminal for providing latched first intermediate data to a decoder; a second latch has an input terminal for receiving a first intermediate control signal from a combination network and an output terminal for providing latched first intermediate control signal to a first AND gate; and a third latch has an input terminal for receiving a second intermediate control signal from a combination network and an output terminal for providing latched second intermediate control signal to a second AND gate; the first, second, and third latches each include: a first logic gate, the first logic gate having a first input terminal connected to the input terminal of the respective latch and a second input terminal for receiving a clock signal through a first inverter; a second logic gate, the first... The second logic gate has a first input terminal that receives a clock signal through a first inverter and a second input terminal that is connected to the input terminal of a corresponding latch through a second inverter; a third logic gate, the third logic gate having a first input terminal connected to the output terminal of the first logic gate; and a fourth logic gate, the fourth logic gate having a first input terminal connected to the output terminal of the second logic gate; the third logic gate and the fourth logic gate are cross-connected, the third logic gate having an output terminal connected to the second input terminal of the fourth logic gate, the fourth logic gate having an output terminal connected to the second input terminal of the third logic gate, the fourth logic gate further including a third input terminal that receives an asynchronous low-level active reset signal, and an output terminal connected to the output terminal of a corresponding latch through a third inverter.

[0013] According to another embodiment, the fourth latch has a first input terminal receiving second intermediate data that is set-enabled from a first AND gate, a second input terminal receiving second intermediate data that is reset-enabled from a second AND gate, and an output terminal providing output data. The fourth latch further includes: a first logic gate having a first input terminal connected to the first input terminal of the fourth latch and a second input terminal receiving a clock signal; a second logic gate having a first input terminal receiving a clock signal and a second input terminal connected to the second input terminal of the fourth latch; a third logic gate having a first input terminal connected to the output terminal of the first logic gate; a fourth logic gate having a first input terminal connected to the output terminal of the second logic gate; and a fifth logic gate having a first input terminal connected to the output terminal of the third logic gate, a second input terminal receiving an asynchronous low-level active reset signal, and an output terminal connected to the output terminal of the fourth latch via an inverter.

[0014] The fourth logic gate has a second input terminal connected to the output terminal of the fifth logic gate and an output terminal connected to the second input terminal of the third logic gate.

[0015] Finally, according to another embodiment, the decoder receives latched first intermediate data from the first latch and provides second intermediate data to the first AND gate and the second AND gate by means of different levels of internal logic gates. Attached Figure Description

[0016] The features and advantages of this disclosure will become apparent from the following description of embodiments of the disclosure, given by way of indicative rather than limiting example with reference to the accompanying drawings, wherein,

[0017] Figure 1 The architecture for outputting data from a microcontroller is shown, based on existing technology solutions.

[0018] Figure 2 A latch architecture according to an embodiment of the present disclosure is shown.

[0019] Figures 3A to 3B and Figures 4A to 4B It shows Figure 2 The circuit structure of different latches in the latch architecture.

[0020] Figure 5 It shows Figure 2 The internal structure of the decoder based on the latch architecture.

[0021] Figure 6 It shows Figure 2 The timing of internal signals in the latch architecture.

[0022] Figures 7A to 7B It shows Figure 2 How the latch architecture operates at different stages according to the clock signal edge. Detailed Implementation

[0023] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Although the invention has been shown and described in conjunction with embodiments thereof, it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention. The terms and words used in the specification and claims should not be construed in their ordinary or dictionary sense. Based on the principle that the inventor can define appropriate concepts of terms in order to best describe his / her own invention, the terms should be interpreted as meanings and concepts consistent with the technical concept of the invention. Furthermore, detailed descriptions of constructions well-known in the art may be omitted to avoid unnecessarily obscuring the clarity of the invention.

[0024] In the accompanying drawings, corresponding features are identified by the same reference numerals.

[0025] Figure 2 A latch architecture 200 according to an embodiment of the present disclosure is shown.

[0026] The latch architecture 200 includes input circuitry 210, which is a delay flip-flop (DFF) and receives input data ROMDATA, for example, from the ROM memory of a microcontroller, at its input IN. It also receives a clock signal CK and an asynchronous active-low reset signal ARN. Input circuitry 210 provides latched data ROMDATA_L to a combinational network 220, which in turn provides first intermediate data NDATA to a first latch 230, a first intermediate control signal SET to a second latch 231, and a second intermediate control signal RES to a third latch 232. The latch architecture 200 may include one or more first latches 230 connected to the combinational network 220.

[0027] The first latch 230 is a level-sensitive latch that receives a clock signal CK, an asynchronous active-low reset signal ARN, and first intermediate data NDATA from the combinational network 220. The first latch 230 is connected to a first AND gate 250 and a second AND gate 251 via a decoder 240. Similarly, the second latch 231 is a level-sensitive latch that receives a clock signal CK, an asynchronous active-low reset signal ARN, and a first intermediate control signal SET from the combinational network 220. The second latch 231 has an output connected to the first AND gate 250. Likewise, the third latch 232 is a level-sensitive latch that receives a clock signal CK, an asynchronous active-low reset signal ARN, and a second intermediate control signal RES from the combinational network 220. The output of the third latch 232 is connected to the second AND gate 251.

[0028] Decoder 240 receives latched first intermediate data NDATA_L from first latch 230 and provides second intermediate data 2 to both first AND gate 250 and second AND gate 251. N DATA. The first AND gate 250 receives the second intermediate data 2 from the decoder 240. N The first AND gate 250 provides a set-enabled second intermediate data 2 to the fourth latch 260, along with the first intermediate control signal SET_L latched from the second latch 231. N DATA_S.

[0029] The second AND gate 251 receives the second intermediate data 2 from the decoder 240. NThe second AND gate 251 connects DATA and the second intermediate control signal RES_L latched from the third latch 232. The second AND gate 251 provides the reset-enabled second intermediate data 2 to the fourth latch 260. N DATA_R.

[0030] The fourth latch 260 is a gated SR latch (SRLAT), which in turn receives the clock signal CK, the asynchronous low-level active reset signal ARN, and the second intermediate data 2 set and enabled from the first AND gate 250. N DATA_S and the second intermediate data 2 from the reset enable of the second AND gate 251 N DATA_R. The fourth latch 260 provides output data MC_OUT at the output terminal OUT of latch architecture 200.

[0031] It should be noted that the latch architecture 200 includes a gated SR latch (SRLAT) as the fourth latch 260 instead of a D-latch (DLAT) to allow memory to be maintained for previously latched data when both inputs of the latch are low and the clock signal CK is high, without adding output feedback and multiplexing logic to the inputs of the latch.

[0032] Appropriately, the first latch 230, the second latch 231, and the third latch 232 are synchronized with low pulses of clock signals CK received at the inverted clock terminals of the first latch 230, the second latch 231, and the third latch 232, respectively, while the fourth latch 260 is synchronized with high pulses of clock signals CK provided to the non-inverted clock terminal of the fourth latch 260.

[0033] Essentially, the latch architecture 200 includes output circuits appropriately divided into a series of D-latches (DLAT) and SR latches (SRLAT), with the size of the circuits from the input data ROMDATA to the output data MC_OUT decreasing sequentially.

[0034] Specifically, since decoder 240 is n to 2 n The decoder, so the first intermediate data NDATA of the n-bit signal is transmitted as 2 n The second intermediate data 2 of the bit signal N DATA.

[0035] Appropriately, a plurality of first latches 230 are included in the first register MC_OUTREGDRVR of the microcontroller, and are connected to a plurality of fourth latches 260 included in the second register MC_OUTREGS of the microcontroller by means of a plurality of first AND gates 250 and second AND gates 251, both of which are combined with a plurality of combinatorial blocks of the decoder 240.

[0036] According to embodiments of this disclosure, such as Figure 3A As shown, the first latch 230, the second latch 231, and the third latch 232 each include a first logic gate PL31 having a first input terminal connected to input terminal IN3 and a second input terminal receiving a clock signal CK through a first inverter INV31, and a second logic gate PL32 having a first input terminal receiving the clock signal CK through the first inverter INV31 and an input terminal IN3 connected to the corresponding latch through a second inverter INV32. The first logic gate PL31 and the second logic gate PL32 each have an output terminal connected to the first input terminal of a cross-connected third logic gate PL33 and a fourth logic gate PL34. Specifically, the third logic gate PL33 has an output terminal connected to the second input terminal of the fourth logic gate PL34, and the fourth logic gate PL34 subsequently has an output terminal connected to the second input terminal of the third logic gate PL33.

[0037] The fourth logic gate PL34 also has a third input that receives an asynchronous low-level active reset signal ARN, and its output is connected to the output OUT3 that provides the output data Q via a third inverter INV33.

[0038] Within latch architecture 200, the input IN3 of the first latch 230 receives first intermediate data NDATA from the combination network 220, and the output OUT3 provides the latched first intermediate data NDATA_L to the decoder 240; the input of the second latch 231 receives the first intermediate control signal SET from the combination network 220, and the output OUT3 provides the latched first intermediate control signal SET_L to the first AND gate 250; and the input of the third latch 232 receives the second intermediate control signal RES from the combination network 220, and its output OUT3 provides the latched second intermediate control signal RES_L to the second AND gate 251.

[0039] All logic gates included in the first latch 230, the second latch 231, and the third latch 232 are NAND gates.

[0040] The first latch 230, the second latch 231, and the third latch 232 are all based on... Figure 3B The implementation shown uses N-type MOS transistors and P-type MOS transistors.

[0041] According to this embodiment, the first latch 230, the second latch 231, and the third latch 232 each include a first PMOS transistor P31 and a second PMOS transistor P32, which are connected in series between the reference voltage VDD and the first internal circuit node X31. The first PMOS transistor P31 has a control terminal or gate terminal connected to the input terminal IN3 for receiving input data D, and the second PMOS transistor P32 has a control terminal or gate terminal for receiving the clock signal CK.

[0042] As previously described, within the latch architecture 200, the input of the first latch 230 receives first intermediate data NDATA from the combination network 220, the input of the second latch 231 receives a first intermediate control signal SET from the combination network 220, and the input of the third latch 232 receives a second intermediate control signal RES from the combination network 220.

[0043] The first latch 230, the second latch 231, and the third latch 232 each further include a first NMOS transistor N31, a second NMOS transistor N32, and a third NMOS transistor N33, which are connected in series between the first internal circuit node X31 and ground GND. The first NMOS transistor N31 has a control terminal or gate terminal that receives an inverted clock signal CKN, the second NMOS transistor N32 has a control terminal or gate terminal that receives an asynchronous low-level active reset signal ARN, and the third NMOS transistor N33 has a control terminal or gate terminal connected to the input terminal IN3.

[0044] In addition, the first latch 230, the second latch 231 and the third latch 232 each include a third PMOS transistor P33 that is inserted between the reference voltage VDD and the first internal circuit node X31 and has a control terminal or gate terminal that receives an asynchronous low-level active reset signal ARN.

[0045] The first latch 230, the second latch 231, and the third latch 232 each also include:

[0046] The fourth PMOS transistor P34 and the fourth NMOS transistor N34 are connected in series between the reference voltage VDD and ground GND, and have their respective control terminals or gate terminals connected to the first internal circuit node X31 and interconnected with each other at the second internal circuit node X32.

[0047] The fifth PMOS transistor P35 and the fifth NMOS transistor N35 are connected in series between the reference voltage VDD and ground GND, and each has a control terminal or gate terminal connected to the second internal circuit node X32 and interconnected with each other at the third internal circuit node X33; and

[0048] The sixth PMOS transistor P36 and the sixth NMOS transistor N36 are connected in series between the reference voltage VDD and ground GND, and have their respective control terminals or gate terminals connected to the third internal circuit node X33 and interconnected with each other at the output terminal OUT3 that provides output data Q.

[0049] Within the latch architecture 200, the output of the first latch 230 provides the first intermediate data NDATA_L latched to the decoder 240; the output of the second latch 231 provides the first intermediate control signal SET_L latched to the first AND gate 250; and the output of the third latch 232 provides the second intermediate control signal RES_L latched to the second AND gate 251.

[0050] Furthermore, the first latch 230, the second latch 231, and the third latch 232 each include a seventh PMOS transistor P37 and an eighth PMOS transistor P38, which are connected in series between the reference voltage VDD and the first internal circuit node X31. The seventh PMOS transistor P37 has a control terminal or gate terminal connected to the second internal circuit node X32, and the eighth PMOS transistor P38 has a control terminal or gate terminal that receives the inverted clock signal CKN.

[0051] Finally, the first latch 230, the second latch 231, and the third latch 232 each include a seventh NMOS transistor N37, an eighth NMOS transistor N38, and a ninth NMOS transistor N39, which are connected in series between the first internal circuit node X31 and ground GND. The seventh NMOS transistor N37 has a control terminal or gate terminal that receives the clock signal CK, the eighth NMOS transistor N38 has a control terminal or gate terminal that receives the asynchronous low-level active reset signal ARN, and the ninth NMOS transistor N39 has a control terminal or gate terminal connected to the second internal circuit node X32.

[0052] According to embodiments of this disclosure, such as Figure 4AAs shown, the fourth latch 260 includes a first logic gate PL41 having a first input terminal IN41 connected to the fourth latch 260 and a second input terminal for receiving a clock signal CK, and a second logic gate PL42 having a first input terminal for receiving the clock signal CK and a second input terminal IN42 connected to the fourth latch 260. The first logic gate PL41 and the second logic gate PL42 each have corresponding output terminals connected to the first input terminals of the third logic gate PL43 and the fourth logic gate PL44.

[0053] The third logic gate PL43 has an output terminal connected to the first input terminal of the fifth logic gate PL45. The fifth logic gate PL45 has a second input terminal that receives the asynchronous low-level active reset signal ARN and an output terminal connected to the output terminal OUT4 of the fourth latch 260 through the inverter INV4.

[0054] The fourth logic gate PL44 has a second input terminal connected to the output terminal of the fifth logic gate PL45, and its output terminal is connected to the second input terminal of the third logic gate PL43.

[0055] The first logic gate PL41 and the second logic gate PL42 are AND gates, the third logic gate PL43 is an OR gate, the fourth logic gate PL44 is a NOR gate, and the fifth logic gate PL45 is a NAND gate.

[0056] Within latch architecture 200, the first input IN41 of the fourth latch 260 receives the second intermediate data 2, which is set and enabled, from the first logic gate 250. N DATA_S, the second input IN42 of the fourth latch 260 receives the second intermediate data 2, which is reset and enabled, from the second logic gate 251. N DATA_R, and the output terminal OUT4 provides output data MC_OUT.

[0057] The fourth latch 260 is based on Figure 4B The N-type MOS transistor and P-type MOS transistor shown in the embodiments of this disclosure are used to implement this.

[0058] According to this embodiment, the fourth latch 260 includes a first PMOS transistor P41 and a second PMOS transistor P42 connected in series between a reference voltage VDD and a first internal circuit node X41, and a third PMOS transistor P43 connected in parallel with the second PMOS transistor P42. The fourth latch 260 also includes a first NMOS transistor N41 connected between the first internal circuit node X41 and ground GND, and a second NMOS transistor N42 and a third NMOS transistor N43 connected in series between the first internal circuit node X41 and ground GND.

[0059] The first PMOS transistor P41 and the first NMOS transistor N41 have their respective control terminals or gate terminals connected to the second internal node X42, the second PMOS transistor P42 and the second NMOS transistor N42 have their respective control terminals or gate terminals for receiving clock signals CK, and the third PMOS transistor P43 and the third NMOS transistor N43 have their respective control terminals or gate terminals for receiving input signals R at the second input terminal IN42.

[0060] The fourth latch 260 also includes a fourth PMOS transistor P44 and a fifth PMOS transistor P45 connected in series between the reference voltage VDD and the second internal circuit node X42, and a sixth PMOS transistor P46 connected in parallel with the fifth PMOS transistor P45. The fourth latch 260 also includes a fourth NMOS transistor N44 connected between the second internal circuit node X42 and the third internal circuit node X43, and a fifth NMOS transistor N45 and a sixth NMOS transistor N46 connected in series between the second internal circuit node X42 and the third internal circuit node X43.

[0061] The fourth PMOS transistor P44 and the fourth NMOS transistor N44 have their respective control terminals or gate terminals connected to the first internal node X41, the fifth PMOS transistor P45 and the fifth NMOS transistor N45 have their respective control terminals or gate terminals for receiving the clock signal CK, and the sixth PMOS transistor P46 and the sixth NMOS transistor N46 have their respective control terminals or gate terminals connected to the first input terminal IN41 of the fourth latch 260.

[0062] Within latch architecture 200, the first input IN41 of the fourth latch 260 receives the second intermediate data 2, which is set and enabled. N DATA_S, and the second input IN42 of the fourth latch 260 receives the second intermediate data 2 for reset enable. N DATA_R.

[0063] In addition, the fourth latch 260 includes a seventh PMOS transistor P47 inserted between the reference voltage VDD and the second internal circuit node X42 and having a control terminal or gate terminal that receives an asynchronous low-level active reset signal ARN, and a seventh NMOS transistor N47 inserted between the third internal circuit node X43 and ground GND and having a control terminal or gate terminal that receives an asynchronous low-level active reset signal ARN.

[0064] Finally, the fourth latch 260 includes an eighth PMOS transistor P48 and an eighth NMOS transistor N48 connected in series between a reference voltage VDD and ground GND. The eighth PMOS transistor P48 and the eighth NMOS transistor N48 have their respective control terminals or gate terminals connected to the second internal circuit node X42 and are interconnected at the output terminal OUT4 of the fourth latch 260.

[0065] Within latch architecture 200, the output terminal OUT4 of the fourth latch 260 provides output data MC_OUT.

[0066] According to embodiments of this disclosure, such as Figure 5 As shown, the decoder 240 of the latch architecture 200 includes logic gates at different levels.

[0067] More specifically, the first intermediate data NDATA is received by a first decoding level DEC_L1 comprising multiple logic blocks BL1-BLn, as shown in the logic block BLn of the first decoding level DEC_L1, each of the multiple logic blocks BL1-BLn comprising a row of NOR logic gates.

[0068] The first decoding level DEC_L1 is connected to the second decoding level DEC_L2, which in turn includes multiple NAND gates capable of providing pre-decoded values ​​to the third decoding level DEC_L3. The third decoding level DEC_L3 then includes multiple NOR gates (i.e., 256 NOR gates) and provides the second intermediate data 2. N DATA.

[0069] Figure 6 The pulse relative to the clock signal CK is shown. Figure 2 The timing of different data signals propagating within the latch architecture 200.

[0070] Specifically, Figure 6 The diagram illustrates how input data ROMDATA is transmitted via input circuit 210 as latched input data ROMDATA_L to combinational network 220 at the first rising edge of clock signal CK, and output as first intermediate data NDATA for first latch 230, first intermediate control signal SET for second latch 231, and second intermediate control signal RES for third latch 232 after a first delay time tp (CL1) due to the operation of combinational network 220.

[0071] The first latch 230 then provides the latched first intermediate data NDATA_L to the decoder 240 on the first falling edge of the clock signal CK. Similarly, on the first falling edge of the clock signal CK, the second latch 231 provides the latched first intermediate control signal SET_L to the first AND gate 250. Likewise, on the first falling edge of the clock signal CK, the third latch 232 provides the latched second intermediate control signal RES_L to the second AND gate 251.

[0072] After the second delay time tp (decoder), decoder 240 provides the second intermediate data 2 to the first AND gate 250 and the second AND gate 251. N DATA.

[0073] After the third delay time tp(AND), the first AND gate 250 provides the second intermediate data 2, which enables the set function, to the first input IN41 of the fourth latch 260. N DATA_S, and the second AND gate 251 provides the second intermediate data 2 for reset enable to the second input IN42 of the fourth latch 260. N DATA_R. The fourth latch 260 then outputs the data MC_OUT on the second rising edge of the clock signal CK.

[0074] Appropriately, when the clock signal CK is low after the first falling edge, the first latch 230, the second latch 231, and the third latch 232 are transparent. On the other hand, when the clock signal CK is high after the second rising edge, the fourth latch 260 is transparent.

[0075] The latch architecture 200 operates based on the pulse of the clock signal CK. Figures 7A to 7B As shown.

[0076] Specifically, refer to Figure 2 , Figure 7A The data is transmitted from input circuit 210 to combinational network 220 at the first rising edge of clock signal CK, indicated as the launching edge. Input circuit 210 is an edge-triggered object. In principle, combinational network 220 should produce a valid output on each of its outputs NDATA, SET, and RES within the first falling edge of clock signal CK, indicated as the DLAT opening edge. The period between the launching edge and the DLAT opening edge of clock signal CK is the set-check period for the first latch 230, the second latch 231, and the third latch 232.

[0077] The rising edge following the clock signal CK is indicated as the DLAT closing edge, and the hold is evaluated against the closing edge that serves as the end of the latch.

[0078] In addition, such as Figure 7B As shown, from the DLAT open edge until the next rising edge indicated as the DLAT close edge, the latched first intermediate data NDATA_L is transmitted to the decoder 240, the latched first intermediate control signal SET_L is transmitted to the first AND gate 250, and the latched second intermediate control signal RES_L is transmitted to the second AND gate 251.

[0079] Decoder 240 provides second intermediate data 2 to first AND gate 250 and second AND gate 251 during the time period between the DLAT open edge and the DLAT close edge. N DATA.

[0080] Subsequently, on the rising edge of CK that is indicated as the SRLAT open edge (which coincides with the DLAT close edge), the first AND gate 250 provides the second intermediate data 2 for setting enable to the first input IN41 of the fourth latch 260. N DATA_S, and the second AND gate 251 provides the second intermediate data 2 for reset enable to the second input IN42 of the fourth latch 260. N DATA_R.

[0081] Finally, on another falling edge of the clock signal CK, which is indicated as the SRLAT off edge, the fourth latch 260, as a gated SR latch, provides output data MC_OUT to the output terminal OUT of the latch architecture 200.

[0082] It can be verified that, using the latch architecture 200 according to an embodiment of this disclosure, the second register MC_OUTREGS shows an area saving of between 15.9% and 17.9%. Similarly, the register including the output data MC_OUT shows an area saving of between 10.0% and 13.3%. Conversely, the first register MC_OUTREGDRVR shows an increase in area footprint of between 15.1% and 16.5%. In any case, the total area saving for the microcontroller averages 4.3%.

[0083] Essentially, the latch architecture using D-latches (DLATs) and gated SR latches (SRLATs) in the output data circuitry according to embodiments of this disclosure exhibits a reduction in area footprint. Using SRLATs (which allow memory to retain previously received data even when the clock signal CK is high and both the first and second inputs are low) also helps reduce the area footprint of DLAT-only architectures where multiplexing logic needs to feed the output back to the inputs of the same latch.

[0084] Furthermore, the latch architecture exhibits synchronous behavior because the latches included therein are synchronized with the falling and rising phases of the same clock signal, respectively.

[0085] As can be understood from the foregoing, although specific embodiments of the invention have been described herein for illustrative purposes, various modifications may be made without departing from the spirit and scope of the invention. Therefore, the invention is not limited except for the appended claims.

[0086] Cross-reference to related applications

[0087] This application claims priority to Italian Patent Application No. 102020000029771, filed with the Italian Intellectual Property Office on December 3, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A latch architecture having an input terminal to receive input data and an output terminal to provide output data, the latch architecture comprising: an input circuit connected to the input terminal of the latch architecture to receive the input data therefrom and to provide latched input data; a combinational network connected to the input circuit to receive the latched input data therefrom and to provide first intermediate data, a first intermediate control signal and a second intermediate control signal; wherein the latch architecture further comprises: one or more first latches connected to the combinational network to receive the first intermediate data and to provide latched first intermediate data; a second latch connected to the combinational network to receive the first intermediate control signal and to provide latched first intermediate control signal; a third latch connected to the combinational network to receive the second intermediate control signal and to provide latched second intermediate control signal; at least one fourth latch connected to the output terminal of the latch architecture and to provide the output data; a decoder connected to the first latch to receive the latched first intermediate data; at least one first AND gate connected to the decoder to receive second intermediate data from the decoder and the latched first intermediate control signal from the second latch and to provide set-enabled second intermediate data to a first input terminal of the fourth latch; and at least one second AND gate connected to the decoder to receive second intermediate data from the decoder and the latched second intermediate control signal from the third latch and to provide reset-enabled second intermediate data to a second input terminal of the fourth latch, wherein the first AND gate and the second AND gate provide respective input signals to the fourth latch, wherein the one or more first latches, the second latch and the third latch receive a clock signal at an inverted clock terminal and the fourth latch receives the clock signal at a clock terminal.

2. The latch architecture of claim 1, wherein, The decoder is n to 2 n The decoder, and the latched first intermediate data as an n-bit signal is transferred as a 2 n bit signal, where n is greater than or equal to 1.

3. The latch architecture of claim 1, wherein, The one or more first latches, the second latch and the third latch are level sensitive latches and further receive an asynchronous active-low reset signal.

4. The latch architecture of claim 3, wherein, The at least one fourth latch is a gated SR latch and further receives the asynchronous active-low reset signal.

5. The latch architecture of claim 1, wherein, The input circuit is a delay flip-flop and further receives an asynchronous active-low reset signal.

6. The latch architecture of claim 1, wherein, The first latch, the second latch and the third latch are included in a first register of a microcontroller and are connected to the at least one fourth latch included in a second register of the microcontroller by means of two logic AND gates and a plurality of combinational blocks of the decoder.

7. The latch architecture of claim 3, wherein, each of the one or more first latches has an input that receives the first intermediate data from the combination network and an output that provides the latched first intermediate data to the decoder, wherein the second latch has an input that receives the first intermediate control signal from the combination network and an output that provides the latched first intermediate control signal to the first AND gate, wherein the third latch has an input that receives the second intermediate control signal from the combination network and an output that provides the latched second intermediate control signal to the second AND gate, wherein each of the one or more first latches, the second latch, and the third latch comprises: a first logic gate having a first input connected to an input of a respective latch and a second input that receives a clock signal through a first inverter; a second logic gate having a first input that receives the clock signal through the first inverter and a second input connected to the input of the respective latch through a second inverter; a third logic gate having a first input connected to an output of the first logic gate; and a fourth logic gate having a first input connected to an output of the second logic gate, wherein the third logic gate and the fourth logic gate are cross-connected, the third logic gate has an output connected to a second input of the fourth logic gate, and the fourth logic gate has an output connected to a second input of the third logic gate, and wherein the fourth logic gate further comprises a third input that receives the asynchronous active-low reset signal and the output connected to the output of the first latch through a third inverter.

8. The latch architecture of claim 7, wherein, The first, second, third, and fourth logic gates of each latch are NAND gates.

9. The latch architecture of claim 3, wherein, each of the one or more first latches has an input that receives the first intermediate data from the combination network and an output that provides the latched first intermediate data to the decoder, wherein the second latch has an input that receives the first intermediate control signal from the combination network and an output that provides the latched first intermediate control signal to the first AND gate, wherein the third latch has an input that receives the second intermediate control signal from the combination network and an output that provides the latched second intermediate control signal to the second AND gate, and wherein each of the one or more first latches, the second latch, and the third latch comprises: a first PMOS transistor and a second PMOS transistor interposed in series with each other between a reference voltage and a first internal circuit node, the first PMOS transistor having a control terminal connected to an input of a respective latch and the second PMOS transistor having a control terminal that receives the clock signal; a first PMOS transistor and a second PMOS transistor interposed in series with each other between a reference voltage and a first internal circuit node, the first PMOS transistor having a control terminal connected to an input of a respective latch and the second PMOS transistor having a control terminal that receives the clock signal; a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, which are inserted in series with each other between the first internal circuit node and ground, the first NMOS transistor having a control terminal that receives an inverted clock signal, the second NMOS transistor having a control terminal that receives the asynchronous active-low reset signal, and the third NMOS transistor having a control terminal that is connected to the input terminal of a corresponding latch; and a third PMOS transistor, which is inserted between the reference voltage and the first internal circuit node and has a control terminal that receives the asynchronous active-low reset signal.

10. The latch architecture of claim 9, wherein, Each of the one or more first latches, the second latch, and the third latch further includes: a fourth PMOS transistor and a fourth NMOS transistor, which are inserted in series with each other between the reference voltage and ground and have respective control terminals that are connected to the first internal circuit node and are interconnected to each other at a second internal circuit node; a fifth PMOS transistor and a fifth NMOS transistor, which are inserted in series with each other between the reference voltage and ground and have respective control terminals that are connected to the second internal circuit node and are interconnected to each other at a third internal circuit node; and a sixth PMOS transistor and a sixth NMOS transistor, which are inserted in series with each other between the reference voltage and ground and have respective control terminals that are connected to the third internal circuit node and are interconnected to each other at an output terminal of a corresponding latch.

11. The latch architecture of claim 10, wherein, Each of the one or more first latches, the second latch, and the third latch further includes: a seventh PMOS transistor and an eighth PMOS transistor, which are inserted in series with each other between the reference voltage and the first internal circuit node, the seventh PMOS transistor having a control terminal that is connected to the second internal circuit node, and the eighth PMOS transistor having a control terminal that receives the inverted clock signal; and a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor, which are inserted in series with each other between the first internal circuit node and ground, the seventh NMOS transistor having a control terminal that receives the clock signal, the eighth NMOS transistor having a control terminal that receives the asynchronous active-low reset signal, and the ninth NMOS transistor having a control terminal that is connected to the second internal circuit node.

12. The latch architecture of claim 4, wherein, The fourth latch has a first input receiving second intermediate data of the set enable from the first AND gate, a second input receiving second intermediate data of the reset enable from the second AND gate, and an output providing the output data, wherein the fourth latch further comprises: a first logic gate having a first input connected to the first input of the fourth latch and a second input receiving a clock signal; a second logic gate having a first input receiving the clock signal and a second input connected to the second input of the fourth latch; a third logic gate having a first input connected to an output of the first logic gate; a fourth logic gate having a first input connected to an output of the second logic gate; and a fifth logic gate having a first input connected to an output of the third logic gate, a second input receiving the asynchronous active low reset signal, and an output connected to the output of the fourth latch through an inverter, wherein the fourth logic gate comprises a second input connected to the output of the fifth logic gate and an output connected to a second input of the third logic gate.

13. The latch architecture of claim 12, wherein, The first and second logic gates of the fourth latch are AND gates, the third logic gate of the fourth latch is an OR gate, the fourth logic gate of the fourth latch is an NOR gate, and the fifth logic gate of the fourth latch is an NAND gate.

14. The latch architecture of claim 4, wherein, The fourth latch has a first input receiving second intermediate data of the set enable from the first AND gate, a second input receiving second intermediate data of the reset enable from the second AND gate, and an output providing the output data, wherein the fourth latch further comprises: a first PMOS transistor and a second PMOS transistor interposed in series with each other between a reference voltage and a first internal circuit node; a third PMOS transistor interposed in parallel with the second PMOS transistor; a first NMOS transistor interposed between the first internal circuit node and ground; and a second NMOS transistor and a third NMOS transistor interposed in series with each other between the first internal circuit node and ground, wherein the first PMOS transistor and the first NMOS transistor comprise respective control terminals connected to a second internal circuit node, the second PMOS transistor and the second NMOS transistor have respective control terminals receiving the clock signal, and the third PMOS transistor and the third NMOS transistor have respective control terminals connected to the second input of the fourth latch.

15. The latch architecture of claim 14, wherein, The fourth latch further comprises: a fourth PMOS transistor and a fifth PMOS transistor interposed in series with each other between a reference voltage and the second internal circuit node; a sixth PMOS transistor interposed in parallel with the fifth PMOS transistor; a fourth NMOS transistor interposed between the second internal circuit node and a third internal circuit node; and a fifth NMOS transistor and a sixth NMOS transistor interposed in series with each other between the second internal circuit node and the third internal circuit node, wherein the fourth PMOS transistor and the fourth NMOS transistor include respective control terminals connected to the first internal circuit node, the fifth PMOS transistor and the fifth NMOS transistor have respective control terminals that receive the clock signal, and the sixth PMOS transistor and the sixth NMOS transistor have respective control terminals connected to the first input terminal of the fourth latch.

16. The latch architecture of claim 15, wherein, The fourth latch further includes: a seventh PMOS transistor interposed between the reference voltage and the second internal circuit node and having a control terminal that receives the asynchronous low-active reset signal; and a seventh NMOS transistor interposed between the third internal circuit node and ground and having a control terminal that receives the asynchronous low-active reset signal.

17. The latch architecture of claim 16, wherein, The fourth latch further includes: an eighth PMOS transistor and an eighth NMOS transistor interposed in series with each other between the reference voltage and ground and having respective control terminals connected to the second internal circuit node and interconnected at the output terminal of the fourth latch.

18. The latch architecture of claim 2, wherein, The decoder receives the latched first intermediate data from the first latch and provides second intermediate data to the first and second AND gates by means of different stages of logic gates.

19. The latch architecture of claim 18, wherein, The decoder includes: a first decoding stage including a plurality of logic blocks receiving the latched first intermediate data, each logic block including a row of NAND logic gates; a second decoding stage connected to the first decoding stage and including a plurality of NAND gates capable of providing pre-decoded values; and a third decoding stage connected to the second decoding stage and including a plurality of NOR gates receiving the pre-decoded values and providing the second intermediate data.

20. A latch circuit, the latch circuit comprising: an input terminal and an output terminal; an input circuit coupled to the input terminal and generating latched input data from input data received at the input terminal; a combinational network coupled to the input circuit and receiving the latched input data from the input circuit and generating first intermediate data, first intermediate control signals, and second intermediate control signals using the latched input data; a first register coupled to the combinational network and receiving the first intermediate data, the first intermediate control signals, and the second intermediate control signals and generating latched first intermediate data, latched first intermediate control signals, and latched second intermediate control signals using a clock signal and an asynchronous active-low reset signal; a decoder coupled to the first register and receiving the latched first intermediate data and generating second intermediate data; one or more logic gates coupled to the decoder and the first register and receiving the second intermediate data, the latched first intermediate control signals, and the latched second intermediate control signals and generating set-enabled second intermediate data and reset-enabled second intermediate data using a combination of the second intermediate data, the latched first intermediate control signals, and the latched second intermediate control signals; and a second register coupled to the logic gates and receiving the set-enabled second intermediate data and the reset-enabled second intermediate data, generating output data using a combination of the set-enabled second intermediate data, the reset-enabled second intermediate data, the clock signal, and the asynchronous active-low reset signal, and outputting the output data to the output, wherein the first register comprises a D-latch and the second register comprises an SR latch. ​

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