trench transistor

Abstract

A trench transistor (100) is provided, comprising: a semiconductor region (2), a trench structure (1) formed in the semiconductor region (2), a gate insulating layer (3, 4) in the trench structure (1), a conductive gate layer (5) formed in the gate insulating layer (3, 4), and a gate contact (6) conductively connected to the gate layer (5) in an edge region (7a) of the trench transistor (100), wherein the thickness (8) of the gate insulating layer (3, 4) is greater in the edge region (7a) of the trench transistor (100) than in the active region (7b) of the trench transistor (100).

Description

Technical Field

[0001] This invention relates to a trench transistor. Background Technology

[0002] A conventional trench transistor, with multiple trenches backfilled with gate oxide and gate polysilicon, has radii of curvature on the upper and lower sides of the trenches, respectively. During operation, the electric field strength decreasing on the gate oxide is greatest in the curved regions and decreases with increasing radius of curvature. The gate polysilicon is led out from the trench and is conductively connected to the gate bond at the edges of the zellefeldes of the trench transistor. A problem with conventional trench transistors occurs at the trench ends, where the radius of curvature decreases compared to areas not located at the trench ends, as the trench ends are implemented as hypertoroids. Therefore, the greatest electric field strength in the gate oxide is located at the trench ends, limiting the area where the gate voltage is available. Summary of the Invention

[0003] The objective of this invention is to provide a trench transistor that eliminates or at least reduces the problems described above.

[0004] This task is solved by a trench transistor according to either the main claim or any of the dependent claims. Advantageous extensions of the invention are described in the dependent claims.

[0005] Here are some examples of trench transistors in which a conductive gate layer, such as highly doped polysilicon (also called gate polysilicon), is conductively connected to a gate contact. The conductive gate layer, as a gate electrode, is located in the trench of the trench transistor and is electrically insulated from the semiconductor region (e.g., made of silicon carbide) through a gate insulating layer (e.g., gate oxide).

[0006] The trench transistor having the features of the main claim has the advantage of providing an optimized trench structure in the edge region of the trench outside the active cell region, thereby increasing the total oxide thickness at the trench ends. If the thickness of the gate insulating layer in the edge region of the trench transistor is increased (that is, if the cross-sectional area of ​​the gate insulating layer increases along the longitudinal direction of the trench extending in the longitudinal direction from the active region of the trench transistor toward the edge region outside the active region), then the advantage of reducing the electric field strength in the gate insulating layer is achieved. This avoids component damage due to excessively high electric field strength in the gate oxide.

[0007] According to another aspect, the conductive gate layer in the edge region of the trench transistor can be configured to extend from the trench structure over the semiconductor region; that is, the conductive gate layer in the trench extends beyond the trench surface along the longitudinal direction of the trench and / or laterally beyond the longitudinal direction. This configuration of the trench transistor has the advantage of improving the conductive contact between the conductive gate layer and the gate contact.

[0008] According to another aspect, a trench transistor can be configured to have a second trench structure and a second gate insulating layer in the second trench structure, wherein a conductive gate layer is further formed on the second gate insulating layer in the second trench structure, and the thickness of the second gate insulating layer is greater in the edge region of the trench transistor than in the active region of the trench transistor. That is, the trench transistor has a second trench structure constructed as a first trench structure, wherein the conductive gate layer forms a common gate electrode for the first and second trench structures. Specifically, if two trenches terminate at the edge region of a cell region of the trench transistor, the potential on the gate contact and the conductive gate layer (e.g., a polysilicon layer) connected thereto is supplied as the gate potential to the respective trench. This produces the advantage that the total thickness and radius of curvature of the gate insulating layer are increased at the ends of each trench structure, thereby preventing limitation on the range of available gate voltage. In addition to the first and second trench structures, other trench structures constructed similarly can be provided.

[0009] According to another aspect, a trench transistor has a third trench structure in addition to the first and second trench structures. This third trench structure is connected to the first and second trench structures by means of a connecting structure (e.g., a curved trench structure). A gate insulating layer and a conductive gate layer are disposed in the trench structure and the connecting structure, such that the gate potential at the gate contact can be applied to the gate electrodes in the first and second trench structures through the gate layers in the third trench structure and the connecting structure. In the trench transistor, at least in the edge region of the third trench structure, the width of the third trench structure (i.e., the extension of the trench perpendicular to its longitudinal direction, in other words, the extension from one trench sidewall to the opposite trench sidewall of the third trench structure) is greater than the width of the first trench structure and / or the second trench structure. In other words, at least two of the multiple trenches merge in a region outside the transistor's cell region and terminate in a wider third trench further away from the active region. Due to the greater width of the third trench, it has a larger radius of curvature at its end closer to the gate contact than at least two merged trenches. This increased radius of curvature reduces the electric field strength in the gate insulating layer. Therefore, voltage breakdown of the gate oxide between the gate polysilicon and silicon carbide can be avoided, for example, under high gate control voltages.

[0010] According to another aspect, the width of the third trench (i.e., the terminating trench) can be configured to be so wide that the gate contact can appear directly in the trench. In this case, for example, it is not necessary for the gate layer (e.g., by means of a polysilicon mask layer) to be led out from the trench.

[0011] According to another aspect, the width of the third trench structure can be configured to be so narrow that the third trench structure can also be filled with gate material deposition (e.g., polysilicon deposition).

[0012] According to another aspect, an insulating layer can be disposed above the semiconductor region, and a via (through-hole) can be provided through the insulating layer (the via is connected to the gate layer in the third trench structure), i.e., a via, which extends through the insulating layer to the surface of the semiconductor region and contacts the conductive gate layer. This trench transistor configuration has the advantage that a conductive gate layer-to-gate contact can be established without bringing the gate layer out of the trench.

[0013] According to another aspect, the radius of curvature of the third trench structure in the edge region can be configured to be greater than the radius of curvature of the first and / or second trench structures in the edge region. This has the advantage of reducing the maximum electric field strength in the gate insulating layer or reducing the electric field strength at the ends of the third trench structure.

[0014] According to another aspect, the third trench structure can be arranged on the centerline between the first and second trench structures, in the edge region of the trench transistor. That is, the third trench structure is oriented parallel to the first and second trench structures, and is positioned at a distance equal to and from the first and second trench structures in the edge region outside the cell area. This has the advantage of achieving a symmetrical arrangement of the trench structures, so that the electric field distribution in the first and second trench structures is substantially the same.

[0015] According to another aspect, the third trench structure can be configured to have a first region (or segment) and a second region (or segment), wherein the width of the first region increases toward the width of the second region. The first region can be closer to the connection structure than the second region. Starting from the region closer to the trench connection structure, the third trench structure can therefore have (e.g., continuously) increasing trench cross-sectional area until reaching the cross-sectional area of ​​the second region of the third trench structure. This has the advantage that the radius of curvature of the trench structure increases (e.g., continuously) toward the edge region of the third trench structure, thereby reducing the electric field strength in the gate insulating layer in the edge region.

[0016] According to another aspect, the third trench structure can be configured such that its longitudinal direction is parallel to that of the first and second trench structures, and that the third trench structure extends in the extension portion of the first or second trench structure outside the cell area. In other words, the transistor is configured such that the first or second trench structure is positioned on the same axis as the third trench structure. This has the advantage of avoiding a small radius of curvature during the transition from the first or second trench structure to the third trench structure. Alternatively, the third trench structure can extend in the extension portion of the first trench structure, and a fourth trench structure can be further provided, which extends in the extension portion of the second trench structure.

[0017] According to another aspect, the conductive gate layer can be configured to completely fill the third trench structure above the gate insulating layer and extend from the third trench structure over the semiconductor region, meaning the internal region of the third trench structure is completely filled with the conductive gate layer. This has the advantage of providing a large conductive cross-sectional area, by means of which a contact to the gate contact can be established.

[0018] According to another aspect, the width of the third trench structure can be at least 1.5 micrometers.

[0019] According to another aspect, the third trench structure can be completely backfilled with polysilicon (polysilicon on an insulating gate oxide).

[0020] According to another aspect, a trench transistor has a trench (i.e., a basin-shaped structure with wall regions and a wide bottom surface) on the edge regions of the first and second trench structures, the surface of which is positioned at the bottom height of the first and second trench structures. The wall regions surround the bottom surface and extend away from it. Thus, the trench structure connects to a wide terminating trench or slot at its termination. This wide slot can be completely filled with polysilicon. This has the advantage of providing a large-area trench termination structure with a large radius of curvature.

[0021] According to another aspect of the trench transistor configuration, the width of the trench structure is larger in the edge region of the trench transistor than in the active region, wherein the conductivity of the conductive gate layer occurs in the edge region of the trench structure. Therefore, the cross-sectional area of ​​the trench structure increases perpendicular to its longitudinal direction. Due to the widening of the trench towards the edge region, the radius of curvature of the trench can be increased in the edge region, thereby reducing the electric field strength in the gate dielectric.

[0022] According to another aspect, the width of the trench structure can be configured to continuously (i.e., persistently) increase from the initial width toward the final width toward the edge region.

[0023] According to another aspect, the gate insulating layer may have a first sublayer and, in addition to the first sublayer, a second sublayer may be present in the edge region of the trench transistor. According to another aspect, the first sublayer may have a thickness in the range of approximately 20 nanometers to 100 nanometers. According to another aspect, the second sublayer may have a thickness in the range of approximately 10 nanometers to 400 nanometers, preferably approximately 20 nanometers to 400 nanometers.

[0024] In another aspect, a trench transistor can be a MOSFET, such as a silicon carbide MOSFET. A trench transistor can also be a power transistor.

[0025] According to another aspect, the semiconductor region can have the layer structure common to vertical transistors, such as power transistors.

[0026] A method for manufacturing the trench transistor illustrated herein may include, for example: fabricating implanted regions in a wafer (e.g., a silicon carbide wafer) and activating the implantation according to common methods; applying the trench structure illustrated herein by means of a first mask layer and a suitable etching method; reprocessing and / or rounding the trench structure, for example, by a high-temperature step; in the case of gate oxide thickening (generally, gate insulating layer thickening): conformally depositing the oxide and structuring the oxide layer with a second mask layer such that the remaining oxide layer remains at least in the edge regions of the trench structure outside the active cell regions; depositing the gate insulating layer (e.g., gate oxide) and the conductive layer (e.g., gate polysilicon); and by means of a third mask. The conductive gate layer is structured in a layer such that the conductive gate layer remains in one or more trench structures and in a region defined by a third mask layer outside the trench structures; an insulating material (e.g., insulating oxide) is deposited and structured in the source region of the transistor; an ohmic source contact is fabricated; at least one gate contact is opened by means of a fourth mask layer such that the insulating material (e.g., insulating oxide) in the region defined by the fourth mask layer (in which the one or more gate contacts are to be formed) is removed; at least one metallization and at least one passivation are applied according to common methods; and a back electrode is fabricated according to common methods.

[0027] The aspects described herein can be combined with other aspects described herein. Attached Figure Description

[0028] Embodiments of the invention are shown in the drawings and explained in more detail in the following description. The drawings show:

[0029] Figure 1 A cross-sectional view of the trench structure of a trench transistor according to one embodiment is shown schematically.

[0030] Figure 2 A schematic plan view of a trench transistor according to a first embodiment is shown.

[0031] Figure 3 A schematic plan view of a trench transistor according to a second embodiment is shown.

[0032] Figure 4 A schematic plan view of a trench transistor according to a third embodiment is shown.

[0033] Figure 5 A schematic plan view of a trench transistor according to a fourth embodiment is shown.

[0034] Figure 6 A schematic plan view of a trench transistor according to a fifth embodiment is shown. Detailed Implementation

[0035] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification, and in which specific embodiments are shown for visual explanation, in which the invention can be practiced. It is self-evident that other embodiments can be used and structural or logical changes can be made without departing from the scope of the invention. It is also self-evident that features of the different embodiments described herein can be combined with each other unless specifically indicated otherwise. Therefore, the following detailed description should not be construed as limiting, and the scope of the invention is defined by the supplementary claims.

[0036] Figure 1A trench structure 1 of a trench transistor is schematically shown in longitudinal section. In the edge region 7a of the trench structure 1, a first gate insulating layer 3 and an additional second gate insulating layer 4, having a total thickness 8 ranging from 20 nm to 600 nm, are provided. The first gate insulating layer is disposed on the bottom region of the trench structure 1, and the additional second gate insulating layer is disposed on the first gate insulating layer 3. The first gate insulating layer 3 is configured to thicken the second gate insulating layer 4 in the edge region 7a. The second gate insulating layer 4 is, for example, a gate oxide. Layer 3 may have an oxide. Alternatively, the first gate insulating layer 3 may have a different material than the second gate insulating layer 4. The first gate insulating layer 3 is disposed in the edge region 7a, preferably on the edge of a cell region of the transistor, and overlaps with the end of the trench, extending partially below the gate contact 6 (e.g., a gate solder joint) in the longitudinal direction of the trench structure 1. The second gate insulating layer 4 overlaps with the end of the trench structure in the longitudinal direction of the trench structure 1 and extends partially below the gate contact 6. The second gate insulating layer 4 extends into the active region 7b of the trench transistor and may have a thickness ranging from approximately 10 nanometers to approximately 100 nanometers. A conductive gate layer 5, such as a polysilicon layer, is disposed on the second gate insulating layer 4, which fills the trench structure 1 and extends to and contacts the gate contact 6. The potential applied by means of the gate contact 6 is conducted to the trench structure 1 by means of the conductive gate layer 5, wherein the section of the conductive gate layer 5 in the active region 7b of the trench transistor is clearly used as the gate electrode of the transistor. The total thickness of the insulating portion at the trench end is increased and the electric field strength in the gate insulating portion (e.g., gate oxide) is reduced by adding an additional insulating layer (e.g., oxide layer) 3 in the edge region 7a of the transistor.

[0037] According to another aspect, the first gate insulating layer 3 may extend from the active region 7b through the edge region 7a to the gate contact 6 in the longitudinal direction of the trench structure 1. The second gate insulating layer 4 may extend only to the gate contact 6 in the edge region 7a. In this case, the second gate insulating layer 4 serves to thicken the first gate insulating layer 3 in the edge region 7a.

[0038] According to another aspect, instead of the first and second gate insulating layers 3 and 4, a single gate insulating layer may be provided, which is implemented more thickly in the edge region 7a.

[0039] Figure 2 A schematic plan view of a trench transistor 100 is shown. The transistor 100 has multiple trench structures 1 in a semiconductor region 2, first and second gate insulating layers 3 and 4, a conductive gate layer 5 located thereon, and a gate contact 6. Figure 2It is evident that the thickening of the gate insulating portion (e.g., oxide thickening) is achieved by constructing two gate insulating layers 3 and 4 only in the edge region 7a of the transistor 100, while only the gate insulating layer 4 is constructed in the active region of the transistor 100.

[0040] Figure 3 A schematic plan view of a trench transistor 200 is shown. At least one first trench structure 10a and a second trench structure 10b are provided in the semiconductor region 2. These at least one first trench structure and the second trench structure are interconnected at their edge regions 11 by means of a trench connection structure 9. Furthermore, the trench connection structure 9 is connected to a third trench structure 10c in the edge region 17 of the transistor 200. A gate insulating layer (not shown, see example in…) is provided in the trench structures 10a, 10b, 10c and in the trench connection structure 9. Figure 1 or Figure 2 The third trench structure 10c is disposed on the centerline 14 between the first trench structure 10a and the second trench structure 10b and extends parallel to the first and second trench structures 10a and 10b. The first region 15a is constructed such that the width or trench cross-section of the third trench structure 10c increases to a width 12 in the direction toward the edge region 15b of the third trench structure 10c, i.e., terminates in the edge region 15b of the third trench structure 10c, which is wider than the first and second trench structures 10a and 10b. The electric field strength in the gate insulator (e.g., gate oxide) is reduced by increasing the radius of curvature 16a of the first or second trench structures 10a and 10b toward the radius of curvature 16b of the third trench structure 10c at the end of the third trench structure 10c.

[0041] According to another aspect, the width of the third trench structure 10c can be set so wide that the gate contact portion (not shown, see example in...) Figure 1 or Figure 2 The gate contact 6 is directly formed in the third trench structure 10c. On the other hand, the trench width can be chosen to be so narrow that the third trench structure 10c is also backfilled by polysilicon deposition. The conductive gate layer 5 in the third trench structure 10c is conductively connected to the gate contact.

[0042] According to another aspect, for optimized protection, the trench transistor 200 may optionally be combined with the oxide thickening in the third trench structure 10c described above.

[0043] Figure 4A schematic plan view of a trench transistor 300 is shown. In the trench transistor 300, in the semiconductor region 2, a plurality of first and second trench structures 10a, 10b are connected to a third trench structure 10c by means of a trench connection structure 9. An insulating layer (not shown, see example in) is provided in the first, second, and third trench structures 10a, 10b, 10c and in the trench connection structure 9. Figure 1 or Figure 2 The third trench structure 10c is configured such that it is disposed in the extended portion of the first trench structure 10a in the edge region 17, respectively, along the longitudinal direction of the first and second trench structures 10a and 10b. The width of the third trench structure 10c is increased compared to the width of the first and / or second trench structures 10a and 10b. The third trench structure 10c has a width, for example, greater than 1.5 micrometers and can be completely filled with the conductive layer 5, for example, polysilicon. The conductive gate layer 5 is connected through a gate contact (not shown, see example in...) Figure 1 or Figure 2 The contact portion 6) is connected in the region of the wide third trench structure 10c. The electric field strength in the gate insulator (e.g., gate oxide) is reduced by increasing the radius of curvature 16a of the first or second trench structures 10a, 10b to the radius of curvature 16b of the third trench structure 10c at the end of the third trench structure 16b.

[0044] According to another aspect, for optimized protection, the trench transistor 300 may optionally be combined with the oxide thickening in the third trench structure 10c described above.

[0045] Figure 5 A schematic plan view of a trench transistor 400 in semiconductor region 2 is shown. Multiple trench structures 10a, 10b are provided in the trench transistor 400, each trench structure having an insulating layer (not shown, see example...) within the trenches. Figure 1 or Figure 2The first and second trench structures 10a and 10b are connected to a trench 18 (i.e., the region where multiple trench structures 10a and 10b terminate in the lateral direction) in the edge region 17 of the transistor 400 in the edge region 11 of the first and second trench structures 10a and 10b. Clearly, the trench structures 10a and 10b are connected to a wide surface (i.e., the trench 18, the surface of which is approximately at the bottom height of the trench) on the edge region 17 of the transistor 400. The trench 18 includes a bottom surface at the bottom height of the trench and a trench wall region surrounding the bottom surface. The trench 18 is filled with a conductive gate layer 5, such as a polysilicon layer. The conductive layer 5 in the trench 18 is conductively connected to the conductive gate layer 5 in the first and second trench structures 10a and 10b. The gate layer 5 and the gate layer 5 in the trench structures 10a and 10b may be the same layer. The conductive gate layer 5 and the gate contact (not shown, see example in…) are connected in… Figure 1 or Figure 2 The contact between the contact portions 6) is established by means of a groove 18 filled with a conductive layer 5. A gate insulating layer (not shown, see example in) is provided between the bottom surface and the conductive gate layer 5 in the groove 18. Figure 1 or Figure 2 (Layer 3 or 4 in the middle). Groove 18 represents a wide third groove structure having a radius of curvature 16b that is slightly larger than the radius of curvature 16a of the first and second groove structures 10a, 10b.

[0046] According to another aspect, for optimized protection, the trench transistor 400 may optionally have the oxide thickening described above, for example, such that the thickness of the gate insulating layer is increased in the region on the outer surface of the edge region 17 of the trench 18. The increased thickness of the gate insulating layer in the edge region 17 reduces the electric field strength in the gate oxide within the edge region 17.

[0047] Figure 6 A schematic plan view of a trench transistor 500 is shown. The transistor 500 has multiple trench structures 10a, 10b in a semiconductor region 2. A gate insulating layer and a conductive gate layer 5 are respectively constructed in the trench structures 10a, 10b. The width 21 in the first region 19a of the trench structures 10a, 10b increases to a width 20 in the edge region 19b of the trench structures 10a, 10b. In the edge region 19b, the conductive layer 5 contacts the gate (not shown, see example in…). Figure 1 or Figure 2 The gate contact 6) is connected. Due to the increased width, the radius of curvature 16b of the trench structures 10a and 10b increases in the edge region 19b.

[0048] According to another aspect, the width of the trench structures 10a and 10b can be continuously (that is, continuously) increased from the initial width 21 of the trench structures 10a and 10b toward the final width 20.

[0049] According to another aspect, regarding the trench transistor 500 Figure 6 The described configuration can be used with each of the configurations of a trench transistor described herein or with each combination of the configurations of a trench transistor described herein.

Claims

1. A trench transistor (100) having: Semiconductor region (2); Construct a trench structure (1) in the semiconductor region (2); In the trench structure (1), there are gate insulating layers (3, 4) and conductive gate layers (5), the conductive gate layers being constructed on the gate insulating layers (3, 4); and A gate contact (6) is electrically connected to the gate layer (5) in the edge region (7a) of the trench transistor (100). The thickness (8) of the gate insulating layer (3, 4) is greater in the edge region (7a) of the trench transistor (100) than in the active region (7b) of the trench transistor (100). The width (21) of the trench structure (10a, 10b) increases continuously from the active region (19a) of the trench transistor (500) toward the edge region (19b) of the trench transistor (500).

2. The trench transistor (100) according to claim 1, wherein, A conductive gate layer (5) in the edge region (7a) of the trench transistor (100) extends from the trench structure (1) over the semiconductor region (2).

3. The trench transistor (100) according to claim 2, wherein the trench transistor further comprises a second trench structure and a second gate insulating layer therein in the second trench structure. in, The conductive gate layer (5) is further formed on the second gate insulating layer in the second trench structure, and The thickness of the second gate insulating layer is greater in the edge region of the trench transistor (100) than in the active region of the trench transistor (100, 200).

4. A trench transistor (200) having: Semiconductor region (2); The first trench structure (10a) and the second trench structure (10b) in the semiconductor region (2); In the semiconductor region (2), there is a trench connection structure (9) that connects the edge regions (11) of the first trench structure (10a) and the edge regions (11) of the second trench structure (10b) to each other. A third trench structure (10c) in the semiconductor region (2) is connected to the trench connection structure (9); The gate insulating layer (3, 4) in the trench structure (10a, 10b, 10c) and the trench connection structure (9), and the conductive gate layer (5) in the trench structure (10a, 10b, 10c) and the trench connection structure (9); and A gate contact portion (6) is electrically connected to the gate layer (5) in the third trench structure (10c). Wherein, at least in the edge region (15b) of the third trench structure (10c), the width (12) of the third trench structure (10c) is greater than the width (13) of the first trench structure (10a) and / or the second trench structure (10b). The third trench structure (10c) includes a first region (15a) and a second region (15b), wherein the width of the first region (15a) increases toward the width (12) of the second region (15b).

5. The trench transistor (200) according to claim 4, further comprising: The insulating layer above the semiconductor region (2), and A via through the insulating layer is connected to the gate layer (5) in the third trench structure (10c).

6. The trench transistor (200) according to claim 4 or 5, wherein, On the edge region (15b) of the third trench structure (10c), the radius of curvature (16b) of the third trench structure (10c) is greater than the radius of curvature (16a) of the first trench structure (10a) on the edge region (11) of the first trench structure (10a) and / or greater than the radius of curvature (16a) of the second trench structure (10b) on the edge region (11) of the second trench structure (10b).

7. The trench transistor (200) according to any one of claims 4 to 6, wherein, The third trench structure (10c) is arranged on the centerline (14) between the first trench structure (10a) and the second trench structure (10b), in the edge region (17) of the trench transistor (200).

8. The trench transistor (300) according to any one of claims 4 to 6, wherein, The third trench structure (10c) is constructed parallel to the first trench structure (10a) and the second trench structure (10b), and extends in the extension portion of the first trench structure (10a) or the second trench structure (10b) in the edge region (17) of the trench transistor (300).

9. The trench transistor (300) according to claim 8, wherein, The conductive gate layer (5) completely fills the third trench structure (10c) and extends out of the third trench structure (10c) over the semiconductor region (2).

10. A trench transistor (400) having: Semiconductor region (2); Multiple trench structures (10a, 10b) arranged side by side in the semiconductor region (2); In the semiconductor region (2), there is a trench (18) that connects to the plurality of trench structures (10a, 10b) in the edge region (17) of the trench transistor (400). In the trench structures (10a, 10b) and in the trench (18) are gate insulating layers (3, 4) and conductive gate layers (5), the conductive gate layers being constructed on the gate insulating layers (3, 4); and A gate contact portion (6) is electrically connected to the gate layer (5) in the trench (18). in, The groove (18) extends laterally from at least the outermost first groove structure (10a) of the plurality of groove structures to the outermost second groove structure (10b) of the plurality of groove structures, wherein the outermost second groove structure is furthest from the outermost first groove structure (10a). The width (21) of the trench structure (10a, 10b) increases continuously from the active region (19a) of the trench transistor (500) toward the edge region (19b) of the trench transistor (500).

11. A trench transistor (500) having: Semiconductor region (2); A trench structure (10a, 10b) is constructed in the semiconductor region (2); In the trench structure (10a, 10b), there are gate insulating layers (3, 4) and conductive gate layers (5), the conductive gate layers being constructed on the gate insulating layers (3, 4); and A gate contact (6) is electrically connected to the gate layer (5) in the edge region (19b) of the trench transistor (500). The width (20) of the trench structure (10a, 10b) is greater in the edge region (10b) of the trench transistor (500) than in the active region (19a) of the trench transistor (500). The width (21) of the trench structure (10a, 10b) increases continuously from the active region (19a) of the trench transistor (500) toward the edge region (19b) of the trench transistor (500).

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