Overvoltage protection for power amplifiers with soft turn-off

Abstract

Various methods and circuit arrangements for protecting power amplifiers from overvoltage are presented. According to one aspect, a protection circuit coupled to a varying supply voltage of a power amplifier controls a bias current to the power amplifier to limit power dissipation through the power amplifier. The overvoltage protection circuit detects a level of the varying supply voltage and reduces the bias current according to a linear function of the increasing supply voltage once the supply voltage reaches a programmable voltage level. A slope of the linear function can be programmable. The programmability of the voltage level and the slope can be used to control the bias current to multiple power amplifiers that operate at different times and have different requirements in terms of voltage limits and thermal breakdown. According to another aspect, a voltage-to-current converter for use in an overvoltage protection circuit is presented.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Application No. 16 / 669,384, filed October 30, 2019, entitled "Overvoltage Protection for Power Amplifier with Soft Shutdown," the entire contents of which are incorporated herein by reference. This application may also relate to U.S. Patent No. 10,153,737 B2, published December 11, 2018, entitled "Power Amplifier Module," the disclosure of which is incorporated herein by reference in its entirety. This application may also relate to U.S. Patent No. 9,413,298, published August 9, 2016, entitled "Amplifiers Operating in Envelope Tracking Mode," the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to amplifiers. Specifically, this application relates to overvoltage protection for power amplifiers (PAs) that operate according to varying supply voltages. Background Technology

[0004] Figure 1A A prior art radio frequency (RF) power amplifier (PA) module (110) is shown, which can be used, for example, in the transmitter section of an RF front-end communication system such as, for example, a mobile communication system. Figure 1A As shown, the power amplifier module (110) may include multiple cascaded amplifier stages (e.g., 112, 113) coupled in series via matching networks (e.g., MN1, MN2, MN3) to amplify the input RF signal RFin, thereby generating an amplified output RF signal RFout. Power to the amplifier stages (112, 113) is provided via a supply voltage Vcc referenced to reference ground Vgnd, which is coupled to the amplifier stages (112, 113) through corresponding inductors (L2, L3). The amplified signal RFout may then be coupled to an antenna of the PA module (e.g., according to the antenna switch described later) via, for example, an antenna switch. Figure 7 Components 740 and 750 were sent.

[0005] like Figure 1AAs shown in Figure 1A , the input stage of each of the amplifier stages (112, 113) can include a respective common-emitter transistor (Tr12, Tr13) whose base receives an input RF signal, which is amplified by the common-emitter transistor (Tr21, Tr13) and output at the respective collector of the transistor (e.g., the detail in the lower right corner of the figure), which is coupled to a supply voltage Vcc through a respective inductor (L2, L3), and to a respective output of the amplifier stage (112, 113). The operating point (i.e., the bias point) of the common-emitter transistor (Tr12, Tr13) can be established based on the biasing of the amplifier stage (112, 113) through the amplification by each of the amplifier stages (112, 113) and, thus, by the PA module (110). As can be seen in Figure 1A , such biasing is provided via a biasing circuit (120) that includes emitter follower transistors (Tr22, Tr23) coupled to respective inputs of the amplifier stages (112, 113). The emitter of each of the emitter follower transistors (Tr22, Tr23) is coupled to the base of the respective common-emitter transistor (Tr21, Tr23) through a series-connected resistor (R12, R13), which is known in the art as a “ballast” resistor. Thus, the biasing circuit (120) provides a biasing signal to each of the amplification stages (112, 113), which can be considered as a biasing voltage or a biasing current.

[0006] With continued reference to Figure 1A , the biasing circuit (120) can generate the biasing signal under the control of a controller circuit (130), which can include a control / interface circuit (132) to receive commands from, for example, a signal perception processor (such as, for example, a transceiver circuit) and convert such commands into control signals to generate the corresponding biasing signal for the biasing of the PA module (110). In the case of the exemplary prior art shown in Figure 1A , a digital-to-analog (DAC) converter (135) is used to generate the control signal (i.e., a current or a voltage) to the emitter follower transistors (Tr22, Tr23) of the biasing circuit (120). For example, as Figure 1AAs shown, the DAC converter (135) can provide a voltage to the base of each of the emitter follower transistors (Tr22, Tr23) such that a desired bias signal can be output at the emitter of each such transistor for use in the biasing of the PA module (110). For example, as described in the above-referenced U.S. Patent No. 10,153,737 B2, under the assumption of a constant supply voltage Vcc, the series-connected diode pairs (D21, D22) and (D31, D32) coupled between the reference ground Vgnd and the base of the respective emitter follower transistors (Tr22, Tr23) can be used to counteract thermal variations of the common-emitter transistors (Tr12, Tr13) and, in certain cases, prevent thermal runaway of the common-emitter transistors (Tr12, Tr13) as known in the art. However, under the assumption of a varying supply voltage Vcc, for values of the supply voltage Vcc that are increased relative to a nominal value, the bias point of the common-emitter transistors (Tr12, Tr13) can change such that a higher (collector) current (Icc2, Icc3) can pass through such common-emitter transistors. Because the base current (Ib2, Ib3) provided by the emitter follower transistors (Tr22, Tr23) via the constant voltage supply (e.g., Vbatt) is not limited, the higher (collector) current (Icc2, Icc3) can be achieved by a higher base current (Ib2, Ib3) which, in combination with the increased supply voltage Vcc, can result in thermal damage of the common-emitter transistors (Tr12, Tr13). In Figure 1B the corresponding curve of the power (thermal) dissipation through the common-emitter transistors (Tr12, Tr13) as a function of the supply voltage Vcc is shown in FIG. 1, where the power dissipation (labeled as Pheat in the figure) is the product of the value of the supply voltage Vcc and the value of the collector current (Icc, e.g., Icc2, Icc3) of the common-emitter transistors (Tr12, Tr13). Because the collector current (Icc2, Icc3) can increase linearly with respect to the value of the increased supply voltage Vcc, the curve shown in FIG. 1 is based on a linear function. Figure 1A Figure 1B Because the collector current (Icc2, Icc3) can increase linearly with respect to the value of the increased supply voltage Vcc, the curve shown in FIG. 1 is based on a linear function. In contrast, the curve shown in FIG. 2 is based on a quadratic function which, as a result, can provide a rapid increase of the power dissipation to reach the thermal breakdown limit (e.g., for Vcc = Vcc_bdl), where the common-emitter transistors (Tr21, Tr22) can become inoperable.

[0007] As described in the above-referenced U.S. Patent No. 10,153,737 B2, Figure 2A the prior art configuration shown in FIG. 1 limits the base current (Ib2, Ib3) by supplying a limited current I OUT_OCP to the collector of the emitter follower transistors (Tr22, Tr23) of the biasing circuit (120). As Figure 2A shown, this can be achieved by the series-connected diode pairs (D21, D22) and (D31, D32) in the biasing circuit (120) of FIG. 1. Figure 2A ​An overcurrent protection (OCP) circuit (235) shown as part of the controller circuit (230) is provided, which can be controlled via, for example, the control / interface circuit (132) to set a higher limit for the current I OUT_OCP as the supply voltage Vcc increases. As the supply voltage Vcc increases, the collector current (Icc2, Icc3) can increase until the current I OUT_OCP set limit is reached. Once the limit for the current I OUT_OCP is reached, no further increase of the base current (Ib2, Ib3) for higher collector current (Icc2, Icc3) in response to further increase of the supply voltage Vcc is provided. However, as the supply voltage Vcc can further increase, the power dissipation in the common emitter transistor (Tr12, Tr13) can still increase linearly with respect to the supply voltage Vcc. This is shown in the power (heat) dissipation curve of Figure 2B , where the power dissipation (labeled as Pheat in the figure) increases as a quadratic function with increasing supply voltage Vcc from a lower value to a higher value until a point (e.g., Vcc = Vcc_lm) where the collector current (labeled as Icc in the figure) saturates due to the limit imposed on the base current (Ib2, Ib3), after which the power dissipation increases as a linear function of the supply voltage Vcc until the thermal breakdown limit is reached (e.g., for Vcc = Vcc_bd2). Thus, when compared to the prior art configuration shown in Figure 1A , Figure 2A the OCP circuit (235) of the prior art configuration shown in Figure 1B and Figure 2B The curves shown in

[0008] RF amplification schemes known in the art such as, for example, envelope tracking, envelope following, average power tracking, and polar modulation require the supply voltage Vcc to be changed by a considerable amount, for example, up to twice the nominal value, if applied to the common emitter transistor (Tr21, Tr22) of the prior art configuration shown in Figure 1A and Figure 2AIn prior art configurations of the type shown in FIG. 1, the supply voltage Vcc can vary / increase due to unintended consequences, such as for example, plugging / unplugging the portable device to / from an external power source. Although a hard shutdown scheme, known in the art, in which power to the amplifier module is removed, can be used to protect the amplifier module from overvoltage, such a scheme can also force an interruption of any activity related to the operation of the amplifier module (e.g., transmission of RF signals). As can be seen, there can be a need for Figure 1A and Figure 2A improved overvoltage protection for RF amplifier modules (110) shown in prior art configurations of the type shown in FIG. 1, which improved overvoltage protection not only protects the amplifier from overvoltage (e.g., thermal breakdown), but also does not interrupt ongoing activities of the amplifier (e.g., soft shutdown). Such improved overvoltage protection is provided in accordance with the teachings of the present disclosure. SUMMARY

[0009] According to a first aspect of the present disclosure, there is presented a circuit comprising: a biasing circuit configured to supply a biasing signal based on a control current; and a protection circuit configured to detect a level of a varying supply voltage and to generate a control current having an upper limit in dependence on the detected level of the varying supply voltage, wherein for i) a detected voltage of the varying supply voltage being below a preset supply voltage limit, the upper limit of the control current is constant, and for ii) a detected voltage of the varying supply voltage being above the preset supply voltage limit, the upper limit of the control current is a linear function of the detected voltage of the varying supply voltage, the linear function having a negative slope with respect to increasing detected voltage values.

[0010] According to a second aspect of the present disclosure, there is presented a method for limiting high currents through an amplifier operating between a varying supply voltage and a reference ground, the method comprising: controlling an upper limit of a current to the amplifier based on a detected value of the varying supply voltage, such that for values of the varying supply voltage being above a preset supply voltage limit, the upper limit of the current linearly decreases with respect to increasing values of the varying supply voltage; and based on the controlling, providing an approximately constant value of maximum power dissipated through the amplifier for values of the varying supply voltage being above the preset supply voltage limit. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings, which are incorporated in and form a part of the specification, illustrate one or more implementations of the present disclosure and, together with the description, serve to explain the principles and implementations of the disclosure.

[0012] Figure 1AA prior art RF power amplifier (PA) module and a bias circuit providing a bias signal to the PA module are shown.

[0013] Figure 1B A curve showing power dissipation of a PA module representing Figure 1A with respect to varying supply voltage to the PA module is shown.

[0014] Figure 2A A prior art RF power amplifier (PA) module and a bias circuit providing a bias signal to the PA module are shown, wherein the bias circuit limits current through the PA module.

[0015] Figure 2B A curve showing power dissipation of a PA module representing Figure 2A with respect to varying supply voltage to the PA module is shown.

[0016] Figure 3A A configuration of a RF power amplifier (PA) module and a bias circuit providing a bias signal to the PA module according to an embodiment of the present disclosure is shown, wherein the bias circuit reduces current through the PA module for increasing values of supply voltage to the PA module.

[0017] Figure 3B A curve showing power dissipation of a PA module representing Figure 3A with respect to varying supply voltage to the PA module is shown.

[0018] Figure 4A A simplified schematic of an overvoltage protection circuit according to an embodiment of the present disclosure is shown.

[0019] Figure 4B A curve showing two currents representing varying supply voltage to a PA module of Figure 3A and a subtraction of such currents performed by an overvoltage protection circuit of Figure 4A is shown.

[0020] Figure 5 A simplified schematic of a voltage-to-current converter circuit used in the overvoltage protection circuit shown in Figure 4A is shown.

[0021] Figure 6A A simplified schematic of a shutdown circuit with transistor protection according to an embodiment of the present disclosure is shown, which can be used to shut down current flow through a current converter circuit of Figure 5 .

[0022] Figure 6B The shutdown circuit of Figure 6A is shown in an enabled state.

[0023] Figure 6C a shutdown circuit of the Figure 6A

[0024] Figure 7 a simplified block diagram of a transmitter portion of an RF front-end communication system using multiple PA modules, each PA module according to Figure 3A the configuration shown and in accordance with Figure 4A a configuration sharing a single overvoltage protection circuit.

[0025] Figure 8 is a process diagram illustrating various steps of a method for limiting high current through an amplifier operating between a varying supply voltage and a reference ground according to embodiments of the present disclosure.

[0026] The same reference numbers and designations in the various drawings represent the same elements. DETAILED DESCRIPTION

[0027] Throughout this disclosure, embodiments and variations are described for purposes of illustrating the inventive concepts of the various embodiments and implementations. The illustrative descriptions should be understood to present examples of the inventive concepts, rather than limit the scope of the concepts disclosed herein.

[0028] Figure 3A ​A configuration (300A) according to an embodiment of the present disclosure is shown, comprising an RF power amplifier (PA) module (110) and a bias circuit (120) providing a bias signal to the PA module (110), wherein, under the control of a controller circuit (330), the bias circuit (120) is configured to reduce the upper limit of the collector current (Icc2, Icc3) through the PA module (110) for an increased supply voltage Vcc to the PA module (110). In other words, for a higher value of the supply voltage Vcc, the maximum current value or high current limit of the collector of the common-emitter transistors (Tr12, Tr13) of the PA module (110) is reduced. According to an exemplary embodiment of the present disclosure, such a reduction in the high current value is a linear reduction with respect to the increased supply voltage Vcc. Therefore, in embodiments of this disclosure, for supply voltage Vcc values ​​below the limit voltage Vcc_lm, the high current value is limited to a constant high value, while for increasing supply voltage Vcc values ​​above the limit voltage Vcc_lm, the high current value is limited according to a decreasing linear function of the supply voltage Vcc. According to another exemplary embodiment of this disclosure, the decreasing linear function can be segmented based on the value of the supply voltage Vcc, wherein the linear segments have different slopes (negative slopes) with respect to increasing supply voltage Vcc values. It should be noted that although the bias circuit (120) is described primarily as a circuit separate from the PA module (110) based on its separation function compared to the PA module, in some embodiments, the PA module (110) can be described as also including the bias circuit (120), or even the controller circuit (330). Therefore, such a circuit combination can be monolithically integrated into a single chip.

[0029] Therefore, as Figure 3B As shown, through Figure 3A The power dissipation of the common-emitter transistors (Tr12, Tr13) in the configuration (300A) can be based on the increasing value of the supply voltage Vcc—up to the limit voltage Vcc_lm increasing as a quadratic function. For example... Figure 3BAs shown, for an increase in the supply voltage Vcc above the limit voltage Vcc_lm, the linear decrease in the high current value offsets the increase in the supply voltage Vcc to effectively provide constant power dissipation through the common-emitter transistors (Tr12, Tr13). In other words, for a varying supply voltage Vcc value greater than the limit voltage Vcc_lm, the product of the high current value and the voltage of the varying supply voltage is constant or nearly constant (e.g., varies less than 20% over time or within the range of the varying supply voltage). According to embodiments of this disclosure, the value of Vcc_lm (which may differ for each of transistors Tr12, Tr13) can be selected to limit the constant power dissipation value to an upper limit value Pheat_lm, which is lower than the thermal breakdown limit of each of the common-emitter transistors (Tr12, Tr13). Therefore, each of the common-emitter transistors (Tr12, Tr13) can operate at a supply voltage Vcc value higher than the limit voltage Vcc_lm without requiring power-off of the transistor. This allows for continued operation at higher values ​​of the supply voltage Vcc. Figure 3A Any ongoing activity of the PA module (110) configured as shown.

[0030] Return to reference Figure 3A According to an embodiment of this disclosure, the controller circuit (330) detects the level of the supply voltage Vcc and generates a restricted current I based on the detected level of the supply voltage Vcc. OUT_OCP The limited current I OUT_OCP The collectors of the emitter follower transistors (Tr22, Tr23) are supplied to the bias circuit (120). (Refer to the above.) Figure 2A The described confined current I OUT_OCP This limits the (high) bias currents (Ib2, Ib3) to the common-emitter transistors (Tr12, Tr13), which in turn limits the (high) collector currents (Ic2, Ic3). For example... Figure 3A As can be seen, the level of the supply voltage Vcc can be detected by a Vcc level detector circuit (338) coupled to the supply voltage Vcc. This Vcc level detector circuit (338) then provides the detected level value to a current control circuit (335), which controls the overcurrent protection (OCP) circuit (235) to output a limited current I. OUT_OCP The limited current I OUT_OCP The current is limited to a high value based on the detection level of the supply voltage Vcc. According to another embodiment of this disclosure, the current control circuit (335) also limits the high current I... OUT_OCPthe value of the (negative) slope of the control. In other words, such slope can be programmable. According to another embodiment of the present disclosure, the current control circuit (335) determines the value of the limit voltage Vcc_lm at which the slope starts. In other words, the value of the limit voltage Vcc_lm can be programmable. The programmability of the value and starting position (i.e., based on Vcc_lm) of the slope via the combination of the Vcc level detector circuit (338) and the current control circuit (335) allows using the OCP circuit (235) to control the bias current to a number of different PA module parts of the same transmitter part of the RF front-end communication system shown in Figure 7 the bias current of a number of different PA module parts of the same transmitter part of the RF front-end communication system shown in

[0031] Figure 4A A simplified schematic (400A) of the elements (235, 335, 338) of the controller circuit (330) including elements (335, 338) for providing overvoltage protection according to the present teachings shown in Figure 3A Figure 4A The Vcc level detector circuit (338) coupled to the supply voltage Vcc detects the level of the supply voltage Vcc and generates therefrom a control signal V CTL CTL to control the magnitude of the current I VCC_PROP output by the current source (3351) of the current control circuit (335). According to an embodiment of the present disclosure, the magnitude of the current I VCC_PROP is proportional to the level of the supply voltage VCC. In other words, within the voltage range of interest, I VCC_PROP = k*Vcc. This can be provided by, for example, varying the number of parallel current sources (current mirrors) of the current source (3351) via designs and methods well known to those skilled in the art, the details of which are beyond the scope of the present disclosure.

[0032] With continued reference to Figure 4A , the current source (3351) is connected in series with two separate current paths, one path including the current source (3352), and the other path including the reference leg of the current mirror (3353). As those skilled in the art will clearly appreciate, as long as the current I VCC_PROP is less than the current I CON generated by the current source (3352), the entire current I VCC_PROP flows through the current source (3352), and thus no current flows through the reference leg of the current mirror (3353). In other words, the current I’ SINK through the reference leg and the corresponding current I SINK through the target leg of the current mirror (3353) is zero. On the other hand, when the current I VCC_PROP ​​greater than the current I generated by the current source (3352) CON a residual (difference) current I higher than the current obtainable by the current source (3352) VC_PROP - I CON flows through the reference branch of the current mirror (3353) and, therefore, the corresponding current I SINK = K * I' SINK = K * (I VC_PROP - I CON ) flows through the target branch of the current mirror (3353), where K is a number corresponding to the ratio of the currents between the reference branch and the target branch of the current mirror (3353).

[0033] According to the above description, the current I SINK flowing through the target branch of the current mirror (3353) is: i) equal to zero for (detected) values of the supply voltage Vcc in which I VCC_PROP ≤ I CON ; and ii) equal to K * (I VCC_PROP - I CON ) for values of the supply voltage Vcc in which I VC_PROP > I CON . Since the current I VCC_PROP is proportional to the value of the supply voltage Vcc, it follows that, for a given value of the current I CON , the current I SINK is also proportional to the value of the supply voltage Vcc and, therefore, when I SINK is not equal to zero, I SINK increases proportionally with the increase of the value of the supply voltage Vcc. Moreover, the rate of increase or slope of the current I SINK with respect to the increasing value of the supply voltage Vcc is based on the number K. In other words, by programmatically varying the value of K, the slope of the current I SINK (when not equal to zero) can be varied. The skilled person is well aware of the design techniques for providing a parameterized (programmable) ratio K of a current mirror, such as 3353. Finally, by programmatically varying the size of the current I CON generated by the current source (3352), the activation of the current I' SINK flowing through the reference branch of the current mirror (3353) and, therefore, of the current I SINK flowing through the target branch of the current mirror (3353) can be varied as a linear function of the value of the supply voltage Vcc. In other words, for higher values of the current I CON , proportionally higher values of the supply voltage Vcc are required to activate the current flow through the current mirror (3353). Therefore, the programmability of the current source (3352) and of the ratio of the current mirror (3353) can provide, respectively, the programmability of the current I SINKThe position and magnitude of the slope. According to exemplary embodiments of this disclosure, such as... Figure 4A As shown, the current source (3352) and current mirror (3353) can be programmed by generating corresponding control signals (CTL). 3352 CTL 3353 The control circuit (3354) is provided. According to alternative embodiments, the control circuit (3354) may be external to the current control circuit (335), such as being part of a signal sensing controller (such as a transceiver system). It should be noted that control of various controllable and / or programmable elements / circuits according to this teaching may require control lines and signals, which may not be shown in the current figures but will undoubtedly be well understood by those skilled in the art.

[0034] Continue to refer to Figure 4A The OCP circuit (235) includes a reference current generation circuit (2351) that generates a reference restricted current Iref, from which the current I generated by the current control circuit (335) is subtracted. SINK To generate such Figure 4A The confined current shown (Iref-I) SINK The confined current is fed to the output stage (2352), which can multiply this current to generate a larger confined current I. OUT_OCP The large confined current I OUT_OCP Provided to Figure 3A The bias circuit (120) shown. Therefore, for I... SINK The supply voltage Vcc is equal to zero, and the restricted current I is... OUT_OCP Limited by a fixed amount determined by the reference restricted current Iref, and for I SINK The non-zero supply voltage Vcc value, and the restricted current I. OUT_OCP Limited by the reference limited current Iref minus the current I, which is a linear function of the supply voltage Vcc as described above. SINK A definite quantity. Figure 4B The corresponding graphs are shown, including: a) a reference limited current Iref with a constant current limit; b) a current I with a zero value for a supply voltage below the limit Vcc_lm. SINK And for supply voltage values ​​higher than the limit Vcc_lm, a positive non-zero current I with a positive slope. SINK ; and c) based on the reference-constrained current Iref and the current I SINK The difference in current is limited.

[0035] Figure 5 Exemplary embodiments of the present disclosure are shown inFigure 4A simplified schematic of a voltage-to-current converter circuit (500) used in the overvoltage protection circuit (335, 338) shown. As Figure 5 The level of the supply voltage Vcc is detected via a resistive voltage divider network, which includes two series-connected resistors R51 and R52, which is coupled between the supply voltage Vcc and a reference ground Vgnd, as shown. Thus, a common node N C provides a detection voltage Va corresponding to the voltage level of the supply voltage Vcc. The operational amplifier (515), which is connected in a non-inverting configuration, receives the detection voltage Va at its non-inverting input (annotated with the symbol + in the drawing). Thus, the voltage at the inverting input (annotated with the symbol - in the drawing) of the operational amplifier (515) takes the detection voltage Va, which is provided to a shunt resistor R55 coupled between the inverting input of the operational amplifier (515) and the reference ground Vgnd. As Figure 5 The current mirror (525) including the first PMOS transistor (525a) part of the reference leg and the second PMOS transistor (525b) part of the target leg of the current mirror (525) is coupled to the operational amplifier (515) such that the gates of the first and second PMOS transistors (525a, 525b) are connected / coupled to the output of the operational amplifier (515), and the drain of the first PMOS transistor (525a) is coupled to the common node coupling the inverting input of the operational amplifier (515) with the shunt resistor R55. Further, the sources of the first and second PMOS transistors (525a, 525b) are coupled to a (generally) fixed supply voltage Vdd. This fixed supply voltage Vdd can be a regulated voltage based on, for example, a battery. In some non-limiting example implementations, the fixed supply voltage Vdd can be about 3 volts, while the supply voltage Vcc can vary from about 3 volts up to about 6.5 volts or more.

[0036] Continuing with reference to Figure 5 Because the voltage at the drain of the first transistor (525a) is equal to the detection voltage Va, the current I' VCC_PROP equals Va / R55 and thus is proportional to the detection voltage Va. Thus, the current I VCC_PROP flowing through the target leg of the current mirror (525), i.e., through 525b, is equal to the current I VCC_PROP which is the current I' VCC_PROPscaled version of the detected voltage Va, and thus proportional to the value of the supply voltage Vcc. Thus, Figure 5 the circuit shown in Figure 3A and Figure 4A the current I described above is proportional to the detected level Va of the supply voltage VCC. VCC_PROP As will be known to those skilled in the art, the ratio in size between the transistor (525b) and the transistor (525a) can determine the scaling (i.e. ratio) of the current I VCC_PROP passing through the transistor (525b) relative to the current I' VCC_PROP passing through the transistor (525a).

[0037] With continued reference to Figure 5 , according to example embodiments of the present disclosure, the shunt resistor R55 can optionally have a programmable, variable, settable resistance that can be controlled / varied in steps and / or continuously. Such programmability of the resistor R55 can allow for calibration of the voltage and current response provided by the resistor R55 in the circuit shown in Figure 5 Such programmability can be used to overcome large resistance variations in the manufacturing process (e.g. CMOS process) used to manufacture the circuit shown in Figure 5 Such calibration via adjustment of the resistance value of the resistor R55 can be performed at any stage of integration of the circuit shown in Figure 5 , including at the factory pre-shipment and / or at the assembly site where the circuit of Figure 3A may be assembled as part of a transmitter device (such as for example a portable / handheld mobile device) integrated with the circuit of Figure 5 .

[0038] According to embodiments of the present disclosure, Figure 5 a discriminator circuit can be included in the circuit shown in Figure 5 to distinguish between the high voltage high frequency component and the high voltage low frequency component of the Vcc supply voltage, as the high voltage high frequency component can be inherent to RF amplification schemes based on envelope tracking of for example RF signals and can not lead to excessive power dissipation within the RF amplifier due to its short duration. Those skilled in the art will be aware of many circuit designs to implement such discriminator functionality, such as for example a low pass filter placed in front of the non-inverting terminal of the operational amplifier (515) of

[0039] According to embodiments of the present disclosure, the current flowing through the resistive voltage divider network (R51, R52) of Figure 5 may be controlled to for example reduce the power consumption during a standby or deactivation mode of the PA module (110) shown in Figure 3A .Figure 6A A simplified schematic of a shutdown circuit (600A) with transistor protection is shown that can be used to shut off current flow through Figure 5 the resistive voltage divider network (R51, R52) shown. Because the supply voltage Vcc can vary and reach higher voltage levels (e.g., 4 volts to 6.5 volts) that exceed the tolerable voltage level (e.g., less than about 3.5 volts) of the low voltage transistors (620, 630, 650) used exclusively in the shutdown circuit (600A), it is important that such a circuit protects the low voltage transistors from the higher voltage levels of the supply voltage Vcc.

[0040] As Figure 6A shown, the shutdown circuit (600A) includes an NMOS transistor (650) coupled at its drain to a first terminal of a resistor R51 and at its source to a first terminal of a resistor R52. In other words, the NMOS transistor (650) acting as a switch is connected in series between the resistor R51 and the resistor R52 such that current flow through these two resistors can be controlled via the NMOS transistor (650). Further, a second terminal of the resistor R51 is coupled to the supply voltage Vcc and a second terminal of the resistor R52 is coupled to the drain of an NMOS transistor (620) with its source coupled to a reference ground Vgnd. In other words, the NMOS transistor (620) acting as a switch is connected in series between the resistor R52 and the reference ground Vgnd such that current flow through the resistor R52 can be controlled via the NMOS transistor (620). Thus, as will be clear to those skilled in the art, current flow from the supply voltage Vcc to the reference ground Vgnd to provide a detected level Va of the supply voltage Vcc via the voltage division provided by the resistors R51 and R52 exists only when both the NMOS transistors (650) and (620) are conductive (i.e., turned on, activated).

[0041] Further, with reference to Figure 6AThe shutdown circuit (600A) is also provided with a PMOS transistor (630) having: i) a source connected to a fixed supply voltage Vdd and to the gate of an NMOS transistor (650); ii) a drain connected to the source of the NMOS transistor (650) that carries a detection level Va when current flows through the resistors (R51, R52) (e.g., the PA module is active and the shutdown circuit is inactive); and iii) a gate connected to the gate of the NMOS transistor (620) for receiving a control signal Ena that controls the active state (i.e., no current flows through the resistors R51 and R52) and the inactive state (i.e., current flows through the resistors R51 and R52) of the shutdown circuit (600A).

[0042] Figure 6B The shutdown circuit (600A) is also provided with a PMOS transistor (630) having: i) a source connected to a fixed supply voltage Vdd and to the gate of an NMOS transistor (650); ii) a drain connected to the source of the NMOS transistor (650) that carries a detection level Va when current flows through the resistors (R51, R52) (e.g., the PA module is active and the shutdown circuit is inactive); and iii) a gate connected to the gate of the NMOS transistor (620) for receiving a control signal Ena that controls the active state (i.e., no current flows through the resistors R51 and R52) and the inactive state (i.e., current flows through the resistors R51 and R52) of the shutdown circuit (600A). Figure 6B Figure 3A Figure 6B

[0043] Figure 6C ​​​A shutdown circuit (600A) in an inactive state is shown, such that current does flow through resistors R51 and R52 in an exemplary case where Vdd equals approximately 3 volts and the supply voltage Vcc varies from approximately 3 volts to approximately 6.5 volts. Because the control signal Ena is at approximately the same level as the fixed voltage Vdd (i.e., Ena = 3V), the NMOS transistor (620) is turned on (conducting current) and the PMOS transistor (630) is turned off (not conducting current). Figure 6B As shown, because the PMOS transistor (630) is off, the gate-source voltage of the NMOS transistor (650) is large enough to turn the transistor on. Therefore, because both NMOS transistors (620, 650) are on, current flows through resistors R51 and R52 to provide a voltage Va at the source of the NMOS transistor (650), which represents the voltage level of the supply voltage Vcc (e.g., a linear function via resistive voltage division). According to an exemplary embodiment of this disclosure, as shown, the resistance ratio of resistors R51 and R52 can be selected such that for a varying supply voltage Vcc that can be up to about 6.5 volts, the maximum value of voltage Va is equal to or less than 1.2 volts. Such a ratio selection ensures that, given a range of varying supply voltage Vcc, the circuit actively detects, as in... Figure 3A During the active mode of operation of the PA module (110) shown, when the level of the supply voltage Vcc required to change is such that no transistor in the circuit is subjected to a voltage greater than approximately 3.5 volts.

[0044] Figure 7 A simplified block diagram of the transmitter section of an RF front-end communication system using multiple PA modules (110a, 110b, ..., 110k) is shown, each PA module according to... Figure 3A The configuration shown is coupled to the corresponding bias circuits (120a, 120b, ..., 120k) and according to... Figure 4A The configurations share a single overvoltage protection circuit (335 and 338). See above for reference. Figure 4A The above references are further considered. Figure 4B The curve is generated by a combination of the Vcc level detector circuit (338) and the current control circuit (335). Figure 7 The limited current I output by the OCP circuit (235) shown is OUT_OCP The programmability of the slope value (the rate of change of Vcc) and the starting position of the slope (i.e., based on Vcc_lm) allows the use of the OCP circuit (235) to control the bias current to multiple different PA modules (110a, 110b, ..., 110k) sections of the same transmitter section of an RF front-end communication system.

[0045] Continue to refer toFigure 7 At any given time, one of the plurality of PA modules (110a, 110b,..., 110k) can be coupled to the antenna (750) via the antenna switch (740) for transmitting an amplified RF signal (RFout_a, RFout_b,..., RFout_k). Thus, based on the above description with reference to Figure 3A the selected PA module (e.g., 110b) coupled to the antenna (750), the DAC converter (135) can control the base voltage of the emitter follower transistors (e.g., Tr22, Tr23) of the corresponding bias circuit (120b) such that a desired bias signal can be output at the emitter of each such emitter follower transistor for biasing of the PA module (110b). Meanwhile, the slope of the limited current I OUT_OCP and the position of the slope can be programmed based on, for example, the thermal characteristics of the selected PA module (110b).

[0046] Figure 8 is a process diagram (800) illustrating various steps of a method for limiting a high current through an amplifier operating between a varying supply voltage and a reference ground. As can be seen in the process diagram (800), the method includes, in accordance with step 810, controlling an upper limit of current to the amplifier based on a detected value of the varying supply voltage such that, for values of the varying supply voltage above a preset supply voltage limit, the upper limit of current decreases linearly with respect to increasing values of the varying supply voltage; and, in accordance with step 820, based on the controlling, providing an approximately constant value of maximum power dissipated through the amplifier for values of the varying supply voltage above the preset supply voltage limit.

[0047] It should be noted that the various embodiments of the PA module with an overvoltage protection circuit for soft turn-off according to the present disclosure can be implemented as a monolithic integrated circuit (IC) according to any fabrication technology and process known to those skilled in the art.

[0048] Applications of the novel apparatuses and systems, which can include various embodiments, include electronic circuitry used in high-speed computers, communications and signal processing circuitry, modems, single or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules, including multi-layer or multi-chip modules. Such apparatuses and systems can also be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), and other electronic systems. Some embodiments can include a plurality of methods.

[0049] The term "MOSFET" technically refers to a metal-oxide-semiconductor; another synonym for MOSFET is "MISFET" for metal-insulator-semiconductor FET. However, "MOSFET" has become the generic label for most types of insulated-gate FETs ("IGFETs"). Nonetheless, it is well known that the term "metal" in the MOSFET and MISFET names is now often a misnomer, as the former metal gate material is now typically a polysilicon (poly) layer. Similarly, "oxide" in the MOSFET name can be a misnomer, as the purpose of using a different dielectric material is to obtain a strong channel at a smaller applied voltage. Thus, the term "MOSFET" as used herein should not be taken literally to be limited to metal-oxide-semiconductors, but rather generally includes IGFETs.

[0050] As should be apparent to those of ordinary skill in the art, various embodiments of the application can be implemented to meet a wide variety of specifications. Selection of appropriate component values is a matter of design choice unless otherwise specified above, and various embodiments of the application can be implemented in any suitable IC technology, including but not limited to MOSFET and IGFET structures, or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the above inventive concepts are particularly useful for SOI-based fabrication processes, including SOS, as well as fabrication processes with similar characteristics. CMOS fabrication on SOI or SOS enables low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (in excess of about 10 GHz, and particularly in excess of about 20 GHz). Monolithic IC embodiments are particularly useful, as parasitic capacitance can generally be kept low (or kept minimal, uniform among all cells, allowing for compensation of parasitic capacitance) through careful design.

[0051] Voltage levels and / or voltage and / or logic signal polarities can be adjusted according to particular specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage handling capability, current handling capability, and power handling capability can be adjusted as needed, for example, by adjusting device sizes, "stacking" components (particularly FETs) in series to withstand larger voltages, and / or by using multiple components in parallel to handle larger currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality, without significantly altering the functionality of the disclosed circuits.

[0052] The examples set forth above are provided to give those of ordinary skill in the art a complete disclosure and description of how to make and use embodiments of the gate driver of the stacked transistor amplifier of the present disclosure, and are not intended to limit the scope of what the inventors regard as their application. Such embodiments can be used, for example, in mobile handsets of current communication systems (e.g., WCDMA, LTE, WiFi, etc.), where amplification of signals with frequency content above 100 MHz and power levels above 50 mW can be required. Those of skill can find other suitable implementations of the presented embodiments.

[0053] Modifications to the above-described modes for carrying out the methods and systems disclosed herein, which are obvious to persons of ordinary skill in the art, are intended to be within the scope of the following claims. All patents and publications mentioned in the specification are indicative of the levels of those skilled in the art to which the present disclosure pertains. All references cited in the present disclosure are hereby incorporated by reference to the same extent as if each reference had been incorporated by reference in its entirety individually.

[0054] It should be understood that the present disclosure is not limited to particular methods or systems, which can, of course, vary. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term "plurality" includes two or more referents unless the content clearly dictates otherwise. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0055] A number of embodiments of the present disclosure have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the present disclosure. Therefore, other embodiments are within the scope of the following claims.

Claims

1. A circuit, comprising: a biasing circuit configured to supply a biasing signal based on a control current; and a protection circuit configured to detect a level of a varying supply voltage and to generate a control current upper limit from the detected level of the varying supply voltage, wherein for i) a detected voltage of the varying supply voltage below a preset supply voltage limit, the control current upper limit is constant, and for ii) a detected voltage of the varying supply voltage above the preset supply voltage limit, the control current upper limit is a function of the detected voltage of the varying supply voltage, the function having a negative slope with respect to increasing values of the detected voltage, and wherein the control current does not exceed the control current upper limit.

2. The circuit of claim 1, further comprising an amplifier configured to operate between a varying supply voltage and a reference ground.

3. The circuit of claim 2, wherein, the biasing circuit comprises an emitter follower transistor configured to supply the biasing signal to the amplifier.

4. The circuit of claim 3, wherein, the control current is provided to a collector of the emitter follower transistor.

5. The circuit of claim 3, wherein the amplifier comprises a first amplification stage containing a common emitter transistor comprising: a collector coupled to the varying supply voltage; an emitter coupled to the reference ground, and a base coupled to an emitter of the emitter follower transistor for receiving the biasing signal, and wherein for values of the varying supply voltage greater than the preset supply voltage limit, a product of a) a maximum current conducted between the collector and the emitter of the transistor and b) a voltage of the varying supply voltage has an approximately constant value.

6. The circuit of claim 5, wherein the constant value represents a maximum power dissipation through the first amplification stage and is configured to be below a thermal breakdown limit of the first amplification stage.

7. The circuit of claim 2, wherein, the control current is based on a combination of: a reference current generated by a reference current source independent of the varying supply voltage, the reference current having a constant reference current upper limit, and an absorption current, wherein for i) a detected voltage of the varying supply voltage below the preset supply voltage limit, the absorption current is zero, and for ii) a detected voltage of the varying supply voltage above the preset supply voltage limit, the absorption current is a linear function of the detected voltage, the linear function having a positive slope with respect to increasing values of the detected voltage, the positive slope having a same magnitude as a negative slope of the control current.

8. The circuit of claim 7, wherein, the control current is based on a result of subtracting the absorption current from the reference current.

9. The circuit of claim 7, wherein, the protection circuit comprises: a voltage level detector circuit configured to detect a level of the varying supply voltage; a first current source configured to generate a current proportional to the detected level of the varying supply voltage; a second current source connected in series with the first current source; and a comparator configured to compare the current generated by the first current source to a threshold current. a first current mirror comprising a reference current branch and a target current branch, the reference current branch being connected in series with the first current source, wherein, when a current generated by the first current source is greater than a current generated by the second current source, a current flows through the reference current branch of the first current mirror, otherwise no current flows through the reference current branch, and wherein the sink current flows through the target current branch of the first current mirror.

10. The circuit of claim 9, wherein, the current generated by the second current source is programmable, and is based on a value of the preset supply voltage limit.

11. The circuit of claim 9, wherein, a ratio of the current through the target current branch relative to the current through the reference current branch of the first current mirror provides the positive slope.

12. The circuit of claim 11, wherein, the ratio is programmable.

13. The circuit of claim 9, wherein, the voltage level detector circuit comprises: a series connected resistor coupled between the varying supply voltage and the reference ground, a common node of the series connected resistor providing the detection voltage; and an operational amplifier comprising: a non-inverting input coupled to the common node; and an inverting input coupled to a shunt resistor, wherein a current through the shunt resistor is proportional to the detection voltage.

14. The circuit of claim 13, wherein: the first current source is a target current branch of a second current mirror, and a reference current branch of the second current mirror is connected in series with the shunt resistor.

15. The circuit of claim 14, wherein: the reference current branch of the second current mirror comprises a reference transistor, a gate of the reference transistor is coupled to an output of the operational amplifier, and a drain of the reference transistor is coupled to the shunt resistor and an inverting input of the operational amplifier.

16. The circuit of claim 2, wherein the circuit is configured to operate in at least an active mode for current amplification and a standby mode for no current amplification in a manner to reduce current consumption, wherein the protection circuit comprises a level detector circuit, when operating in the active mode, the level detector circuit is configured to detect a level of the varying supply voltage based on a current through a series connected resistor coupled between the varying supply voltage and the reference ground, and when operating in the standby mode, the level detector circuit is configured to shut off current flow through the series connected resistor solely via a plurality of low voltage FET switches having respective withstand voltages lower than a higher value of the varying supply voltage.

17. The circuit of claim 16, wherein, the level detector circuit comprises: a series connected sequence of a first resistor, a first NMOS FET switch, a second resistor, and a second NMOS FET switch coupled between the varying supply voltage at one terminal of the first resistor and the reference ground at a source node of the second NMOS FET switch; and a PMOS FET switch comprising: a source node coupled to a fixed supply voltage having a voltage level lower than the respective withstand voltage; a drain node coupled to a common node of the first NMOS FET switch and another terminal of the first resistor, the common node being configured to carry a level of the varying supply voltage during operation in the active mode, and a gate node coupled to a gate node of the second NMOS FET switch for receiving a control signal to selectively enable / disable operation according to an active / standby mode of operation.

18. The circuit of claim 16, wherein, a higher value of the varying supply voltage is in a range between 4 volts and 6.5 volts, and wherein the respective withstand voltage is less than 3.5 volts.

19. The circuit of claim 5, wherein the amplifier comprises a second amplification stage arranged in cascade with the first amplification stage, and wherein the biasing circuit comprises a further emitter follower transistor configured to supply a further biasing signal to the second amplification stage based on a control current provided to a collector of the further emitter follower transistor.

20. The circuit of claim 2, further comprising a further one or more amplifiers and a further respective one or more biasing circuits configured to supply a respective biasing signal, wherein at any given time, the circuit processes an RF signal through only one of the amplifier and the further one or more amplifiers, and wherein the protection circuit is further configured to generate, based on a detected level of the varying supply voltage, a control current based on a negative slope of a pre-set supply voltage limit specific to the amplifier and the control current upper limit.

21. The circuit of claim 1, wherein, the control current upper limit is a linear function of a detected voltage of the varying supply voltage.

22. The circuit of claim 1, wherein, the circuit is monolithically integrated.

23. A power amplifier module comprising the circuit of claim 1.

24. A method for limiting high current through an amplifier operating between a varying supply voltage and a reference ground, the method comprising: controlling an upper limit of current to the amplifier based on a detected value of the varying supply voltage, such that for values of the varying supply voltage higher than a pre-set supply voltage limit, the upper limit of current linearly decreases with respect to increasing values of the varying supply voltage, and based on the control, for values of the varying supply voltage higher than the pre-set supply voltage limit, providing an approximately constant value of maximum power dissipated through the amplifier.

25. A power amplifier circuit, comprising: an amplifier configured to operate between a varying supply voltage and a reference ground; a biasing circuit comprising an emitter follower transistor configured to supply a biasing signal to the amplifier based on a control current provided to a collector of the emitter follower transistor; and a protection circuit configured to detect a level of the varying supply voltage and generate, according to the level of the varying supply voltage, a control current having an upper limit of control current, wherein, for detection voltages of the varying supply voltage below a preset supply voltage limit, the control current upper limit is constant, and for detection voltages of the varying supply voltage above the preset supply voltage limit, the control current upper limit is a function of the detection voltage, the function having a negative slope with respect to increasing values of the detection voltage, and wherein the control current does not exceed the control current upper limit.

26. The power amplifier circuit of claim 25, wherein, The control current upper limit is a linear function of the detection voltage.

27. A circuit, comprising: a protection circuit configured to detect a level of a varying supply voltage to an amplifier and to generate a control current for a bias of the amplifier in dependence on the level of the varying supply voltage, the control current having a control current upper limit, wherein: for detection voltages of the varying supply voltage below a preset supply voltage limit, the control current upper limit is constant, for detection voltages of the varying supply voltage above the preset supply voltage limit, the control current upper limit is a linear function of the detection voltage of the varying supply voltage, the linear function having a negative slope with respect to increasing values of the detection voltage, and the control current does not exceed the control current upper limit.

28. The circuit of claim 27, further comprising the amplifier configured to operate between the varying supply voltage and a reference ground.

29. The circuit of claim 28, further comprising an emitter follower transistor configured to supply a bias signal to the amplifier.

30. The circuit of claim 29, wherein, The control current is provided to a collector of the emitter follower transistor.

31. The circuit of claim 29, wherein the amplifier comprises a first amplification stage containing a common emitter transistor, the common emitter transistor comprising: a collector coupled to the varying supply voltage; an emitter coupled to the reference ground, and a base coupled to an emitter of the emitter follower transistor for receiving the bias signal, and wherein, for values of the varying supply voltage greater than the preset supply voltage limit, a product of a) a maximum current conducted between the collector and the emitter of the transistor and b) a voltage of the varying supply voltage has an approximately constant value.

32. The circuit of claim 31, wherein the constant value represents a maximum power dissipation through the first amplification stage and is configured to be below a thermal breakdown limit of the first amplification stage.

33. The circuit of claim 27, wherein, The control current is based on a combination of: a reference current generated by a reference current source independent of the varying supply voltage, the reference current having a constant reference current upper limit, and an absorption current, wherein: for detection voltages of the varying supply voltage below the preset supply voltage limit, the absorption current is zero, and for detection voltages of the varying supply voltage above the preset supply voltage limit, the absorption current is a function of the detection voltage of the varying supply voltage, the function having a positive slope with respect to increasing values of the detection voltage. For detection voltages of ii) the varying supply voltage above the preset supply voltage limit, the sink current is a linear function of the detection voltage, the linear function having a positive slope with respect to values of the increasing detection voltage, the positive slope having the same magnitude as a negative slope of the control current.

34. The circuit of claim 33, wherein, The control current is based on a result of subtracting the sink current from the reference current.

35. The circuit of claim 33, wherein, The protection circuit comprises: a voltage level detector circuit configured to detect a level of the varying supply voltage; a first current source configured to generate a current proportional to a detected level of the varying supply voltage; a second current source connected in series with the first current source; and a first current mirror comprising a reference current branch and a target current branch, the reference current branch connected in series with the first current source, wherein, when the current generated by the first current source is greater than the current generated by the second current source, a current flows through the reference current branch of the first current mirror, otherwise no current flows through the reference current branch, and wherein the sink current flows through the target current branch of the first current mirror.

36. The circuit of claim 35, wherein, The current generated by the second current source is programmable and based on a value of the preset supply voltage limit.

37. The circuit of claim 35, wherein, A ratio of the current through the target current branch relative to the current through the reference current branch of the first current mirror provides the positive slope.

38. The circuit of claim 37, wherein, The ratio is programmable.

39. The circuit of claim 27, wherein the circuit being configured to operate in at least an active mode for current amplification and a standby mode for no current amplification in a manner to reduce current consumption, wherein the protection circuit comprises a level detector circuit, when operating in the active mode, the level detector circuit being configured to detect a level of the varying supply voltage based on a current through a series-connected resistor coupled between the varying supply voltage and a reference ground, and when operating in the standby mode, the level detector circuit being configured to shut off current flow through the series-connected resistor solely via a plurality of low-voltage FET switches, respective withstand voltages of the plurality of low-voltage FET switches being lower than a higher value of the varying supply voltage.

40. The circuit of claim 39, wherein, The level detector circuit comprises: a series-connected sequence of a first resistor, a first NMOS FET switch, a second resistor, and a second NMOS FET switch, the series-connected sequence coupled between the varying supply voltage at one terminal of the first resistor and the reference ground at a source node of the second NMOS FET switch; and a PMOS FET switch comprising: a source node coupled to a fixed supply voltage, the fixed supply voltage having a voltage level lower than the respective withstand voltage; a drain node coupled to a common node of the first NMOS FET switch and another terminal of the first resistor, the common node configured to carry a level of the varying supply voltage during operation in the active mode, and a gate node coupled to a gate node of the second NMOS FET switch for receiving a control signal to selectively enable / disable operation according to an active / standby mode of operation.

41. The circuit of claim 31, wherein the amplifier comprises a second amplification stage arranged in cascade with the first amplification stage, and wherein the circuit further comprises a further emitter follower transistor configured to supply a further bias signal to the second amplification stage based on a control current provided to a collector of the further emitter follower transistor.

42. The circuit of claim 27, wherein at any given time, the circuit processes RF signals through only one of the amplifier or a further one or more amplifiers, and wherein the protection circuit is further configured to generate, based on a detected level of the varying supply voltage, a control current based on a pre-set supply voltage limit specific to the amplifier and a negative slope of the upper limit of the control current.

43. A method for limiting high currents through an amplifier operating between a varying supply voltage and a reference ground, the method comprising: controlling an upper limit of a current to the amplifier based on a detected value of the varying supply voltage, such that for values of the varying supply voltage higher than a pre-set supply voltage limit, the upper limit of the current decreases with respect to increasing values of the varying supply voltage, and based on the control, providing an approximately constant value of maximum power dissipated through the amplifier for values of the varying supply voltage higher than the pre-set supply voltage limit.

44. A power amplifier circuit, comprising: an amplifier configured to operate between a varying supply voltage and a reference ground; and a protection circuit configured to detect a level of the varying supply voltage to the amplifier and generate, according to the level of varying supply voltage, a control current for biasing of the amplifier, the control current having an upper limit of control current, wherein: for detected voltages of the varying supply voltage lower than a pre-set supply voltage limit, the upper limit of the control current is constant, for detected voltages of the varying supply voltage higher than the pre-set supply voltage limit, the upper limit of the control current is a function of the detected voltage of the varying supply voltage, the function having a negative slope with respect to increasing values of the detected voltage, the control current does not exceed the upper limit of the control current.

45. The power amplifier circuit of claim 44, wherein, the upper limit of the control current is a linear function of the detected voltage. the upper limit of the control current is a linear function of the detected voltage.

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