Imaging Test System, Test Component and Image Acquisition Card

Abstract

The present invention provides an image testing system, comprising: a testing component and an image acquisition card. The testing component is used to obtain a test signal of a device under test, and includes an interface conversion circuit for converting the signal transmission form of the test signal. The image acquisition card is used to obtain the test signal from the testing component and acquire image data from the test signal. Wherein, the image testing system further includes a test signal clock generation circuit for obtaining a test signal clock from the test signal, or the image acquisition card further includes a pair of clock input pins for directly obtaining the test signal clock from the device under test.

Description

Technical Field

[0001] The present invention relates to a test system, a test element thereof, and a data acquisition card, and particularly to an image test system, a test element thereof, and an image acquisition card. Background Art

[0002] The image acquisition card configured with a semiconductor device test device usually has a logic processing unit, which can pre-decode the image signal obtained by an imaging element (such as a camera), and then transmit the decoded image signal to a backend image processing device for processing. Therefore, image testing is a very important part of current semiconductor device test items. In order to meet the demand for ultra-high definition, image signals have gradually been transmitted in the form of C-type physical layer (hereinafter referred to as C-PHY) signals during transmission, and have replaced the original D-type physical layer (hereinafter referred to as D-PHY) signal form. Currently, D-PHY signals are transmitted in a differential manner and have a clock data for the test system to perform timing correction of image data; in contrast, C-PHY signals are not transmitted in a differential manner, and therefore C-PHY signals are only applicable to shorter signal transmission paths (compared with D-PHY signals). In addition, currently, C-PHY signals only have data information and do not have clock information for correction.

[0003] Under the existing image test system architecture, the image acquisition card will obtain C-PHY signals from a test element (such as a prober), and then convert the C-PHY signals into a signal format that can be read by the logic processing unit in the image acquisition card through a data conversion unit. However, due to motherboard layout limitations, sometimes there will be a relatively long signal transmission path between the prober and the data conversion unit. In this case, the C-PHY signals will have more losses and delays due to the long path, and often there will be a problem of jitter due to signal timing offset, which will further affect the accuracy of the test system. Therefore, even if a clock generator is set in the data conversion unit to generate a correction clock (ideal value), its timing may not be able to align with the timing of the delayed C-PHY signals.

[0004] In view of this, the present invention provides an improved image test system, test element, and image acquisition card to solve the above problems. Summary of the Invention

[0005] An object of the present invention is to provide an image testing system, comprising: a testing element and an image acquisition card. The testing element is used to obtain a test signal of a device under test, and includes an interface conversion circuit for converting the signal transmission form of the test signal; the image acquisition card obtains the test signal from the testing element and acquires image data from the test signal. Wherein, the image testing system further includes a test signal clock generation circuit for obtaining a test signal clock from the test signal, or the image acquisition card further includes a pair of clock input pins for directly obtaining the test signal clock from the device under test.

[0006] Another object of the present invention is to provide a testing element disposed in an image testing system including an image acquisition card, wherein the testing element includes a first transmission interface, a test signal clock generation circuit, an interface conversion circuit, and a second transmission interface. The first transmission interface is used to obtain a test signal of a device under test; the test signal clock generation circuit is used to obtain a test signal clock from the test signal and transmit the test signal clock to the image acquisition card; the interface conversion circuit converts the signal transmission form of the test signal; the second transmission interface is used to transmit the test signal to the image acquisition card.

[0007] Yet another object of the present invention is to provide an image acquisition card disposed in an image testing system, and the image testing system includes a testing element for transmitting a test signal to the image acquisition card, wherein the image acquisition card includes a test signal clock generation circuit and a logic processing unit. The test signal clock generation circuit is used to obtain a test signal clock from the test signal; the logic processing unit acquires image data from the test signal according to the test signal clock. Description of the Drawings

[0008] Figure 1 is a schematic diagram of the basic architecture of an image testing system according to an embodiment of the present invention;

[0009] FIG. 2(A) is a schematic diagram of the detailed architecture of a testing element and an image acquisition card according to the first embodiment of the present invention;

[0010] FIG. 2(B) is a schematic diagram of a testing element and an image acquisition card of a comparative example;

[0011] Figure 3 is a schematic diagram of the detailed architecture of a testing element and an image acquisition card according to the second embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of the detailed architecture of a testing element and an image acquisition card according to the third embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of the detailed architecture of a testing element and an image acquisition card according to the fourth embodiment of the present invention;

[0014] FIG. 6(A) is a circuit structure diagram of a test signal clock generation circuit according to an embodiment of the present invention;

[0015] FIG. 6(B) is a timing diagram of sub-signals of a test signal according to an embodiment of the present invention;

[0016] Figure 7 is a schematic diagram of the detailed structure of a test element and an image acquisition card according to the fifth embodiment of the present invention;

[0017] Figure 8 is a schematic diagram of the detailed structure of a test element and an image acquisition card according to the sixth embodiment of the present invention.

[0018] [Symbol description]

[0019] Image test system 1

[0020] Test head 2

[0021] Test element 3

[0022] Image acquisition card 4

[0023] Object under test 7

[0024] Test signal S0

[0025] Image processing element 9

[0026] Probe card 32

[0027] Probe 33

[0028] Light source supply device 6a

[0029] First bridging board 60

[0030] First transmission interface 34

[0031] Interface conversion circuit 36

[0032] Second transmission interface 38

[0033] Test signal clock generation circuit 80

[0034] Clock output pin 41a

[0035] Test signal clock CLK

[0036] Sub-signals S1, S2, S3

[0037] Differential sub-signals S11, S12, S21, S22, S31, S32, S41, S42

[0038] Probe card daughter board 35

[0039] Logic input interface 41

[0040] Logic processing unit 44

[0041] Transmission unit 46

[0042] Data conversion circuit 42

[0043] Clock generator 440

[0044] Preset clock clk0

[0045] First input terminal 81

[0046] First clock acquisition module 82

[0047] Second input terminal 83

[0048] Second clock acquisition module 84

[0049] Third input terminal 85

[0050] Third clock acquisition module 86

[0051] Circuit output terminal 87

[0052] First sub-signal clock clk_s1

[0053] Second sub-signal clock clk_s2

[0054] Third sub-signal clock clk_s3

[0055] First buffer 821

[0056] First delay unit 822

[0057] First exclusive-OR gate 823

[0058] Second buffer 841

[0059] Second delay unit 842

[0060] Second exclusive-OR gate 843

[0061] Third buffer 861

[0062] Third delay unit 862

[0063] Third exclusive-OR gate 863

[0064] First delayed sub-signal S1_L

[0065] Second delayed sub-signal S2_L

[0066] Third delayed sub-signal S3_L

[0067] Periods T1 to T6

[0068] Signal transmission distances L1, L2. Detailed implementation manners

[0069] The following will illustrate the implementation forms and working principles of the image test system and the image acquisition card of the present invention through multiple embodiments. Those skilled in the art can understand the features and effects of the present invention through the above embodiments, and can make combinations, modifications, substitutions or conversions based on the spirit of the present invention.

[0070] The term "connection" referred to herein includes forms such as direct connection or indirect connection, and is not limited. The terms "when..." and "... time" herein mean "at present, before or after", and are not limited.

[0071] The ordinal numbers used herein, such as "first", "second", etc., are used to modify the claimed elements, and do not themselves imply or represent that the claimed elements have any previous ordinal numbers, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0072] Figure 1 is a schematic diagram of the basic architecture of the image test system 1 according to an embodiment of the present invention. As Figure 1 shown, the image test system 1 includes a test head 2, a test element 3, and an image acquisition card 4. The test element 3 can be used to contact a device under test 7, where the device under test 7 can be a wafer or other semiconductor element that needs to be electrically tested. The test head 2 can provide a test program for electrical testing to the test element 3. The test element 3 can obtain a test signal S0 from the device under test 7. The image acquisition card 4 can be used to obtain image data from the test signal S0. For example, if the device under test 7 can be an image sensor, the image acquisition card 4 can obtain the image data captured by the device under test 7 from the test signal S0 and convert the image data into a data format suitable for a subsequent image processing element 9 (such as an external computer). If the device under test 7 is a processing chip of a display, the image acquisition card 4 can also obtain the image data being played on the display from the test signal S0 and convert the image data into a data format suitable for the subsequent image processing element 9 (such as a processor of a computer); the above examples are only for illustration and are not limited.

[0073] The test head 2 can be provided with various interface cards that provide necessary test programs, such as a physical electronics card (PE card), a device power supply card (DPS card), a serial test card (SEQ card), etc., and are not limited thereto.

[0074] The test element 3 can be a probe machine and includes a probe card 32, or the test element 3 itself is the probe card 32, and is not limited thereto. A plurality of probes 33 can be provided on the probe card 32, and the probes 33 can contact the pins of the object under test 7, so that the test head 2 can perform an electrical test on the object under test 7. In addition, the image test system 1 can also include a light source supply device 6a. The light source supply device 6a can be a tubular light source supply device and is provided on the test head 2, but is not limited thereto. In one embodiment, the light source supply device 6a focuses the light source on the object under test 7 (such as an integrated circuit provided with a plurality of image sensors in a wafer) to test the actual reception range of the image sensors of the object under test 7 for comprehensive image detection, and the probe card 32 can obtain a test signal from the image sensors of the object under test, where the test signal is a C-PHY signal. In addition, in one embodiment, the image acquisition card 4 can be an image acquisition card of the Mobile Industry Processor Interface (MIPI) and is connected to the probe card 32 through a first bridge board 60, but is not limited thereto. In addition, the test element 3 can include a first transmission interface 34, an interface conversion circuit 36, and a second transmission interface 38. The first transmission interface 34 can receive the test signal S0 obtained by the probes 33, the interface conversion circuit 36 can be connected to the first transmission interface 34, the second transmission interface 38 can be connected to the interface conversion circuit 36, and the signal acquisition card 4 can be connected to the second transmission interface 38 and obtain the test signal from the second transmission interface 38. Among them, the first transmission interface 34 and the second transmission interface 38 correspond to different signal transmission forms, and the interface conversion circuit 36 can be used to convert the signal transmission form of the test signal.

[0075] One of the inventive points of the present invention lies in the improvement of the test element 3 or the image acquisition card 4: In one embodiment, the image test system 1 further includes a test signal clock generation circuit 80 for obtaining a test signal clock CLK (marked in FIG. 2(A)) from the test signal S0, where the test signal clock generation circuit 80 can be provided in the test element 3 or the image acquisition card 4; or, in another embodiment, the image acquisition card 4 can include a pair of clock output pins 41a for directly obtaining the test signal clock CLK from the object under test 7.

[0076] To highlight the effects of the present invention, an embodiment of the present invention will be compared with a comparative example below.

[0077] First, the embodiment of this case will be described. FIG. 2(A) is a schematic diagram of the detailed structure of the test element 3 and the image acquisition card 4 according to the first embodiment of the present invention, where the test signal clock generation circuit 80 is provided in the test element 3.

[0078] As shown in FIG. 2(A), the first transmission interface 34 is used to obtain the test signal S0 from the device under test 7 end and transmit the test signal S0 to the test signal clock generation circuit 80, where the test signal S0 is transmitted in a first signal transmission form; in an embodiment, the first transmission interface 34 may be a C-type physical layer interface (MIPI C-PHY interface) of a mobile industry processor interface and includes a three-wire serial signal channel. Therefore, the test signal S0 can be divided into 3 sub-signals S1, S2, S3 (hereinafter referred to as the first sub-signal S1, the second sub-signal S2, and the third sub-signal S3) for transmission. The test signal clock generation circuit 80 is used to transmit the test signal S0 (i.e., S1, S2, S3) to the interface conversion circuit 36 and to obtain the test signal clock CLK from the test signal S0. The interface conversion circuit 36 can convert the test signal S0 from the first signal transmission form to a second signal transmission form and transmit the test signal S0 (i.e., S1, S2, S3) to the second transmission interface 38. In addition, the interface conversion circuit 36 can also convert the test signal clock CLK to the second signal transmission form and transmit the test signal clock CLK to the second transmission interface 38; in an embodiment, the second transmission interface 38 may be a high-speed logic interface and includes multiple pairs of high-speed logic signal channels, where each pair of high-speed logic signal channels may be differential logic signal channels.

[0079] Therefore, the first sub-signal S1 is transmitted in the form of a pair of differential sub-signals S11, S12, the second sub-signal S2 is transmitted in the form of a pair of differential sub-signals S21, S22, the third sub-signal S3 is transmitted in the form of a pair of differential sub-signals S31, S32, and the test signal clock CLK is also transmitted in the form of a pair of differential sub-signals S41, S42.

[0080] It should be noted that the test signal clock CLK is directly obtained from the test signal S0 and then transmitted to the image acquisition card 4 through the same transmission path. Therefore, the timing of the test signal clock CLK can substantially correspond to the timing of the test signal S0. Here, "substantially" allows for slight differences, such as the difference being less than 5%, less than 3%, or less than 1%, and is not limited thereto.

[0081] In an embodiment, the test element 3 may include a probe card daughter board 35, and the test signal clock generation circuit 80 and the interface conversion circuit 36 may be disposed on the probe card daughter board 35, but it is not limited. One of the beneficial effects of providing the probe card daughter board 35 is that it can make the configuration of each component on the test element 3 more flexible.

[0082] In addition, the image acquisition card 4 may include a logic input interface 41, a logic processing unit 44, and a transmission unit 46. The logic input interface 41 includes a plurality of pins and a data conversion circuit 42. Some of the pins are used to receive the test signals S0 (S11 to S32) and the test signal clock CLK (S41, S42) from the test element 3. The data conversion circuit 42 is used to convert the test signals S0 and the test signal clock CLK in the second signal transmission form into a data format that can be read by the logic processing unit 44. In an embodiment, if the logic processing unit 44 can read the data format in the second signal transmission form, the test signals S0 and the test signal clock CLK may not need to be converted. For the convenience of description, the subsequent paragraphs will take the example of the test signal clock CLK being input to the logic processing unit 44 in the second signal transmission form (differential) (the test signal S0 is directly shown as a single signal, but in fact the test signal S0 can be various signal transmission types). The logic processing unit 44 can obtain the image data from the test signal S0 according to the test signals S0 and the test signal clock CLK. The image data can be transmitted to the image processing element 9 at the back end (such as an external computer) through the transmission unit 46. In an embodiment, the transmission unit 46 may be, for example, a fiber optic interface, but is not limited thereto.

[0083] In this embodiment, the image acquisition card 4 may be provided with an additional pair of clock input pins 41a for receiving the test signal clock CLK (S41, S42) from the test element 3. Also in this embodiment, the logic processing unit 44 is a field programmable gate array (FPGA) chip. Its existing architecture already has enough pins to receive the test signals S0 and the test signal clock CLK (S41, S42). Therefore, the logic processing unit 44 does not need to add additional pins.

[0084] Next, the comparative example will be described. FIG. 2(B) is a schematic diagram of the test element 3 and the image acquisition card 4 of a comparative example. This comparative example has a structure substantially the same as that of the embodiment in FIG. 2(A), but it does not have the test signal clock generation circuit 80, and its image acquisition card 4 is provided with a clock generator 440.

[0085] As shown in FIG. 2(B), since the test component 3 does not have a test signal clock generation circuit 80, the test component 3 only transmits the test signal S0 to the image acquisition card 4, and the logic processing unit 44 must generate a preset clock clk0 of the test signal S0 through the clock generator 440 to obtain the image data. However, the preset clock clk0 generated by the clock generator 440 is a preset value and cannot correspond to the delay that occurs in the transmission path of the test signal S0. Therefore, there may still be a phase difference in the timing between the clock clk0 and the test signal S0, which may cause signal jitter in the image data obtained by the logic processing unit 44, limit the effective signal bandwidth, and thus reduce the quality of the image data. To repair this problem, the logic processing unit 44 must add more processing components and use more complex algorithms, which will increase the cost.

[0086] In contrast, in the present invention, the test signal clock generation circuit 80 directly obtains the test signal clock CLK from the test signal S0. Therefore, even if the test signal S0 is delayed, the obtained test signal clock CLK will also be delayed accordingly. Therefore, the test signal clock CLK can correspond to the timing state of the test signal S0, which can greatly reduce the problem of phase difference and improve the quality of the image data.

[0087] The present invention can also have different embodiments. Figure 3 FIG. 3 is a schematic diagram of the detailed architecture of the test component 3 and the image acquisition card 4 according to the second embodiment of the present invention. Please also refer to Figure 1 FIG. 2(A). Figure 3 The embodiment is substantially the same as the embodiment of FIG. 2(A), except that the test signal clock generation circuit 80 is disposed in the image acquisition card 4.

[0088] As Figure 3As shown, the test signal clock generation circuit 80 is disposed on the logic input interface 41. In one embodiment, the test component 3 transmits the test signal S0 (S11 and S12, S21 and S22, S31 and S32) in the second signal transmission form to the logic input interface 41. The data conversion circuit 42 can convert the test signal S0 in the second signal transmission form into a data format that the logic processing unit 44 can read, and transmit the converted test signal S0 to the logic processing unit 44. Also, the data conversion circuit 42 can convert the test signal S0 in the second signal transmission form into the first signal transmission form and transmit it to the test signal clock generation circuit 80, so that the test signal clock generation circuit 80 obtains the test signal clock CLK from the test signal S0 and transmits it to the logic processing unit 44 (the data conversion circuit 42 transmits the test signal S0 to the logic processing unit 44). In another embodiment, the data conversion circuit 42 can first convert the test signal S0 in the second signal transmission form into the first signal transmission form and transmit it to the test signal clock generation circuit 80. The test signal clock generation circuit 80 then transmits the obtained test signal clock CLK and the test signal S0 to the logic processing unit 44 (the signal clock generation circuit 80 transmits the test signal S0 to the logic processing unit 44). After that, the logic processing unit 44 decodes the test signal S0 according to the test signal S0 and the test signal clock CLK to obtain the image data. Since the test signal clock CLK is obtained from the test signal S0, their timings can correspond to each other, and good-quality image data can be provided.

[0089] In this embodiment, the logic processing unit 44 is a field programmable gate array chip (FPGA). Its existing architecture already has enough pins to receive the test signal S0 and the test signal clock CLK. Therefore, the logic processing unit 44 does not need to add extra pins.

[0090] The present invention can also have different embodiments. Figure 4 is a schematic diagram of the detailed architecture of the test component 3 and the image acquisition card 4 in the third embodiment of the present invention. Please also refer to Figure 1 and FIG. 2(A).

[0091] Figure 4 The embodiment is substantially the same as the embodiment of FIG. 2(A), except that the logic processing unit 44 is a customized adjustment chip (such as an application specific integrated circuit (ASIC)). Since the logic processing unit 44 in this embodiment is an application specific integrated circuit chip (ASIC), it can add extra input pins 44a (such as adding an extra pair of pins) for receiving the test signal clock CLK from the data conversion circuit 42.

[0092] The present invention has different embodiments. Figure 5 It is a schematic diagram of the detailed structure of the test element 3 and the image acquisition card 4 in the fourth embodiment of the present invention. Please also refer to Figures 1 to 4 .

[0093] Figure 5 The embodiment is substantially the same as Figure 3 the embodiment, except that the logic processing unit 44 is a customized adjustment chip (such as an application-specific integrated circuit (ASIC)). Since the logic processing unit 44 in this embodiment is an application-specific integrated circuit chip (ASIC), it can add additional input pins 44a (such as adding an additional pair of pins) for receiving the test signal clock CLK from the test signal clock generation circuit 80.

[0094] In addition, to make the present invention clearer, the details of the test signal clock generation circuit 80 will be described next. FIG. 6(A) is a circuit structure diagram of the test signal clock generation circuit 80 in an embodiment of the present invention, and FIG. 6(B) is a timing diagram of the sub-signals of the test signal S0 in an embodiment of the present invention. Please refer to Figures 1 to 5 for assistance.

[0095] As shown in FIG. 6(A), the test signal clock generation circuit 80 includes a first input terminal 81, a first clock acquisition module 82, a second input terminal 83, a second clock acquisition module 84, a third input terminal 85, a third clock acquisition module 86, and a circuit output terminal 87. The first input terminal 81 is connected to the first clock acquisition module 82, the second input terminal 83 is connected to the second clock acquisition module 84, the third input terminal 85 is connected to the third clock acquisition module 86, and the first clock acquisition module 82, the second clock acquisition module 84, and the third clock acquisition module 86 are each connected to the circuit output terminal 87.

[0096] The first input terminal 81 is used to obtain a first sub-signal S1 of the test signal S0 (the first signal transmission form). The first clock acquisition module 82 is used to obtain a first sub-signal clock clk_s1 from the first sub-signal S1 and transmit the first sub-signal clock clk_s1 to the circuit output terminal 87. The second input terminal 83 is used to obtain a second sub-signal S2 of the test signal S0. The second clock acquisition module 84 is used to obtain a second sub-signal clock clk_s2 from the second sub-signal S2 and transmit the second sub-signal clock clk_s2 to the circuit output terminal 87. The third input terminal 85 is used to obtain a third sub-signal S3 of the test signal S0. The third clock acquisition module 86 is used to obtain a third sub-signal clock clk_s3 from the third sub-signal S3 and transmit the third sub-signal clock clk_s3 to the circuit output terminal 87. The circuit output terminal 87 is used to integrate the first sub-signal clock clk_s1, the second sub-signal clock clk_s2, and the third sub-signal clock clk_s3 into the test signal clock CLK.

[0097] In one embodiment, the first clock acquisition module 82 includes a first buffer 821, a first delay unit 822, and a first exclusive OR gate (XOR) 823. The first buffer 821 includes at least two output terminals, which are respectively connected to the first exclusive OR gate 823 and the first delay unit 822. The first exclusive OR gate 823 has two input terminals, one of which is connected to the first buffer 821 and the other is connected to the first delay unit 822. The first exclusive OR gate 823 has an output terminal, which is connected to the circuit output terminal 87.

[0098] Further, the first buffer 821 obtains the first sub-signal S1 from the first input terminal 81 and transmits the first sub-signal S1 to the first delay unit 822 and the first exclusive OR gate 823. The first delay unit 822 converts the first sub-signal S1 into a first delayed sub-signal S1_L and transmits the first delayed sub-signal S1_L to the first exclusive OR gate 823. The first exclusive OR gate 823 performs an exclusive OR operation on the first sub-signal S1 and the first delayed sub-signal S1_L to generate the first sub-signal clock clk_s1. In one embodiment, the delay of the first delay unit 822 for the first delayed sub-signal S1_L can be preset by the user. In one embodiment, the first delayed sub-signal S1_L is delayed by at least 1 / 4 cycle compared to the first sub-signal S1; in one embodiment, the first delayed sub-signal S1_L is delayed by at least 1 / 2 cycle compared to the first sub-signal S1, but it is not limited.

[0099] In one embodiment, the second clock acquisition module 84 includes a second buffer 841, a second delay unit 842, and a second exclusive-OR gate 843. The second buffer 841 includes at least two output terminals, which are respectively connected to the second exclusive-OR gate 843 and the second delay unit 842. The second exclusive-OR gate 843 has two input terminals, one of which is connected to the second buffer 841, and the other is connected to the second delay unit 842. The output terminal of the second exclusive-OR gate 843 is connected to the circuit output terminal 87.

[0100] Further, the second buffer 841 obtains the second sub-signal S2 from the second input terminal 83, and transmits the second sub-signal S2 to the second delay unit 842 and the second exclusive-OR gate 843. The second delay unit 842 converts the second sub-signal S2 into a second delayed sub-signal S2_L, and transmits the second delayed sub-signal S2_L to the second exclusive-OR gate 843. The second exclusive-OR gate 843 performs an exclusive-OR operation on the second sub-signal S2 and the second delayed sub-signal S2_L to generate the second sub-signal clock clk_s2. In one embodiment, the delay of the second delayed sub-signal S2_L by the second delay unit 842 can be preset by the user. In one embodiment, the second delayed sub-signal S2_L is delayed by at least 1 / 4 cycle compared to the second sub-signal S2; in one embodiment, the second delayed sub-signal S2_L is delayed by at least 1 / 2 cycle compared to the second sub-signal S2, but it is not limited.

[0101] In one embodiment, the third clock acquisition module 86 includes a third buffer 861, a third delay unit 862, and a third exclusive-OR gate 863. The third buffer 861 includes at least two output terminals, which are respectively connected to the third exclusive-OR gate 863 and the third delay unit 862. The third exclusive-OR gate 863 has two input terminals, one of which is connected to the third buffer 861, and the other is connected to the third delay unit 862. The output terminal of the third exclusive-OR gate 863 is connected to the circuit output terminal 87.

[0102] Further, the third buffer 861 receives the third sub-signal S3 from the third input terminal 85, and transmits the third sub-signal S3 to the third delay unit 862 and the third exclusive-OR gate 863. The third delay unit 862 converts the third sub-signal S3 into a third delayed sub-signal S3_L, and transmits the third delayed sub-signal S3_L to the third exclusive-OR gate 863. The third exclusive-OR gate 863 performs an exclusive-OR operation on the third sub-signal S3 and the third delayed sub-signal S3_L to generate the third sub-signal clock clk_s3. In one embodiment, the delay of the third delay unit 862 for the third delayed sub-signal S3_L can be preset by the user. In one embodiment, the third delayed sub-signal S3_L is delayed by at least 1 / 4 cycle compared to the third sub-signal S3; in one embodiment, the third delayed sub-signal S3_L is delayed by at least 1 / 2 cycle compared to the third sub-signal S3, but is not limited thereto.

[0103] In one embodiment, the circuit output terminal 87 can be an OR gate, which is used to perform an OR operation on the first sub-signal clock clk_s1, the second sub-signal clock clk_s2, and the third sub-signal clock clk_s3.

[0104] In one embodiment, the first delay unit 822, the second delay unit 842, and the third delay unit 862 can be implemented by an electronic circuit having a signal delay function, and are not limited thereto.

[0105] In one embodiment, when it is necessary to output the test signal S0 through the test signal clock generation circuit 80, the first buffer 821, the second buffer 841, and the third buffer 861 can each additionally have an output terminal to output the first sub-signal S1, the second sub-signal S2, and the third sub-signal S3.

[0106] The details of the generation process of the test signal clock CLK are described below with reference to FIG. 6(B).

[0107] As shown in FIG. 6(B), the first sub-signal S1 of the test signal S0 has a high potential (i.e., has valid data) during the first period T1, and the first sub-signal S1 forms a first delayed sub-signal S1_L after being delayed by the first delay unit 842. The timing of the first delayed sub-signal S1_L is delayed by half a cycle compared to the timing of the first sub-signal S1. Therefore, when the first sub-signal S1 and the first delayed sub-signal S1_L perform an exclusive-OR operation through the first exclusive-OR gate 823 to generate the first sub-signal clock clk_s1, the first sub-signal clock clk_s1 can have a high potential corresponding to the first half of the first period T1, and is low potential corresponding to the second half of the first period T1 (the timing situation of the fourth period T4 can be deduced similarly). Therefore, the acquisition process of the first sub-signal clock clk_s1 can be known.

[0108] Similarly, the second sub-signal S2 of the test signal S0 has a high potential during the second period T2, and the second sub-signal S2 forms a second delayed sub-signal S2_L after being delayed by the second delay unit 842. The timing of the second delayed sub-signal S2_L is delayed by half a cycle compared to the timing of the second sub-signal S2. Therefore, when the second sub-signal S2 and the second delayed sub-signal S2_L perform an exclusive OR operation, the second sub-signal clock clk_s2 can have a high potential during the first half of the second period T2, and a low potential during the second half of the second period T2 (the timing situation of the fifth period T5 can be deduced similarly). Therefore, the acquisition process of the second sub-signal clock clk_s2 can be understood.

[0109] The acquisition process of the third sub-signal clock clk_s3 can be deduced from the acquisition processes of the aforementioned first sub-signal clock clk_s1 and second sub-signal clock clk_s2, so it will not be elaborated here.

[0110] When the first sub-signal clock clk_s1, the second sub-signal clock clk_s2, and the third sub-signal clock clk_s3 perform an OR operation through the circuit output terminal 87, they can be integrated into the test signal clock CLK. Therefore, the formation of the test signal clock CLK and the operation of the test signal clock generation circuit 80 can be understood.

[0111] Next, other embodiments of the present invention will be described. When the test object 7 can provide the test signal clock CLK by itself, the present invention may not have the test signal clock generation circuit 80. Figure 7 is a schematic diagram of the detailed structure of the test element 3 and the image acquisition card 4 according to the fifth embodiment of the present invention, and please refer to Figures 1 to 6(B) .

[0112] As Figure 7 shown, neither the test element 3 nor the image acquisition card 4 has the test signal clock generation circuit 80, and the image acquisition card 4 has an additional pair of clock input pins 41a. The clock output pin 41a is electrically connected to the test object 7 and is used to receive the test signal clock CLK from the test object 7. It should be noted that the test object 7 terminal in this embodiment must be able to provide the test signal clock CLK itself. In other words, the test object 7 terminal can have an additional pair of differential output terminals for outputting the test signal clock CLK (S41, S42) to the image acquisition card 4.

[0113] In this embodiment, the logic processing unit 44 is a field programmable gate array chip (FPGA), and its existing architecture has enough pins to receive the test signal S0 and the test signal clock CLK. Therefore, the logic processing unit 44 does not need to add additional pins.

[0114] Again, as Figure 7 shown, sinceFigure 7 It can be regarded as an equivalent schematic diagram configured between components. When testing a signal clock CLK, the signal transmission distance from the device under test 7 to the image acquisition card 4 (for example Figure 7 L1 in) is substantially equal (or approximate) to the signal transmission distance of the test signal S0 from the device under test 7, the test component 3 to the image acquisition card 4 (for example Figure 7 L2 in), so the delay situations that occur during the transmission of the test signal S0 and the test signal clock CLK will also be approximate. Therefore, when the logic processing unit 44 processes the test signal S0 and the test signal clock CLK, the phase difference between the two can be relatively small. Therefore, the image data obtained from the test signal S0 can have good quality.

[0115] In one embodiment, "substantially equal transmission distances" means that the difference between the two transmission distances is within 20%. In one embodiment, "substantially equal transmission distances" means that the difference between the two transmission distances is within 10%. In one embodiment, "substantially equal transmission distances" means that the difference between the two transmission distances is within 5%. The present invention is not limited thereto.

[0116] Figure 8 It is a detailed architecture schematic diagram of the test component 3 and the image acquisition card 4 of the sixth embodiment of the present invention. Please also refer to Figures 1 to 7 .

[0117] Figure 8 The embodiment is substantially similar to Figure 7 the embodiment, and the difference lies in Figure 8 the logic processing unit 44 of the embodiment is an application-specific integrated circuit (ASIC). Since the logic processing unit 44 is an application-specific integrated circuit (ASIC), it has an additional pair of input pins for receiving the test signal clock CLK.

[0118] and Figure 7 the embodiment are similar. The transmission distance of the test signal S0 in the architecture of this embodiment is substantially equal to the transmission distance of the test signal clock CLK. Therefore, the image data obtained from the test signal S0 can also have good quality.

[0119] The above configuration methods are only examples. There are still more configuration methods between the test component 3 and the image acquisition card 4 of the present invention.

[0120] Therefore, the present invention provides an improved image test system, test component and image acquisition card, which can reduce the phase difference between the test signal and the test signal clock, thereby solving the problem of limited signal bandwidth, and can reduce cost expenditure and improve the quality of image data.

[0121] The above embodiments are only examples for convenience of description. The scope of protection claimed by the present invention shall be subject to the scope of protection claimed in the claims, rather than being limited to the above embodiments.

Claims

1. An image testing system, comprising: A test element for obtaining a test signal of a device under test, and the test element includes an interface conversion circuit for converting the signal transmission form of the test signal; An image acquisition card for obtaining the test signal from the test element and obtaining an image data from the test signal; and Wherein, The image test system further includes a test signal clock generation circuit for obtaining a test signal clock from the test signal, or the image acquisition card further includes a pair of clock input pins for directly obtaining the test signal clock from the device under test; Wherein, the test signal clock generation circuit is disposed in the test element or the image acquisition card; wherein, the test signal includes a first sub-signal, a second sub-signal and a third sub-signal, and the test signal clock generation circuit includes a first input terminal, a first clock acquisition module, a second input terminal, a second clock acquisition module, a third input terminal, a third clock acquisition module and a circuit output terminal. The first input terminal is used for obtaining the first sub-signal, the first clock acquisition module is used for obtaining a first sub-signal clock from the first sub-signal and transmitting the first sub-signal clock to the circuit output terminal, the second input terminal is used for obtaining the second sub-signal, the second clock acquisition module is used for obtaining a second sub-signal clock from the second sub-signal and transmitting the second sub-signal clock to the circuit output terminal, the third input terminal is used for obtaining the third sub-signal, the third clock acquisition module is used for obtaining a third sub-signal clock from the third sub-signal and transmitting the third sub-signal clock to the circuit output terminal, and the circuit output terminal integrates the first sub-signal clock, the second sub-signal clock and the third sub-signal clock into the test signal clock.

2. The image testing system according to claim 1, wherein, The circuit output terminal is an OR gate.

3. The image testing system according to claim 2, wherein, The first clock acquisition module includes a first buffer, a first delay unit and a first exclusive OR gate. The first buffer obtains the first sub-signal from the first input terminal and transmits the first sub-signal to the first delay unit and the first exclusive OR gate. The first delay unit converts the first sub-signal into a first delayed sub-signal and transmits the first delayed sub-signal to the first exclusive OR gate. The first exclusive OR gate performs an exclusive OR operation on the first sub-signal and the first delayed sub-signal to form the first sub-signal clock.

4. The image testing system according to claim 3, wherein, The second clock acquisition module includes a second buffer, a second delay unit, and a second exclusive-OR gate. The third clock acquisition module includes a third buffer, a third delay unit, and a third exclusive-OR gate. The second buffer acquires the second sub-signal from the second input terminal and transmits the second sub-signal to the second delay unit and the second exclusive-OR gate. The second delay unit converts the second sub-signal into a second delayed sub-signal and transmits the second delayed sub-signal to the second exclusive-OR gate. The second exclusive-OR gate performs an exclusive-OR operation on the second sub-signal and the second delayed sub-signal to form the second sub-signal clock. The third buffer acquires the third sub-signal from the third input terminal and transmits the third sub-signal to the third delay unit and the third exclusive-OR gate. The third delay unit converts the third sub-signal into a third delayed sub-signal and transmits the third delayed sub-signal to the third exclusive-OR gate. The third exclusive-OR gate performs an exclusive-OR operation on the third sub-signal and the third delayed sub-signal to form the third sub-signal clock.

5. The image testing system according to claim 4, wherein, When the test signal clock generation circuit is disposed in the test element, the first buffer further transmits the first sub-signal to the image acquisition card, the second buffer further transmits the second sub-signal to the image acquisition card, and the third buffer further transmits the third sub-signal to the image acquisition card.

6. The image testing system according to claim 1, wherein, When the image acquisition card includes the pair of clock input pins and directly obtains the test signal clock from the device under test, a signal transmission distance of the test signal from the device under test to the image acquisition card is equal to a signal transmission distance of the test signal from the device under test, the test element to the image acquisition card.

7. A test element, disposed in an image testing system, the image testing system further comprising an image acquisition card, wherein the test element comprises: A first transmission interface for acquiring a test signal of a device under test; A test signal clock generation circuit for obtaining a test signal clock from the test signal and transmitting the test signal clock to the image acquisition card; An interface conversion circuit for converting a signal transmission form of the test signal; and A second transmission interface for transmitting the test signal to the image acquisition card; Wherein, the test signal includes a first sub-signal, a second sub-signal, and a third sub-signal. The test signal clock generation circuit includes a first input terminal, a first clock acquisition module, a second input terminal, a second clock acquisition module, a third input terminal, a third clock acquisition module, and a circuit output terminal. The first input terminal is used to acquire the first sub-signal. The first clock acquisition module is used to acquire a first sub-signal clock from the first sub-signal and transmit the first sub-signal clock to the circuit output terminal. The second input terminal is used to acquire the second sub-signal. The second clock acquisition module is used to acquire a second sub-signal clock from the second sub-signal and transmit the second sub-signal clock to the circuit output terminal. The third input terminal is used to acquire the third sub-signal. The third clock acquisition module is used to acquire a third sub-signal clock from the third sub-signal and transmit the third sub-signal clock to the circuit output terminal. The circuit output terminal integrates the first sub-signal clock, the second sub-signal clock, and the third sub-signal clock into the test signal clock.

8. The test element according to claim 7, wherein, The circuit output terminal is an OR gate.

9. The test element according to claim 8, wherein, The first clock acquisition module includes a first buffer, a first delay unit, and a first exclusive-OR gate. The first buffer acquires the first sub-signal from the first input terminal and transmits the first sub-signal to the first delay unit and the first exclusive-OR gate. The first delay unit converts the first sub-signal into a first delayed sub-signal and transmits the first delayed sub-signal to the first exclusive-OR gate. The first exclusive-OR gate performs an exclusive-OR operation on the first sub-signal and the first delayed sub-signal to form the first sub-signal clock.

10. The test element according to claim 9, wherein, The second clock acquisition module includes a second buffer, a second delay unit, and a second exclusive-OR gate. The second buffer acquires the second sub-signal from the second input terminal and transmits the second sub-signal to the second delay unit and the second exclusive-OR gate. The second delay unit converts the second sub-signal into a second delayed sub-signal and transmits the second delayed sub-signal to the second exclusive-OR gate. The second exclusive-OR gate performs an exclusive-OR operation on the second sub-signal and the second delayed sub-signal to form the second sub-signal clock.

11. The test element according to claim 10, wherein, The third clock acquisition module includes a third buffer, a third delay unit, and a third exclusive-OR gate. The third buffer acquires the third sub-signal from the third input terminal and transmits the third sub-signal to the third delay unit and the third exclusive-OR gate. The third delay unit converts the third sub-signal into a third delayed sub-signal and transmits the third delayed sub-signal to the third exclusive-OR gate. The third exclusive-OR gate performs an exclusive-OR operation on the third sub-signal and the third delayed sub-signal to form the third sub-signal clock.

12. An image acquisition card, disposed in an image testing system, the image testing system further comprising a test element, for obtaining a test signal of a test object, and the test element comprises an interface conversion circuit for converting the signal transmission form of the test signal, wherein the image acquisition card comprises: A test signal clock generation circuit, configured to receive the test signal from a test element and obtain a test signal clock from the test signal; and a logic processing unit, configured to obtain an image data from the test signal according to the test signal clock; Among them, the test signal includes a first sub-signal, a second sub-signal, and a third sub-signal. The test signal clock generation circuit includes a first input terminal, a first clock acquisition module, a second input terminal, a second clock acquisition module, a third input terminal, a third clock acquisition module, and a circuit output terminal. The first input terminal is used to acquire the first sub-signal. The first clock acquisition module is used to acquire a first sub-signal clock from the first sub-signal and transmit the first sub-signal clock to the circuit output terminal. The second input terminal is used to acquire the second sub-signal. The second clock acquisition module is used to acquire a second sub-signal clock from the second sub-signal and transmit the second sub-signal clock to the circuit output terminal. The third input terminal is used to acquire the third sub-signal. The third clock acquisition module is used to acquire a third sub-signal clock from the third sub-signal and transmit the third sub-signal clock to the circuit output terminal. The circuit output terminal integrates the first sub-signal clock, the second sub-signal clock, and the third sub-signal clock into the test signal clock.

13. The image acquisition card according to claim 12, wherein, The circuit output terminal is an OR gate.

14. The image acquisition card according to claim 13, wherein, The first clock acquisition module includes a first buffer, a first delay unit, and a first exclusive-OR gate. The first buffer acquires the first sub-signal from the first input terminal and transmits the first sub-signal to the first delay unit and the first exclusive-OR gate. The first delay unit converts the first sub-signal into a first delayed sub-signal and transmits the first delayed sub-signal to the first exclusive-OR gate. The first exclusive-OR gate performs an exclusive-OR operation on the first sub-signal and the first delayed sub-signal to output the first sub-signal clock.

15. The image acquisition card according to claim 14, wherein, The second clock acquisition module includes a second buffer, a second delay unit, and a second exclusive-OR gate. The second buffer acquires the second sub-signal from the second input terminal and transmits the second sub-signal to the second delay unit and the second exclusive-OR gate. The second delay unit converts the second sub-signal into a second delayed sub-signal and transmits the second delayed sub-signal to the second exclusive-OR gate. The second exclusive-OR gate performs an exclusive-OR operation on the second sub-signal and the second delayed sub-signal to output the second sub-signal clock.

16. The image acquisition card according to claim 15, wherein, The third clock acquisition module includes a third buffer, a third delay unit, and a third exclusive-OR gate. The third buffer acquires the third sub-signal from the third input terminal and transmits the third sub-signal to the third delay unit and the third exclusive-OR gate. The third delay unit converts the third sub-signal into a third delayed sub-signal and transmits the third delayed sub-signal to the third exclusive-OR gate. The third exclusive-OR gate performs an exclusive-OR operation on the third sub-signal and the third delayed sub-signal to output the third sub-signal clock.

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