Memory device with a plane

Abstract

The present disclosure relates to a memory device having planes. The present technology includes a memory device comprising: a plurality of planes in which data is stored; peripheral circuits configured to perform operations on the plurality of planes; microcontroller circuits configured to control the peripheral circuits so that operations on the plurality of planes are independently performed; and a memory manager including a control memory storing therein different control codes for controlling the peripheral circuits and configured to output the control codes to the microcontroller circuits, wherein the memory manager is configured to sequentially output selected control codes from among the control codes to the microcontroller circuits respectively corresponding to the planes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0170766, filed on December 8, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to memory devices, and more particularly, to memory devices including control memories. Background Art

[0004] The memory device may include a volatile memory device in which stored data is destroyed when power is cut off, and may include a nonvolatile memory device in which stored data is retained even if power is cut off.

[0005] Volatile memory devices may include dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory devices may include read-only memory (ROM), programmable read-only memory (PROM), erasable programm ...

[0006] A memory device may include a memory cell array, peripheral circuits, and control circuits.

[0007] The memory cell array may include a plurality of memory cells, and the plurality of memory cells may store data. A method of storing one bit of data in one memory cell is called a single-level cell (SLC) method, and a method of storing two or more bits of data in one memory cell is called a multi-level cell (MLC) method. Depending on the number of bits stored in the memory cell, the programming operation of the MLC method may be classified as a three-level cell (TLC) method or a four-level cell (QLC) method. In the TLC method, three bits of data may be stored in one memory cell, and in the QLC method, four bits of data may be stored in one memory cell.

[0008] The peripheral circuits may include a plurality of circuits capable of performing program, read, or erase operations.

[0009] The control circuit may include a control memory for storing a control code for controlling the peripheral circuit, and may be configured to control the peripheral circuit using the control code selected according to the command. Summary of the Invention

[0010] One embodiment of the present disclosure provides a memory device capable of reducing the size of a control memory storing control codes therein.

[0011] According to one embodiment of the present disclosure, a memory device includes: multiple planes in which data is stored; peripheral circuits configured to perform operations on the multiple planes; micro-control circuits configured to control the peripheral circuits so that operations on the multiple planes are performed independently; and a memory manager including a control memory in which different control codes for controlling the peripheral circuits are stored, and configured to output the control codes to the micro-control circuits, wherein the memory manager is configured to: sequentially output selected control codes among the control codes to the micro-control circuits respectively corresponding to the planes.

[0012] According to one embodiment of the present disclosure, a memory device includes: a control memory, including first to Nth memory groups storing different control codes therein; first to Nth sub-latch groups, respectively connected to the first to Nth memory groups, and configured to sequentially store the control codes stored in the first to Nth memory groups, respectively; and first to Nth plane multiplexers, configured to: jointly receive the control codes from the first to Nth sub-latch groups, and output the received control codes to a selected micro-control circuit among the first to Nth micro-control circuits.

[0013] According to an embodiment of the present disclosure, a memory device includes: a memory cell array divided into a number N of groups, the number N of groups being configured to store different control codes, the groups sequentially outputting corresponding control codes one by one at each interval; a number N of latch circuits, the number N of latch circuits each being configured to latch a control code output from a corresponding one of the groups; a number N of multiplexers being activated sequentially at the interval and each being configured to: provide, at the interval, the control code latched in the latch circuit at the interval, thereby sequentially providing, through the interval, the control code sequentially output from the memory cell array; and a number N of control circuits each being configured to: control a corresponding one of the number N storage circuits by providing a control code to the corresponding storage circuit at the interval to perform a plane interleaving operation, the control code being provided from a corresponding one of the multiplexers.

[0014] According to one embodiment of the present disclosure, a memory device includes: a number N of control circuits configured to control the memory circuits to perform plane interleaving operations by providing a control code to the number N of memory circuits at each interval; a memory cell array configured to output one control code among different control codes stored therein at the interval; and a management circuit configured to provide the control code output from the memory cell array to one of the control circuits at the interval, thereby providing each of the control codes output from the memory cell array in sequence to the control circuits in sequence through the intervals.

[0015] The present technology can perform interleaving on multiple planes and can reduce the size of a memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0017] Figure 2 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0018] Figure 3 is a diagram illustrating a multi-plane structure according to one embodiment of the present disclosure.

[0019] Figure 4 is a diagram illustrating a memory block according to one embodiment of the present disclosure.

[0020] Figure 5 is a diagram illustrating threshold voltage distribution of memory cells according to one embodiment of the present disclosure.

[0021] Figure 6 is a diagram illustrating a memory manager according to one embodiment of the present disclosure.

[0022] Figure 7 is a diagram illustrating a control memory according to one embodiment of the present disclosure.

[0023] Figures 8A to 8E is a diagram illustrating a method of outputting a control code for performing a read operation of a selected plane according to one embodiment of the present disclosure.

[0024] Figures 9A to 9E is a diagram illustrating a method of outputting a control code for sequentially performing a read operation of a plurality of planes according to one embodiment of the present disclosure.

[0025] Figure 10 is a diagram illustrating a plane interleaving operation according to one embodiment of the present disclosure.

[0026] Figure 11 is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0027] Figure 12 is a diagram illustrating a solid-state drive (SSD) system to which a memory device according to one embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0028] Various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. However, it is noted that the present invention can be implemented in different forms and variations and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete and will fully convey the present invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

[0029] Figure 1 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0030] refer to Figure 1 , the memory system 1000 may include a memory device 1100 and a controller 1200 .

[0031] The host 1500 may generate request RQs for various operations and may output the generated request RQs to the memory system 1000. For example, the request RQs may include a program request that may control a program operation, a read request that may control a read operation, an erase request that may control an erase operation, and the like.

[0032] The host 1500 can communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced MiniDisk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0033] The controller 1200 can communicate between the host 1500 and the memory device MD. The controller 1200 can generate a command CMD for controlling the memory device MD based on a request RQ from the host 1500, and even if a request RQ from the host 1500 is not present, the controller 1200 can perform background operations to improve the performance of the system 1000. During a read operation, the controller 1200 can receive a logical address from the host 1500 and output a physical address mapped to the logical address to the memory device 1100. The physical address is the address of an area in the memory device 1100 where data is stored.

[0034] The memory device 1100 may include a plurality of memory devices MD, and the memory devices MD may be connected to the controller 1200 through channels. The memory devices MD may perform a program operation, a read operation, an erase operation, etc. in response to a command CMD received through the channel.

[0035] Figure 2 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0036] refer to Figure 2 The memory device MD may include a memory cell array 110 in which data is stored, a peripheral circuit 200 that performs a program, read, or erase operation, and a control circuit (logic circuit) 160 that controls the peripheral circuit 200 .

[0037] The memory cell array 110 may include planes PL1 to PLk (k is a positive integer) in which data is stored. A plane may be a unit of area accessed when performing a program, read, or erase operation. The memory cell array 110 may be formed in a single-plane structure including a single plane, but in this embodiment, as an example, a memory cell array 110 formed in a multi-plane structure including multiple planes PL1 to PLk is described. Each of the planes PL1 to PLk may include multiple memory blocks, and each of the multiple memory blocks may include multiple memory cells. The memory blocks may store user data and metadata required for the operation of the memory device MD. The memory blocks may be implemented in a two-dimensional or three-dimensional structure. A memory block with a two-dimensional structure may include memory cells arranged parallel to a substrate, while a memory block with a three-dimensional structure may include memory cells stacked perpendicular to the substrate.

[0038] The peripheral circuit 200 may include a voltage generator 120 , a row decoder group 130 , a page buffer group 140 , and an input / output circuit 150 .

[0039] The voltage generator 120 may generate and output an operating voltage Vop required for various operations in response to the voltage code VCD. For example, the voltage generator 120 may generate a program voltage, a verification voltage, a read voltage, a pass voltage, an erase voltage, etc. having various levels and output the generated voltage as the operating voltage Vop.

[0040] The row decoder group 130 may be configured to transmit the operating voltage Vop to the planes PL1 to PLk included in the memory cell array 110 according to the row address RADD. For example, the row decoder group 130 may include a row decoder corresponding to each of the planes PL1 to PLk, and transmit the operating voltage Vop to the selected memory block included in each of the planes PL1 to PLk.

[0041] Page buffer group 140 can be connected to planes PL1 to PLk via bit lines. For example, page buffer group 140 may include a plurality of page buffers for independently operating planes PL1 to PLk in response to an operation signal OPS#. During a program operation, the page buffers can temporarily store data received from input / output circuit 150 and can adjust the voltage of the bit lines based on the temporarily stored data. During a read operation, the page buffers can temporarily store data read from a selected memory cell and can output the temporarily stored data to input / output circuit 150.

[0042] The input / output circuit 150 can be connected to the Figure 1 The controller 1200 of the present invention is configured to receive the data DATA received from the page buffer group 140. The input / output circuit 150 can input / output commands CMD, addresses ADD, and data DATA through the input / output lines. For example, the input / output circuit 150 can transmit commands CMD and addresses ADD received through the input / output lines to the control circuit 160, and transmit data DATA received through the input / output lines to the page buffer group 140. The input / output circuit 150 can output data DATA received from the page buffer group 140 to the controller 1200 through the input / output lines.

[0043] The control circuit 160 may output a voltage code VCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, the control circuit 160 may include software that executes an algorithm in response to the command CMD and may include hardware configured to output various signals based on the address ADD and the algorithm.

[0044] The control circuit 160 may be configured to control the peripheral circuit 200 in response to a command CMD and an address ADD. For example, the control circuit 160 may output a voltage code VCD, a row address RADD, and an operation signal OPS# in response to the command CMD and the address ADD.

[0045] The control circuit 160 may include a micro-control circuit group 350 for outputting an operation signal OPS#, and may include a memory manager 300 in which control codes are stored. The micro-control circuit group 350 may include multiple micro-control circuits, and the multiple micro-control circuits may be configured to output the operation signal OPS# in response to a control code output from the memory manager 300. For example, the control code may include code for performing a program operation, a read operation, or an erase operation, and may include code for performing a plane interleaving operation. The multiple micro-control circuits may include circuits configured to output the operation signal OPS# in response to the control code. The memory manager 300 may include a control memory in which the control code is stored, and may include hardware and software configured to output the control code stored in the control memory according to the order of selected planes. The control memory may be a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), or the like, and may be located outside the control circuit 160 depending on the memory device MD.

[0046] Figure 3 is a diagram illustrating a multi-plane structure according to one embodiment of the present disclosure.

[0047] refer to Figure 2 and Figure 3 , the memory device MD having a multi-plane structure may include a plurality of planes PL1 to PLk. For example, the first plane PL1 to the k-th plane PLk may be included in one memory device MD.

[0048] Each of the first to k-th planes PL1 to PLk may be connected to the row decoders 1RD to kRD and the page buffer groups 1PBG to kPBG and may operate independently. For example, the first plane PL1 may be connected to the first row decoder 1RD and the first page buffer group 1PBG and may operate, the second plane PL2 may be connected to the second row decoder 2RD and the second page buffer group 2PBG and may operate, the third plane PL3 may be connected to the third row decoder 3RD and the third page buffer group 3PBG and may operate, and the k-th plane PLk may be connected to the k-th row decoder kRD and the k-th page buffer group kPBG and may operate.

[0049] When describing a read operation as an example, each row decoder from the first to kth row decoders 1RD to kRD can apply a read voltage to a memory block selected from each of the first to kth planes PL1 to PLk in response to a received row address. The first to kth page buffer groups 1PBG to 1PBG can temporarily store read data by sensing the voltage or current of bit lines connected to the first to kth planes PL1 to PLk. When all sensing operations on the first to kth planes PL1 to PLk are completed, the read data temporarily stored in the first to kth page buffer groups 1PBG to 1PBG can be sequentially output via the input / output circuit 150. For example, after the read data stored in the first to kth page buffer groups 1PBG is output, the read data stored in the second to kth page buffer groups 2PBG to 1PBG can be sequentially output.

[0050] A memory device MD including a plurality of planes PL1 to PLk can simultaneously perform read, program, or erase operations on memory blocks or pages located in different planes. Figure 1 The controller 1200 may transmit a command CMD indicating a read operation to the control circuit 160, and the control circuit 160 may control the peripheral circuit 200 to simultaneously read memory blocks or pages included in different planes in response to the command CMD. For example, the control circuit 160 may include first to kth micro-control circuits M1 to Mk to control the peripheral circuit 200 in a plane interleaving method.

[0051] The first to k-th micro-control circuits M1 to Mk may be circuits included in the micro-control circuit group 350 and may be configured to control the first to k-th planes PL1 to PLk, respectively. Each of the first to Mk-th micro-control circuits may control the first to k-th row decoders 1RD to k-th row decoders kRD and the first to k-th page buffer groups 1PBG to kPBG in response to the first to m-th control codes CCD1 to CCDm output from the memory manager 300. For example, the first micro-control circuit M1 may control the first row decoder 1RD and the first page buffer group 1PBG, the second micro-control circuit M2 may control the second row decoder 2RD and the second page buffer group 2PBG, the third micro-control circuit M3 may control the third row decoder 3RD and the third page buffer group 3PBG, and the k-th micro-control circuit Mk may control the k-th row decoder kRD and the k-th page buffer group kPBG. For example, when a plurality of logical page data are stored in the memory cells, the first to m-th control codes CCD1 to CCDm may be codes for reading the plurality of logical page data. For example, the first to m-th control codes CCD1 to CCDm may include codes for performing a least significant bit read operation, codes for performing a mid-significant bit read operation, or codes for performing a most significant bit read operation.

[0052] The least significant bit, the middle significant bit, and the most significant bit can vary depending on the method used to program the memory cell. This will refer to Figure 4 Described in detail.

[0053] Figure 4 is a diagram illustrating a memory block, and according to one embodiment of the present disclosure, Figure 3 Among the plurality of memory blocks BLK1 to BLKi shown in , the i-th memory block BLKi is shown as an example.

[0054] refer to Figure 4 , the i-th memory block BLKi may include a plurality of strings ST1 to STj (j is a positive integer). The first string ST1 to the j-th string STj may be connected between the bit lines BL1 to BLj and the source line SL. For example, the first string ST1 may be connected between the first bit line BL1 and the source line SL, the second string ST2 may be connected between the second bit line BL2 and the source line SL, and the j-th string STj may be connected between the j-th bit line BLj and the source line SL.

[0055] Each of the first to j-th strings ST1 to STj may include a source select transistor SST, a plurality of memory cells C1 to Cn, and a drain select transistor DST. Although not shown in the drawings, a dummy cell may be further included between the memory cells C1 to Cn and the source select transistor SST or the drain select transistor DST. The configuration of the string will be specifically described below using the j-th string STj as an example.

[0056] The source select transistor SST included in the jth string STj can be electrically connected or disconnected between the source line SL and the first memory cell Cl according to the voltage applied to the source select line SSL. The gates of the first memory cell C1 to the nth memory cell Cn can be connected to the first word line WL1 to the nth word line WLn, respectively. The drain select transistor DST can be electrically connected or disconnected between the jth bit line BLj and the nth memory cell Cn according to the voltage applied to the drain select line DSL. The gates of the source select transistors SST included in different strings ST1 to STj can be connected to the source select line SSL in common, and the gates of the first memory cell C1 to the nth memory cell Cn can be connected to the first word line WL1 to the nth word line WLn, and the gates of the drain select transistors DST can be connected to the drain select line DSL in common. A group of memory cells connected to the same word line is called a page PG, and programming and reading operations can be performed in units of page PG.

[0057] The memory cell can be programmed in various ways depending on the number of bits stored in one memory cell, and a read operation can be performed in the same way as the programming method. For example, a method in which one bit of data is stored in one memory cell can be referred to as a single-level cell method, a method in which two bits of data are stored in one memory cell can be referred to as a multi-level cell method, a method in which three bits of data are stored in one memory cell can be referred to as a triple-level cell method, and a method in which four bits of data are stored in one memory cell can be referred to as a quad-level cell method. In addition, the memory cell can be programmed in various ways depending on the number of bits stored in one memory cell.

[0058] When describing the multi-level cell method as an example, in a programming operation of the multi-level cell method, two bits of data can be stored in a memory cell. The two bits of data become two different logical pages of data. The different logical pages of data can include the least significant bit data and the most significant bit data. Therefore, a read operation of a memory cell programmed using the multi-level cell method can also be performed on different logical pages of data. For example, an operation of reading the least significant bit data and an operation of reading the most significant bit data can be performed.

[0059] When describing the three-level cell method as an example, in the programming method of the three-level cell, three bits of data can be stored in one memory cell. The three bits of data become three different logical pages of data. The different logical pages of data may include the least significant bit data, the middle significant bit data, and the most significant bit data. Therefore, the read operation of the memory cell programmed with the three-level cell method can also be performed on different logical pages of data. For example, an operation of reading the least significant bit data, an operation of reading the middle significant bit data, and an operation of reading the most significant bit data can be performed. That is, the read operation on the memory cell can be performed as many times as the number of logical pages of data stored in the memory cell.

[0060] Figure 5 is a diagram illustrating threshold voltage distribution of memory cells according to one embodiment of the present disclosure.

[0061] refer to Figure 5 , different logical page data stored in a memory cell can be represented by a Gray code. When describing the Gray code of the three-level cell method as an example, in the three-level cell method, logical page data corresponding to the least significant bit (LSB), the middle significant bit (CSB), and the most significant bit (MSB) can be stored in one memory cell. Each of the LSB data, the CSB data, and the MSB data can become different logical page data and can be represented as 0 or 1. Here, 0 or 1 is a Gray code. The Gray code can be arranged in the order of LSB, CSB, and MSB, and can be represented in various combinations. For example, the erase state ER can be represented as '111', the first programming state PV1 can be represented as '110', and the second programming state PV2 can be represented as '100'. Figure 5 The Gray code shown in corresponds to one embodiment and can be set in various combinations according to the memory device.

[0062] In the read operation of the three-level cell method, a read operation using the LSB read voltage V LSB LSB read operation, use CSB to read voltage V CSB CSB read operation, and use the MSB read voltage V MSB MSB read operation.

[0063] Figure 6 is a diagram illustrating a memory manager according to one embodiment of the present disclosure.

[0064] refer to Figure 6The memory manager 300 may be configured to output a plurality of control codes CCD# for controlling each plane in response to a command CMD. The memory manager 300 may include a control memory 60, a latch group 61, a plane multiplexer group 62, an address multiplexer 63, and a scheduler 64.

[0065] The control memory 60 may be configured to store various control codes for controlling peripheral circuits according to commands. For example, the memory cells included in the control memory 60 may be configured by cells that only perform read operations on them, and may also be configured by cells that can be reprogrammed in some cases. For example, the control memory 60 may be configured by a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), or the like. Therefore, after the control code CCD# is stored in the control memory 60, the memory manager 300 may only perform a read operation on the control memory 60.

[0066] The control memory 60 can be configured from a single cell array, regardless of the number of planes. In some proposed memory devices, multiple control memories are used, and the number of control memories corresponds to the number of planes. However, in this embodiment, a single control memory 60 can be used to cover multiple planes. To perform read operations on multiple planes in an interleaved manner, the memory cells included in the control memory 60 can be divided into a first memory group GR1 to a kth memory group GRk. A control code CCD# for controlling operations on the first plane can be stored in the first memory group GR1, a control code CCD# for controlling operations on the second plane can be stored in the second memory group GR2, a control code CCD# for controlling operations on the third plane can be stored in the third memory group GR3, and a control code CCD# for controlling operations on the kth plane can be stored in the kth memory group GRk. The memory cells included in the first to kth memory groups GR1 to GRk can be physically connected to each of the first to rth row lines RL1 to RLr and can be logically divided into the first to kth memory groups GR1 to GRk. For example, memory cells connected to the first row line RL1 may be divided into first to kth memory groups GR1 to GRk, and memory cells connected to the rth row line RLr may be divided into first to kth memory groups GR1 to GRk.

[0067] The latch group 61 can be connected to the first memory group GR1 to the kth memory group GRk via the data line D# and can be configured to temporarily store the control code CCD# read from the first memory group GR1 to the kth memory group GRk. For example, the latch group 61 may include a first sub-latch group SLG1 to a kth sub-latch group SLGk. The first sub-latch group SLG1 may include a latch capable of temporarily storing the control code CCD# read from the first memory group GR1, and the second sub-latch group SLG2 may include a latch capable of temporarily storing the control code CCD# read from the second memory group GR2. In this way, the kth sub-latch group SLCk may include a latch capable of temporarily storing the control code CCD# read from the kth memory group GRk. The first sub-latch group SLG1 to the kth sub-latch group SLGk can operate simultaneously in response to the sub-latch signal SLS.

[0068] The plane multiplexer group 62 can be configured to receive the control code CCD# temporarily stored in the latch group 61 in response to the code transmission signal CTS# and selectively output the received control code CCD#. For example, the plane multiplexer group 62 can include a first plane multiplexer PM1 through a kth plane multiplexer PMk. The first plane multiplexers PM1 through PMk can be connected to each of the first through kth sub-latch groups SLG1 through SLGk, collectively receive the control code CCD# from each of the first through kth sub-latch groups SLG1 through SLGk in response to the code transmission signal CTS#, and selectively output the control code CCD#.

[0069] The address multiplexer 63 may be configured to receive the first to k-th plane addresses PADD1 to PADDk and selectively output read voltages to the first to r-th row lines RL1 to RLr in response to the address multiplexer signal ADMS.

[0070] The scheduler 64 may include software capable of adjusting the output order of the control codes CCD# stored in the first to k-th memory groups GR1 to GRk, and may include hardware configured to output the address multiplexer signal ADMS, the sub-latch signal SLS, and the code transmission signal CTS# according to the output order, so as to perform a plane interleaving operation in response to the command CMD. For example, when a read command CMD for the first to k-th planes is input, the scheduler 64 may output the address multiplexer signal ADMS, the sub-latch signal SLS, and the code transmission signal CTS# so that the control code CCD# read from the first memory group GR1 is output to perform a read operation on the first plane, and then the control code CCD# read from the second memory group GR2 is output to perform a read operation on the second plane.

[0071] The structures of the first to kth memory groups GR1 to GRk and the plane interleaving operation are described in detail as follows.

[0072] Figure 7 is a diagram illustrating a control memory according to one embodiment of the present disclosure.

[0073] refer to Figure 7 The control memory 60 may include a plurality of memory cells MC for storing control codes. The plurality of memory cells MC may be connected between some of the first to r-th row lines RL1 to RLr and some of the first to i-th data lines D1 to Di. Since the memory device can be operated according to the control codes stored in the control memory 60, the memory cells MC may be connected to areas where the first to r-th row lines RL1 to RLr overlap with the first to i-th data lines D1 to Di, thereby preventing a reduction in the reliability of the control memory 60. As the distance between the memory cells MC included in the control memory 60 increases, interference between the memory cells MC decreases, thereby preventing a reduction in the reliability of the control memory 60.

[0074] exist Figure 7 , the cells connected to the first row line RL1 to the r-th row line RLr are included one by one in the memory cells MC included in the first memory group GR1 to the k-th memory group GRk. However, in this embodiment, the structure of the control memory 60 is not limited to Figure 7 The structure shown in .

[0075] Figures 8A to 8E is a diagram illustrating a method of outputting a control code for performing a read operation of a selected plane according to one embodiment of the present disclosure.

[0076] refer to Figures 8A to 8EThe memory device includes four planes PL1 to PL4. When the memory device includes four planes PL1 to PL4, the memory cells included in the control memory 60 may also be divided into four memory groups GR1 to GR4. For example, different control codes CCD1, CCD2, CCD3, CCD4, etc. for controlling the operation of each of the first to fourth planes PL1 to PL4 may be stored in the first to fourth memory groups GR1 to GR4. For example, the first control code CCD1 may be a code for performing an LSB read operation LSB_R on each of the first to fourth planes PL1 to PL4, the second control code CCD2 may be a code for performing a CSB read operation CSB_R on each of the first to fourth planes PL1 to PL4, and the third control code CCD3 may be a code for performing an MSB read operation MSB_R on each of the first to fourth planes PL1 to PL4. In this embodiment, a read operation using a three-level cell method is described as an example, but various control codes may be stored in the first to fourth memory groups GR1 to GR4.

[0077] The first to fourth memory groups GR1 to GR4, the first to fourth sub-latch groups SLG1 to SLG4, and the first to fourth plane multiplexers PM1 to PM4 are formed by Figure 6 The scheduler 64 is controlled and referenced Figures 8A to 8E In the description, the transmission order of the control code is mainly described.

[0078] refer to Figures 8A to 8E , as an embodiment, a method of outputting a control code for controlling the operation of the first plane PL1 is described, and with reference to Figures 9A to 9E , a method of outputting a control code for controlling operations of the first to fourth planes PL1 to PL4 is described.

[0079] refer to Figure 8A, the first control code CCD1 stored in the first memory group GR1 may be transmitted to the first sub-latch group SLG1. The first control code CCD1 stored in the first sub-latch group SLG1 may be transmitted to the first plane multiplexer PM1 to the fourth plane multiplexer PM4. In response to the first code transmission signal CTS1 to the fourth code transmission signal CTS4, only the first plane multiplexer PM1 outputs the first control code CCD1, and the remaining second plane multiplexers PM2 to the fourth plane multiplexer PM4 do not output the first control code CCD1. The first control code CCD1 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1. The first micro-control circuit M1 may sense the first control code CCD1 and may use the first control code CCD1 to control Figure 3 The peripheral circuits 1RD and 1PBG are configured to perform a read operation of the first plane PL1.

[0080] refer to Figure 8B , after the first control code CCD1 is output from the first micro-control circuit M1, the second control code CCD2 of the second memory group GR2 may be transmitted to the second sub-latch group SLG2. The second control code CCD2 output from the second sub-latch group SLG2 may be transmitted to the first plane multiplexer PM1 to the fourth plane multiplexer PM4, and the first plane multiplexer PM1 may output the second control code CCD2 in response to the first code transmission signal CTS1. The remaining second plane multiplexers PM2 to the fourth plane multiplexer PM4 do not output the second control code CCD2. The second control code CCD2 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1. The first micro-control circuit M1 may sense the second control code CCD2 and may use the second control code CCD2 to control Figure 3 The peripheral circuits 1RD and 1PBG are configured to perform a read operation of the first plane PL1.

[0081] refer to Figure 8C, after the second control code CCD2 is output from the first micro-control circuit M1, the third control code CCD3 of the third memory group GR3 may be transmitted to the third sub-latch group SLG3. The third control code CCD3 output from the third sub-latch group SLG3 may be transmitted to the first plane multiplexer PM1 to the fourth plane multiplexer PM4, and the first plane multiplexer PM1 may output the third control code CCD3 in response to the first code transmission signal CTS1. The remaining second plane multiplexers PM2 to the fourth plane multiplexer PM4 do not output the third control code CCD3. The third control code CCD3 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1. The first micro-control circuit M1 may sense the third control code CCD3 and use the third control code CCD3 to control Figure 3 The peripheral circuits 1RD and 1PBG are configured to perform a read operation of the first plane PL1.

[0082] refer to Figure 8D , after the third control code CCD3 is output from the first micro-control circuit M1, the fourth control code CCD4 of the fourth memory group GR4 may be transmitted to the fourth sub-latch group SLG4. The fourth control code CCD4 output from the fourth sub-latch group SLG4 may be transmitted to the first plane multiplexer PM1 to the fourth plane multiplexer PM4, and the first plane multiplexer PM1 may output the fourth control code CCD4 in response to the first code transmission signal CTS1. The remaining second plane multiplexers PM2 to the fourth plane multiplexer PM4 do not output the fourth control code CCD4. The fourth control code CCD4 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1. The first micro-control circuit M1 may sense the fourth control code CCD4 and use the fourth control code CCD4 to control Figure 3 The peripheral circuits 1RD and 1PBG are configured to perform a read operation of the first plane PL1.

[0083] refer to Figure 8E, after the fourth control code CCD4 is output from the first micro-control circuit M1, the fifth control code CCD5 of the first memory group GR1 may be transmitted to the first sub-latch group SLG1. The fifth control code CCD5 output from the first sub-latch group SLG1 may be transmitted to the first plane multiplexer PM1 to the fourth plane multiplexer PM4, and the first plane multiplexer PM1 may output the fifth control code CCD5 in response to the first code transmission signal CTS1. The remaining second plane multiplexers PM2 to the fourth plane multiplexer PM4 do not output the fifth control code CCD5. The fifth control code CCD5 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1. The first micro-control circuit M1 may sense the fifth control code CCD5 and use the fifth control code CCD5 to control Figure 3 The peripheral circuits 1RD and 1PBG are configured to perform a read operation of the first plane PL1.

[0084] As described above, the control codes output from the first to fourth memory groups GR1 to GR4 can be selectively transmitted to the first micro control circuit M1 using the first to fourth plane multiplexers PM1 to PM4. Figures 8A to 8E A method of outputting a control code for controlling a read operation of a plurality of planes according to an embodiment of the present invention is described as follows.

[0085] Figures 9A to 9E is a diagram illustrating a method of outputting a control code for sequentially performing a read operation of a plurality of planes according to an embodiment of the present disclosure.

[0086] refer to Figure 9A , the first control code CCD1 stored in the first memory group GR1 may be transmitted to the first sub-latch group SLG1. The first control code CCD1 stored in the first sub-latch group SLG1 may be transmitted to the first plane multiplexer PM1 to the fourth plane multiplexer PM4. In response to the first code transmission signal CTS1 to the fourth code transmission signal CTS4, only the first plane multiplexer PM1 outputs the first control code CCD1, and the remaining second plane multiplexers PM2 to the fourth plane multiplexer PM4 do not output the first control code CCD1. The first control code CCD1 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1. The first micro-control circuit M1 may sense the first control code CCD1 and use the first control code CCD1 to control Figure 3 The peripheral circuits 1RD and 1PBG are configured to perform a read operation of the first plane PL1.

[0087] refer to Figure 9BAfter the first microcontroller M1 outputs the first control code CCD1, the second control code CCD2 of the second memory group GR2 may be transmitted to the second sub-latch group SLG2. At this time, the first control code CCD1 received from the first memory group GR1 may be held in the first sub-latch group SLG1. The second control code CCD2 output from the second sub-latch group SLG2 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the first plane multiplexer PM1 may output the second control code CCD2 in response to the first code transmission signal CTS1. The first control code CCD1 output from the first sub-latch group SLG1 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the second plane multiplexer PM2 may output the first control code CCD1 in response to the second code transmission signal CTS2. The remaining third plane multiplexers PM3 and PM4 do not output the first and second control codes CCD1 and CCD2. The second control code CCD2 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1, and the first control code CCD1 output from the second plane multiplexer PM2 may be transmitted to the second micro-control circuit M2. The first micro-control circuit M1 may sense the second control code CCD2 and use the second control code CCD2 to control Figure 3 The peripheral circuits 1RD and 1PBG of the second micro-control circuit M2 can sense the first control code CCD1 and use the first control code CCD1 to control the first plane PL1. Figure 3 The peripheral circuits 2RD and 2PBG are used to perform a read operation of the second plane PL2.

[0088] refer to Figure 9CAfter the second control code CCD2 and the first control code CCD1 are output from the first micro-control circuit M1 and the second micro-control circuit M2, the third control code CCD3 of the third memory group GR3 can be transmitted to the third sub-latch group SLG3. At this time, the first control code CCD1 received from the first memory group GR1 can be held in the first sub-latch group SLG1, and the second control code CCD2 received from the second memory group GR2 can be held in the second sub-latch group SLG2. The third control code CCD3 output from the third sub-latch group SLG3 can be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the first plane multiplexer PM1 can output the third control code CCD3 in response to the first code transmission signal CTS1. The second control code CCD2 output from the second sub-latch group SLG2 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the second plane multiplexer PM2 may output the second control code CCD2 in response to the second code transmission signal CTS2. The first control code CCD1 output from the first sub-latch group SLG1 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the third plane multiplexer PM3 may output the first control code CCD1 in response to the third code transmission signal CTS3. The remaining fourth plane multiplexer PM4 does not output the first to third control codes CCD1 to CCD3. The third control code CCD3 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1, the second control code CCD2 output from the second plane multiplexer PM2 may be transmitted to the second micro-control circuit M2, and the first control code CCD1 output from the third plane multiplexer PM3 may be transmitted to the third micro-control circuit M3. The first micro-control circuit M1 may sense the third control code CCD3 and use the third control code CCD3 to control Figure 3 The peripheral circuits 1RD and 1PBG of the first plane PL1 are used to perform a read operation of the first plane PL1. The second micro control circuit M2 can sense the second control code CCD2 and use the second control code CCD2 to control the Figure 3 The peripheral circuits 2RD and 2PBG of the third micro-control circuit M3 can sense the first control code CCD1 and use the first control code CCD1 to control the second plane PL2. Figure 3 The peripheral circuits 3RD and 3PBG are used to perform a read operation of the third plane PL3.

[0089] refer to Figure 9DAfter the third control code CCD3, the second control code CCD2, and the first control code CCD1 are output from the first to third micro-control circuits M1 to M3, the fourth control code CCD4 of the fourth memory group GR4 can be transmitted to the fourth sub-latch group SLG4. At this time, the first control code CCD1 received from the first memory group GR1 can be held in the first sub-latch group SLG1, the second control code CCD2 received from the second memory group GR2 can be held in the second sub-latch group SLG2, and the third control code CCD3 received from the third memory group GR3 can be held in the third sub-latch group SLG3. The fourth control code CCD4 output from the fourth sub-latch group SLG4 can be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the first plane multiplexer PM1 can output the fourth control code CCD4 in response to the first code transmission signal CTS1. The third control code CCD3 output from the third sub-latch group SLG3 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the second plane multiplexer PM2 may output the third control code CCD3 in response to the second code transmission signal CTS2. The second control code CCD2 output from the second sub-latch group SLG2 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the third plane multiplexer PM3 may output the second control code CCD2 in response to the third code transmission signal CTS3. The first control code CCD1 output from the first sub-latch group SLG1 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the fourth plane multiplexer PM4 may output the first control code CCD1 in response to the fourth code transmission signal CTS4. The fourth control code CCD4 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1, the third control code CCD3 output from the second plane multiplexer PM2 may be transmitted to the second micro-control circuit M2, the second control code CCD2 output from the third plane multiplexer PM3 may be transmitted to the third micro-control circuit M3, and the first control code CCD1 output from the fourth plane multiplexer PM4 may be transmitted to the fourth micro-control circuit M4. The first micro-control circuit M1 may sense the fourth control code CCD4 and use the fourth control code CCD4 to control Figure 3 The peripheral circuits 1RD and 1PBG of the second micro-control circuit M2 can sense the third control code CCD3 and use the third control code CCD3 to control the first plane PL1. Figure 3The peripheral circuits 2RD and 2PBG of the third micro-control circuit M3 can sense the second control code CCD2 and use the second control code CCD2 to control the peripheral circuits 3RD and 3PBG to perform the read operation of the third plane PL3. The fourth micro-control circuit M4 can sense the first control code CCD1 and use the first control code CCD1 to control the peripheral circuits 3RD and 3PBG to perform the read operation of the third plane PL3. Figure 3 The peripheral circuits 4RD and 4PBG are used to perform a read operation of the fourth plane PL4.

[0090] refer to Figure 9E After the fourth control code CCD4, the third control code CCD3, the second control code CCD2, and the first control code CCD1 are output from the first microcontrol circuit M1 to the fourth microcontrol circuit M4, the fifth control code CCD5 of the first memory group GR1 can be transmitted to the first sub-latch group SLG1. That is, the first control code CCD1 can be removed from the first sub-latch group SLG1, and the fifth control code CCD5 can be newly stored. At this time, the second control code CCD2 received from the second memory group GR2 can be retained in the second sub-latch group SLG2, the third control code CCD3 received from the third memory group GR3 can be retained in the third sub-latch group SLG3, and the fourth control code CCD4 received from the fourth memory group GR4 can be retained in the fourth sub-latch group SLG4. The fifth control code CCD5 output from the first sub-latch group SLG1 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the first plane multiplexer PM1 may output the fifth control code CCD5 in response to the first code transmission signal CTS1. The second control code CCD2 output from the second sub-latch group SLG2 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the fourth plane multiplexer PM4 may output the second control code CCD2 in response to the fourth code transmission signal CTS4. The third control code CCD3 output from the third sub-latch group SLG3 may be transmitted to the first to fourth plane multiplexers PM1 to PM4, and the third plane multiplexer PM3 may output the third control code CCD3 in response to the third code transmission signal CTS3. The fourth control code CCD4 output from the fourth sub-latch group SLG4 may be transmitted to the first to fourth plane multiplexers PM1 to PM4 , and the second plane multiplexer PM2 may output the fourth control code CCD4 in response to the second code transmission signal CTS2 .

[0091] The fifth control code CCD5 output from the first plane multiplexer PM1 may be transmitted to the first micro-control circuit M1, the fourth control code CCD4 output from the second plane multiplexer PM2 may be transmitted to the second micro-control circuit M2, the third control code CCD3 output from the third plane multiplexer PM3 may be transmitted to the third micro-control circuit M3, and the second control code CCD2 output from the fourth plane multiplexer PM4 may be transmitted to the fourth micro-control circuit M4. The first micro-control circuit M1 may sense the fifth control code CCD5 and use the fifth control code CCD5 to control Figure 3 The peripheral circuits 1RD and 1PBG of the second micro-control circuit M2 can sense the fourth control code CCD4 and use the fourth control code CCD4 to control the first plane PL1. Figure 3 The peripheral circuits 2RD and 2PBG of the second plane PL2 are used to perform a read operation of the second plane PL2. The third micro control circuit M3 can sense the third control code CCD3 and use the third control code CCD3 to control the Figure 3 The fourth micro-control circuit M4 can sense the second control code CCD2 and use the second control code CCD2 to control the Figure 3 The peripheral circuits 4RD and 4PBG are used to perform a read operation of the fourth plane PL4.

[0092] The plane interleaving operations performed in the first to fourth planes PL1 to PL4 according to the control codes output from the first to fourth micro control circuits M1 to M4 are described as follows.

[0093] Figure 10 is a diagram illustrating a plane interleaving operation according to one embodiment of the present disclosure.

[0094] refer to Figure 10 At the first time t1, since the first control code CCD1 output from the first sub latch group SLG1 is transmitted to the first micro control circuit M1, the first micro control circuit M1 may control the read operation of the first plane PL1 in response to the first control code CCD1.

[0095] At the second time t2, the second control code CCD2 output from the second sub-latch group SLG2 can be transmitted to the first micro-control circuit M1, and the first control code CCD1 output from the first sub-latch group SLG1 can be transmitted to the second micro-control circuit M2. Therefore, the first micro-control circuit M1 can control the read operation of the first plane PL1 in response to the second control code CCD2, and the second micro-control circuit M2 can control the read operation of the second plane PL2 in response to the first control code CCD1.

[0096] At a third time t3, the third control code CCD3 outputted from the third sub-latch group SLG3 may be transmitted to the first micro-control circuit M1, the second control code CCD2 outputted from the second sub-latch group SLG2 may be transmitted to the second micro-control circuit M2, and the first control code CCD1 outputted from the first sub-latch group SLG1 may be transmitted to the third micro-control circuit M3. Thus, the first micro-control circuit M1 may control a read operation of the first plane PL1 in response to the third control code CCD3, the second micro-control circuit M2 may control a read operation of the second plane PL2 in response to the second control code CCD2, and the third micro-control circuit M3 may control a read operation of the third plane PL3 in response to the first control code CCD1.

[0097] At a fourth time t4, the fourth control code CCD4 outputted from the fourth sub-latch group SLG4 may be transmitted to the first micro-control circuit M1, the third control code CCD3 outputted from the third sub-latch group SLG3 may be transmitted to the second micro-control circuit M2, the second control code CCD2 outputted from the second sub-latch group SLG2 may be transmitted to the third micro-control circuit M3, and the first control code CCD1 outputted from the first sub-latch group SLG1 may be transmitted to the fourth micro-control circuit M4. Therefore, the first micro-control circuit M1 may control the read operation of the first plane PL1 in response to the fourth control code CCD4, the second micro-control circuit M2 may control the read operation of the second plane PL2 in response to the third control code CCD3, the third micro-control circuit M3 may control the read operation of the third plane PL3 in response to the second control code CCD2, and the fourth micro-control circuit M4 may control the read operation of the fourth plane PL4 in response to the first control code CCD1.

[0098] At the fifth time t5, the fifth control code CCD5 can be newly stored in the first sub-latch group SLG1 and transmitted to the first micro-control circuit M1. The fourth control code CCD4 output from the fourth sub-latch group SLG4 can be transmitted to the second micro-control circuit M2, the third control code CCD3 output from the third sub-latch group SLG3 can be transmitted to the third micro-control circuit M3, and the second control code CCD2 output from the second sub-latch group SLG2 can be transmitted to the fourth micro-control circuit M4. Therefore, the first micro-control circuit M1 can control the read operation of the first plane PL1 in response to the fifth control code CCD5, the second micro-control circuit M2 can control the read operation of the second plane PL2 in response to the fourth control code CCD4, the third micro-control circuit M3 can control the read operation of the third plane PL3 in response to the third control code CCD3, and the fourth micro-control circuit M4 can control the read operation of the fourth plane PL4 in response to the second control code CCD2.

[0099] At the sixth time t6, the sixth control code CCD6 can be newly stored in the second sub-latch group SLG2 and transmitted to the first micro-control circuit M1. The fifth control code CCD5 output from the first sub-latch group SLG1 can be transmitted to the second micro-control circuit M2, the fourth control code CCD4 output from the fourth sub-latch group SLG4 can be transmitted to the third micro-control circuit M3, and the third control code CCD3 output from the third sub-latch group SLG3 can be transmitted to the fourth micro-control circuit M4. Therefore, the first micro-control circuit M1 can control the read operation of the first plane PL1 in response to the sixth control code CCD6, the second micro-control circuit M2 can control the read operation of the second plane PL2 in response to the fifth control code CCD5, the third micro-control circuit M3 can control the read operation of the third plane PL3 in response to the fourth control code CCD4, and the fourth micro-control circuit M4 can control the read operation of the fourth plane PL4 in response to the third control code CCD3.

[0100] In the above method, control codes may be sequentially stored in the first to fourth sub-latch groups SLG1 to SLG4, and the control codes stored in the first to fourth sub-latch groups SLG1 to SLG4 may be respectively transmitted to the micro-control circuits M1 to M4 selected by the plane multiplexer. The micro-control circuits M1 to M4 may sense the transmitted control codes and, in response to the sensed control codes, control the peripheral circuits connected to the first to fourth planes PL1 to PL4, respectively.

[0101] Figure 11is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0102] refer to Figure 11 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0103] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control programming, reading, or erasing operations of the memory device 2200, or to control background operations. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory device 2200 may communicate with a reference Figure 2 The described memory devices MD are configured identically.

[0104] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 is configured to communicate with an external device through at least one communication standard in various communication standards, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Minidisk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WIFI, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one communication standard in the various communication standards mentioned above.

[0105] For example, the memory device 2200 may be configured by various nonvolatile memory devices, such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque-magnetic RAM (STT-MRAM).

[0106] The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure memory cards such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a Universal Flash Storage device (UFS).

[0107] Figure 12 is a diagram illustrating a solid-state drive (SSD) system to which a memory device according to one embodiment of the present disclosure is applied.

[0108] refer to Figure 12 , an SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0109] According to one embodiment of the present disclosure, the flash memories 3221 to 322n can be connected to the reference Figure 2 The described memory devices MD are configured identically.

[0110] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100. For example, the signal may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced MiniDisk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0111] The auxiliary power supply 3230 is connected to the host 3100 via the power connector 3002. The auxiliary power supply 3230 can receive power from the host 3100 and can be charged with this power. When the power supply from the host 3100 is insufficient, the auxiliary power supply 3230 can provide power to the SSD 3200. For example, the auxiliary power supply 3230 can be located in the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the motherboard and can provide auxiliary power to the SSD 3200.

[0112] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0113] Although the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are provided for illustration and are not intended to be limiting. Furthermore, it should be noted that, as will be appreciated by those skilled in the art in light of the present disclosure, the present disclosure may be implemented in various ways through substitutions, changes, and modifications within the scope of the appended claims.

Claims

1. A memory device comprising: a plurality of planes in which data is stored; peripheral circuitry configured to perform operations on the plurality of planes; a microcontroller configured to control the peripheral circuits so that the operations on the plurality of planes are independently performed; as well as a memory manager including a control memory storing therein different control codes for controlling the peripheral circuits and configured to output the control codes to the micro-control circuit, The memory manager is configured to sequentially output selected control codes from among the control codes to the micro-control circuits corresponding to the planes respectively. 2 . The memory device of claim 1 , wherein each of the planes comprises a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of memory cells in which the data is stored.

3. The memory device of claim 1, wherein the peripheral circuit comprises a row decoder and a page buffer group respectively controlled by the micro-control circuit. 4 . The memory device of claim 3 , wherein one of the row decoders and one of the page buffer groups form a pair to control a corresponding plane among the planes. 5 . The memory device of claim 4 , wherein each of the micro-control circuits is configured to independently control corresponding pairs among the pairs of the row decoder and the page buffer group in response to the control code.

6. The memory device of claim 1 , wherein the memory manager comprises: The control memory includes a plurality of memory groups corresponding to the plurality of planes respectively; sub-latch groups, corresponding to the memory groups respectively, and configured to respectively store the control codes stored in the memory groups; a plane multiplexer configured to sequentially output the control codes received from the sub-latch groups according to an order of the operations performed on each of the plurality of planes; An address multiplexer configured to: output a read voltage of the memory group according to a plane address; as well as The scheduler is configured to control the sub-latch group, the plane multiplexer, and the address multiplexer in response to a command. 7 . The memory device of claim 6 , wherein the memory manager is configured to output the control code for controlling the plane using the control memory as a single memory for storing the control code. 8 . The memory device of claim 6 , wherein the sub latch group is configured to temporarily store the control code read from each of the memory groups and transmit the control code to the plane multiplexer.

9. The memory device according to claim 6, wherein the plane multiplexer is configured to: receive the control code from the sub-latch groups in common, and output the selected control code to the selected micro-control circuit according to the control of the scheduler.

10. The memory device according to claim 6, wherein when the control code stored in the last sub-latch group among the sub-latch groups is output, the scheduler controls the sub-latch groups so that the previous control code stored in the first sub-latch group among the sub-latch groups is removed, and the next control code stored in the memory group corresponding to the first sub-latch group among the memory groups is stored in the first sub-latch group.

11. A memory device comprising: a control memory including first to Nth memory groups storing different control codes therein; The first to Nth sub-latch groups are connected to the first to Nth memory groups, respectively, and are configured to sequentially store the control codes stored in the first to Nth memory groups, respectively; as well as The first plane multiplexer to the Nth plane multiplexer are configured to: jointly receive the control codes from the first sub-latch group to the Nth sub-latch group, and output the received control codes to the selected micro-control circuits among the first micro-control circuit to the Nth micro-control circuit.

12. The memory device according to claim 11, wherein the control memory comprises a memory unit configured by a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), or an electrically erasable and programmable ROM (EEPROM). 13 . The memory device of claim 11 , further comprising a scheduler configured to control the first to N th sub-latch groups and the first to N th plane multiplexers in response to a command.

14. The memory device of claim 13 , wherein the scheduler is configured to: controlling the first memory group to transmit the first control code stored therein to the first sub-latch group, controlling the second memory group among the first to Nth memory groups to transmit the second control code stored therein to the second sub-latch group among the first to Nth sub-latch groups, controlling the first sub-latch group to transmit the first control code stored therein to the first plane multiplexer to the Nth plane multiplexer, and The second sub-latch group is controlled to transmit the second control code stored therein to the first plane multiplexer to the Nth plane multiplexer. 15 . The memory device of claim 14 , wherein the scheduler controls the first to N-th plane multiplexers so that the first control code transmitted to the first plane multiplexer is output to the first micro-control circuit. 16 . The memory device of claim 15 , wherein when the first plane multiplexer outputs the first control code, the scheduler stops outputs of the remaining second to Nth plane multiplexers.

17. A memory device according to claim 15, wherein after the first control code is output to the first micro-control circuit, the scheduler controls the first plane multiplexer to the N-th plane multiplexer so that the second control code transmitted to the first plane multiplexer is output to the first micro-control circuit, and the first control code transmitted to the second plane multiplexer among the first plane multiplexer to the N-th plane multiplexer is output to the second micro-control circuit among the first micro-control circuit to the N-th micro-control circuit. 18 . The memory device of claim 17 , wherein the scheduler stops outputs of the remaining third to Nth plane multiplexers when the first plane multiplexer outputs the second control code and the second plane multiplexer outputs the first control code.

19. The memory device of claim 11, wherein the control code is provided for the first to Nth micro-control circuits to control different read operations on a plurality of planes in which data is stored.

20. A memory device comprising: A number N of control circuits are configured to: control the number N of storage circuits by providing a control code to the storage circuits at each interval, thereby controlling the storage circuits to perform a plane interleaving operation; a memory cell array configured to: output one control code among different control codes stored therein at the intervals; as well as The management circuit is configured to: provide the control code output from the memory cell array to one of the control circuits at the interval, thereby providing each of the control codes output from the memory cell array in sequence to the control circuit in sequence through the interval.

Images