error type indication

Abstract

This application relates to error type indication. A memory device can detect an error while performing an error detection procedure on a codeword. The memory device can transmit one or more bits to a host device, which can be one or more error flags indicating a type of error detected by the memory device. By transmitting the one or more bits to a requesting device, such as a host device, the memory device can indicate that a particular type of error was detected in the set of data returned to the requesting device.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to U.S. Patent Application No. 63 / 121,744, filed December 4, 2020, by BUCH, titled “ERROR TYPE INDICATION,” assigned to the present assignee, and expressly incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] The technical field relates to error type indication. BACKGROUND

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two supported states, often represented by a logical 1 or logical 0. In some examples, individual memory cells can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memories (RAM), read-only memories (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, chalcogenide memory technologies, and others. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain their stored logic state for a long period of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0006] An apparatus is described. The apparatus can include a decoder configured to detect one or more errors in a codeword, a first logic gate coupled with the decoder and configured to perform a first logical OR operation on a first set of bits output from the decoder, the first set of bits representing error flags for a set of parity bits included in the codeword, and a second logic gate coupled with the decoder and configured to perform a second logical OR operation on a second set of bits output from the decoder, the second set of bits representing error flags for a set of data bits included in the codeword.

[0007] A method is described. The method can be performed by a memory device and can include performing, by a decoder, an error detection procedure on a codeword protected by an error correction code, outputting, by the decoder, based at least in part on the error detection procedure, a first set of bits representing error flags for a set of parity bits included in the codeword and a second set of bits representing error flags for a set of data bits included in the codeword, performing a first logical OR operation on the first set of bits representing error flags for the set of parity bits included in the codeword, and performing a second logical OR operation on the second set of bits representing error flags for the set of data bits included in the codeword.

[0008] An apparatus is described. The apparatus can include a controller configured to couple with a memory device, where the controller is configured to cause the apparatus to: transmit, to the memory device, a read command for a set of data, receive, from the memory device, the set of data based at least in part on transmitting the read command, and receive, from the memory device, a set of bits associated with the set of data and indicative of a type of error detected during an error detection procedure for the set of data, the type of error comprising a data bit error, a parity bit error, or a multi-bit error. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system that supports error type indication is shown in accordance with examples disclosed herein.

[0010] Figure 2 An example of a device that supports error type indication is shown in accordance with examples disclosed herein.

[0011] Figure 3 An example of a device that supports error type indication is shown in accordance with examples disclosed herein.

[0012] Figure 4 An example of a device that supports error type indication is shown in accordance with examples disclosed herein.

[0013] Figure 5 An example of a process flow that supports error type indication is shown in accordance with examples disclosed herein.

[0014] Figure 6 A block diagram illustrating a memory device supporting error type indication is shown in accordance with examples of the present disclosure.

[0015] Figure 7 A block diagram illustrating a host device supporting error type indication is shown in accordance with examples of the present disclosure.

[0016] Figure 8 And 9 A flow diagram illustrating one or more methods supporting error type indication in accordance with examples disclosed herein is shown. DETAILED DESCRIPTION

[0017] Devices, such as electronic devices, can improve reliability by performing error detection and correction on data read from a memory array of the device. To do so, the device can encode data prior to storing the data in the memory array. Upon receiving a read command, the device can read and decode the data so that the device can detect and correct any errors prior to, for example, sending the data to a requesting device (e.g., a host). Devices implementing such error correction schemes can encounter different types of errors, but can be unable to classify the errors or indicate the type of error to the requesting device. As a result, the requesting device can be unaware of the type of error detected or corrected or both by the device, which can negatively impact system performance.

[0018] In accordance with the techniques described herein, a device can transmit one or more error flags to, for example, a requesting device (e.g., a host) that indicate a type of error detected or corrected or both in a set of data returned (e.g., already returned, concurrently returned, or to be returned) by the device. The error flags can be generated by circuitry coupled with a decoder of the device. The circuitry can perform a logical operation on syndrome bits input into the decoder and error indication bits output by the decoder. The result of the logical operation can be one or more error flags in the form of bits that individually or collectively indicate a particular type of error in a codeword. By transmitting the error flags to the requesting device, the device can indicate whether a particular type of error detected exists in the set of data returned to the requesting device.

[0019] Features of the disclosure are first described in the context of a system as described with reference to Figure 1 Features of the disclosure are described in the context of a device as described with reference to Figures 2-4 Additional features of the disclosure are described in the context of a process flow as described with reference to Figure 5 These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams and flowcharts related to error type indication as described with reference to Figures 6-9 These and other features of the disclosure are further illustrated by and described with reference to apparatus diagrams and flowcharts related to error type indication as described with reference to

[0020] Figure 1 An example of a system 100 that supports error type indication is shown in accordance with examples disclosed herein. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 can include one or more memory devices 110, but aspects of the one or more memory devices 110 can be described in the context of a single memory device (e.g., the memory device 110).

[0021] The system 100 can include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular telephone, a wearable device, an internet-connected device, a vehicle controller, etc. The memory device 110 can be a component of a system that can be used to store data for one or more other components of the system 100.

[0022] At least portions of the system 100 can be an example of the host device 105. The host device 105 can be an example of a processor or other circuitry within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular telephone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, the host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 can be referred to as a host or host device 105.

[0023] The memory device 110 can be a standalone device or component that can be used to provide physical memory addresses / space that can be used or referenced by the system 100. In some examples, the memory device 110 can be configurable to work with one or more different types of host devices. Signaling between the host device 105 and the memory device 110 can be used to support one or more of modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for physical packaging of the host device 105 and the memory device 110, clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other factors.

[0024] Memory device 110 can be operable to store data for components of host device 105. In some examples, memory device 110 can act as a slave type device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands can include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0025] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. Components of host device 105 can be coupled with each other using bus 135.

[0026] Processor 125 can be operable to provide control or other functionality for at least portions of system 100 or at least portions of host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 can be implemented by or be a part of processor 125.

[0027] BIOS component 130 can be a software component that includes a BIOS operated as firmware that can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and the various components of system 100 or host device 105. BIOS component 130 can include a program or software stored in one or more of read only memory (ROM), flash memory, or other nonvolatile storage.

[0028] In some examples, system 100 or host device 105 can include an I / O controller. The I / O controller can manage data communication between processor 125 and peripheral components, input devices, or output devices. The I / O controller can manage peripheral devices that are not integrated with or are external to system 100 or host device 105. In some examples, the I / O controller can represent a physical connection or port to external peripheral components.

[0029] In some examples, system 100 or host device 105 can include an input component, an output component, or both. An input component can represent a device or signal external to system 100 that provides input to system 100 or to a component thereof. In some examples, an input component can include a user interface or an interface to or between other devices. In some examples, an input component can be a peripheral device interfaced with system 100 via one or more peripheral components, or can be managed by an I / O controller. An output component can represent a device or signal external to system 100 that receives output from system 100 or any component thereof. Examples of output components can include a display, an audio speaker, a printing device, another processor on a printed circuit board, and the like. In some examples, an output can be a peripheral device interfaced with system 100 via one or more peripheral components, or can be managed by an I / O controller.

[0030] In some examples, memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired capacity or a specified capacity for data storage. In some examples (e.g., in low power double data rate (LPDDR) applications), memory device 110 can not include a device memory controller 155. Each memory die 160 can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 can be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections) where each memory cell can be used to store at least one bit of data. A memory device 110 that includes two or more memory dies can be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0031] Device memory controller 155 can include circuitry, logic, or components that can be used to control operations of memory device 110. Device memory controller 155 can include hardware, firmware, or instructions that enable memory device 110 to perform various operations, and can be used to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 can be used to communicate with one or more of external memory controller 120, the one or more memory dies 160, or processor 125. In some examples, device memory controller 155 can control operations of memory device 110 described herein in conjunction with local memory controllers 165 of memory dies 160.

[0032] In some examples, the memory device 110 can receive data or commands or both from the host device 105. For example, the memory device 110 can receive a write command instructing the memory device 110 to store data for the host device 105 or a read command instructing the memory device 110 to provide data stored in the memory die 160 to the host device 105.

[0033] The local memory controller 165 (e.g., local to the memory die 160) can include circuitry, logic, or components that can be used to control operations of the memory die 160. In some examples, the local memory controller 165 can be used to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155 and the local memory controller 165 or the external memory controller 120 that can perform the various functions described herein. As such, the local memory controller 165 can be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165 or both can include a receiver to receive signals (e.g., from the external memory controller 120), a transmitter to transmit signals (e.g., to the external memory controller 120), a decoder to decode or demodulate received signals, an encoder to encode or modulate signals to be transmitted, or various other circuitry or controllers operable to support the operations of the described device memory controller 155 or local memory controller 165 or both.

[0034] The external memory controller 120 can be used to enable the transfer of one or more of information, data, or commands between components of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 can translate or interpret communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or the host device 105 or the functions described herein can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software or some combination thereof implemented by the processor 125 or other components of the system 100 or the host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or the functions described herein can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0035] The components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be operable to support communications between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and a memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. A signal path can be an example of an electrically conductive path that can be used to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of an electrically conductive input or output point of a device of the system 100, and a pin can be operable to function as part of a channel.

[0036] The channels 115 (and associated signal paths and terminals) can be dedicated to communicating one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be communicated on the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal can be registered for each clock period (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock period (e.g., on a rising edge and a falling edge of a clock signal).

[0037] The system 100 can include any number of non-transitory computer- readable media that support data separation for garbage collection. For example, the host device 105 or the memory device 110 can include or otherwise have access to one or more non-transitory computer-readable media (e.g., firmware) that store instructions for performing the functions attributed herein to the host device 105 or the memory device 110. For example, such instructions, when executed by the host device 105 (e.g., by the processor 125 or the external memory controller 120) or by the memory device 110 (e.g., by the device memory controller 155 or the local memory controller 165), can cause the host device 105 or the memory device 110 to perform the associated functions as described herein.

[0038] In some cases, data in the memory device 110 can be stored incorrectly or corrupted over time, resulting in one or more errors in the data. To improve the reliability of the memory device 110, the memory device 110 can implement an error correction scheme to detect, identify, and correct such errors. For example, prior to storing a set of data, the memory device 110 can use an error correction code to generate a codeword consisting of data bits and corresponding parity bits that can be used by the memory device 110 to detect errors in the codeword. The parity bits of the codeword can be generated by applying the error correction code to the set of data, which can involve running the set of data through a logic circuit, such as consisting of a series of components, such as XOR logic gates. The memory device 110 can store the set of data and the parity bits (collectively referred to as a “codeword”) in memory, such that one or more errors in the codeword can be detected during a read operation. For example, the memory device 110 can detect errors in the codeword based on syndrome bits generated (e.g., during a decoding process) from the bits of the codeword stored in memory.

[0039] The memory device 110 can encounter different types of errors when decoding a codeword. For example, the memory device 110 can detect a data bit error (or “single bit error” (SBE)), which can be an error in a data bit of the codeword. As another example, the memory device 110 can detect a parity bit error, which can be an error in a parity bit of the codeword. As another example, the memory device 110 can detect an address bit error, which can be an error in an address bit of the codeword in instances where the error correction code is applied to address bits in addition to data bits. As another example, the memory device 110 can detect a multi-bit error (MBE), which can be an error in two or more bits of the codeword. In some instances, a multi-bit error can also be referred to as a ghost error. Further, the memory device 110 can detect no error at all (e.g., the set of data can be error-free).

[0040] Upon detecting an error in a codeword, the memory device 110 can correct the error (if the error is correctable) prior to returning the set of data to a requesting device (e.g., the host device 105). The memory device 110 can also indicate to the host device 105 that the set of data once had or now has an error detected by the memory device 110. However, the memory device 110 can not have a mechanism for indicating to the host device 105 the type of error detected by the memory device 110, which can impact or compromise the performance of the host device 105. For example, the host device 105 can treat the returned data as error-free even though the memory device 110 was unable to correct a detected error in the data (e.g., a multi-bit error), or can not take corrective measures that it could have taken had the type of error been known to the host device 105.

[0041] According to the techniques described herein, the memory device 110 can transmit a set of error flags in bit form to the host device 105 that individually or collectively represent one or more types of errors detected during a codeword decoding process. The host device 105 can process data of the codeword or take other measures based on the type of error indicated by the error flags, which can improve system performance. As used herein, a set can include one or more elements, such that a set of error flags, for example, can include one or more error flags.

[0042] Figure 2 An example of a device 200 that supports error type indication is shown in accordance with examples disclosed herein. The device 200 can include a memory 205 in which the device 200 stores information, such as codewords. The device 200 can also include syndrome generation circuitry 210, a decoder 215, correction circuitry 220, error classification circuitry 225, and a counter 230. As described herein, the error classification circuitry 225 can output one or more error flags that indicate a type of error detected in a codeword read from the memory 205. The error flags can be output to a host device (or other device) so that the host device can take into account the type of error when processing data from the codeword or interacting with the device 200. As described with reference to Figure 3 And 4 In contrast to the error classification circuitry described, the error classification circuitry 225 can be configured to transmit a respective error flag for each type of error that the decoder 215 can detect.

[0043] In the illustrated example, the components of the device 200 are configured for an error correction code that protects four data bits using three parity check bits (of course, the parity check bits are also protected by the error correction code). Such an error correction code (ECC) can be denoted as ECC(4, 3). However, the techniques described herein are not limited to ECC(4, 3) and can be implemented for different or more complex error correction codes, such as ECC(136, 128), etc. For other error correction codes, different numbers of logic gates and / or different numbers of inputs per logic gate can be used without departing from the techniques described herein.

[0044] At a high level, the device 200 can store codewords in the memory 205. When a read command for a codeword is received, the syndrome generation circuitry 210 can generate syndrome bits for the codeword by performing logical operations on the bits of the codeword read from the memory 205. The decoder 215 can use the syndrome bits to detect one or more errors in the codeword (assuming the codeword has one or more errors, but this can not be the case). The decoder 215 can output one or more error indication bits that can cause the correction circuitry 220 to correct errors in the data bits of the codeword before returning the data bits to the host device. The decoder 215 can also drive various components of the error classification circuitry 225, which can output error flags indicating the type of error detected by the decoder 215 (or no error if none was detected). Additional details are described herein regarding the functions of the various components of the device 300.

[0045] As noted, the error classification circuitry 225 can output error flags, each of which can represent a respective error type. For example, the error classification circuitry 225 can output a codeword error flag indicating an error in the codeword, a multi-bit error flag indicating a multi-bit error, a parity bit error flag indicating a parity bit error, and a data bit error flag indicating a data bit error. Each of the error flags can be associated with the same codeword and can be transmitted over a respective wire. The transmission of the error flags can at least partially overlap in time with the transmission of the respective data from the correction circuitry 220, or can occur before or after the data transmission. Additionally, the error flags can be transmitted in parallel (e.g., during an overlapping time period) or serially (e.g., at different times). The error flags can also be referred to as bits, signals, indications, or other suitable terminology.

[0046] The error classification circuitry 225 can generate the codeword error flag by performing one or more OR operations on the syndrome bits of the codeword. For example, a logic gate 240 (e.g., an OR gate) can perform an OR operation on the syndrome bits (denoted as S0, S1, and S2) of the codeword decoded by the decoder 215. The logic gate 240 can output a logical zero when the syndrome bits are all logical zeros (which occurs when the codeword has no errors) and can output a logical one when one or more of the syndrome bits is a logical one (which occurs when the codeword has an error). Thus, the logic gate 240 can output a logical zero when the codeword has no errors and can output a logical one when the codeword has an error. Accordingly, the host device can determine whether an error was detected for the codeword based at least in part on the logical value of the codeword error flag. A single logic gate (as shown) or a combination of logic gates can be used to generate the codeword error flag.

[0047] Error classification circuitry 225 can generate the parity error flag by performing one or more OR operations on parity error indication bits of the codeword (e.g., bits that indicate which parity bit, if any, in the codeword has an error) and inverting the resulting signal. For example, logic gate 235-a (e.g., an OR gate) can perform an OR operation on parity error indication bits (e.g., denoted as El, E2, E3) of the parity bits of the codeword decoded by decoder 215. And inverter 245-a can invert the signal resulting from the OR operation. Logic gate 235-a can output a logical zero when all of the parity error indication bits are zero (which occurs when the parity bits are error free) and can output a logical one when one or more of the parity error indication bits is a logical one (which occurs when the parity bits have an error). Thus, inverter 245-a can output a logical one when the parity bits are error free and can output a logical zero when the parity bits have an error.

[0048] Error classification circuitry 225 can generate the data error flag by performing one or more OR operations on data error indication bits of the codeword (e.g., bits that indicate which data bit, if any, in the codeword has an error) and inverting the resulting signal. For example, logic gate 235-b (e.g., an OR gate) can perform an OR operation on data error indication bits (e.g., denoted as Ql to Q3) of the data bits of the codeword subjected to the decoding process by decoder 215. And inverter 245-b can invert the signal resulting from the OR operation. Logic gate 235-b can output a logical zero when all of the data error indication bits are zero (which occurs when the data bits are error free) and can output a logical one when one or more of the data error indication bits is a logical one (which occurs when the data bits have an error). Thus, inverter 245-b can output a logical one when the data bits are error free and can output a logical zero when the data bits have an error.

[0049] Although described with reference to a single OR operation performed by a single OR gate and a single inversion operation performed by a single inverter, respectively, multiple OR operations performed by multiple OR gates and multiple inversion operations performed by multiple inverters or some combination thereof can be used to generate the parity error flag and the data error flag.

[0050] When the decoder 215 is configured to detect unit errors (as opposed to multi-bit errors) and the codeword has multiple errors, the device 200 can be unable to correct the errors. Moreover, in such a case, the codeword error flag can conflict with the parity error flag and the data error flag. For example, the codeword error flag can indicate that there is an error in the codeword, but the parity error flag and the data error flag can indicate that there is no error in the codeword (or vice versa). This can occur when the syndrome bits indicate an error, but the location of the error indicated by the syndrome bits does not exist (e.g., the syndrome bits can indicate the tenth data bit in the codeword, but the codeword has fewer than ten data bits). For example, if a multi-bit error results in conflicting error flags, the host device incorrectly determines that there is no error in the codeword, which can negatively impact system performance. Thus, detection and indication of multi-bit errors can be desired.

[0051] The error classification circuitry 225 can generate the multi-bit error flag by performing one or more AND operations on the codeword error flag, the parity error flag, and the data bit error flag. For example, a logic gate 250 (e.g., an AND gate) can perform an AND operation on the codeword error flag output by the logic gate 240, the parity error flag output by the inverter 245-a, and the data error flag output by the inverter 245-a. The logic gate 250 can output a logic zero when there is no error detected in the codeword, parity bits, or data bits (e.g., the multi-bit error flag can be a logic zero when there are no multi-bit errors in the codeword). The logic gate 250 can output a logic one when there is an error in the codeword but no error in the parity bits or data bits or when there is an error in the parity bits and data bits but no error in the codeword (e.g., the multi-bit error flag can be a logic one when there are multi-bit errors in the codeword). Although described with reference to a single AND operation performed by a single AND gate, multiple AND operations performed by multiple AND gates can be used to generate the multi-bit error flag.

[0052] The syndrome generation circuitry 210 can generate syndrome bits (denoted as SO, SI, and S2) for a codeword stored in the memory 205. The syndrome bits can allow the decoder 215 to detect errors in the codeword. As described above, the codeword can be composed of data bits and parity bits protected by an error correcting code. For example, the codeword can include data bits 237— which can include data bit 0 (DO), data bit 1 (Dl), data bit 2 (D2), and data bit 3 (D30)— and parity bits 239, which can include parity bit 0 (P0), parity bit 1 (PI), and parity bit 2 (P2). Thus, the syndrome generation circuitry 210 can generate syndrome bits (e.g., SO, SI, S2) based on the data bits DO through D3 that can be included in the data bits 237. Additionally, the syndrome generation circuitry 210 can generate syndrome bits (e.g., SO, SI, S2) based on the parity bits P0 through P2.

[0053] The syndrome generation circuitry 210 can generate syndrome bits by performing logical operations on the bits in the codeword. For example, as shown, XOR gate A, XOR gate B, and XOR gate C can perform a logical XOR operation on the data bits D0 through D2. The bits output by XOR gates A, B, C can represent a version of the parity bits (e.g., P0, P1, P2) based on the data bits read from the memory, and thus are denoted as P0’, P1’, and P2’. To complete the generation of the syndrome bits (e.g., S0, S1, S2), the syndrome generation circuitry 210 can perform XOR operations on the stored parity bits (e.g., P0, P1, P2) and the generated parity bits (e.g., P0’, P1’, P2’). For example, XOR gate D can generate the syndrome bit S0 by performing a logical XOR operation on P0 and P0’. A similar analysis applies to XOR gate E and XOR gate F. Thus, the syndrome generation circuitry 210 can generate syndrome bits for a codeword stored in the memory 205.

[0054] The decoder 215 can decode the syndrome bits of a codeword to detect errors in the codeword. For example, the decoder 215 can decode the syndrome bits S0, S1, and S2 to detect errors in a codeword read from the memory 205. In some instances, if the syndrome bits (e.g., S0, S1, S2) are all logical zeros, the decoder 215 can detect that the codeword is error free. If one or more of the syndrome bits are logical ones, the decoder 215 can detect an error and determine the location of the error based on the values of the syndrome bits. Thus, the decoder 215 can perform a decoding process on a codeword to determine not only which bits, if any, are in error, but also the location of those bits.

[0055] Upon completion of the decoding process for a codeword, the decoder 215 can output error indication bits that indicate which bits in the codeword are in error. The error indication bits can enable the correction circuitry 220 to correct errors in the codeword and can drive various components of the error classification circuitry 225. The decoder 215 can output an error indication bit for each bit in a codeword, and the error indication bit can indicate the error status of the bit. Thus, the decoder 215 can output an error indication bit for each of the parity bits P0, P1, and P2; and the decoder 215 can output an error indication bit for each of the data bits D0, D1, D2, and D3. An error indication bit for a parity bit x can be referred to as a parity error indication bit and can be denoted as Ex. An error indication bit for a data bit y can be referred to as a data error indication bit and can be denoted as Qy.

[0056] In addition to outputting one or more error indication bits for each bit in a codeword, the decoder 215 can also output an error indication bit indicating whether the codeword has errors, denoted as QC. The error indication bit for a codeword can be referred to as a codeword error indication bit and can be transmitted to the counter 230 so that the device 200 can monitor the reliability of the device 200.

[0057] The correction circuitry 220 can correct errors in the data bits of a codeword before transmitting the data bits to a host device. The correction circuitry 220 can correct errors in the data bits by performing an XOR operation on the data bits and the data error indication flags for the data bits (as such an XOR operation will invert the data bits if the data error indication bit is a logical “1”, indicating an error). For example, when the data bit D0 has an error, the XOR gate J can correct the data bit D0 by performing an XOR operation on the data bit D0 and the error indication bit Q0. Similar analysis applies to the XOR gates G, H, and I. Thus, in addition to driving the various components of the error classification circuitry 225, the error indication bits can also drive the correction of the erroneous data bits in a codeword.

[0058] The device 200 can include one or more switches, such as the switch 255, that when appropriately activated can selectively couple different conductive paths. For example, the switch 255-a can selectively couple the memory 205 to different conductive paths coupled to the inputs of the XOR gates A, B, and C in order to load the appropriate data bits into the XOR gates A, B, and C. Similarly, the switch 255-b can selectively couple the memory 205 to different conductive paths coupled to the inputs of the XOR gates D, E, and F in order to load the appropriate parity bits into the XOR gates D, E, and F. And the switch 255-c can selectively couple the memory 205 to different conductive paths coupled to the inputs of the OR gates G through J in order to load the appropriate data bits into the OR gates G through J.

[0059] Although described in example configurations with reference to example logic gates, the error classification circuitry 225 can be composed of other types of logic gates (e.g., AND gates, NAND gates, OR gates, NOR, XOR gates, and NOT gates) in different configurations that can provide the functionality of the logic gates described herein or similar functionality. Additionally, logic operations described as being performed by some number of logic gates can be performed using a different number of logic gates in some examples.

[0060] Figure 3 An example of a device 300 that supports error type indication is shown in accordance with examples disclosed herein. The device 300 can include a memory 305 in which the device 300 stores information, such as codewords. The device 300 can also include syndrome generation circuitry 310, a decoder 315, correction circuitry 320, and a counter 330, which can be used as referencedFigure 2 The described corresponding components. In addition, the device 300 can include error classification circuitry 325, which can output one or more error flags indicative of a type of error detected in the codeword read from the memory 305. The error flags can be output to a host device (or other device) so that the host device can take into account the type of error when processing data from the codeword or interacting with the device 300. The switches 355 (e.g., switch 355-a, switch 355-b, and switch 355-c) can operate similarly to the switches 255 described with reference to FIG. 2. Figure 2 The described corresponding components. In addition, the device 300 can include error classification circuitry 325, which can output one or more error flags indicative of a type of error detected in the codeword read from the memory 305. The error flags can be output to a host device (or other device) so that the host device can take into account the type of error when processing data from the codeword or interacting with the device 300. The switches 355 (e.g., switch 355-a, switch 355-b, and switch 355-c) can operate similarly to the switches 255 described with reference to FIG. 2.

[0061] In comparison to the error classification circuitry 225, the error classification circuitry 325 can be configured to transmit a set of error flags (e.g., one or more error flags) that collectively indicate a type of error detected by the decoder 315 (e.g., the error classification circuitry 325 can encode the error type indication such that the number of bits used to transmit the error type indication is reduced relative to the number output by the error classification circuitry 225). For purposes of this disclosure, the error flags can be referred to as error bits. Figure 3

[0062] The error classification circuitry 325 can output a first error bit (Bl) and a second error bit (B2) that collectively indicate a type of error detected in the codeword. Each combination of logical values of the error bits can map to a respective type of error, as shown in Table 1. For example, when both the error bit Bl and the error bit 2 are logical zeros, a multi-bit error can be indicated. When the error bit Bl is a logical zero and the error bit B2 is a logical one, a data bit error can be indicated. When the error bit Bl is a logical one and the error bit B2 is a logical zero, a parity bit error can be indicated. And when both the error bit Bl and the error bit B2 are logical ones, no error can be indicated. The error bits can be generated by components of the error classification circuitry 325.

[0063] Table 1

[0064] Error Type B1 B2 Multi-bit error 0 0 Data bit error 0 1 Parity bit error 1 0 No error 1 1

[0065] The first error bit Bl can be generated by performing an OR operation on the signal output by the inverter 345 and the signal output by the logic gate 335-a, which can be a NOR gate as described with reference to FIG. 2. The second error bit B2 can be generated by performing an OR operation on the signal output by the inverter 345 and the signal output by the logic gate 335-b, which can be a NAND gate as described with reference to FIG. 2. Figure 2 ​An example of a logic gate 235-a is described (e.g., an OR gate). For example, logic gate 350-a (e.g., an OR gate) can perform an OR operation on a signal II that can be output from inverter 345 and a signal I2 that can be output from logic gate 335-a. The signal that is inverted by inverter 345 can be received from logic gate 340. Signal II can be a logical zero when the codeword is in error and a logical one when the codeword is not in error. Further, signal I2 can be a logical zero when the parity bit is not in error and a logical one when the parity bit is in error. Thus, error bit Bl can be a logical zero when the syndrome bit indicates that the codeword is in error and the parity error indication bit indicates that there is no error (which can occur when there is a multi-bit error or a data bit error).

[0066] A second error bit B2 can be generated by performing an OR operation on the signal output from inverter 345 and a signal output from logic gate 335-b, which can be a reference Figure 2 An example of a logic gate 235-b is described. For example, logic gate 350-b (e.g., an OR gate) can perform an OR operation on a signal II that can be output from inverter 345 and a signal I3 that can be output from logic gate 335-b (e.g., an OR gate). As mentioned, signal II can be a logical zero when the codeword is in error and a logical one when the codeword is not in error. Further, signal I3 can be a logical zero when the data bit is not in error and a logical one when the data bit is in error. Thus, error bit B2 can be a logical zero when the syndrome bit indicates that the codeword is in error and the data error indication bit indicates that there is no error (which can occur when there is a multi-bit error or a parity bit error).

[0067] The extended language and disclaimers described with reference to device 200 can similarly apply to aspects described with respect to device 300. For example, while described with reference to one or more operations performed by one or more gates or components, one or more error flags can be generated using any number of operations performed by any number of gates or using any number of operations performed by any number of various components. Various aspects of device 300 can be incorporated into device 200 and device 400, and vice versa.

[0068] Figure 4 An example of a device 400 that supports error type indication is shown in accordance with examples disclosed herein. While omitted in Figure 4 for ease of illustration, device 400 can include a reference Figure 2The described memory, syndrome generation circuitry, counters, and error correction circuitry. The apparatus 400 can also include a decoder 415 and error classification circuitry 425. The error classification circuitry 425 can be similar to the error classification circuitry 325, but can be configured to output an additional error flag that allows the apparatus 400 to indicate an address bit error in addition to the other types of errors described herein. For purposes of Figure 4 the error flag can be referred to as an error bit.

[0069] In some examples, a codeword can include address bits in addition to data bits and parity bits. For example, a codeword can include one or more bits that represent an address at which a data set was written. Such a codeword can be generated by applying an error correction code to the address bits in addition to the data set (e.g., the address bits can be seeded into the ECC) so that the parity bits protect the address bits as well as the data set. Including address bits in the codeword can allow the apparatus 400 to detect when an incorrect address was written or read.

[0070] As an example, consider a scenario in which the apparatus 400 receives a data set for storage in the memory. After receiving the data set, the apparatus 400 can generate a codeword based on the data bits and one or more address bits corresponding to the address at which the data is to be written. Rather than storing the entire codeword in the memory, however, the apparatus 400 can store only the data bits and parity bits of the codeword (e.g., the apparatus 400 can exclude the address bits from storage). When the apparatus 400 receives a read command for the data set, the apparatus 400 can generate (in a process similar to that described with reference to Figure 2 the address bits corresponding to the address that the apparatus 400 reads. The decoder 415 can then perform a decoding process on the syndrome bits of the codeword to detect any errors in the codeword. An error in the address bits can indicate that the apparatus 400 read from an incorrect address (e.g., the apparatus 400 wrote and read from a different memory address). If the decoder 415 detects an error in the address bits, the decoder 415 can output an address error indication flag (denoted as Ax for address bit x) that indicates which address bit contains the error. Thus, the address error indication bits can be used to detect inconsistencies between the write address and the read address, which can be referred to as an address error.

[0071] Error classification circuitry 425 can be configured to indicate an address error. For example, error classification circuitry 425 can output a first error bit (B1), a second error bit (B2), and a third error bit (B3) that collectively indicate a type of error detected in the codeword. Each combination of logic values of the error bits can map to a respective type of error, as shown in Table 2. For example, when all of the error bits are logic zeros, a multi-bit error can be indicated. When error bits B1 and B2 are logic zeros and error bit B3 is a logic one, an address bit error can be indicated. When error bits B1 and B3 are logic zeros and error bit B2 is a logic one, a data bit error can be indicated. When error bit B1 is a logic one and error bits B2 and B3 are logic zeros, a parity bit error can be indicated. And when all of the error bits are logic ones, no error can be indicated. The error bits can be generated by components of error classification circuitry 425.

[0072] Table 2

[0073] Error Type B1 B2 B3 Multi-bit error 0 0 0 Address bit error 0 0 1 Data bit error 0 1 0 Parity bit error 1 0 0 No error 1 1 1

[0074] First error bit B1 and second error bit B2 can be generated as described with reference to Figure 3 Thus, logic gate 435-a, logic gate 435-b, logic gate 440, inverter 445, logic gate 450-a, and logic gate 450-b can function similarly to the respective components described with reference to Figure 3

[0075] Third error bit B3 can be generated by performing an OR operation on a signal output by inverter 445 and a signal output by logic gate 435-c, which can perform an OR operation on address error indication bits (AO, Al) of the codeword. For example, logic gate 450-c can perform an OR operation on signal II, which can be output from inverter 445, and signal 14, which can be output from logic gate 435-c (e.g., an OR gate). As mentioned, signal II can be a logic zero when the codeword is in error and a logic one when the codeword is not in error. Further, signal 14 can be a logic zero when the address bits are not in error and a logic one when the address bits are in error. Thus, when the syndrome bits indicate a codeword error and the address error indication bits indicate no error (which can occur when there is a multi-bit error, a parity bit error, or a data bit error), error bit B3 can be a logic zero.

[0076] ​Various aspects of the device 400 can be incorporated into the device 200 and the device 300, and vice versa. For example, the logic gate 435-c can be added to the error classification circuitry 225 such that the device 200 outputs an address bit error flag that indicates an address bit error in the codeword. In such an example, the logic gate 435-c can output a logic zero when the address bit is error free and a logic one when the address bit is in error. Although described with reference to a single OR operation performed by a single OR gate, multiple OR operations performed by multiple OR gates can be used to generate the address error flag.

[0077] The expanded language and disclaimers described with reference to the device 200 can also apply to the device 400. For example, although described with reference to one or more operations performed by one or more gates or components, any number of operations performed by any number of gates or any number of operations performed by any number of various components can be used to generate one or more error flags.

[0078] Figure 5 An example of a process flow 500 that supports error type indication is shown in accordance with examples disclosed herein. In some examples, the process flow 500 can be implemented by a host device as described with reference to the host device 105. Of course, other types of devices can also implement the process flow 500. The process flow 500 can illustrate the operation of a device that receives the error flags described herein and uses the error flags to determine a type of error detected in a codeword. Figure 1

[0079] For ease of reference, the process flow 500 is described with reference to a host device. For example, aspects of the process flow 500 can be implemented by a host device coupled with a memory device. Additionally or alternatively, aspects of the process flow 500 can be implemented by a controller (e.g., a controller of a host device or a memory device) as well as other components. Additionally or alternatively, aspects of the process flow 500 can be implemented as instructions stored in a memory (e.g., firmware stored in the memory device 110). For example, the instructions, when executed by a controller (e.g., the processor 125 or the external memory controller 120), can cause the controller to perform the operations of the process flow 500.

[0080] At 505, a read command for a set of data can be transmitted. For example, a host device can transmit a read command for a set of data to a memory device. As used herein, the term “set” can refer to one or more elements in the set.

[0081] ​At 510, the host device can receive a set of data and a set of error flags from the memory device. The set of data and the set of error flags can be received based at least in part on transmission of the read command. The set of data can be received before the set of error flags, after the set of error flags, or concurrently with the set of error flags (e.g., the reception of the set of data can at least partially overlap in time with the reception of the set of error flags). The set of error flags can be received serially (e.g., at different times) or partially or fully in parallel (e.g., multiple flags can be received concurrently). In some instances, the set of error flags includes error flags received over different pins and / or conductive paths. In some instances, the set of error flags includes error flags received over the same conductive path at different times (e.g., the error flags can be time-division multiplexed).

[0082] At 515, the logical values of the error flags can be determined using various instances of circuitry or other components.

[0083] At 520, the logical values of the error flags can be associated or mapped to one or more error types. For example, if the error correction circuitry of the memory device is configured as shown in Figure 2 , the host device can associate each error flag with a respective error type described with reference to Figure 2 . If the error correction circuitry of the memory device is configured as shown in Figure 3 or Figure 4 , the host device can associate a set of logical values with a particular error type described with reference to Figure 3 and Figure 4 .

[0084] At 525, an error type of the code word can be determined based at least in part on the logical values of the set of error flags and the determined associations. For example, the host device can determine that a code word error, a multi-bit error, a parity error, a data error, an address bit error, or no error was detected in the code word.

[0085] At 530, the data can be processed and / or the memory device can be operated based at least in part on the error type. For example, if the set of error flags indicates a multi-bit error (e.g., because the code word has at least two errors that the memory device cannot correct), the host device can discard the set of data. As another example, if an address error is indicated (e.g., because the memory device returned an erroneous set of data), the host device can transmit a second read command for the set of data. As another example, the host device can instruct the memory device to perform one or more procedures that improve the reliability of the memory device (e.g., if a threshold number of errors are detected within a threshold amount of time). Thus, the host device can make one or more operational decisions based on the error type detected for the code word, which can improve system performance, among other benefits.

[0086] Figure 6 A block diagram 600 showing a memory device 605 that supports error type indication according to examples disclosed herein is shown. The memory device 605 can be an example of aspects of a device as described with reference to Figures 2 to 4 The memory device 605 can include a decoder 610, a first logic component 615, a second logic component 620, a first inverter 625, a second inverter 630, a third logic component 635, a fourth logic component 640, a fifth logic component 645, a sixth logic component 650, a third inverter 655, a seventh logic component 660, an eighth logic component 665, and a fourth inverter 670. Each of these modules can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0087] The decoder 610 can perform an error detection procedure on a codeword protected by an error correcting code.

[0088] In some examples, the decoder 610 can output, based on the error detection procedure, a first set of bits representing error flags for a set of parity check bits included in the codeword and a second set of bits representing error flags for a set of data bits included in the codeword. The first logic component 615 can perform a first logical OR operation on the first set of bits representing error flags for the set of parity check bits included in the codeword. The first logic component 615 can be one or more logical OR gates or a circuit configured to function as one or more logical OR gates. The second logic component 620 can perform a second logical OR operation on the second set of bits representing error flags for the set of data bits included in the codeword. The second logic component 620 can be one or more logical OR gates or a circuit configured to function as one or more logical OR gates.

[0089] The first inverter 625 can invert a first signal based on the first logical OR operation. The second inverter 630 can invert a second signal based on the second logical OR operation.

[0090] The third logic component 635 can perform a logical AND operation on the inverted first signal and the inverted second signal. The third logic component 635 can be one or more logical AND gates or a circuit configured to function as one or more logical AND gates. The fourth logic component 640 can perform a third logical OR operation on a set of syndrome bits for the codeword, where a third signal based on the third logical OR operation is performed a logical AND operation. The fourth logic component 640 can be one or more logical OR gates or a circuit configured to function as one or more logical OR gates.

[0091] In some examples, the fourth logic component 640 can perform a fifth logical OR operation on the set of syndrome bits for the codeword. In some examples, the fourth logic component 640 can perform a seventh logical OR operation on the set of syndrome bits for the codeword.

[0092] The fifth logic component 645 can perform a third logical OR operation on the first signal based on the first logical OR operation. The fifth logic component 645 can be one or more logic OR gates or circuitry configured to function as one or more logic OR gates. In some examples, the fifth logic component 645 can perform a fourth logical OR operation on the first signal based on the first logical OR operation.

[0093] The sixth logic component 650 can perform a fourth logical OR operation on the second signal based on the second logical OR operation. The sixth logic component 650 can be one or more logic OR gates or circuitry configured to function as one or more logic OR gates. In some examples, the sixth logic component 650 can perform a fifth logical OR operation on the second signal based on the second logical OR operation.

[0094] The third inverter 655 can invert the third signal based on the fifth logical OR operation, where the third logical OR operation is performed on the inverted third signal and the fourth logical OR operation is performed on the inverted third signal.

[0095] The seventh logic component 660 can perform a third logical OR operation on a third set of bits representing error flags for a set of address bits included in a codeword. The seventh logic component 660 can be one or more logic OR gates or circuitry configured to function as one or more logic OR gates. The eighth logic component 665 can perform a sixth logical OR operation on a third signal based on the third logical OR operation. The eighth logic component 665 can be one or more logic OR gates or circuitry configured to function as one or more logic OR gates.

[0096] The fourth inverter 670 can invert the fourth signal based on the seventh logical OR operation, where the fourth logical OR operation, the fifth logical OR operation, and the sixth logical OR operation are performed on the inverted fourth signal.

[0097] Figure 7 A block diagram 700 showing a host device 705 that supports error type indication in accordance with examples as disclosed herein is shown. The host device 705 can be an example of aspects of the host device described with reference to Figure 1 Examples of aspects of the host device are described. The host device 705 can include a driver 710, a receiver 715, and a processor 720. Each of these modules can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0098] The driver 710 can transmit a read command for a data set to a memory device. The driver 710 can be or include a transmitter, a transceiver, or a circuit configured to function as a transmitter or a transceiver. The receiver 715 can receive the data set from the memory device based on transmitting the read command. The receiver 715 can be or include a transceiver, a data bus interface, or a circuit configured to function as a transceiver or a data bus interface. In some examples, the receiver 715 can receive, from the memory device, a set of bits associated with the data set and indicative of a type of error detected during an error detection procedure for the data set, the type of error including a data bit error, a parity bit error, or a multi-bit error.

[0099] In some cases, the host device 705 is configured to receive the set of bits at least partially overlapping in time with receiving the data set. In some cases, the host device 705 is configured to receive the set of bits over different wires. In some cases, the host device 705 is configured to receive the set of bits over the same wire at different times.

[0100] The processor 720 can determine a type of error detected during the error detection procedure based on respective logical values of the first bit, the second bit, and the third bit. In some examples, the processor 720 can process the data set based on the determined type of error.

[0101] In some examples, the processor 720 can determine that the set of bits has a set of logical values associated with the type of error.

[0102] In some examples, the processor 720 can determine the type of error detected during the error detection procedure based on the set of logical values being associated with the type of error. In some examples, the processor 720 can process the data set based on the determined type of error.

[0103] In some examples, the processor 720 can determine a first logical value of the first bit and a second logical value of the second bit.

[0104] In some examples, the processor 720 can determine the type of error detected during the error detection procedure based on the type of error being associated with the first logical value of the first bit and the second logical value of the second bit. In some examples, the processor 720 can process the data set based on the determined type of error.

[0105] In some examples, the processor 720 can determine a third logical value of the third bit, wherein the address bit error is determined based on the address bit error being associated with the third logical value of the third bit.

[0106] Figure 8A flow diagram illustrating a method 800 of one or more methods supporting error type indication in accordance with aspects of the present disclosure is shown. The operations of method 800 can be implemented by a memory device or its components described herein. For example, the operations of method 800 can be performed by a memory device as described with reference to Figure 6 The memory device described is described. In some examples, the memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the described functions using special-purpose hardware.

[0107] At 805, the method can include performing, by a decoder, an error detection procedure on a codeword protected by an error correcting code. The operations of 805 can be performed according to the methods described herein. In some examples, aspects of the operations of 805 can be performed by a decoder as described with reference to Figure 6 The decoder described.

[0108] At 810, the method can include outputting, by the decoder, a first set of bits representing error flags for a set of parity bits included in the codeword and a second set of bits representing error flags for a set of data bits included in the codeword based on the error detection procedure. The operations of 810 can be performed according to the methods described herein. In some examples, aspects of the operations of 810 can be performed by a decoder as described with reference to Figure 6 The decoder described.

[0109] At 815, the method can include performing a first logical OR operation on the first set of bits representing error flags for the set of parity bits included in the codeword. The operations of 815 can be performed according to the methods described herein. In some examples, aspects of the operations of 815 can be performed by a first logic component as described with reference to Figure 6 The first logic component described.

[0110] At 820, the method can include performing a second logical OR operation on the second set of bits representing error flags for the set of data bits included in the codeword. The operations of 820 can be performed according to the methods described herein. In some examples, aspects of the operations of 820 can be performed by a second logic component as described with reference to Figure 6 The second logic component described.

[0111] In some examples, an apparatus as described herein can perform one or more methods, such as the method 800. The apparatus can include features, means, or instructions for (e.g., a non-transitory computer-readable medium storing instructions executable by a processor to) performing an error detection procedure on a code word protected by an error correcting code by a decoder, outputting, by the decoder, a first set of bits representing error flags for a set of parity check bits included in the code word and a second set of bits representing error flags for a set of data bits included in the code word based at least in part on the error detection procedure, performing a first logical OR operation on the first set of bits representing error flags for the set of parity check bits included in the code word, and performing a second logical OR operation on the second set of bits representing error flags for the set of data bits included in the code word.

[0112] The method 800 and some examples of the apparatus described herein can further include operations, features, means, or instructions for inverting a first signal that can be based on the first logical OR operation and inverting a second signal that can be based on the second logical OR operation.

[0113] The method 800 and some examples of the apparatus described herein can further include operations, features, means, or instructions for performing a logical AND operation on the inverted first signal and the inverted second signal.

[0114] The method 800 and some examples of the apparatus described herein can further include operations, features, means, or instructions for performing a third logical OR operation on a set of syndrome bits of the code word, where a third signal that can be based on the third logical OR operation can be subjected to the logical AND operation.

[0115] The method 800 and some examples of the apparatus described herein can further include operations, features, means, or instructions for performing a third logical OR operation on the first signal that can be based on the first logical OR operation and performing a fourth logical OR operation on the second signal that can be based on the second logical OR operation.

[0116] The method 800 and some examples of the apparatus described herein can further include operations, features, means, or instructions for performing a fifth logical OR operation on a set of syndrome bits of the code word and inverting a third signal that can be based on the fifth logical OR operation, where the inverted third signal can be subjected to the third logical OR operation and the inverted third signal can be subjected to the fourth logical OR operation.

[0117] The method 800 and some examples of the apparatus described herein can further include operations, features, means, or instructions for performing a third logical OR operation on a third set of bits representing error flags for a set of address bits included in the code word.

[0118] The method 800 and some examples of the apparatus described herein can further include operations, features, means, or instructions for performing a fourth logical OR operation on a first signal that can be based on the first logical OR operation, performing a fifth logical OR operation on a second signal that can be based on the second logical OR operation, and performing a sixth logical OR operation on a third signal that can be based on the third logical OR operation.

[0119] The method 800 and some examples of the apparatus described herein can further include operations, features, means, or instructions for performing a seventh logical OR operation on the syndrome bit set of the codeword and inverting a fourth signal that can be based on the seventh logical OR operation, wherein the fourth logical OR operation, the fifth logical OR operation, and the sixth logical OR operation can be performed on the inverted fourth signal.

[0120] In some examples, an apparatus as described herein can perform one or more methods, such as the method 800. The apparatus can include a decoder configured to detect one or more errors in a codeword, a first logic gate coupled with the decoder and configured to perform a first logical OR operation on a first set of bits output from the decoder, the first set of bits representing error flags of a set of parity bits included in the codeword, and a second logic gate coupled with the decoder and configured to perform a second logical OR operation on a second set of bits output from the decoder, the second set of bits representing error flags of a set of data bits included in the codeword.

[0121] Some examples of the apparatus can include a first inverter coupled with the first logic gate and configured to invert a signal from the first logic gate that can be based on the first logical OR operation, and a second inverter coupled with the second logic gate and configured to invert a signal from the second logic gate that can be based on the second logical OR operation.

[0122] Some examples of the apparatus can include a third logic gate coupled with the first inverter and the second inverter and configured to perform a logical AND operation on the signal from the first inverter and the signal from the second inverter.

[0123] Some examples of the apparatus can include a fourth logic gate coupled with the decoder and configured to perform a logical OR operation on a set of syndrome bits of the codeword, wherein the third logic gate can be configured to perform a logical AND operation on a signal from the fourth logic gate.

[0124] Some examples of the apparatus can include a third logic gate configured to perform a third logical OR operation on a signal from the first logic gate that can be based on the first logical OR operation, and a fourth logic gate configured to perform a fourth logical OR operation on a signal from the second logic gate that can be based on the second logical OR operation.

[0125] Some examples of the apparatus can include a fifth logic gate coupled with the decoder and configured to perform a logical OR operation on the set of syndrome bits of the codeword; and an inverter coupled with the fifth logic gate and configured to invert a signal from the fifth logic gate, wherein the third logic gate can be configured to perform a third logical OR operation on the signal from the inverter, and wherein the fourth logic gate can be configured to perform a fourth logical OR operation on the signal from the inverter.

[0126] Some examples of the apparatus can include a third logic gate coupled with the decoder and configured to perform a third logical OR operation on a third set of bits output from the decoder, the third set of bits representing an error flag for a set of address bits included in the codeword.

[0127] Some examples of the apparatus can include a fourth logic gate coupled with the first logic gate and configured to perform a fourth logical OR operation on a signal from the first logic gate; a fifth logic gate coupled with the second logic gate and configured to perform a fifth logical OR operation on a signal from the second logic gate; and a sixth logic gate coupled with the third logic gate and configured to perform a sixth logical OR operation on a signal from the third logic gate.

[0128] Some examples of the apparatus can include a seventh logic gate coupled with the decoder and configured to perform a seventh logical OR operation on the set of syndrome bits of the codeword; and an inverter coupled with the seventh logic gate and configured to invert a signal from the seventh logic gate, wherein the fourth logic gate can be configured to perform a fourth logical OR operation on the signal from the inverter, the fifth logic gate can be configured to perform a fifth logical OR operation on the signal from the inverter, and the sixth logic gate can be configured to perform a sixth logical OR operation on the signal from the inverter.

[0129] Figure 9 A flow diagram illustrating a method 900 for supporting error type indication in accordance with aspects of the present disclosure is shown. The operations of method 900 can be implemented by a host device or its components as described herein. For example, the operations of method 900 can be performed by a host device as described with reference to FIGS. 1-8. In some examples, a host device can execute a set of instructions to control the functional elements of the host device to perform the described functions. Additionally or alternatively, the host device can perform aspects of the described functions using special-purpose hardware. Figure 7 A flow diagram illustrating a method 900 for supporting error type indication in accordance with aspects of the present disclosure is shown. The operations of method 900 can be implemented by a host device or its components as described herein. For example, the operations of method 900 can be performed by a host device as described with reference to FIGS. 1-8. In some examples, a host device can execute a set of instructions to control the functional elements of the host device to perform the described functions. Additionally or alternatively, the host device can perform aspects of the described functions using special-purpose hardware.

[0130] At 905, the method can include transmitting, to a memory device, a read command for a set of data. The operations of 905 can be performed according to the methods described herein. In some examples, aspects of the operations of 905 can be performed by a driver as described with reference to FIGS. 1-8. Figure 7 A flow diagram illustrating a method 900 for supporting error type indication in accordance with aspects of the present disclosure is shown. The operations of method 900 can be implemented by a host device or its components as described herein. For example, the operations of method 900 can be performed by a host device as described with reference to FIGS. 1-8. In some examples, a host device can execute a set of instructions to control the functional elements of the host device to perform the described functions. Additionally or alternatively, the host device can perform aspects of the described functions using special-purpose hardware.

[0131] At 910, the method can include receiving a set of data from the memory device based on transmitting the read command. The operations of 910 can be performed according to the methods described herein. In some examples, aspects of the operations of 910 can be performed by a receiver as described with reference to FIGs. Figure 7 The receiver described above.

[0132] At 915, the method can include receiving, from the memory device, a set of bits associated with the set of data and indicative of a type of error detected during an error detection procedure for the set of data, the type of error including a data bit error, a parity bit error, or a multi-bit error. The operations of 915 can be performed according to the methods described herein. In some examples, aspects of the operations of 915 can be performed by a receiver as described with reference to FIGs. Figure 7 The receiver described above.

[0133] In some examples, an apparatus as described herein can perform a method, such as method 900. The apparatus can include features, means, or instructions for transmitting, to a memory device, a read command for a set of data, receiving, from the memory device based on transmitting the read command, the set of data, and receiving, from the memory device, a set of bits associated with the set of data and indicative of a type of error detected during an error detection procedure for the set of data, the type of error including a data bit error, a parity bit error, or a multi-bit error, e.g., a non-transitory computer-readable medium storing instructions executable by a processor.

[0134] Method 900 and some examples of the apparatus described herein can further include operations, features, means, or instructions for determining a type of error detected during the error detection procedure based on respective logical values of the first bit, the second bit, and the third bit, and processing the set of data based on the determined type of error.

[0135] Method 900 and some examples of the apparatus described herein can further include operations, features, means, or instructions for determining that the set of bits can have a set of logical values associated with the type of error, determining a type of error detected during the error detection procedure based on the set of logical values being associated with the type of error, and processing the set of data based on the determined type of error.

[0136] In method 900 and some examples of the apparatus described herein, the set of bits can include operations, features, means, or instructions for determining a first logical value of the first bit and a second logical value of the second bit, determining a type of error detected during the error detection procedure based on the type of error being associated with the first logical value of the first bit and the second logical value of the second bit, and processing the set of data based on the determined type of error.

[0137] In some examples of the method 900 and the apparatus described herein, the error type can include operations, features, means, or instructions for determining a third logic value of a third bit, where the address bit error can be determined based on the address bit error being associated with the third logic value of the third bit.

[0138] In some examples of the method 900 and the apparatus described herein, the apparatus can be configured to receive the set of bits at least partially overlapping in time with receiving the set of data. In some examples of the method 900 and the apparatus described herein, the apparatus can be configured to receive the set of bits over different wires. In some examples of the method 900 and the apparatus described herein, the apparatus can be configured to receive the set of bits over the same wire at different times.

[0139] In some examples, the techniques described herein can be implemented by an apparatus. The apparatus can include a decoder configured to detect one or more errors in a codeword, a first logic gate coupled with the decoder and configured to perform a first logical OR operation on a first set of bits output from the decoder, the first set of bits representing error flags included in a set of parity bits in the codeword, and a second logic gate coupled with the decoder and configured to perform a second logical OR operation on a second set of bits output from the decoder, the second set of bits representing error flags included in a set of data bits in the codeword.

[0140] In some examples, the apparatus can include a first inverter coupled with the first logic gate and configured to invert a signal from the first logic gate based at least in part on the first logical OR operation, and a second inverter coupled with the second logic gate and configured to invert a signal from the second logic gate based at least in part on the second logical OR operation. In some examples, the apparatus can include a third logic gate coupled with the first inverter and the second inverter and configured to perform a logical AND operation on the signal from the first inverter and the signal from the second inverter. In some examples, the apparatus can include a fourth logic gate coupled with the decoder and configured to perform a logical OR operation on a set of syndrome bits of the codeword, where the third logic gate is configured to perform a logical AND operation on the signal from the fourth logic gate.

[0141] In some examples, the device can include a third logic gate configured to perform a third logical OR operation on a signal from the first logic gate that is based at least in part on the first logical OR operation; and a fourth logic gate configured to perform a fourth logical OR operation on a signal from the second logic gate that is based at least in part on the second logical OR operation. In some examples, the device can include a fifth logic gate coupled with the decoder and configured to perform a logical OR operation on a set of syndrome bits of the codeword; and an inverter coupled with the fifth logic gate and configured to invert a signal from the fifth logic gate, wherein the third logic gate is configured to perform the third logical OR operation on a signal from the inverter, and wherein the fourth logic gate is configured to perform the fourth logical OR operation on a signal from the inverter.

[0142] In some examples, the device can include a third logic gate coupled with the decoder and configured to perform a third logical OR operation on a third set of bits output from the decoder, the third set of bits representing an error flag for a set of address bits included in the codeword. In some examples, the device can include a fourth logic gate coupled with the first logic gate and configured to perform a fourth logical OR operation on a signal from the first logic gate; a fifth logic gate coupled with the second logic gate and configured to perform a fifth logical OR operation on a signal from the second logic gate; and a sixth logic gate coupled with the third logic gate and configured to perform a sixth logical OR operation on a signal from the third logic gate. In some examples, the device can include a seventh logic gate coupled with the decoder and configured to perform a seventh logical OR operation on a set of syndrome bits of the codeword; and an inverter coupled with the seventh logic gate and configured to invert a signal from the seventh logic gate, wherein the fourth logic gate is configured to perform the fourth logical OR operation on a signal from the inverter, the fifth logic gate is configured to perform the fifth logical OR operation on a signal from the inverter, and the sixth logic gate is configured to perform the sixth logical OR operation on a signal from the inverter.

[0143] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods can be combined.

[0144] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can be represented by a bus of three (3) signals, where the bus can have various bit widths.

[0145] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which an electron is supported to flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of a signal between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) can be open or closed at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of a signal between connected components can be interrupted for a period of time, e.g., using one or more intervening components such as switches or transistors.

[0146] The term "coupled" refers to the condition of components moving from an open relationship between the components, in which a signal cannot currently be communicated between the components through a conductive path, to a closed relationship between the components, in which a signal can be communicated between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows a signal to flow between the other components via a conductive path that previously did not permit the flow of a signal.

[0147] The term "isolated" refers to a relationship between components in which a signal cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. Components that are isolated from each other by a switch that is positioned between the two components are isolated from each other when the switch is open. When a controller isolates two components, the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously permitted the flow of a signal.

[0148] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) is not absolute but is close enough to the characteristic to be of no significance.

[0149] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0150] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be conductive and can include heavily doped, e.g., degenerate, semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. A transistor can be "off' or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0151] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" or "advantageous over other examples." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0152] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of using a first reference label in combination with a second reference label that distinguishes among different instances of that component. For example, a first instance of a component might be referred to as "22," whereas a second instance of that same type of component might be referred to as "22a." The disclosure can refer to a component using only the first reference label, even if the component is comprised of multiple instances, such as the first and second instances of a component.

[0153] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0154] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0155] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a referring to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” is intended to be similarly interpreted as the phrase “based, at least in part, on.”

[0156] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0157] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a decoder configured to detect one or more errors in a codeword; a first logic gate coupled with the decoder and configured to perform a first logical OR operation on a first set of bits output from the decoder, the first set of bits representing error flags of a set of parity bits included in the codeword; and a second logic gate coupled with the decoder and configured to perform a second logical OR operation on a second set of bits output from the decoder, the second set of bits representing error flags of a set of data bits included in the codeword.

2. The memory device of claim 1, further comprising: a first inverter coupled with the first logic gate and configured to invert a signal from the first logic gate based at least in part on the first logical OR operation; a second inverter coupled with the second logic gate and configured to invert a signal from the second logic gate based at least in part on the second logical OR operation.

3. The memory device of claim 2, further comprising: a third logic gate coupled with the first inverter and the second inverter and configured to perform a logical AND operation on a signal from the first inverter and a signal from the second inverter.

4. The memory device of claim 3, further comprising: a fourth logic gate coupled with the decoder and configured to perform a logical OR operation on a set of syndrome bits of the codeword, wherein the third logic gate is configured to perform the logical AND operation on a signal from the fourth logic gate.

5. The memory device of claim 1, further comprising: a third logic gate configured to perform a third logical OR operation on a signal from the first logic gate based at least in part on the first logical OR operation; a fourth logic gate configured to perform a fourth logical OR operation on a signal from the second logic gate based at least in part on the second logical OR operation.

6. The memory device of claim 5, further comprising: a fifth logic gate coupled with the decoder and configured to perform a logical OR operation on a set of syndrome bits of the codeword; an inverter coupled with the fifth logic gate and configured to invert a signal from the fifth logic gate, wherein the third logic gate is configured to perform the third logical OR operation on a signal from the inverter, and wherein the fourth logic gate is configured to perform the fourth logical OR operation on the signal from the inverter.

7. The memory device of claim 1, further comprising: a third logic gate coupled with the decoder and configured to perform a third logical OR operation on a third set of bits output from the decoder, the third set of bits representing error flags of a set of address bits included in the codeword.

8. The memory device of claim 7, further comprising: a fourth logic gate coupled with the first logic gate and configured to perform a fourth logical OR operation on a signal from the first logic gate. ​ ​ ​ ​ a fifth logic gate coupled with the second logic gate and configured to perform a fifth logical OR operation on a signal from the second logic gate; and a sixth logic gate coupled with the third logic gate and configured to perform a sixth logical OR operation on a signal from the third logic gate.

9. The memory device of claim 8, further comprising: a seventh logic gate coupled with the decoder and configured to perform a seventh logical OR operation on a set of syndrome bits of the codeword; and an inverter coupled with the seventh logic gate and configured to invert a signal from the seventh logic gate, wherein the fourth logic gate is configured to perform the fourth logical OR operation on a signal from the inverter, the fifth logic gate is configured to perform the fifth logical OR operation on the signal from the inverter, and the sixth logic gate is configured to perform the sixth logical OR operation on the signal from the inverter.

10. A method performed by a memory device, the method comprising: performing, by a decoder, an error detection procedure on a codeword protected by an error correcting code; outputting, by the decoder, a first set of bits representing error flags for a set of parity check bits included in the codeword and a second set of bits representing error flags for a set of data bits included in the codeword based at least in part on the error detection procedure; performing a first logical OR operation on the first set of bits representing error flags for the set of parity check bits included in the codeword; and performing a second logical OR operation on the second set of bits representing error flags for the set of data bits included in the codeword.

11. The method of claim 10, further comprising: inverting a first signal based at least in part on the first logical OR operation; and inverting a second signal based at least in part on the second logical OR operation.

12. The method of claim 11, further comprising: performing a logical AND operation on the inverted first signal and the inverted second signal.

13. The method of claim 12, further comprising: performing a third logical OR operation on a set of syndrome bits of the codeword, wherein the logical AND operation is performed on a third signal based at least in part on the third logical OR operation.

14. The method of claim 10, further comprising: performing a third logical OR operation on a first signal based at least in part on the first logical OR operation; and performing a fourth logical OR operation on a second signal based at least in part on the second logical OR operation.

15. The method of claim 14, further comprising: performing a fifth logical OR operation on a set of syndrome bits of the codeword; and inverting a third signal based at least in part on the fifth logical OR operation, wherein the third logical OR operation is performed on the inverted third signal and the fourth logical OR operation is performed on the inverted third signal.

16. The method of claim 10, wherein the decoder outputs a third set of bits representing error flags for a set of address bits included in the codeword, the method further comprising: performing a third logical OR operation on a third set of bits representing error flags for the set of address bits included in the codeword.

17. The method of claim 16, further comprising: performing a fourth logical OR operation on a first signal based at least in part on the first logical OR operation; performing a fifth logical OR operation on a second signal based at least in part on the second logical OR operation; and performing a sixth logical OR operation on a third signal based at least in part on the third logical OR operation.

18. The method of claim 17, further comprising: performing a seventh logical OR operation on a set of syndrome bits of the codeword; and inverting a fourth signal based at least in part on the seventh logical OR operation, wherein the fourth logical OR operation, the fifth logical OR operation, and the sixth logical OR operation are performed on the inverted fourth signal.

19. A memory device, comprising: a controller configured to couple with a memory device, wherein the controller is configured to cause the memory device to: transmit, to the memory device, a read command for a set of data included in a codeword, the codeword further including a parity check bit; receive, from the memory device, the set of data based at least in part on transmitting the read command; receive, from the memory device, a set of error indication bits associated with the codeword, the set of error indication bits including a first error indication bit of a first set of error indication bits based at least in part on the set of data in the codeword and a second error indication bit of a second set of error indication bits based at least in part on the parity check bit in the codeword; and determine, based at least in part on the set of error indication bits, a type of error detected during an error detection procedure for the codeword, the type of error including a data bit error, a parity check bit error, or a multi-bit error.

20. The memory device of claim 19, wherein the first error indication bit is associated with a single data bit error and the second error indication bit is associated with a single parity check bit error, and wherein the controller is further configured to cause the memory device to: determine, based at least in part on respective logical values of the first error indication bit and the second error indication bit, the type of error detected during the error detection procedure; and process the set of data based at least in part on the determined type of error.

21. The memory device of claim 19, wherein the controller is further configured to cause the memory device to: determine that the set of error indication bits has a set of logical values associated with the type of error; determine, based at least in part on the set of logical values being associated with the type of error, the type of error detected during the error detection procedure; and process the set of data based at least in part on the determined type of error.

22. The memory device of claim 19, wherein the controller is further configured to cause the memory device to: determine a first logical value of the first error indication bit and a second logical value of the second error indication bit; ​ ​ determining a type of error detected during the error detection procedure based at least in part on the type of error being associated with the first logical value of the first error indication bit and the second logical value of the second error indication bit; and processing the set of data based at least in part on the determined type of error.

23. The memory device of claim 22, wherein the type of error comprises an address bit error and the set of bits comprises a third error indication bit, and wherein the controller is further configured to cause the memory device to: determine a third logical value of the third error indication bit, wherein the address bit error is determined based at least in part on the address bit error being associated with the third logical value of the third error indication bit.

24. The memory device of claim 19, wherein the memory device is configured to receive the set of error indication bits at least partially overlapping in time with receiving the set of data.

25. The memory device of claim 19, wherein the memory device is configured to receive the set of error indication bits over different wires.

26. The memory device of claim 19, wherein the memory device is configured to receive the set of error indication bits over the same wire at different times.

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