A method for manufacturing a shielded gate trench device

Abstract

The present application provides a method for manufacturing a shielded gate trench device, which relates to the field of semiconductor technology. First, an epitaxial layer with a trench is provided, and then a field oxide layer and a polycrystalline are grown in sequence based on the surface of the epitaxial layer and the trench, wherein the polycrystalline is located in the trench and on the surface of the epitaxial layer, and then oxygen is ion-implanted along the surface of the polycrystalline to oxidize the surface of the epitaxial layer and the polycrystalline in contact with the surface of the epitaxial layer, and an isolation layer is formed, and then a wet etching process is used to successively remove the polycrystalline and the isolation layer located on the surface of the isolation layer to form an epitaxial structure with polycrystalline, and finally the epitaxial structure is used to manufacture a shielded gate trench device. The method for manufacturing a shielded gate trench device provided by the present application has the advantages of low cost and improved production capacity.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a shielded gate trench device. Background Art

[0002] Shielded gate MOSFET (SGT-MOSFET) is an improved structure of U-MOSFET. Compared with traditional U-MOSFET power devices, SGT reduces Miller capacitance, speeds up the switching speed of the device, and realizes charge coupling effect, reduces the critical electric field strength in the drift region, reduces the on-resistance of the device, and reduces the switching loss. Therefore, it is widely used in medium and low voltage high-performance DC / DC converters, low voltage system motor control, motor drive and other fields, and plays a very important role in the field of medium and low voltage power devices.

[0003] In the process of manufacturing shielded gate MOSFET, it is necessary to deposit polycrystals in the grooves and then etch away the excess polycrystals. Since wet etching may simultaneously etch away the polycrystals in the grooves while etching the polycrystals on the surface of the epitaxial layer, affecting the performance of the device, dry etching is generally used in the prior art to remove the polycrystals on the surface of the epitaxial layer.

[0004] However, dry etching requires specific dry etching equipment, which has a high production cost; at the same time, dry etching is heavily dependent on equipment operation and has low production capacity.

[0005] In summary, in the prior art, when manufacturing shielded gate trench devices, there are problems of high cost and low production capacity. Summary of the invention

[0006] The purpose of the present application is to provide a method for manufacturing a shielded gate trench device to solve the problems of high cost and low production capacity in the prior art when manufacturing a shielded gate trench device.

[0007] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0008] The present application provides a method for manufacturing a shielded gate trench device, the method comprising:

[0009] providing an epitaxial layer having a trench;

[0010] Based on the surface of the epitaxial layer and the groove, a field oxide layer and a polycrystalline are successively grown, wherein the polycrystalline is located in the groove and on the surface of the epitaxial layer;

[0011] Ion implantation of oxygen along the surface of the polycrystal to oxidize the surface layer of the epitaxial layer and the polycrystal in contact with the surface layer of the epitaxial layer, and to form an isolation layer;

[0012] Using a wet etching process to successively remove the polycrystal located on the surface of the isolation layer and the isolation layer to form an epitaxial structure with polycrystals;

[0013] The epitaxial structure is used to manufacture a shielded gate trench device.

[0014] Optionally, the step of manufacturing a shielded gate trench device using the epitaxial structure includes:

[0015] Etching a portion of the polycrystalline and field oxide layers within the trench;

[0016] Growing a gate oxide layer based on the trench and the surface of the epitaxial layer, and continuing to deposit polycrystalline based on the trench to form a gate polycrystalline;

[0017] doping a surface layer of the epitaxial layer to form a body region, wherein the doping type of the body region is opposite to the doping type of the epitaxial layer;

[0018] Doping a surface layer of the body region to form a source region, wherein the doping type of the source region is the same as the doping type of the epitaxial layer;

[0019] Depositing a dielectric layer on the surface of the epitaxial layer, etching contact holes and then annealing;

[0020] Depositing a metal layer along the contact hole and the surface of the dielectric layer, and etching the metal layer to form a source and a gate;

[0021] A passivation layer is deposited along the surface of the metal layer and a window is photoetched;

[0022] A back metal is plated along the back side of the epitaxial layer to form a drain.

[0023] Optionally, before the step of depositing a metal layer along the contact hole and the surface of the dielectric layer, the method further comprises:

[0024] A barrier layer is deposited along the surface of the contact hole by using an MOCVD process.

[0025] Optionally, the step of etching the metal layer to form a source and a gate includes:

[0026] The metal layer is wet-etched and then dry-etched to form a source and a gate; the thickness of the wet etching is greater than or equal to the thickness of the dry etching.

[0027] Optionally, the epitaxial layer is N-type doped, and the step of doping the surface layer of the epitaxial layer comprises:

[0028] Performing P-type doping on the surface layer of the epitaxial layer;

[0029] The step of doping the surface layer of the body region comprises:

[0030] The surface layer of the body region is N-type doped.

[0031] Optionally, the step of depositing a dielectric layer on the surface of the epitaxial layer includes:

[0032] Based on the epitaxial layer, SiO 2 and borophosphosilicate glass, and the thickness of the borophosphosilicate glass is greater than or equal to SiO 2 Thickness.

[0033] Optionally, the step of depositing a metal layer along the contact hole and the surface of the dielectric layer includes:

[0034] Depositing tungsten metal based on the contact hole, wherein the tungsten metal is located in the contact hole and on the surface of the dielectric layer;

[0035] removing tungsten metal located on the surface of the dielectric layer;

[0036] Aluminum metal is deposited on the surface of the dielectric layer.

[0037] Optionally, the step of depositing a passivation layer along the surface of the metal layer and photolithographically forming a window comprises:

[0038] SiO2 and Si are deposited successively along the surface of the metal layer. 3 N 4 , where Si 3 N 4 The thickness is greater than or equal to the thickness of SiO2.

[0039] Optionally, the step of providing an epitaxial layer with a trench comprises:

[0040] providing a first doping type substrate;

[0041] growing a first doping type epitaxial layer based on the substrate;

[0042] The epitaxial layer is etched to form a trench.

[0043] Optionally, the step of providing a first doping type substrate includes:

[0044] Providing an N-type substrate;

[0045] The step of growing a first doping type epitaxial layer based on the substrate comprises:

[0046] An N-type epitaxial layer is grown based on the substrate.

[0047] Compared with the prior art, this application has the following beneficial effects:

[0048] The present application provides a method for manufacturing a shielded gate trench device, first providing an epitaxial layer with a trench, then growing a field oxide layer and a polycrystal based on the surface of the epitaxial layer and the trench, wherein the polycrystal is located in the trench and on the surface of the epitaxial layer, then ion-implanting oxygen along the surface of the polycrystal to oxidize the surface of the epitaxial layer and the polycrystal in contact with the surface of the epitaxial layer, and forming an isolation layer, then using a wet etching process to successively remove the polycrystal and the isolation layer located on the surface of the isolation layer to form an epitaxial structure with polycrystals, and finally using the epitaxial structure to manufacture a shielded gate trench device. Since the present application uses ion implantation to inject oxygen, the surface of the epitaxial layer and the polycrystal in contact with the surface of the epitaxial layer are oxidized, and then an isolation layer is formed, the polycrystal in the trench is isolated from the polycrystal on the surface of the epitaxial layer, and then the polycrystal on the surface of the isolation layer can be etched first by a wet etching process, and then the isolation layer is etched, which will not affect the polycrystal in the trench. The process of using wet etching instead of dry etching is realized, and wet etching does not require the use of specific equipment, so the cost is low and the production capacity is improved.

[0049] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 It is a schematic diagram of the structure in which the redundant polycrystal is not etched in the prior art.

[0052] Figure 2 It is a schematic diagram of a structure in which excess polycrystal has been etched in the prior art.

[0053] Figure 3 A first schematic flow chart of a method for manufacturing a shielded gate trench device provided in an embodiment of the present application.

[0054] Figure 4 A second flow chart of the method for manufacturing a shielded gate trench device provided in an embodiment of the present application.

[0055] Figure 5 This is a schematic diagram of the structure corresponding to S1022 provided in an embodiment of the present application.

[0056] Figure 6 A structural schematic diagram of etching a groove in an epitaxial layer is provided for an embodiment of the present application.

[0057] Figure 7 This is a schematic diagram of the structure corresponding to S1023 provided in the embodiment of the present application.

[0058] Figure 8 This is a schematic diagram of the structure corresponding to S104 provided in the embodiment of the present application.

[0059] Fig. 9 This is a first structural diagram corresponding to S106 provided in an embodiment of the present application.

[0060] Fig.10 A second structural diagram corresponding to S106 provided in an embodiment of the present application.

[0061] Fig.11 This is a schematic diagram of the structure corresponding to S108 provided in the embodiment of the present application.

[0062] Fig.12 A flowchart of the sub-steps corresponding to S110 provided in an embodiment of the present application.

[0063] Fig.13 This is a schematic diagram of the structure corresponding to S111 provided in an embodiment of the present application.

[0064] Fig.14 This is a schematic diagram of the structure corresponding to S112 provided in the embodiment of the present application.

[0065] Fig.15 This is a schematic diagram of the structure corresponding to S113 provided in an embodiment of the present application.

[0066] Fig.16 This is a schematic diagram of the structure corresponding to S114 provided in the embodiment of the present application.

[0067] Fig.17 This is a schematic diagram of the structure corresponding to S115 provided in the embodiment of the present application.

[0068] Fig.18 This is a schematic diagram of the structure corresponding to S116 provided in the embodiment of the present application.

[0069] Fig.19 This is a schematic diagram of the structure corresponding to S118 provided in the embodiment of the present application. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0071] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0072] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0073] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0074] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0075] As described in the background art, in the current process of manufacturing shielded gate MOSFET, it is necessary to deposit polycrystalline in the trench and then etch away the excess polycrystalline. Figure 1 In the prior art, after polycrystals are deposited in the epitaxial layer with grooves, polycrystals exist in the grooves and on the surface of the epitaxial layer, and the polycrystals in the grooves and on the surface of the epitaxial layer are interconnected. On this basis, if wet etching is used to remove the polycrystals on the surface of the epitaxial layer, a Figure 2 In the structure, the polycrystalline in the trench and the surface of the epitaxial layer are interconnected as one. When wet etching is performed, the polycrystalline in the trench may be etched away at the same time as the polycrystalline on the surface of the epitaxial layer, thus affecting the performance of the device.

[0076] Therefore, dry etching is commonly used in the prior art to remove polycrystalline on the surface of the epitaxial layer. However, dry etching requires specific dry etching equipment, which has a high production cost. At the same time, dry etching is heavily dependent on equipment operation and has low production capacity. In addition, since the dry etching in the prior art is anisotropic, it is easy to not etch completely at uneven surfaces and corners, leaving polycrystalline residues, which makes the device prone to short circuit.

[0077] In view of this, in order to solve the above-mentioned problems, the present application provides a method for manufacturing a shielded gate trench device, in which part of the epitaxial layer and the polycrystal are oxidized by ion implantation of oxygen to form an isolation layer, and then wet etching can be used to remove the polycrystal on the surface of the epitaxial layer without affecting the polycrystal in the trench, thereby achieving the effect of reducing costs and improving production capacity.

[0078] The following is an exemplary description of the method for manufacturing a shielded gate trench device provided by the present application:

[0079] As an alternative implementation, see Figure 3 , the shielded gate trench device manufacturing method comprises:

[0080] S102, providing an epitaxial layer with trenches.

[0081] S104, a field oxide layer and a polycrystalline are grown sequentially based on the surface of the epitaxial layer and the trench, wherein the polycrystalline is located in the trench and on the surface of the epitaxial layer.

[0082] S106, oxygen is ion-implanted along the surface of the polycrystal to oxidize the surface layer of the epitaxial layer and the polycrystal in contact with the surface layer of the epitaxial layer, and to form an isolation layer.

[0083] S108, using a wet etching process to successively remove the polycrystalline and the isolation layer located on the surface of the isolation layer to form an epitaxial structure with polycrystalline.

[0084] S110, manufacturing a shielded gate trench device using the epitaxial structure.

[0085] It should be noted that the polycrystalline described in the present application can be polycrystalline silicon. After oxygen is injected along the surface of the polycrystalline by ion implantation, by adjusting the implantation parameters, such as the implantation amount or the implantation speed, the surface layer of the epitaxial layer and the polycrystalline in contact with the surface layer of the epitaxial layer can be oxidized to form an isolation layer effect. The isolation layer can isolate the polycrystalline in the groove from the polycrystalline on the surface of the epitaxial layer, and then the polycrystalline on the surface of the isolation layer can be etched by a wet etching process, and then the isolation layer can be etched, which will not affect the polycrystalline in the groove. The process of using wet etching instead of dry etching is realized, and wet etching does not require the use of specific equipment, so the cost is low and the production capacity is improved.

[0086] As an implementation, see Figure 4 , the step of S102 includes:

[0087] S1021, providing a first doping type substrate.

[0088] S1022, growing a first doping type epitaxial layer based on the substrate.

[0089] S1023, etching the epitaxial layer to form a groove.

[0090] Among them, the present application does not limit the doping type. For example, when it is necessary to manufacture an N-type device, the first doping type substrate is an N-type substrate, and on this basis, the first doping type epitaxial layer refers to the N-type epitaxial layer; of course, if it is necessary to manufacture a P-type device, the first doping type substrate is a P-type substrate, and on this basis, the first doping type epitaxial layer refers to the P-type epitaxial layer.

[0091] In addition, the substrate can be heavily doped, the resistivity of the substrate can be selected to be 1-2.5mohm.cm, and the resistivity and thickness of the epitaxial layer can be selected to be 0.209ohm.cm and 7.3um respectively.

[0092] See also Figure 5-Figure 7 In the present application, when making the groove, the groove pattern is formed by photolithography. For example, a masking layer is first grown on the surface of the epitaxial layer, wherein SiO 2 As a masking layer, the thickness of the masking layer is 5000A, and then the pattern of the masking layer is etched by photolithography to form a mask; then the epitaxial layer is etched using the blocking of the mask, and a groove is formed on the epitaxial layer, as shown in the schematic diagram Figure 7 In the embodiment, two trenches are formed on the epitaxial layer; of course, it is understandable that Figure 7 This is just an illustration. In actual applications, the number of grooves may be greater, for example, 10 or 20 grooves, which is not limited here.

[0093] Optionally, the CD (critical dimension, referring to the groove width) of the groove is 0.95 um and the depth is 5.1 um. In addition, after the groove is made, the masking layer needs to be removed, for example, by wet etching.

[0094] After making trenches in the epitaxial layer, see Figure 8 , a field oxide layer and polycrystal can be grown successively based on the surface of the epitaxial layer and the trench. As can be seen from the figure, the field oxide layer and polycrystal are both located in the trench and on the surface of the epitaxial layer. Optionally, a 4100A field oxide layer can be deposited first, and then 8000A polycrystal can be deposited.

[0095] On this basis, see Fig. 9 Oxygen can be injected vertically downward along the surface of the polycrystal by ion implantation to oxidize the surface of the epitaxial layer and the polycrystal in contact with the surface of the epitaxial layer, and form an isolation layer. Fig. 9 In the figure, the area between the dotted line a and the dotted line b is the area that needs to be oxidized. The polycrystalline and epitaxial layers both include silicon materials. After oxygen ions are implanted, the area between the dotted line a and the dotted line b will generate SiO 2 .like Fig.10As shown in the figure, after being oxidized by oxygen, an isolation layer is formed between the polycrystalline and the epitaxial layer. The isolation layer is composed of the field oxide layer and the SiO2 generated after oxidation. 2 Combination.

[0096] After forming the isolation layer, the polycrystal and the isolation layer can be directly removed by wet etching process. Since the isolation layer and the polycrystal are two different materials, mutual influence is avoided during wet etching. In the wet etching process, the top polycrystal is first etched, and then the isolation layer is etched, and the polycrystal in the groove is exposed after etching, forming an epitaxial structure with polycrystal, and then the epitaxial structure is used to make a shielded gate trench device.

[0097] Please note that Fig.11 When the polycrystalline in the groove is exposed after the wet etching process, the field oxide layer on the surface of the epitaxial layer has been completely etched.

[0098] As an implementation, see Fig.12 , S110 includes:

[0099] S111, etching a portion of the polycrystalline and field oxide layers in the trench.

[0100] S112, growing a gate oxide layer based on the surface of the trench and the epitaxial layer, and continuing to deposit polycrystalline based on the trench to form a gate polycrystalline.

[0101] S113, doping the surface layer of the epitaxial layer to form a body region, wherein the doping type of the body region is opposite to the doping type of the epitaxial layer.

[0102] S114, doping the surface layer of the body region to form a source region, wherein the doping type of the source region is the same as the doping type of the epitaxial layer.

[0103] S115, depositing a dielectric layer on the surface of the epitaxial layer, etching contact holes, and then annealing.

[0104] S116, depositing a metal layer along the contact hole and the surface of the dielectric layer, and etching the metal layer to form a source and a gate.

[0105] S117, a passivation layer is deposited along the surface of the metal layer and windows are photolithographically formed.

[0106] S118, plating a back metal along the back side of the epitaxial layer to form a drain.

[0107] Among them, see Fig.13 In step S111, part of the polycrystalline and the field oxide layer in the groove can be etched away by photolithography and etching. Part of the polycrystalline in the groove can be etched away by dry etching first, and then part of the field oxide layer in the groove can be etched away by wet etching, and at the same time, the field oxide layer on the surface of the epitaxial layer can also be etched away.

[0108] See also Fig.14 , a gate oxide layer is grown based on the surface of the trench and the epitaxial layer, and polycrystalline is further deposited based on the trench to form gate polycrystalline. Among them, the present application can grow a 680A gate oxide layer, and then deposit 12000A polycrystalline, and then polysilicon is dry-etched back to remove the excess polycrystalline on the surface, thereby forming gate polycrystalline.

[0109] It should be noted that the gate oxide layer and the field oxide layer can be made of the same material or different materials, which is not limited here. Fig.14 It can be seen that through the above steps, the polycrystal in the groove can be divided into two parts, the upper layer is the gate polycrystal, and the lower layer is the shielding polycrystal. The figure includes two grooves, the shielding polycrystal in the left groove is interconnected with the shielding polycrystal in the right groove (not shown in the figure), and the gate polycrystal and the shielding polycrystal in the right groove are isolated by the gate oxide layer.

[0110] Then, the surface layer of the epitaxial layer is doped to form a body region, wherein the doping type of the body region is opposite to the doping type of the epitaxial layer. The structure after doping is as follows: Fig.15 Then, the surface layer of the body region is doped to form a source region, wherein the doping type of the source region is the same as the doping type of the epitaxial layer. The structure after doping is as shown in FIG. Fig.16 shown.

[0111] Among them, the present application can be doped by photolithography and impurity injection, and when making an N-type device, the epitaxial layer is N-type doped, the surface layer of the epitaxial layer is P-type doped to form a body region, and then the surface layer of the body region is N-type doped to form a source region. When making a P-type device, the epitaxial layer is P-type doped, the surface layer of the epitaxial layer is N-type doped to form a body region, and then the surface layer of the body region is P-type doped to form a source region, which is not limited here.

[0112] The present application is explained by taking the manufacture of an N-type device as an example. Optionally, when forming the body region, photolithography and injection of P-type impurities B may be selected; when forming the source region, photolithography and injection of N-type impurities As may be selected.

[0113] After doping, see Fig.17 , continue to deposit a dielectric layer along the surface of the epitaxial layer, and anneal after etching the contact holes. Among them, the present application combines the annealing after the source region is implanted with the annealing of the dielectric layer deposition, which can save the cost of an annealing process and reduce the device production cost.

[0114] As an implementation, the dielectric layer includes SiO 2 As with borophosphosilicate glass, the step of depositing the dielectric layer includes depositing SiO on the basis of the epitaxial layer. 2and borophosphosilicate glass, and the thickness of the borophosphosilicate glass is greater than or equal to SiO 2 For example, first deposit 2000ASiO 2 , and then deposit 5000A borophosphosilicate glass.

[0115] A contact hole may be formed on the dielectric layer by using photolithography and etching processes, wherein the CD of the contact hole may be 0.3 um.

[0116] It should be noted that after the contact hole is formed, a barrier layer is deposited along the surface of the contact hole using a MOCVD (Metal-organic Chemical Vapor Deposition) process. The barrier layer can be made of TiN, and when depositing the barrier layer, a 50A TiN barrier layer is deposited by MOCVD instead of a 600A TiN barrier layer grown by magnetron sputtering in the existing process. The TiN film grown by MOCVD has better quality and better effect, so the thickness of the TiN film can be reduced, which is more beneficial for mass production.

[0117] See also Fig.18 After depositing the barrier layer, a metal layer is deposited along the contact hole and the surface of the dielectric layer, and the metal layer is etched (not shown) to form a source and a gate.

[0118] As an implementation method, when depositing metal, tungsten metal can be deposited based on the contact hole, wherein the tungsten metal is located in the contact hole and on the surface of the dielectric layer, and then the tungsten metal located on the surface of the dielectric layer is removed, and finally aluminum metal is deposited based on the surface of the dielectric layer. Of course, other metals can also be used. When the contact hole is small, the deposition effect of the contact hole is better, so tungsten metal is preferably used to fill the contact hole.

[0119] Furthermore, when aluminum metal is deposited on the surface of the dielectric layer, part of copper metal may also be added to the aluminum metal, which is not limited here.

[0120] Optionally, when etching the metal layer, the metal layer may be wet etched and then dry etched to form a source and a gate, and the thickness of the wet etching is greater than or equal to the thickness of the dry etching. For example, using wet etching 2.5um + dry etching 1.5um instead of dry etching 4um in the prior art can greatly save dry etching capacity and achieve the effect of improving device production capacity.

[0121] Please continue reading Fig.19 , a passivation layer is deposited along the surface of the metal layer and a window is photolithographically formed, and then a back metal is plated along the back of the epitaxial layer to form a drain, thereby completing the fabrication of a shielded gate trench device.

[0122] Optionally, when depositing the passivation layer, SiO 2 With Si 3 N 4 , where Si 3 N 4 The thickness is greater than or equal to SiO 2 For example, first deposit 5000A of SiO 2 Then deposit 6000A of Si 3 N 4 And open the PAD window by photolithography and etching.

[0123] When manufacturing the back metal, the drain electrode may be formed by using 1000A Ti+2000A Ni+10000A Ag, which is not limited here.

[0124] In summary, the present application provides a method for manufacturing a shielded gate trench device, first providing an epitaxial layer with a trench, then growing a field oxide layer and a polycrystal based on the surface of the epitaxial layer and the trench, wherein the polycrystal is located in the trench and on the surface of the epitaxial layer, then ion-implanting oxygen along the surface of the polycrystal to oxidize the surface of the epitaxial layer and the polycrystal in contact with the surface of the epitaxial layer, and forming an isolation layer, then using a wet etching process to successively remove the polycrystal and the isolation layer located on the surface of the isolation layer to form an epitaxial structure with polycrystals, and finally using the epitaxial structure to manufacture a shielded gate trench device. Since the present application uses ion implantation to inject oxygen, the surface of the epitaxial layer and the polycrystal in contact with the surface of the epitaxial layer are oxidized, and then an isolation layer is formed, the polycrystal in the trench is isolated from the polycrystal on the surface of the epitaxial layer, and then the polycrystal on the surface of the isolation layer can be etched first by a wet etching process, and then the isolation layer is etched, which will not affect the polycrystal in the trench. The process of using wet etching instead of dry etching has been realized, and wet etching does not require the use of specific equipment, so the cost is low and the production capacity is improved.

[0125] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0126] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A method for manufacturing a shielded gate trench device, characterized in that: The method comprises: providing an epitaxial layer having a trench; Based on the surface of the epitaxial layer and the groove, a field oxide layer and a polycrystalline are successively grown, wherein the polycrystalline is located in the groove and on the surface of the epitaxial layer; Ion implantation of oxygen along the surface of the polycrystal to oxidize the surface layer of the epitaxial layer and the polycrystal in contact with the surface layer of the epitaxial layer, and to form an isolation layer; wherein the polycrystal at the top is not oxidized, so that the epitaxial layer, the isolation layer and the polycrystal are arranged layer by layer; Using a wet etching process to successively remove the polycrystal located on the surface of the isolation layer and the isolation layer to form an epitaxial structure with polycrystals; The epitaxial structure is used to manufacture a shielded gate trench device.

2. The method for manufacturing a shielded gate trench device according to claim 1, wherein: The step of using the epitaxial structure to manufacture a shielded gate trench device comprises: Etching a portion of the polycrystalline and field oxide layers within the trench; Growing a gate oxide layer based on the trench and the surface of the epitaxial layer, and continuing to deposit polycrystalline based on the trench to form a gate polycrystalline; Doping a surface layer of the epitaxial layer to form a body region, wherein the doping type of the body region is opposite to the doping type of the epitaxial layer; Doping a surface layer of the body region to form a source region, wherein the doping type of the source region is the same as the doping type of the epitaxial layer; Depositing a dielectric layer on the surface of the epitaxial layer, etching contact holes and then annealing; Depositing a metal layer along the contact hole and the surface of the dielectric layer, and etching the metal layer to form a source and a gate; Depositing a passivation layer along the surface of the metal layer and photolithography a window; A back metal is plated along the back side of the epitaxial layer to form a drain.

3. The method for manufacturing a shielded gate trench device according to claim 2, wherein: Before the step of depositing a metal layer along the contact hole and the surface of the dielectric layer, the method further comprises: A barrier layer is deposited along the surface of the contact hole by using an MOCVD process.

4. The method for manufacturing a shielded gate trench device according to claim 2, wherein: The step of etching the metal layer to form a source and a gate comprises: The metal layer is wet-etched and then dry-etched to form a source and a gate; the thickness of the wet etching is greater than or equal to the thickness of the dry etching.

5. The method for manufacturing a shielded gate trench device according to claim 2, wherein: The epitaxial layer is N-type doped, and the step of doping the surface layer of the epitaxial layer comprises: Performing P-type doping on the surface layer of the epitaxial layer; The step of doping the surface layer of the body region comprises: The surface layer of the body region is N-type doped.

6. The method for manufacturing a shielded gate trench device according to claim 2, wherein: The step of depositing a dielectric layer on the surface of the epitaxial layer comprises: Based on the epitaxial layer, SiO2 and borophosphosilicate glass are deposited in sequence, and the thickness of the borophosphosilicate glass is greater than or equal to the thickness of SiO2.

7. The method for manufacturing a shielded gate trench device according to claim 2, wherein: The step of depositing a metal layer along the contact hole and the surface of the dielectric layer comprises: Depositing tungsten metal based on the contact hole, wherein the tungsten metal is located in the contact hole and on the surface of the dielectric layer; removing tungsten metal located on the surface of the dielectric layer; Aluminum metal is deposited on the surface of the dielectric layer.

8. The method for manufacturing a shielded gate trench device according to claim 2, wherein: The steps of depositing a passivation layer along the surface of the metal layer and photolithography a window include: SiO2 and Si3N4 are deposited successively along the surface of the metal layer, wherein the thickness of Si3N4 is greater than or equal to the thickness of SiO2.

9. The method for manufacturing a shielded gate trench device according to claim 1, wherein: The step of providing an epitaxial layer with a trench comprises: providing a first doping type substrate; growing a first doping type epitaxial layer based on the substrate; The epitaxial layer is etched to form a trench.

10. The method for manufacturing a shielded gate trench device according to claim 9, wherein: The step of providing a first doping type substrate comprises: Providing an N-type substrate; The step of growing a first doping type epitaxial layer based on the substrate comprises: An N-type epitaxial layer is grown based on the substrate.

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