Three-dimensional memory and methods of manufacturing the same

Abstract

This application provides a three-dimensional memory and a method for manufacturing the same. The three-dimensional memory includes multiple storage planes, each storage plane including at least one dummy storage block and multiple storage blocks arranged along a first direction. The dummy storage block is located on both sides of the multiple storage blocks. The storage blocks and the dummy storage blocks include a stepped structure with multiple steps. A group of marker structures is disposed in the stepped structure of at least two storage planes, each of which includes at least one dummy storage block. Each group of marker structures includes multiple marker structures spaced apart on the steps along a second direction intersecting the first direction. The height of the marker structures is greater than or equal to the height of the steps, and the arrangement of the marker structures in different storage planes is different from each other.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a three-dimensional storage device and a method for manufacturing the same. Background Technology

[0002] With the rapid development of 3D memory technology, the number of stacked layers in memory arrays is constantly increasing, as is the number of steps in the stepped structure. This increasing number of stacked layers makes the process control for etching to form the stepped structure more challenging. In 3D memory manufacturing, multiple marker structures are typically placed in the step area or the bridging area connected to the step area. These marker structures are then used as position references to etch the step area to form the stepped structure.

[0003] It should be understood that the background section is intended to provide some useful background for understanding the technology; however, this content is not necessarily what was known or understood by a person skilled in the art prior to the filing date of this application. Summary of the Invention

[0004] One aspect of this application provides a three-dimensional memory, comprising: a plurality of storage planes, each storage plane including at least one dummy storage block and a plurality of storage blocks disposed along a first direction, the dummy storage block being located on both sides of the plurality of storage blocks, the storage blocks and the dummy storage blocks including a stepped structure having a plurality of steps; and a group of marker structures disposed in the stepped structure of at least one dummy storage block included in at least two of the plurality of storage planes, each group of marker structures including a plurality of marker structures spaced apart on the steps along a second direction intersecting the first direction, wherein the arrangement of the marker structures in different storage planes is different from each other.

[0005] In one embodiment of this application, in a plurality of storage planes arranged sequentially in the same direction, at least a portion of the marking structures do not overlap with each other in the orthographic projection of the same direction.

[0006] In one embodiment of this application, the marking structure is a protrusion or a groove.

[0007] In one embodiment of this application, the storage block and the dummy storage block further include: a storage array located on opposite sides of the stepped structure; and a bridging structure located on the other opposite sides of the stepped structure, wherein the storage area is connected to the stepped structure through the bridging structure; wherein the marker structure is located between the bridging structures.

[0008] In one embodiment of this application, the marking structure is a protrusion, and the bridging structure is connected to the marking structure.

[0009] In one embodiment of this application, a portion of the sidewall of the bridging structure overlaps with at least a portion of the marking structure.

[0010] In one embodiment of this application, the top surface of the marking structure is coplanar with the top surface of the bridging structure.

[0011] Another aspect of this application provides a method for manufacturing a three-dimensional memory, comprising: forming a semiconductor structure including a plurality of memory planes, each memory plane including at least one dummy memory block and a plurality of memory blocks disposed along a first direction, the dummy memory block being located on both sides of the plurality of memory blocks, the memory blocks and the dummy memory blocks including step regions; forming a group of marker structures in the step regions of at least two of the memory planes including at least one of the dummy memory blocks, each group of marker structures including a plurality of marker structures spaced apart along a second direction intersecting the first direction, wherein the arrangement of the marker structures in different memory planes is different from each other; and forming a stepped structure having a plurality of steps in the step regions with the marker structures as position references, wherein the marker structures are spaced apart on the steps, and the height of the marker structures is greater than or equal to the height of the steps.

[0012] In one embodiment of this application, forming a marker structure group in the step region of the dummy memory block includes: forming a mask layer on the semiconductor structure; patterning the mask layer to form a pattern corresponding to the opening in the step region and the marker structure; and forming the marker structure using the patterned mask layer as a mask.

[0013] In one embodiment of this application, the storage block and the dummy storage block further include storage areas located on opposite sides of the stepped structure, wherein patterning the mask layer includes: forming a pattern of a bridging structure, wherein the pattern of the marker structure is located between and connected to the pattern of the bridging structure; and forming the bridging structure using the patterned mask layer as a mask; wherein the bridging structure is located on another opposite side of the stepped structure, and the storage area is connected to the stepped structure through the bridging structure.

[0014] In one embodiment of this application, forming the stepped structure includes: using the marked structure as a position reference, forming a stepped structure with multiple steps in the stepped area via the opening. Attached Figure Description

[0015] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. In the drawings,

[0016] Figure 1 This is a top view schematic diagram of a three-dimensional memory according to an embodiment of this application.

[0017] Figure 2 and Figure 3 This is a partial structural diagram of some virtual storage blocks of a three-dimensional memory according to an embodiment of this application;

[0018] Figure 4 According to Figure 2 A schematic diagram of a partial cross-section of the dummy storage block along the AA direction is shown.

[0019] Figure 5 According to Figure 3 A schematic cross-sectional view of the marker structure of the dummy storage block shown in the BB direction;

[0020] Figure 6 According to Figure 3 A schematic cross-sectional view of the marker structure of the virtual storage block shown in the CC direction;

[0021] Figure 7 A schematic flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of this application; and

[0022] Figure 8 In order to be in Figure 2 The diagram shows a structure in which a patterned mask layer is formed on a dummy storage block. Detailed Implementation

[0023] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0024] Note that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, implementing that feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0025] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least partly on the context.

[0026] It should be readily understood that the meanings of “above,” “on top,” and “above” in this disclosure should be interpreted in the broadest sense, such that “above” means not only “directly on something” but also includes “on something” with an intermediate feature or layer therebetween, and that “on top” or “above” means not only “above” or “above” something but also includes “above” or “above” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0027] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and another element(s)(s)(s) as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and accordingly, the spatial relative descriptors used herein may be interpreted similarly.

[0028] As used herein, the term "layer" may extend over the entire upper or lower structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, wherein the non-homogeneous continuous structure has a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple sublayers.

[0029] In addition, the accompanying drawings in this application are for illustrative purposes only and are not drawn to scale. The thickness, size and shape of the parts have been slightly adjusted for ease of explanation.

[0030] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when a statement such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0031] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0032] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] In describing the embodiments of this application, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] like Figure 1 As shown, the three-dimensional memory 100 provided in this application includes a plurality of storage planes (e.g., storage planes 10, 20, 30, and 40). Taking storage plane 10 as an example, the storage plane 10 includes storage blocks 11 and 12 disposed along a first direction (e.g., the Y direction) and dummy storage blocks 11' and 12', wherein the dummy storage blocks 11' and 12' are disposed at two ends of the storage plane 10.

[0035] It should be noted that the structures of dummy storage blocks 11' and 12' may be the same as those of storage blocks 11 and 12, but dummy storage blocks 11' and 12' are not used to perform storage functions. In some examples, dummy storage blocks 11' and 12' may be used as boundaries separating adjacent storage planes.

[0036] It should be understood that storage planes 20, 30, and 40 may have the same structure as storage plane 10, for example. Figure 1 The number of storage blocks and dummy storage blocks shown is merely an example for illustrating this application. The number of storage blocks and dummy storage blocks can be set according to actual needs, and this application does not limit this.

[0037] In some embodiments, the storage plane 10 may include a storage area 13 and a stepped area 14, wherein in the storage area 13, each storage block (e.g., storage block 11, 12) and dummy storage blocks (e.g., dummy storage blocks 11', 12') includes a storage array 131. Figure 2 In the stepped area 14, each storage block (e.g., storage blocks 11, 12) and dummy storage blocks (e.g., dummy storage blocks 11', 12') may include a stepped structure (e.g., Figure 2 The stepped structure 50 is shown. In some examples, each memory block (e.g., memory blocks 11, 12) and dummy memory blocks (e.g., dummy memory blocks 11', 12') in the stepped area 14 may also include a bridging structure 80 corresponding to the stepped structure 50. Figure 2 ).

[0038] Continue to refer to Figure 1 In some examples, the stepped area 14 may be located in the middle or near the middle of the storage area 13 to divide the storage area 13 into two parts. In other examples, the stepped area 14 may also be located on both sides of the storage area 13. This application does not limit this.

[0039] Figure 2 A schematic diagram of a virtual storage block 11' according to an embodiment of this application is shown. Figure 2 As shown, the virtual storage block 11' may include a storage array 131, a ladder structure 50, and a bridging structure 80. In some examples, the storage array 131 may be located on opposite sides of the ladder structure 50, and the bridging structure 80 may be located on the other opposite sides of the ladder structure 50. The storage array 131 is connected to the ladder structure 50 through the bridging structure 80.

[0040] Continue to refer to Figure 2 In some examples, the three-dimensional memory 100 also includes a marker structure group 60. In some examples, the marker structure group 60 may be disposed in at least two memory planes, for example, disposed in... Figure 1At least two of the four storage planes 10, 20, 30, and 40 shown each include at least one dummy storage block. In other examples, at least one dummy storage block in each of the storage planes 10, 20, and 30 (e.g., dummy storage blocks 11', 21', 22', 31', 32') may be configured with a tag structure group 60. Optionally, the tag structure 601 of the tag structure group 60 ( Figure 2 The arrangement can vary depending on the storage plane.

[0041] Figure 1 The dashed boxes in the figure represent the tag structure group 60 of different dummy storage blocks (e.g., dummy storage blocks 11', 21', 22', 31', 32') in different storage planes (e.g., storage planes 10, 20, 30). It can be seen that the dummy storage block 12' included in storage plane 10 may not have the tag structure group 60 set, and the dummy storage blocks included in storage plane 40 may not have the tag structure group 60 set.

[0042] In some examples, within multiple storage planes arranged sequentially in the same direction, the orthographic projections of at least a portion of the marker structures 601 of each marker structure group 60 in that same direction do not coincide with each other. Figure 1 Taking the two storage planes 10 and 20 arranged along the X direction as shown in the figure as an example, the dummy storage block 11' includes at least a portion of the marker structure 601 ( Figure 2 The tag structure 701 (including at least a portion of the dummy storage block 21') and the virtual storage block 21' Figure 3 The orthographic projections along the X direction do not coincide with each other.

[0043] The marker structure group 601 provided in this application can be distributed in different virtual storage blocks on different storage planes, and the arrangement in different virtual storage blocks is different. This can not only meet the positional requirements of the marker structure 601 for the subsequent etching step area to form the storage block or the stepped structure of the virtual storage block, but also increase the spacing between adjacent marker structures 601 to a certain extent, thereby reducing the problem of photoresist residue.

[0044] Continue to refer to Figure 2 The marking structure group 60 may include a plurality of marking structures 601, which may be spaced apart along the X direction. For example, the marking structure 601 may be a protrusion or a groove. In some embodiments, the top surface of the marking structure 601 is coplanar with the top surface of the bridging structure 80.

[0045] In some embodiments, the marker structure 601 may be located between the bridging structures 80. As an example, when the marker structure 601 is a protruding structure, the bridging structure 80 may be in contact with the marker structure 601. As another example, a portion of the sidewall of the bridging structure 80 may overlap with at least a portion of the marker structure 601.

[0046] When etching to form a stepped structure of memory blocks or dummy memory blocks in subsequent processes, the marking structure 601 provided in some embodiments of this application can be a protrusion connected to the bridging structure 80. The top of the marking structure 601 will not shift during the etching process. The marking structure 601 serves as an accurate reference position for measurement, and the measured offset of the stepped structure is accurate.

[0047] Figure 4 A portion of the stepped area 14 is shown; in some embodiments, a dummy storage block 11' is provided. Figure 2 The device may include a semiconductor layer 133 and a stacked structure 132, wherein the stacked structure 132 includes alternately stacked conductive layers 135 and dielectric layers 134, and a stepped structure 50 (FIG. 2) may be formed at an intermediate position in the stacked structure 132. In some examples, the stepped structure 50 may include, for example, Figure 4 The multiple steps 51 shown may each have a thickness of a pair of conductive layers 135 / dielectric layers 134.

[0048] Continue to refer to Figure 4 In some examples, the marker structure 601 may be spaced apart on multiple steps 51. Alternatively, the height of the marker structure 601 may be the same as the height of the steps 51 in a direction perpendicular to or substantially perpendicular to the semiconductor layer 133. Alternatively, the height of the marker structure 601 may be greater than the height of the steps 51 in a direction perpendicular to or substantially perpendicular to the semiconductor layer 133.

[0049] In some examples, the width of the marker structure 601 is smaller than the width of the step 51 in a direction parallel or substantially parallel to the semiconductor layer 133. Optionally, the marker structure 601 and the conductive layer 135 / dielectric layer 134 pair may have the same material and stacking orientation.

[0050] In some examples, storage array 131 ( Figure 2 It can be formed in such Figure 4 On both sides of the stacked structure 132 shown, the stepped structure 50 may also be covered with an insulating dielectric layer 136 to provide structural support.

[0051] In some embodiments, the stacked structure 132 may include multiple pairs of dielectric layers 134 / conductive layers 135, and the number of pairs can be selected according to various application scenarios. For example, the number of pairs may be 32, 64, 96, 128, 160, 192, 224, 256 or more.

[0052] In some examples, the material used to fabricate the semiconductor layer 133 may include, for example, polycrystalline silicon. In some examples, the material used to fabricate the conductive layer 135 may include, for example, metallic conductive materials such as W, Co, Cu, Al, Ti, Ta, and Ni. In other examples, the material used to fabricate the conductive layer 135 may also include, for example, polycrystalline silicon, doped silicon, metal silicides (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof.

[0053] In some examples, the material used for dielectric layer 134 may include, for example, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric material, dielectric metal oxides (e.g., alumina, hafnium oxide, etc.) and their silicates, which are commonly referred to as high dielectric constant (high k) dielectric oxides, dielectric metal oxynitrides and their silicates, and organic insulating materials.

[0054] It should be noted that a storage block (e.g., storage block 11) may include the same structure as described above as the dummy storage block 11', except for the tag structure group 60. As an example, in storage block 11 ( Figure 1 In ), conductive layer 135 ( Figure 4 It can be used as a control gate layer to bring out word lines (not shown).

[0055] Each character line consists of a stepped structure of 50 ( Figure 4 The word line is divided into two parts, which can be connected at the corresponding steps of the stepped structure 50 by a bridging structure. Figure 2 Incoming communication. In some examples, the storage plane (e.g., storage plane 10) may also include a gate gap structure (not shown) for separating two adjacent storage blocks (e.g., storage blocks 11 and 12) or adjacent storage blocks (e.g., storage block 11) from a dummy storage block (e.g., dummy storage block 11'), the gate gap structure extending through the stack structure 132.

[0056] In some examples, the memory array of memory blocks (e.g., memory block 11) and dummy memory blocks (e.g., dummy memory block 11') may also include a channel structure (not shown) extending through the stacked structure 132. The channel structure includes a channel layer (not shown) for transmitting charge and a functional layer (not shown), wherein the functional layer includes, from the outside in, a barrier layer, a tunneling layer, and a storage layer, and the storage layer can be used to store charge. During operation of the three-dimensional memory 100 (e.g., erasing, programming, or reading), the channel structure of the dummy memory block (e.g., dummy memory block 11') will not be electrically connected.

[0057] In some examples, the marker structure 601 is along Figure 3 The cross-sectional views in the BB and CC directions are as follows: Figure 5 and Figure 6 As shown, the marker structure 701 may be formed on the upper part of the stacked structure 132 away from the semiconductor layer 133. As an example, the marker structure 701 may be located on the stepped structure 50 (FIG. 2) formed by the conductive layer 135 and the dielectric layer 134. In some examples, the shape of the marker structure 701 is, for example, a cuboid or a frustum. Figure 5 As an example, the marker structure 701 is located away from the semiconductor layer 133. Figure 4 The top surface area of ​​the semiconductor layer 133 can be smaller than the bottom surface area of ​​the semiconductor layer 133.

[0058] Some embodiments of this application also provide a method for manufacturing the above-described three-dimensional memory 100. Figure 7 A flowchart of a method 300 for manufacturing a three-dimensional memory 100 according to an embodiment of this application is shown. It should be understood that the operations shown in the method are not exhaustive, and other operations may be performed before, after, or between any of the operations described.

[0059] like Figure 7 As shown, method 300 begins with operation S310, in which a semiconductor structure (not shown) can be formed, the semiconductor structure including the aforementioned plurality of memory planes (e.g., memory planes 10, 20, 30, 40), each memory plane (e.g., memory plane 10) including at least one dummy memory block (e.g., dummy memory block 11') and a plurality of memory blocks (e.g., memory blocks 11 and 12) disposed along a first direction (e.g., the Y direction), the dummy memory blocks may be located on both sides of the plurality of memory blocks, and the memory blocks and dummy memory blocks may include a stepped structure 50 to be formed ( Figure 2 The stepped area (not shown).

[0060] In some embodiments, the semiconductor structure includes a substrate (not shown) and a stacked structure (not shown) formed on the substrate. In some examples, the material used to fabricate the substrate may be any suitable semiconductor material, such as single-crystal silicon, polycrystalline silicon, single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds.

[0061] In some examples, a stacked structure can be formed on a substrate by alternatingly forming multiple dielectric layers 134 (FIG. 4) and sacrificial layers (not shown) on a substrate using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof.

[0062] In some embodiments, under the same etching process, the sacrificial layer and dielectric layer 134 have a high etching selectivity and can be subsequently replaced by the conductive layer 135. Figure 4 To form a layered structure 132 ( Figure 4 When ), the dielectric layer 134 is hardly removed.

[0063] In some embodiments, the storage block (e.g., storage block 11) and the dummy storage block (e.g., dummy storage block 11') may also include the storage array described above, wherein the step may be located in the middle or near the middle of the storage array.

[0064] See also Figure 7 Method 300 continues to operation S320, wherein a group of marker structures is formed in the step region of at least one dummy storage block included in at least two storage planes, each group of marker structures including a plurality of marker structures spaced apart along a second direction intersecting the first direction, wherein the arrangement of the marker structures in different storage planes is different from each other.

[0065] like Figure 8 As shown, in some examples, a mask layer 143 may be formed on a semiconductor structure (not shown), and then the mask layer 143 may be patterned to form an opening 142 corresponding to the step region and a pattern 144 marking the structure group.

[0066] In some embodiments, the semiconductor structure includes four memory planes (e.g., Figure 1 The storage planes 10, 20, 30, and 40 shown in the figure, wherein at least one dummy storage block (e.g., covering each of the storage planes 10, 20, and 30) can be configured to... Figure 1 The mask layer 143 of the virtual storage blocks 11', 21', 22', 31', 32' in the middle is patterned to form a pattern of marker structure groups with different arrangements.

[0067] In some examples, taking the mask layer 143 covering portions of two storage planes 10 and 20 arranged along the Y direction as an example, the pattern 144 of the mark structure group formed on the mask layer 143 corresponding to the portion of the dummy storage block 11' is similar to that on the dummy storage block 21'. Figure 1 The pattern (not shown) of the marker structure group formed in the corresponding partial mask layer 143 is arranged differently. Alternatively, the patterns of multiple marker structures in the two marker structure groups with different arrangements do not overlap along the orthographic projection of the Y direction.

[0068] In some embodiments, the mask layer 143 may be made of, for example, polysilicon, a high dielectric constant (high k) dielectric, titanium nitride (TiN), or any other suitable hard mask material. It may first be deposited on the stacked structure 132 using one or more thin-film deposition processes including CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. Figure 4 A hard mask material is deposited on the mask to form a mask layer 143. The mask layer 143 can then be patterned using photolithography and dry etching and / or wet etching processes (such as reactive ion etching (RIE)) to form a pattern 144 of openings 142 and marker structure groups.

[0069] In some embodiments, such as Figure 8 As shown, while forming the pattern 144 of the opening 142 and the marking structure group, a pattern 141 of bridging structures can be formed, wherein the pattern 144 of the marking structure group can be located between the patterns 141 of the bridging structures. Alternatively, the pattern 144 of the marking structure group can also be connected to the pattern 141 of the bridging structures. Alternatively, a portion of the sidewall of the pattern 141 of the bridging structures can be part of the pattern 144 of the marking structure group.

[0070] In some examples, after forming the pattern 144 of the marker structure group and the pattern 141 of the bridging structure, a patternable mask layer can be used to mask the formation of the marker structure 601 (FIG. 2) and the bridging structure 80 (FIG. 2). Figure 2 Since the pattern 144 of the marking structure group and the pattern 141 of the bridging structure can be formed simultaneously, the formed marking structure 601 can be a raised structure.

[0071] In some 3D memory manufacturing processes, a groove-shaped marking structure (not shown) is typically formed first in the step region. This groove-shaped marking structure is then etched to form a stepped structure 50. Figure 2 During the process, the marker structure will be continuously etched, and its size will gradually increase and deviate from the baseline. This makes the marker structure an inaccurate baseline for measurement, resulting in inaccurate measurement of the offset of the stepped structure 50.

[0072] The raised marking structure 601 formed by some embodiments of this application is beneficial to improving the accuracy of measuring the offset of the stepped structure.

[0073] Some embodiments of this application can simultaneously form an opening 142 in the step region, a pattern 144 of the marking structure group, and a pattern 141 of the bridging structure in the mask layer 143. Compared with some existing manufacturing methods that perform the above processes step by step, some embodiments of this application can simplify the manufacturing process.

[0074] In some examples, after the marking structure 601 and bridging structure 80 are formed, residues (e.g., photoresist) on the opening 142, marking structure 601, and bridging structure 80 can be removed by an asher process. Typically, the photoresist can comprise an organic material. In this step, for example, oxygen can be used to burn off the photoresist remaining after the photolithography process forms the opening and marking structures, converting it into carbon dioxide for emission.

[0075] In some examples, after the asher process, a wet stripping process can be performed on the opening 142, the marking structure 601, and the bridging structure 80 to remove residues from the asher process (e.g., photoresist burn-off residue). In this step, the ashered material can be cleaned using diluted sulfuric acid and hydrofluoric acid.

[0076] Return to reference Figure 7 The method continues to operation S330, where a stepped structure with multiple steps can be formed in the step area using the marked structure as a position reference. The marked structures are spaced apart on the steps, and the height of the marked structures is greater than or equal to the height of the steps.

[0077] In some embodiments, the stacked structure 132 can be repeatedly etched on the stacked structure using an etching mask (e.g., a patterned PR) via the aforementioned opening 142. Figure 4 In some examples, structure 601 can be labeled. Figure 2 Using a reference position, the etch mask (not shown) is repeatedly trimmed inwards and incrementally in all directions to expose the portion of the stacked structure 132 to be etched. The amount of trimmed PR can be directly related to (e.g., decisively) the size of the step. For example, the amount of trimmed PR along the X direction can determine the width of the step along the X direction. The trimming of the PR layer can be achieved using appropriate etching (e.g., isotropic etching such as wet etching). One or more PR layers can be continuously formed and trimmed to form a structure with multiple steps 51 ( Figure 4 Step structure () Figure 2 ).

[0078] In some embodiments, the PR layer is trimmed after the stacked structure has been etched using a suitable etching process such as dry etching and / or wet etching. In some embodiments, after each trimming of the PR layer, the stacked structure is etched to a step depth along a direction perpendicular to the X and Y directions. The depth of this step 51 may be equal to the number of sacrificial / dielectric layer pairs included in a step. In some examples, each step may include one sacrificial / dielectric layer pair. In some embodiments, the number of sacrificial / dielectric layers is one. The trimming of the PR and the etching of the stacked structure are referred to herein as trim-etch cycles. The number of trim-etch cycles can determine the number of steps formed along the Y-axis in the stacked structure.

[0079] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory characterized by, Comprising: a plurality of memory planes, each of the memory planes comprising a plurality of memory blocks and at least one dummy memory block disposed along a first direction, the dummy memory block being located at a side of the plurality of memory blocks, the memory blocks and the dummy memory block comprising a staircase structure having a plurality of steps; and a plurality of marker structure sets disposed in the staircase structure of at least one of the dummy memory blocks of at least two of the memory planes, each of the marker structure sets comprising a plurality of marker structures spaced apart on the steps along a second direction intersecting the first direction, wherein a height of the marker structures is greater than or equal to a height of the steps, and an arrangement of the marker structures in different ones of the memory planes is different from each other.

2. The three-dimensional memory of claim 1, wherein, In a plurality of the memory planes disposed sequentially in the same direction, at least a portion of the marker structures do not overlap with each other in a projection in the same direction.

3. The three-dimensional memory of claim 1, wherein, The marker structures are protrusions.

4. The three-dimensional memory of claim 1, the memory blocks and the dummy memory block further comprising: memory regions located at opposite sides of the staircase structure; and bridge structures located at another opposite sides of the staircase structure, the memory regions being electrically connected to the staircase structure through the bridge structures; wherein the marker structures are located between the bridge structures. The marker structures are protrusions, and the bridge structures are connected to the marker structures.

5. The three-dimensional memory of claim 4, wherein, A portion of a sidewall of the bridge structures overlaps at least a portion of the marker structures.

6. The three-dimensional memory of claim 5, wherein, A top surface of the marker structures is coplanar with a top surface of the bridge structures.

7. The three-dimensional memory as recited in claim 5, wherein, Comprising:

8. A method of manufacturing a three-dimensional memory, comprising: forming a semiconductor structure, the semiconductor structure comprising a plurality of memory planes, each of the memory planes comprising a plurality of memory blocks and at least one dummy memory block disposed along a first direction, the dummy memory block being located at two sides of the plurality of memory blocks, the memory blocks and the dummy memory block comprising a staircase region; forming a plurality of marker structure sets in the staircase region of at least one of the dummy memory blocks of at least two of the memory planes, each of the marker structure sets comprising a plurality of marker structures spaced apart along a second direction intersecting the first direction, wherein an arrangement of the marker structures in different ones of the memory planes is different from each other; and forming a staircase structure having a plurality of steps in the staircase region with the marker structures as position references, wherein the marker structures are spaced apart on the steps, and a height of the marker structures is greater than or equal to a height of the steps. Forming the marker structure sets in the staircase region of the dummy memory block comprises:

9. The production method according to claim 8, wherein forming a mask layer on the semiconductor structure; patterning the mask layer to form an opening corresponding to the staircase region and a pattern of the marker structures; and forming the marker structures with the patterned mask layer as a mask. The memory blocks and the dummy memory block further comprise memory regions located at opposite sides of the staircase structure, 10. The manufacturing method according to claim 9, wherein wherein patterning the mask layer comprises: forming a pattern of bridge structures, wherein the pattern of the marker structures is located between and connected to the pattern of the bridge structures; and ​ forming the bridge structure by taking the patterned mask layer as a mask; wherein the bridge structure is located on the other opposite two sides of the step structure, and the storage area is connected with the step structure through the bridge structure.

11. The manufacturing method according to claim 9, wherein forming the step structure comprises: forming a step structure with multiple steps in the step area via the opening by taking the mark structure as a position reference.

12. The manufacturing method according to claim 8, wherein In the multiple storage planes arranged in the same direction in sequence, the orthographic projections of at least part of the mark structures in the same direction do not coincide with each other.

13. The manufacturing method according to claim 8, wherein The mark structure is a protrusion.

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