Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes an electrostatic ring disposed in the non-display area and multiple signal lines disposed in the display area. The multiple signal lines include at least a ground signal line. An electrostatic discharge structure is provided on the side of the ground signal line near the electrostatic ring to release static electricity from the ground signal line to the electrostatic ring. This prevents static electricity from damaging the signal lines and driver chip in the display area, avoids adverse effects of static electricity on the display area, improves the overall electrostatic discharge (ESD) resistance of the product, and further ensures normal display operation of the display device.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] In the field of display panel manufacturing technology, electrostatic discharge (ESD) has always been a difficult problem to solve. ESD can lead to reduced product yield, increased costs, and decreased production capacity, which has always affected the quality of display devices.

[0003] In the manufacturing process of display panels, the substrate is typically moved between different film-layer processing machines via rolling rollers. As the rollers move the substrate, static charge is generated between the rollers and the substrate due to continuous friction. Furthermore, static charge is also generated between the support ends that hold the substrate and the substrate during each processing step on the film-forming machine due to contact and friction. This static charge accumulates on the substrate, and when it reaches a certain level, it can cause electrostatic breakdown between metal signal lines. This breakdown can damage the insulating layers between different metal signal lines, resulting in short circuits between metal signal line layers. In some cases, the static charge can even be transmitted to the driver chip, causing damage to it. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a display panel and display device that solves the technical problem in the prior art where static electricity can easily damage signal lines and driver chips on the display panel.

[0005] Firstly, this application provides a display panel, including...

[0006] A substrate, wherein the substrate includes a display area and a non-display area located around the display area;

[0007] An electrostatic ring is disposed within the non-display area;

[0008] Multiple signal lines are arranged within the display area;

[0009] The plurality of signal lines include at least a ground signal line, and an electrostatic discharge structure is provided on the side of the ground signal line near the electrostatic ring. The electrostatic discharge structure is used to release the static electricity on the ground signal line to the electrostatic ring.

[0010] In some embodiments, in the above-described display panel, the electrostatic discharge structure includes a protrusion extending in a direction close to the electrostatic ring.

[0011] In some embodiments, in the above-described display panel, the line width of the protrusion gradually decreases along the direction close to the electrostatic ring.

[0012] In some embodiments, in the above-described display panel, there is a gap between the orthographic projection of the electrostatic discharge structure on the substrate and the orthographic projection of the electrostatic ring on the substrate.

[0013] In some embodiments, the width of the gap in the above-described display panel is greater than or equal to 0.2 mm.

[0014] In some embodiments, in the above-described display panel, the grounding signal line and the electrostatic ring are located on the same layer.

[0015] In some embodiments, in the above-described display panel, the grounding signal line includes a main body portion and a transition portion disposed between the protrusion portion and the main body portion.

[0016] In some embodiments, in the above-described display panel, the line widths of the transition portion and the protrusion are both smaller than the line width of the main body portion.

[0017] In some embodiments, the display panel further includes:

[0018] Multiple cascaded driver chips are disposed within the display area; wherein, each driver chip includes multiple terminals, and the multiple terminals include at least a ground terminal, and the ground terminal of the driver chip is connected to the ground signal line;

[0019] Multiple light-emitting units are respectively connected to the driving chip and disposed in the display area.

[0020] In some embodiments, in the above-described display panel, the plurality of signal lines further include drive signal lines, and the plurality of terminals further include address signal input terminals and output terminals;

[0021] Wherein, the first end of the light-emitting unit is connected to the driving signal line, and the second end of the light-emitting unit is connected to the output terminal of the corresponding driving chip;

[0022] The output terminal of the driver chip at the previous stage is connected to the address signal input terminal of the driver chip at the next stage.

[0023] In some embodiments, in the above-described display panel, the plurality of signal lines further include power signal lines, and the plurality of terminals further include power signal input terminals;

[0024] The power signal input terminal of the driver chip is connected to the power signal line.

[0025] In some embodiments, in the above-described display panel, the resistance of the ground signal line is less than the resistance between the ground terminal of the previous stage driver chip and the address signal input terminal of the next stage driver chip.

[0026] In some embodiments, in the above-described display panel, the resistance between the ground terminal of the previous-level driver chip and the address signal input terminal of the next-level driver chip includes:

[0027] The resistance between the ground terminal and the output terminal of the previous stage driver chip, and the resistance between the output terminal of the previous stage driver chip and the address signal input terminal of the next stage driver chip.

[0028] In some embodiments, in the above-described display panel, the light-emitting unit includes at least one light-emitting device connected in series or in parallel.

[0029] In some embodiments, in the above-described display panel, the side of the light-emitting device away from the substrate is covered with a protective layer;

[0030] Wherein, the orthogonal projection of the grounding signal line on the substrate does not cover the orthogonal projection of the protective layer on the substrate.

[0031] In some embodiments, in the above-described display panel, in a direction perpendicular to the extension direction of the protrusion, the distance between the end of the protrusion away from the electrostatic ring and the adjacent light-emitting devices on both sides is the same.

[0032] In some embodiments, in the above-described display panel, in a direction parallel to the extension direction of the protrusion, the distance between the end of the protrusion away from the electrostatic ring and the adjacent light-emitting devices on both sides is the same.

[0033] In a second aspect, this application provides a display device including a display panel as described in any one of the first aspects.

[0034] By adopting the above technical solution, at least the following technical effects can be achieved:

[0035] This application provides a display panel and a display device. The display panel includes an electrostatic ring disposed in the non-display area and multiple signal lines disposed in the display area. The multiple signal lines include at least a ground signal line. An electrostatic discharge structure is provided on the side of the ground signal line near the electrostatic ring to release static electricity from the ground signal line to the electrostatic ring. This prevents static electricity from damaging the signal lines and driver chip in the display area, avoids adverse effects of static electricity on the display area, improves the overall electrostatic discharge (ESD) resistance of the product, and further ensures normal display operation of the display device. Attached Figure Description

[0036] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0037] Figure 1 This is a top view of a display panel;

[0038] Figure 2 yes Figure 1 The diagram shows the conduction of static electricity in the display panel.

[0039] Figure 3 This is a top view schematic diagram illustrating a display panel according to an exemplary embodiment of this application;

[0040] Figure 4 yes Figure 3 A partial enlarged view of the display panel shown;

[0041] Figure 5 yes Figure 3 The diagram shows the conduction of static electricity in the display panel.

[0042] In the accompanying drawings, the same parts use the same reference numerals, and the drawings are not drawn to scale.

[0043] The attached figures are labeled as follows:

[0044] 11-Substrate; 111-Display area; 112-Non-display area; 12-Electrostatic ring; 13-Signal line; 131-Ground signal line; 131a-Electrostatic discharge structure; 131b-Transition section; 132c-Main body; 132-Drive signal line; IC-Driver chip; 14-Light-emitting unit; 141-Light-emitting device; 15-Bonding pin; 16-Connecting line;

[0045] Gnd - Grounding terminal; Di - Addressing signal input terminal; Out - Output terminal; Pwr - Power signal input terminal. Detailed Implementation

[0046] The following detailed description of the embodiments of this application, in conjunction with the accompanying drawings, will provide a thorough understanding of how this application uses technical means to solve technical problems and achieve corresponding technical effects, enabling its implementation. The embodiments of this application and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this application. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0047] It should be understood that although the terms "first," "second," "third," etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] To fully understand this application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0050] With the continuous development of display technology, light-emitting diode (LED) display technology has gradually become a research hotspot as a new type of display technology. Among them, micro LEDs and mini LEDs, which have smaller dimensions, are increasingly being used in large-size backlights due to their small size and thin backlight thickness. Micro-LED and mini-LED technologies shrink the size of existing LEDs to below 100μm and between 100 and 300μm, respectively.

[0051] Inside the display panel, the cathode of the Mini / Micro LED needs to be connected to the driver chip. The driver chip and the Mini / Micro LED are set together in the display area. The correspondence between the driver chip and the Mini / Micro LED is one-to-one or one-to-many. The anode of the Mini / Micro LED is supplied with a constant voltage through an external driving unit. The light emission state of the Mini / Micro LED is realized by the driver chip in the display area.

[0052] However, static electricity in existing Micro-LED and mini-LED display panels can damage the LED driver chips within the display area.

[0053] A structure of a display panel, such as Figure 1 As shown, the display panel includes a display area (not labeled) and a non-display area (not labeled). The display area contains an array of multiple light-emitting units and multiple cascaded driver ICs, with each light-emitting unit connected to a corresponding driver IC. The non-display area has bonding pins for bonding to a flexible printed circuit (FPC).

[0054] The aforementioned driver chip IC includes four bonding terminals, including three input terminals: address signal input terminal Di, power signal input terminal Pwr, and ground terminal Gnd, and one output terminal Out.

[0055] The display area also includes multiple signal lines, including drive signal lines (not shown in the figure) and ground signal lines (not shown in the figure).

[0056] In the aforementioned display panel, among the cascaded driver ICs, the output terminal Out of the previous stage driver IC is connected to the address signal input terminal Di of the next stage driver IC via a connecting line. The address signal input terminal Di of the first stage driver IC is connected to the corresponding bonding pin. The ground terminal Gnd of each driver IC is connected to the ground signal line.

[0057] The anode of the light-emitting unit is connected to the drive signal line via a connecting line, and the cathode of the light-emitting unit is connected to the output terminal Out of the corresponding driver chip IC via a connecting line, so as to control the light-emitting state of the light-emitting unit through the driver chip IC.

[0058] The aforementioned light-emitting unit may include at least one light-emitting device connected in series or in parallel, such as a mini LED light-emitting device or a micro LED light-emitting device.

[0059] In the aforementioned display panel manufacturing process, the possible breakdown paths of electrostatic discharge (ESD) accumulated on the substrate are as follows: Figure 2 In the direction indicated by the middle arrow, static electricity (ESD) can easily be conducted through the ground signal line to the ground terminal Gnd of the previous stage driver chip IC, to its output terminal Out, and then to the address signal input terminal Di of the next stage driver chip IC. Since the address signal input terminal Di of the driver chip IC has a weak resistance to static electricity (ESD), it will eventually lead to damage to the corresponding driver chip IC.

[0060] The circuit structure between the ground terminal Gnd of the previous stage driver chip IC and its output terminal Out is as follows: Figure 2 As shown, it includes an amplifier, resistor R4, N-type transistor (NMOS) K1, and transistor K2.

[0061] In the above path, the total resistance of electrostatic discharge (ESD) conduction includes the resistance R2 between the ground signal line and the ground terminal Gnd of the previous stage driver chip IC, the reverse resistance of N-type transistor (NMOS) K1 and transistor K2, and the resistance R1 of the connection line between the output terminal Out of the previous stage driver chip IC and the address signal input terminal Di of the next stage driver chip IC.

[0062] The reverse resistances of N-type transistor (NMOS) K1 and transistor K2 can be approximated by the reverse resistance of the PN junction (without breakdown), which are 500kΩ and 1kkΩ respectively.

[0063] The resistance R2 between the ground signal line and the ground terminal Gnd of the previous stage driver chip IC, and the resistance R1 between the output terminal Out of the previous stage driver chip IC and the address signal input terminal Di of the next stage driver chip IC, are both trace resistances. The trace resistance is calculated as: Resistance R = ρL / S = ρL / (hW). Where ρ is the resistivity of the trace (e.g., the resistivity ρ of copper traces is 0.0175Ωmm^2 / m), L is the length of the trace, W is the width of the trace, and h is the thickness of the trace. However, compared to the reverse resistance of N-type transistor (NMOS) K1 and transistor K2, the trace resistance is negligible. That is, the total resistance of electrostatic discharge (ESD) conduction in the above path is approximately 1kΩ.

[0064] In some cases, such as Figure 1 In the structure shown, the driver ICs corresponding to the light-emitting units in the same column can be connected to the same ground signal line and the same drive signal line. The driver ICs corresponding to the light-emitting units in the same row are cascaded sequentially. Since electrostatic discharge (ESD) will continue to conduct in the ground signal line until it reaches the end of the ground signal line where conduction is blocked, it will then be transmitted to the driver IC, causing damage. Therefore, most of the driver ICs damaged by ESD in the above display panel are concentrated in the first row of driver ICs on the side of the display area furthest from the bonding pins. Furthermore, because the driver ICs corresponding to the light-emitting units in the same row are cascaded, the static electricity in the above display panel may eventually concentrate on a few driver ICs in the first row. When the ESD reaches 12kV, it will cause damage to the driver IC at that location. Figure 1 As shown.

[0065] Therefore, embodiments of this application provide a display panel, such as... Figure 3and Figure 4 As shown, it includes a substrate 11, an electrostatic ring 12, and multiple signal lines 13.

[0066] The substrate 11 includes a display area 111 and a non-display area 112 located around the display area 111.

[0067] An electrostatic ring 12 is located within the non-display area 112.

[0068] The aforementioned multiple signal lines 13 are located within the display area 111.

[0069] Among them, the above-mentioned multiple signal lines 13 include at least a ground signal line 131. A static discharge structure 131a is provided on the side of the ground signal line 131 near the static ring 12. The static discharge structure 131a is used to release the static electricity on the ground signal line 131 to the static ring 12.

[0070] The aforementioned electrostatic discharge (ESD) protection structure prevents electrostatic discharge from damaging the signal lines and driver ICs within the display area 111, avoids adverse effects of ESD on the display area 111, enhances the overall anti-static (ESD) capability of the product, and further enables the normal display of the display device.

[0071] In some embodiments, the electrostatic discharge structure 131a includes a protrusion extending in a direction close to the electrostatic ring 12.

[0072] The protrusion allows static electricity to concentrate in it. When the charge in the protrusion accumulates to a certain extent, forming a large electric field, the static electricity can be released to the static ring 12.

[0073] In some embodiments, the line width of the protrusion gradually decreases along the direction close to the electrostatic ring 12.

[0074] In other words, the protrusion is a pointed protrusion that utilizes the principle of tip discharge, allowing static electricity to be concentrated at the tip of the protrusion. When a large charge accumulates at the tip of the protrusion, a large electric field is formed, and the static electricity can be transferred from the tip of the protrusion to the static ring 12 for release.

[0075] Furthermore, in this application, the electrostatic ring 12 is a wire-like structure, which can realize unidirectional discharge from the protrusion to the electrostatic ring 12. The static electricity on the electrostatic ring 12 cannot be released back into the display area 111, further protecting the signal lines, driver chip IC and other components in the display area 111, and further realizing the normal display of the display device.

[0076] In some embodiments, the shape of the orthographic projection of the protrusion onto the substrate 11 can be a triangle (including but not limited to an equilateral triangle, a right triangle, etc.), a trapezoid, or other pointed shapes with rounded ends.

[0077] In some embodiments, the line width of the electrostatic ring 12 is 0.2 mm.

[0078] In some embodiments, there is a gap between the orthographic projection of the electrostatic discharge structure 131a on the substrate 11 and the orthographic projection of the electrostatic ring 12 on the substrate 11.

[0079] In some embodiments, the gap width d between the orthographic projection of the electrostatic discharge structure 131a on the substrate 11 and the orthographic projection of the electrostatic ring 12 on the substrate 11 is greater than or equal to 0.2 mm.

[0080] In some embodiments, the electrostatic ring 12 and the ground signal line 131 may be located on the same layer. Furthermore, the electrostatic ring 12 and the electrostatic discharge structure 131a are at the same vertical distance from the substrate 11, so that the electrostatic ring 12 and the electrostatic discharge structure 131a are at the same height, so that the electrostatic discharge structure 131a can directly discharge the electrostatic ring 12.

[0081] Correspondingly, the minimum distance between the electrostatic discharge structure 131a and the ground signal line 131 can be understood as the limit value that the patterning process in the current display panel manufacturing process will not produce a short circuit, such as the limit value of the signal line spacing distance.

[0082] However, it should be noted that the gap between the electrostatic ring 12 and the grounding signal line 131 can have a certain upper limit to avoid the electrostatic discharge effect being affected when the distance between the electrostatic ring 12 and the grounding signal line 131 is too large, which may cause the static electricity to be released through other paths and damage the components in the display area 111.

[0083] In some embodiments, the electrostatic ring 12 and the ground signal line 131 may be located on different layers. In this case, the orthogonal projections of the electrostatic release structure 131a and the electrostatic ring 12 on the substrate 11 may contact or overlap. However, the electrostatic release structure 131a and the electrostatic ring 12 are separated by a dielectric layer, which also allows static electricity to be released from the electrostatic release structure 131a to the electrostatic ring 12.

[0084] In some embodiments, the grounding signal line 131 includes a main body 131c and a transition portion 131b disposed between the protrusion and the main body 131c.

[0085] In some embodiments, the line widths of the transition portion 131b and the protrusion are both smaller than the line width of the main body portion 131c.

[0086] In some embodiments, as the ground signal line 131 extends toward the electrostatic ring 12 to ensure the electrostatic discharge distance, the ground signal line 131 may overlap with other components. In order to avoid the formation of capacitance between different components and affect the display effect, the line width of the ground signal line 131 can be adaptively adjusted when the gap between other components is small during the extension of the ground signal line 131 toward the electrostatic ring 12, so as to avoid overlapping with other components.

[0087] In some embodiments, a bonding pin 15 is provided on the non-display area 112 for bonding connection with a flexible printed circuit (FPC). The aforementioned signal lines 13 and electrostatic rings 12 are all connected to their respective bonding pins 15 via connecting lines 16.

[0088] In some embodiments, the electrostatic ring 12 may be disposed on the other three sides of the non-display area 112 excluding the bonding area, and connected to the ground pin in the bonding pin 15 via the connecting line 16.

[0089] In some embodiments, the aforementioned multiple signal lines 13 may extend from the bonding pins 15 of the non-display area 112 into the display area 111 and then extend into the electrostatic ring 12.

[0090] In some embodiments, such as Figure 3 and Figure 4 As shown, in order to achieve a regular arrangement of the multiple signal lines 13 within the display area 111 and reduce the risk of short circuits between signal lines, the multiple signal lines 13 can extend from the bonding pins 15 in the non-display area 112 into the display area 111, and then to the side opposite to the bonding pins 15 (e.g., Figure 3 and Figure 4 The electrostatic ring 12 portion extends from the upper side shown.

[0091] Correspondingly, the electrostatic discharge structure 131a is located at the end of the grounding signal line 131 away from the bonding pin 15.

[0092] In some embodiments, the display panel further includes a plurality of light-emitting units 14 and a plurality of cascaded driver chip ICs.

[0093] The cascaded driver chip ICs are disposed within the display area 111; the driver chip ICs include multiple terminals, including at least a ground terminal Gnd, and the ground terminal Gnd of the driver chip ICs is connected to the ground signal line 131.

[0094] Multiple light-emitting units 14 are respectively connected to the driver chip IC and disposed in the display area 111.

[0095] The aforementioned multiple light-emitting units 14 can be arranged in an array within the display area 111, and the driving chip ICs corresponding to the light-emitting units 14 in the same column can be connected to the same ground signal line 131.

[0096] The light-emitting unit 14 may include at least one light-emitting device 141 connected in series or in parallel.

[0097] The light-emitting device 141 includes a mini LED light-emitting device 141 or a micro LED light-emitting device 141.

[0098] It can be understood that the light-emitting unit 14 includes one or more mini LED light-emitting devices 141 or micro LED light-emitting devices 141. When a light-emitting unit 14 includes multiple mini LED light-emitting devices 141 or multiple micro LED light-emitting devices 141, the connection method of each mini LED light-emitting device 141 or micro LED light-emitting device 141 in the light-emitting unit 14 is either in series or in parallel.

[0099] This means that the electrostatic discharge structure 131a described above can be applied to Micro-LED and mini-LED display panels. It can prevent electrostatic discharge from damaging the driver IC and light-emitting device 141 within the display area 111.

[0100] In some embodiments, the plurality of signal lines 13 further include a drive signal line 132, and the plurality of terminals further include an address signal input terminal Di and an output terminal Out; wherein, the first end of the light-emitting unit 14 is connected to the drive signal line 132, and the second end of the light-emitting unit 14 is connected to the output terminal Out of its corresponding driver chip IC; the output terminal Out of the previous stage driver chip IC is connected to the address signal input terminal Di of the next stage driver chip IC.

[0101] In some embodiments, the aforementioned plurality of terminals further include a power signal input terminal Pwr. Correspondingly, the aforementioned plurality of signal lines 13 also include power signal lines (not shown in the figure), and the power signal input terminal Pwr of each driver chip IC is connected to the power signal line.

[0102] In some embodiments, the connection lines 16 between the light-emitting devices 141 in the light-emitting unit 14 and the connection lines 16 between the driving chips IC can be insulated from and overlapped with the aforementioned multiple signal lines 13.

[0103] Among them, such as Figure 3 and Figure 4As shown, the light-emitting unit 14 may include nine light-emitting devices 141 connected in series. These nine devices are arranged in a 3x3 configuration, forming an S-shape. The ground signal line 131 corresponding to the light-emitting unit 14 can pass between the second and third columns of light-emitting devices 141. However, the projections of the light-emitting unit 14 and the ground signal line 131 onto the substrate 11 do not contact each other to avoid forming a capacitor that would affect the display effect. Furthermore, the ground signal line 131 corresponding to the light-emitting unit 14 can overlap with the connecting line 16 between the second and third columns of light-emitting devices 141 insulated manner. The overlap area is very small, resulting in a negligible capacitance. This overlap will not significantly affect the voltage on the connecting line 16 between the second and third columns of light-emitting devices 141, and the voltage here is still sufficient to meet the driving requirements of the light-emitting devices 141. If the bias voltage of a single light-emitting device 141 is 3V, the voltage difference at the overlap needs to provide voltage for the three light-emitting devices 141 in the third column. Therefore, at the overlap, the voltage difference between the connection line 16 of the light-emitting device 141 and the ground signal line 131 is the difference between 9V and the ground signal line 131, which is approximately 9V.

[0104] In some embodiments, the side of the light-emitting device 141 away from the substrate 11 is covered with a protective layer (not shown); wherein the orthographic projection of the ground signal line 131 on the substrate 11 does not cover the orthographic projection of the protective layer on the substrate 11. This is to prevent the ground signal line 131 from overlapping the edge of the protective layer, forming a gap, and causing some optical or short-circuit problems.

[0105] In some embodiments, the material of the protective layer includes lens adhesive, which is an organic material.

[0106] In some embodiments, the end of the protrusion furthest from the electrostatic ring 12 is equidistant from the adjacent light-emitting devices 141 on both sides in a direction parallel to the extension direction of the protrusion. This ensures that the electrostatic discharge structure 131a has the same effect on the adjacent light-emitting devices 141 in this direction, thereby minimizing the impact on the adjacent light-emitting devices 141 in this direction.

[0107] It can be understood that when the protrusion is a tip, according to the basic principle of tip discharge, the charge gradually accumulates from the bottom of the tip to the top. Compared with other non-tip positions, the amount of ESD charge accumulated from the bottom of the tip is greater. Therefore, when the end of the tip away from the electrostatic ring 12 (the bottom opposite the top) is at the same distance from the adjacent light-emitting devices 141 on both sides in the direction parallel to the extension direction of the protrusion, the influence on the adjacent light-emitting devices 141 on both sides is minimized.

[0108] In some embodiments, the length e of the electrostatic discharge structure 131a and the length k of the transition portion 131b can be determined based on the above structure and the gap width d between the orthogonal projection of the electrostatic discharge structure 131a on the substrate 11 and the orthogonal projection of the electrostatic ring 12 on the substrate 11.

[0109] like Figure 3 and Figure 4 As shown, the end (bottom) of the electrostatic discharge structure 131a (protrusion) away from the electrostatic ring 12 can be located between the first row of light-emitting devices 141 and the second row of light-emitting devices 141, and is located at the middle position between the first row of light-emitting devices 141 and the second row of light-emitting devices 141.

[0110] Correspondingly, in some embodiments, the length k of the transition portion 131b is 13.5 mm, and the length e of the electrostatic discharge structure 131a is 5.27 mm (i.e., the distance from the midpoint between the first row of light-emitting devices 141 and the second row of light-emitting devices 141 to the end of the electrostatic discharge structure 131a near the electrostatic ring 12). The sum of the two is the distance from the main body 131c of the grounding signal line 131 to the end of the electrostatic discharge structure 131a near the electrostatic ring 12.

[0111] In some embodiments, the end (bottom) of the electrostatic discharge structure 131a (protrusion) away from the electrostatic ring 12 may also be located between the second row of light-emitting devices 141 and the third row of light-emitting devices 141, and at the middle position between the second row of light-emitting devices 141 and the third row of light-emitting devices 141.

[0112] Correspondingly, in some embodiments, the length e of the electrostatic discharge structure 131a is 5.27 mm (i.e., the distance from the midpoint between the first row of light-emitting devices 141 and the second row of light-emitting devices 141 to the end of the electrostatic discharge structure 131a near the electrostatic ring 12) and the longitudinal distance of the two adjacent light-emitting devices 141 is 9.9 mm, resulting in 15.17 mm (i.e., the distance from the midpoint between the second row of light-emitting devices 141 and the third row of light-emitting devices 141 to the end of the electrostatic discharge structure 131a near the electrostatic ring 12); the length k of the transition portion 131b is 13.5 mm and the difference between the longitudinal distance of the two adjacent light-emitting devices 141 and 9.9 mm, resulting in 3.6 mm.

[0113] It should be noted that when the end of the electrostatic discharge structure 131a (protrusion) furthest from the electrostatic ring 12 is located between the first row of light-emitting devices 141 and the second row of light-emitting devices 141, the charge accumulated on the electrostatic discharge structure 131a may affect four light-emitting devices 141 within that range (four light-emitting devices 141 located in rows 1 and 2, and columns 2 and 3). Conversely, when the end of the electrostatic discharge structure 131a (protrusion) furthest from the electrostatic ring 12 is located between the second row of light-emitting devices 141 and the third row of light-emitting devices 141, the charge accumulated on the electrostatic discharge structure 131a may affect six light-emitting devices 141 within that range (six light-emitting devices 141 located in rows 1 and 3, and columns 2 and 3). Therefore, the first structure is superior to the second structure.

[0114] In some embodiments, the end of the protrusion away from the electrostatic ring 12 is equidistant from the adjacent light-emitting devices 141 on both sides in a direction perpendicular to the extension direction of the protrusion. This ensures that the electrostatic discharge structure 131a has the same effect on the adjacent light-emitting devices 141 in this direction, thereby minimizing the impact on the adjacent light-emitting devices 141 in this direction.

[0115] like Figure 3 and Figure 4 As shown, the end of the electrostatic discharge structure 131a (protrusion) away from the electrostatic ring 12 is located between the second row of light-emitting devices 141 and the third row of light-emitting devices 141, and is located at the middle position between the second row of light-emitting devices 141 and the third row of light-emitting devices 141.

[0116] like Figure 4 As shown, the line width 'a' of the drive signal line 132 can be designed based on the layout of the light-emitting devices 141 within the display area 111. For example, based on the width of the panel and the number of columns of the light-emitting devices 141, the total trace width and gap width corresponding to a single column of light-emitting units 14 are calculated, and then the width allocated to each trace is calculated. In addition, the wiring space in the sector area must also be considered.

[0117] Similarly, the maximum line width b of the grounding signal line 131 (the line width of the main body 131c) can also be designed in the same way as described above.

[0118] In addition, the design principle of the line width c of the transition portion 131b of the ground signal line 131 and the line width of the end (tip bottom) of the electrostatic discharge structure 131a away from the electrostatic ring 12 is as follows: the orthogonal projection of the ground signal line 131 on the substrate 11 does not cover the orthogonal projection of the protective layer covering the light-emitting device 141 on the substrate 11, so as to prevent the ground signal line 131 from overlapping with the edge of the protective layer, forming a break, and causing some optical or short-circuit problems. The orthogonal projection of the protective layer on the substrate 11 can be a circle with the center of the light-emitting device 141 as the center, that is, it can be calculated based on the distance between the light-emitting devices 141 and the diameter of the orthogonal projection of the protective layer on the substrate 11.

[0119] In some embodiments, the line width c of the transition portion 131b of the ground signal line 131 and the line width of the end (bottom of the tip) of the electrostatic discharge structure 131a away from the electrostatic ring 12 can be obtained by subtracting the superposition error of the protective layer from the distance between the protective layers corresponding to two adjacent columns of light-emitting devices 141.

[0120] In some embodiments, the distance between the protective layers corresponding to two adjacent columns of light-emitting devices 141 is 7.40 mm. Subtracting the superposition error of 0.40 mm, the line width c of the transition portion 131b of the ground signal line 131 and the line width of the end (bottom of the tip) of the electrostatic discharge structure 131a away from the electrostatic ring 12 are designed to be 7.00 mm.

[0121] The design values ​​for the above parameters can be found in Table 1.

[0122] Table 1 shows the design values ​​of various parameters in the display panel.

[0123] parameter illustrate Numerical value (mm) Line width of electrostatic ring 12 0.20 c Line width of transition section 131b of ground signal line 131 7.00 k The length of the transition section 131b of the grounding signal line 131 13.5 or 3.6 e Length of electrostatic discharge structure 131a 5.27 or 15.17 d The gap width between the electrostatic discharge structure 131a and the electrostatic ring 12 0.20

[0124] In such Figure 4 In the structure shown, there may be two paths for the transmission of static electricity: the first path (Path A) is: through the ground signal line 131, it is conducted through the ground terminal Gnd of the previous stage driver chip IC to its output terminal Out, and then to the address signal input terminal Di of the next stage driver chip IC; the second path (Path B) is: through the ground signal line 131 to the static discharge structure 131a, so as to release it onto the static ring 12. However, the first path (Path A) will cause damage to the driver chip IC and needs to be avoided.

[0125] Therefore, in some embodiments, the resistance of the electrostatic discharge structure 131a (especially the resistance between the ground signal line 131 and the end of the electrostatic discharge structure 131a near the electrostatic ring 12) is less than the resistance between the ground terminal Gnd of the previous stage driver chip IC and the address signal input terminal Di of the next stage driver chip IC. That is, the resistance of the second path (Path B) is less than the resistance of the first path (Path A). This ensures that static electricity can be conducted to the electrostatic discharge structure 131a through the second path (Path B) and released onto the electrostatic ring 12, rather than being conducted to the next stage driver chip IC through the ground terminal Gnd of the previous stage driver chip IC via the first path (Path A).

[0126] like Figures 3 to 5 As shown, the resistance between the grounding signal line 131 and the end of the electrostatic discharge structure 131a near the electrostatic ring 12 is the trace resistance. The trace length is the sum of the length of the transition portion 131b of the grounding signal line 131 and the length of the electrostatic discharge structure 131a. The trace resistance is calculated as: Resistance R = ρL / S = ρL / (hW). Where ρ is the resistivity of the connecting line 16 (e.g., the resistivity ρ of copper traces is 0.0175Ωmm^2 / m), L is the length of the connecting line 16, W is the width of the connecting line 16, and h is the thickness of the connecting line 16. According to the above formula, the resistance between the grounding signal line 131 and the end of the electrostatic discharge structure 131a near the electrostatic ring 12 is less than 1Ω, that is, the resistance of the second path (Path B) is less than 1Ω.

[0127] In some embodiments, the resistance between the ground terminal Gnd of the previous stage driver chip IC and the address signal input terminal Di of the next stage driver chip IC includes:

[0128] The resistance between the ground terminal Gnd of the previous stage driver chip IC and its output terminal Out, and the resistance between the output terminal Out of the previous stage driver chip IC and the address signal input terminal Di of the next stage driver chip IC.

[0129] In some embodiments, the circuit structure between the ground terminal Gnd of the previous-level driver chip IC and its output terminal Out is as follows: Figure 5 As shown, it includes an amplifier, resistor R4, N-type transistor (NMOS) K1, and transistor K2.

[0130] The total resistance of the first path (Path A) includes the resistance R2 between the ground signal line 131 and the ground terminal Gnd of the previous stage driver chip IC, the reverse resistance of the N-type transistor (NMOS) K1 and the transistor K2, and the resistance R1 of the connection line 16 between the output terminal Out of the previous stage driver chip IC and the address signal input terminal Di of the next stage driver chip IC.

[0131] The reverse resistances of N-type transistor (NMOS) K1 and transistor K2 can be approximated by the reverse resistance of the PN junction (without breakdown), which are 500kΩ and 1kkΩ respectively.

[0132] The resistance R2 between the ground signal line 131 and the ground terminal Gnd of the previous stage driver chip IC, and the resistance R1 of the connection line 16 between the output terminal Out of the previous stage driver chip IC and the address signal input terminal Di of the next stage driver chip IC, are both trace resistances. The trace resistance is calculated as: Resistance R = ρL / S = ρL / (hW). Where ρ is the resistivity of the connection line 16 (e.g., the resistivity ρ of copper traces is 0.0175Ωmm^2 / m), L is the length of the connection line 16, W is the width of the connection line 16, and h is the thickness of the connection line 16. However, compared to the reverse resistance of the N-type transistor (NMOS) K1 and the transistor K2, this trace resistance is negligible, that is, the total resistance of the first path (Path A) is approximately 1kΩ.

[0133] Clearly, the total resistance of the first path (Path A) is much greater than the resistance of the second path (Path B). That is, static electricity will be conducted through the second path (Path B) to the static discharge structure 131a and then released onto the static ring 12, instead of being conducted through the first path (Path A) to the next level driver chip IC via the internal structure of the previous level driver chip IC.

[0134] The first path (Path A) and the second path (Path B) can be considered as two parallel circuits. In this case, most of the electrostatic discharge (ESD) will discharge through the second path (Path B), thus protecting the driver IC on the first path (Path A) and improving the overall ESD resistance of the product. The discharge resistance of the static electricity released from the electrostatic discharge structure 131a to the electrostatic ring 12 is resistor R3.

[0135] In this application, an electrostatic discharge structure 131a is provided on the side of the grounding signal line 131 near the electrostatic ring 12 to release static electricity on the grounding signal line 131 to the electrostatic ring 12. This avoids damage to the signal lines and driver chip IC in the display area 111 caused by static electricity, prevents adverse effects of static electricity on the display area 111, improves the overall anti-static (ESD) capability of the product, and further enables the normal display of the display device.

[0136] This application also provides a display device, which includes the display panel described above.

[0137] In some embodiments, the display device further includes a housing, to which the display panel is connected; for example, the display panel is embedded within the housing. The display device can be, for example, any device with a display function such as a mobile phone, tablet computer, television, laptop computer, digital photo frame, or navigator.

[0138] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the scope of protection of this application. Although the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and variations in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display panel, characterized in that, include: A substrate, wherein the substrate includes a display area and a non-display area located around the display area; An electrostatic ring is disposed within the non-display area; Multiple signal lines are arranged within the display area; Multiple cascaded driver chips are disposed within the display area; The plurality of signal lines include at least a ground signal line, and an electrostatic discharge structure is provided on the side of the ground signal line near the electrostatic ring. The electrostatic discharge structure is used to release static electricity on the ground signal line to the electrostatic ring. The driver chip includes a plurality of terminals, and the plurality of terminals include at least a ground terminal, which is connected to the ground signal line. The plurality of terminals also include an address signal input terminal and an output terminal, and the output terminal of the driver chip at the previous stage is connected to the address signal input terminal of the driver chip at the next stage. The resistance of the electrostatic discharge structure is less than the resistance between the ground terminal of the previous stage driver chip and the address signal input terminal of the next stage driver chip.

2. The display panel according to claim 1, characterized in that, The electrostatic discharge structure includes a protrusion extending in a direction close to the electrostatic ring.

3. The display panel according to claim 2, characterized in that, The line width of the protrusion gradually decreases along the direction close to the electrostatic ring.

4. The display panel according to claim 1, characterized in that, There is a gap between the orthographic projection of the electrostatic discharge structure on the substrate and the orthographic projection of the electrostatic ring on the substrate.

5. The display panel according to claim 4, characterized in that, The width of the gap is greater than or equal to 0.2 mm.

6. The display panel according to claim 4, characterized in that, The grounding signal line and the electrostatic ring are located on the same layer.

7. The display panel according to claim 2, characterized in that, The grounding signal line includes a main body and a transition portion disposed between the protrusion and the main body.

8. The display panel according to claim 7, characterized in that, The line widths of the transition portion and the protrusion are both smaller than the line width of the main body portion.

9. The display panel according to claim 2, characterized in that, Also includes: Multiple light-emitting units are respectively connected to the driving chip and disposed in the display area.

10. The display panel according to claim 9, characterized in that, The plurality of signal lines also includes drive signal lines; The first end of the light-emitting unit is connected to the driving signal line, and the second end of the light-emitting unit is connected to the output terminal of the corresponding driving chip.

11. The display panel according to claim 10, characterized in that, The plurality of signal lines also include power signal lines, and the plurality of terminals also include power signal input terminals; The power signal input terminal of the driver chip is connected to the power signal line.

12. The display panel according to claim 1, characterized in that, The resistance between the ground terminal of the driver chip at the previous stage and the address signal input terminal of the driver chip at the next stage includes: The resistance between the ground terminal and the output terminal of the previous stage driver chip, and the resistance between the output terminal of the previous stage driver chip and the address signal input terminal of the next stage driver chip.

13. The display panel according to claim 9, characterized in that, The light-emitting unit includes at least one light-emitting device connected in series or in parallel.

14. The display panel according to claim 13, characterized in that, The side of the light-emitting device away from the substrate is covered with a protective layer; Wherein, the orthogonal projection of the grounding signal line on the substrate does not cover the orthogonal projection of the protective layer on the substrate.

15. The display panel according to claim 13, characterized in that, In a direction perpendicular to the extension direction of the protrusion, the end of the protrusion away from the electrostatic ring is equidistant from the adjacent light-emitting devices on both sides.

16. The display panel according to claim 13, characterized in that, In a direction parallel to the extension direction of the protrusion, the end of the protrusion away from the electrostatic ring is equidistant from the adjacent light-emitting devices on both sides.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 16.

Images