Electronic devices including capacitors and related methods and systems

Abstract

This application relates to electronic devices including capacitors, and related methods and systems. The electronic devices include one or more capacitors proximate to a base material. The one or more capacitors include at least one electrode extending horizontally within the base material and an additional electrode extending vertically within the base material and contacting the at least one electrode. The at least one electrode is located below and isolated from an upper surface of the base material.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 17 / 115,469, “ELECTRONIC DEVICES INCLUDING CAPACITORS, AND RELATED METHODS AND SYSTEMS,” filed December 8, 2020. TECHNICAL FIELD

[0003] Embodiments disclosed herein relate to electronic devices and electronic device manufacturing. More specifically, embodiments of the present disclosure relate to electronic devices including capacitors and to related methods and systems. BACKGROUND

[0004] Electronic device designers generally desire to increase the integration, which can also be described as the density, of features within an electronic device by reducing the size of individual features and by reducing the distance between adjacent features. In addition, electronic device designers generally desire to design architectures that are not only compact but also provide performance advantages and simplify design. Reducing the size and pitch of features increases the need for methods for forming electronic devices. One solution is to form three-dimensional (3D) electronic devices, such as non-volatile memory devices (e.g., 3D NAND flash memory devices), in which memory cells are positioned vertically on a substrate. In such memory devices, capacitors are used for various types of peripheral circuitry, such as charge pump circuitry, sense amplifiers, page buffers, etc. These capacitors are formed as metal-oxide-semiconductor (MOS) capacitors or well capacitors over a base material (e.g., a semiconductor substrate) by the same methods used to form transistors used in other circuitry. Such memory devices can include one or more memory arrays, which can be over a complementary metal-oxide-semiconductor (CMOS) region, such as a below-array CMOS (CuA) region. The reliability and performance of integrated circuits can be affected by the quality of their interconnect structures. However, as memory cells and associated capacitors are formed more closely and in smaller sizes, it is increasingly difficult to increase capacitance within a given area and / or reduce footprint to optimize packing density SUMMARY

[0005] The embodiments described herein include electronic devices containing capacitors and related methods and systems. According to the embodiments described herein, an electronic device includes one or more capacitors adjacent to a substrate material. The one or more capacitors include at least one electrode extending horizontally within the substrate material. The at least one electrode is located below and isolated from a higher surface of the substrate material. The one or more capacitors include additional electrodes extending vertically within the substrate material and contacting the at least one electrode.

[0006] According to an additional embodiment described herein, an electronic device includes a capacitor comprising gate electrodes. Each of the gate electrodes includes an upper electrode adjacent to an upper surface of a substrate material, at least one lower electrode extending horizontally within the substrate material, and a post region extending vertically within the substrate material between the upper electrode and the at least one lower electrode.

[0007] Furthermore, according to an additional embodiment described herein, a system includes: a processor operatively coupled to input and output devices; and an electronic device operatively coupled to the processor. The electronic device includes at least one array of memory cells and embedded capacitors adjacent to a substrate material. Each of the embedded capacitors includes a gate electrode having a first region extending in a vertical direction and at least one second region extending in a horizontal direction substantially transverse to the vertical direction. The first region and the at least one second region are substantially continuous.

[0008] According to other embodiments described herein, a method of forming an electronic device includes forming a sacrificial material extending horizontally within a substrate material. The sacrificial material is located below and isolated from a upper surface of the substrate material. The method includes: forming an opening extending into the sacrificial material; removing the sacrificial material within the opening; and forming a conductive material adjacent to the upper surface of the substrate material and within the opening. The conductive material is configured as a gate electrode of a capacitor. Attached Figure Description

[0009] FIGS. 1A-1E A cross-sectional view illustrating the formation of an electronic device including a capacitor according to an embodiment of the present disclosure;

[0010] FIG. 1F According to embodiments of this disclosure FIGS. 1A-1E A perspective view of an electronic device;

[0011] FIGS. 2A-2E A cross-sectional view illustrating the formation of an electronic device including a capacitor according to other embodiments of the present disclosure;

[0012] FIG. 2F According to embodiments of this disclosure FIGS. 2A-2E A perspective view of an electronic device;

[0013] FIGS. 3A-3E A top view illustrating an electronic device according to an embodiment of the present disclosure ( FIG. 3A , 3C and 3E) and cross-sectional view ( FIG. 3B and 3D ),in FIG. 3B and 3D The cross-sectional views are respectively along FIG. 3A and 3C Cut off the AA and BB lines in the middle;

[0014] FIGS. 4A-4C A top view illustrating an electronic device according to an embodiment of the present disclosure ( FIG. 4A ) and cross-sectional view ( FIG. 4B and 4C ),in FIG. 4B and 4C The cross-sectional view along FIG. 4A The CC line in the middle is cut off;

[0015] FIG. 5A and 5B In order to be with FIG. 3A and 3B A top view of a conventional electronic device at a processing stage similar to the processing stage. FIG. 5A ) and cross-sectional view ( FIG. 5B ),in FIG. 5B The cross-sectional view along FIG. 5A Extract the DD line in the middle;

[0016] FIG. 6 A partial cross-sectional perspective view of an electronic device according to an embodiment of the present disclosure;

[0017] FIG. 7A A schematic block diagram illustrating an electronic device according to an embodiment of the present disclosure;

[0018] FIG. 7B for FIG. 7A A portion of the schematic diagram of the electronic device; and

[0019] FIG. 8 A schematic block diagram illustrating a system according to an embodiment of the present disclosure. Detailed Implementation

[0020] Disclosed are electronic devices (e.g., apparatus, semiconductor devices, memory devices) comprising one or more capacitors. The electronic device includes one or more capacitors adjacent to a substrate material. The capacitor includes at least one electrode (e.g., one or more lower electrodes) extending horizontally within the substrate material, and an additional electrode (e.g., within a post region) extending vertically within the substrate material and contacting the at least one electrode. The at least one electrode is located below and isolated from an upper surface of the substrate material. The capacitor also includes an upper electrode covering the upper surface of the substrate material. The upper electrode contacts the additional electrode, wherein the main surface of the upper electrode is substantially transverse to the longitudinal axis of the additional electrode. The combination of the upper electrode, the additional electrode, and the at least one electrode serves as the gate electrode of the capacitor. At least one electrode of the gate electrode can be formed by: forming a sacrificial material (e.g., a doped material) extending horizontally within the substrate material; removing the sacrificial material; and forming a conductive material of the gate electrode (e.g., a lower electrode) within a region of the substrate material vacated after the removal of the sacrificial material. In some embodiments, the width of the at least one lower electrode is relatively larger in the horizontal direction than the width of the upper electrode. The capacitors can be configured as so-called "embedded" double-sided capacitors. At least some of the capacitors may be located within the page buffer region of an array-under-array CMOS (CuA) region beneath at least one memory cell array.

[0021] The capacitor can be configured as a so-called "embedded" two-sided capacitor. For example, since at least one electrode extends horizontally within the substrate material and an additional electrode extends vertically within the substrate material, the additional electrode is side-connected to a first opposing surface of the substrate material and the at least one electrode is side-connected to a second opposing surface of the substrate material, wherein the second opposing surface of the substrate material is substantially orthogonal to the first opposing surface of the substrate material. By providing a capacitor with an orthogonal arrangement of two-sided regions within the substrate material and different (e.g., horizontal and vertical) orientations of individual regions of the gate electrode within the substrate material of the electronic device, such a configuration allows for improvements (e.g., increases) in the capacitance of the capacitor within a given footprint, which can result in an increase in capacitance in a given region or a reduction in the area allocated to the capacitor. Such a configuration can result in an increase in capacitance within a given region during the use and operation of the electronic device without requiring an increase in the capacitor's footprint.

[0022] The following description provides specific details, such as material type, material thickness, and processing conditions, to provide a sufficient description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the descriptions provided herein do not constitute a complete description of an electronic device or a complete process flow for manufacturing an electronic device, and the structures described below do not constitute a complete electronic device. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions to form a complete electronic device can be performed using conventional techniques.

[0023] Unless otherwise indicated, the materials described herein may be formed using conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionized PVD, and / or plasma-enhanced CVD), or epitaxial growth. Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the materials may be selected by one of ordinary skill in the art. Unless the context otherwise indicates, material removal may be achieved by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization (e.g., chemical mechanical planarization), or other known methods.

[0024] The figures presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, electronic device, or electronic system. The shapes depicted in the figures are expected to vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but should include, for example, shape variations caused by manufacturing processes. For instance, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may include some rough and / or linear characteristics. Furthermore, illustrated acute angles may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The figures are not necessarily drawn to scale. Additionally, common elements between figures may retain the same numerical designation.

[0025] Unless the context clearly indicates otherwise, the singular forms “a (a, an)” and “the” as used herein are intended to also include the plural forms.

[0026] As used in this article, “and / or” includes any and all combinations of one or more of the associated listed items.

[0027] As used herein, the term "about" or "approximately" with respect to a particular parameter includes the value, and those skilled in the art will understand that the deviation from the value is within acceptable tolerances for the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​within 90.0% to 110.0% of the value, such as within 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0028] As used herein, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” and “right” may be used to describe the relationship between one element or feature and another illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures were inverted, then an element described as “below,” “under,” “below,” or “on the bottom” of another element or feature would be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may cover both above and below orientations depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0029] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by structural surfaces that have a relatively large area compared to the other surfaces of the structure.

[0030] As used herein, the term "conductive material" means and includes electrically conductive materials. Conductive materials may include, but are not limited to, one or more of the following: doped polysilicon, undoped polysilicon, metals, alloys, conductive metal oxides, conductive metal nitrides, conductive metal silicides, and conductive doped semiconductor materials. By way of example only, conductive materials may be one or more of the following: tungsten (W), tungsten nitride (WN) yNickel (Ni), Tantalum (Ta), Tantalum nitride (TaN) y ), Tantalum silicide (TaSi) x Platinum (Pt), Copper (Cu), Silver (Ag), Gold (Au), Aluminum (Al), Molybdenum (Mo), Titanium (Ti), Titanium Nitride (TiN) y Titanium silicide (TiSi) x Titanium silicon nitride (TiSi) x N y ), Titanium aluminum nitride (TiAl) x N y ), molybdenum nitride (MoN) x ), iridium (Ir), iridium oxide (IrO) z ), Ruthenium (Ru), Ruthenium oxide (RuO) z ), n-doped polycrystalline silicon, p-doped polycrystalline silicon, undoped polycrystalline silicon, and conductive doped silicon.

[0031] As used herein, the term "dielectric material" means and includes electrically insulating materials. Dielectric materials may include, but are not limited to, one or more insulating oxide materials or insulating nitride materials. Insulating oxides may be silicon oxide materials, metal oxide materials, or combinations thereof. Insulating oxides may include, but are not limited to, silicon oxide (SiO₂). x Silicon dioxide (SiO2), phosphosilicate glass, borosilicate glass, borosilicate-phosphosilicate glass, fluorosilicate glass, alumina (AlO2) x ), gadolinium oxide (GdO) x ), Hafnium oxide (HfO) x ), magnesium oxide (MgO) x ), niobium oxide (NbO) x ), tantalum oxide (TaO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x Hafnium silicate, dielectric oxide nitride materials (e.g., SiO2), x N y ), dielectric carbon oxynitride materials (e.g., SiO2) x C z N y ( ), or combinations thereof, or combinations of one or more of the listed materials with silicon oxide. Insulating nitride materials may include, but are not limited to, silicon nitride.

[0032] As used herein, the term “configured as” refers to the size, shape, material composition, and arrangement of one or more of at least one structure and at least one device, which in a predetermined manner facilitates the operation of one or more of the structure and device.

[0033] As used herein, the term "selectively etchable" means and includes a material exhibiting a greater etching rate relative to another material exposed to a given etching chemical and / or processing condition in response to exposure to the same etching chemical and / or processing conditions. For example, the material may exhibit an etching rate at least about five times greater than that of another material, such as about ten times, about twenty times, or about forty times greater. Those skilled in the art can select the etching chemicals and etching conditions used for selectively etching the desired material.

[0034] As used herein, the term "electronic device" includes, but is not limited to, memory devices, and semiconductor devices, such as logic devices, processor devices, or radio frequency (RF) devices, which may or may not incorporate memory. Furthermore, electronic devices may incorporate memory and other functionalities, such as a so-called "system-on-a-chip (SoC)" that includes a processor and memory, or an electronic device that includes logic and memory. Electronic devices can be, for example, 3D electronic devices, such as 3D NAND flash memory devices.

[0035] As used herein, features described as “adjacent” to each other (e.g., area, material, structure, device) mean and include features of one or more disclosed identifiers located closest to each other (e.g., closest to each other). Additional features of one or more disclosed identifiers that do not match “adjacent” features (e.g., additional area, additional material, additional structure, additional device) may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other mean and include features of one or more disclosed identifiers located closest to each other (e.g., vertically closest to each other). Furthermore, features described as “horizontally adjacent” to each other mean and include features of one or more disclosed identifiers located closest to each other (e.g., horizontally closest to each other).

[0036] As used herein, referring to an element as “on” or “above” another element means and includes that the element is directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) another element, below another element, or in direct contact with another element. This also includes that the element is indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) another element, below another element, or near another element where other elements are present. Conversely, when an element is referred to as “directly on” or “immediately adjacent to” another element, there is no intervening element.

[0037] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition is satisfied with a deviation (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. As an example, depending on the specific parameter, property, or condition that is substantially satisfied, it may be satisfied with at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0038] As used herein, the term "substrate" means and includes materials (e.g., base materials) on which additional materials are formed. A substrate can be an electronic substrate, a semiconductor substrate, a base semiconductor layer on a support structure, electrodes, an electronic substrate on which one or more materials, layers, structures, or regions are formed, or a semiconductor substrate on which one or more materials, layers, structures, or regions are formed. Materials on an electronic or semiconductor substrate may include, but are not limited to, semiconductive, insulating, and conductive materials. A substrate can be a conventional silicon substrate or other bulk substrate including layers of semiconductive material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a base semiconductor, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. A substrate can be doped or undoped.

[0039] FIGS. 1A-1F This description illustrates a method for forming an electronic device including a capacitor at various stages of a process according to embodiments of the present disclosure. For simplicity, the formation of a single device structure is described; however, those skilled in the art will understand that the method includes simultaneously forming multiple electronic devices (e.g., more than one electronic device, an array of electronic devices). For ease of description... FIGS. 1A-1F The first direction can be defined as the X direction, and the second direction, which is laterally (e.g., perpendicular to) the first direction, is defined as the Y direction. A third direction, which is laterally (e.g., perpendicular to) each of the first and second directions, can be defined as the Z direction. FIGS. 2A-6 The examples shown here limit the direction, as will be discussed in more detail below.

[0040] FIGS. 1A-1F The diagram shows a configuration comprising one or more capacitors 130 (see also...) FIG. 1E A method for using an electronic device 100. The electronic device 100 includes a substrate material 102 (e.g., a semiconducting material, a substrate), a mask material 104, a sacrificial material 105 for a doped region 106, and an undoped region 108 of the substrate material 102. FIG. 1AAs shown, mask material 104 (e.g., mask or resist material) may optionally be positioned adjacent to (e.g., on or above) the upper surface 102a of substrate material 102. Mask material 104 may be formed from and contain at least one of the following: amorphous carbon, silicon, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, and silicon oxynitride. In some embodiments, mask material 104 is formed from and contains at least one dielectric oxide material (e.g., one or more of silicon dioxide and aluminum oxide). In other embodiments, mask material 104 is formed from and contains silicon nitride. Mask material 104 may be homogeneous (e.g., may contain a single material) or heterogeneous (e.g., may contain a stack of at least two different materials). Mask material 104 may be formed using conventional processes and patterned using conventional patterning and material removal processes, such as conventional photolithography exposure processes, conventional development processes, conventional etching processes, and conventional processing equipment, which are not described in detail herein.

[0041] After the mask material 104 is formed, selected portions of the substrate material 102 may be doped (e.g., implanted) with one or more dopants (e.g., chemicals) to form doped regions 106 within undoped regions 108 (e.g., less doped or substantially undoped material) of the substrate material 102. In some embodiments, the dopant is dispersed in a region A below and away from the upper surface 102a of the substrate material 102 at a selected distance from said upper surface 102a, and the dopant is dispersed only partially through (e.g., less than completely through) the height of the substrate material 102 (e.g., in the Z direction). For example, such as FIG. 1A As shown, the substrate material 102 may include a horizontally extending portion of a doped region 106 and an undoped region 108 horizontally adjacent to (e.g., laterally adjacent to) the doped region 106. In other words, at least a portion of the undoped region 108 may be vertically aligned with (e.g., shielded by) the mask material 104. Additional portions of the undoped region 108 may be vertically adjacent to (e.g., vertically over, vertically under) the doped region 106. Thus, the doped region 106 may be substantially (e.g., completely) surrounded by the undoped region 108 of the substrate material 102.

[0042] The substrate material 102 may be doped with at least one dopant using conventional processes (e.g., conventional implantation processes, conventional diffusion processes) to form the sacrificial material 105 of the doped region 106. As a non-limiting example, at least one n-type dopant, such as phosphorus, arsenic, antimony, and bismuth, may be implanted into a desired portion of the substrate material 102 to form the doped region 106. As another non-limiting example, at least one p-type dopant, such as boron, aluminum, and gallium, may be implanted into a desired portion of the substrate material 102 to form the doped region 106. As yet another non-limiting example, the dopant may comprise one or more of carbon, fluorine, chlorine, bromine, hydrogen, deuterium, helium, neon, and argon. In some embodiments, hydrogen is used as the dopant to form the hydrogen-implanted doped region 106. The doped region 106 may be doped to a sufficient degree to provide etch selectivity between the doped region 106 and the undoped region 108 of the substrate material 102.

[0043] After dopant implantation, an annealing action can be performed, for example, to diffuse the dopant into the doped region 106. For example, the substrate material 102 containing at least one dopant can be annealed (e.g., thermal annealing, laser annealing) to form the doped region 106 within the substrate material 102. By forming the doped region 106, the sacrificial material 105 can be selectively removed (e.g., selectively etched) relative to the material of the undoped region 108. After forming the sacrificial material 105 of the doped region 106, the mask material 104 (if present) can be removed.

[0044] An opening 110 (e.g., an access point) is formed in the substrate material 102, such as FIG. 1B As shown in the diagram. Opening 110 may be adjacent to the doped region 106 (e.g., above the doped region 106) to expose the desired portion of the doped region 106 and may extend through the undoped region 108 of the substrate material 102. Opening 110 may be formed using conventional techniques. Although FIG. 1B This describes three openings 110, but more than three openings 110 may exist. Opening 110 corresponds to the gate electrode 120 to be ultimately formed (see [reference]). FIG. 1E The location of the post region 124 (e.g., an additional electrode). In some embodiments, the opening 110 may extend from the upper surface 102a of the substrate material 102 to the upper surface of the doped region 106, such as... FIG. 1BAs shown in the figure. In other embodiments, at least some of the openings 110 may extend through the doped region 106 and into the lower portion of the substrate material 102. In yet another embodiment, alternative access points may be provided to expose a portion of the sacrificial material 105 within the doped region 106. For example, one or more lateral openings (not shown) may be formed to provide access to the sacrificial material 105 of the doped region 106, but other configurations are contemplated. The size of the openings 110 may be selected to expose the desired surface area of ​​the undoped region 108 of the substrate material 102. As a non-limiting example, the height of the openings 110 may range from about 200 nanometers (nm) to about 1000 nm (1 μm), for example, in the range of about 200 nm to about 400 nm, about 400 nm to about 600 nm, about 600 nm to about 800 nm, or about 800 nm to about 1000 nm. In some embodiments, the opening 110 has an aspect ratio (e.g., high aspect ratio (HAR)) in the range of about 5:1 to about 40:1, for example, between about 5:1 and about 10:1, between about 10:1 and about 20:1, or between about 20:1 and about 40:1. In other embodiments, the aspect ratio of the opening 110 is in the range of about 2:1 to about 5:1, for example, between about 3:1 and about 5:1. The aspect ratio of the opening 110 can be adjusted to have a desired value that can be selected at least in part based on the design requirements of the electronic device 100.

[0045] refer to FIG. 1C The sacrificial material 105 of the doped region 106 can be substantially removed by the opening 110 extending vertically through the substrate material 102. FIG. 1B An opening 112 is formed, extending laterally within the substrate material 102. Removing the sacrificial material 105 exposes the horizontally extending surface of the sacrificial material 105 of the undoped region 108 of the substrate material 102, which was previously adjacent to the doped region 106 within the opening 112. The opening 112 corresponds to the gate electrode 120 to be ultimately formed (see...). FIG. 1EThe location of the lower electrode 126 of the doped region 106. As a non-limiting example, the sacrificial material 105 of the doped region 106 can be selectively removed by exposing the sacrificial material 105 to at least one wet etchant, said at least one wet etchant comprising one or more of the following: phosphoric acid, sulfuric acid, acetic acid, nitric acid, hydrochloric acid, aqua regia, hydrogen peroxide, or another etching chemical. In some embodiments, a phosphoric acid-acetic acid-nitric acid (PAN) etchant is used to remove the sacrificial material 105. However, this disclosure is not limited thereto, and other etchants and / or material removal processes (e.g., vapor phase removal processes, atomic layer removal processes) can be used to remove the sacrificial material 105 of the doped region 106. In some embodiments, the sacrificial material 105 of the doped region 106 is removed by exposing it to one or more dry etchants (e.g., one or more chlorine-containing dry etchants). As a non-limiting example, the one or more dry etchants may contain one or more of chlorine, boron trichloride (BCL3), oxygen, and argon. In some embodiments, the sacrificial material 105 of the doped region 106 is selectively removed by exposure to a dry etchant comprising chlorine gas and boron trichloride. The sacrificial material 105 of the doped region 106 can be removed (e.g., substantially completely removed). FIG. 1B This results in the electronic device 100 being substantially free of (e.g., substantially lacking) the sacrificial material 105 of the doped region 106. In other embodiments, a portion of the sacrificial material 105 of the doped region 106 may be retained within one or more of the openings 110 and 112 (e.g., along the periphery of the openings). In some cases, a portion of the undoped region 108 exposed after the removal of the sacrificial material 105 may also be removed, such that the final dimensions (e.g., final height, final width) of one or more of the openings 110 and 112 are relatively larger than the initial dimensions (e.g., initial height, initial width) of the openings 110 and 112.

[0046] like FIG. 1D As shown in the figure, in the removal of the doped region 106, the sacrificial material 105 ( FIG. 1BSubsequently, dielectric material 114 (e.g., gate dielectric) may be formed within openings 110 and 112 and above the exposed upper and side surfaces of the substrate material 102. For example, dielectric material 114 may be formed adjacent to the upper surface 102a of the substrate material 102 outside opening 110 (e.g., on or above said upper surface 102a). Dielectric material 114 may also be formed adjacent to the exposed surfaces of the substrate material 102 (e.g., upper surface, lower surface) (e.g., below or above said exposed surfaces) and laterally adjacent to the sidewalls of the substrate material 102 within openings 110 and 112. In other words, dielectric material 114 may substantially completely cover the exposed surfaces of the substrate material 102 within each of openings 110 and 112. In some embodiments, dielectric material 114 is formed immediately adjacent to the exposed surfaces of the substrate material 102, and not formed in the central portions of openings 110 and 112. In some embodiments, the dielectric material 114 is a high-quality silicon oxide material, such as ALD SiO2. x For example, a highly uniform and conformal silicon oxide material (e.g., a highly uniform and conformal silicon dioxide material) can be used such that no voids are formed within the openings 110, 112. Specifically, the dielectric material 114 can be formulated to form in high aspect ratio (HAR) openings, such as openings having a HAR of at least about 20:1, at least about 50:1, at least about 100:1, or at least about 1000:1, without forming voids. As a non-limiting example, the thickness of the dielectric material 114 can be in the range of about 3 nm to about 30 nm, for example, in the range of about 3 nm to about 5 nm, about 5 nm to about 10 nm, about 10 nm to about 20 nm, or about 20 nm to about 30 nm. The dielectric material 114 can be formed using one or more conformal deposition processes, such as one or more of conventional conformal CVD processes or conventional ALD processes.

[0047] Still referencing FIG. 1DThe exposed surfaces of the substrate material 102 on the opposing surfaces within the opening 110 facilitate the formation of a first opposing surface 116 of the substrate material 102, which is adjacent to (e.g., horizontally adjacent to) the opposing sides of the opening 110 and extends in a vertical direction (e.g., the Z direction). The exposed surfaces of the substrate material 102 on the opposing surfaces within the opening 112 facilitate the formation of a second opposing surface 118 of the substrate material 102, which is adjacent to (e.g., vertically adjacent to) the opposing sides of the opening 112 and extends in a horizontal direction (e.g., the X direction). In other words, for illustrative purposes only, the first opposing surface 116 and the second opposing surface 118 are defined as the surfaces of the substrate material 102 that are respectively adjacent to the dielectric material 114 within the openings 110 and 112. A first opposing surface 116 of the substrate material 102 extending in a vertical direction and a second opposing surface 118 of the substrate material 102 extending in a horizontal direction and orthogonal to the first opposing surface 116 provide a larger surface area of ​​the substrate material 102 within a given region for a capacitor subsequently formed within the substrate material 102, as described in more detail below. Since the first opposing surface 116 of the substrate material 102 is adjacent to the opening 110, a two-sided (e.g., opposing) region is formed within the substrate material 102. Similarly, since the second opposing surface 118 of the substrate material 102 is adjacent to the opening 112, a two-sided (e.g., opposing) region is formed within the substrate material 102. The formation of such two-sided regions within the substrate material 102 enhances (e.g., increases) the presence of more than one side (e.g., two opposing sides) within the substrate material 102 for forming the capacitor 130. FIG. 1E The available surface area of ​​the first opposing surface 116 relative to the upper surface 102a of the substrate material 102 and the horizontal orientation of the second opposing surface 118 below and isolated from the upper surface 102a of the substrate material 102 contribute to the formation of a multi-dimensional (e.g., two-dimensional) region between the openings 110 and 112 within the substrate material 102, such as... FIG. 1D As shown in the image.

[0048] like FIG. 1E As shown, the conductive material 119 of the gate electrode 120 is formed in the opening 110. FIG. 1D ) and opening 112 ( FIG. 1DIn the process of forming a capacitor 130, the conductive material 119 of the gate electrode 120 may be formed of and contain polysilicon. In some embodiments, the conductive material 119 of the gate electrode 120 is n-doped polysilicon, p-doped polysilicon, or undoped polysilicon. In other embodiments, the conductive material 119 of the gate electrode 120 may be formed of and contain tungsten-containing material or other conductive metal. The gate electrode 120 may be formed to include individual portions comprising an upper electrode 122, a post region 124, and a lower electrode 126. The upper electrode 122 is formed adjacent to (e.g., above) a dielectric material 114, which covers the upper surface of the substrate material 102 outside the opening 110, wherein the main surface of the upper electrode 122 is substantially parallel to the upper surface 102a of the substrate material 102. The post region 124 is formed as a dielectric material 114 adjacent to the opening 110, wherein the longitudinal axis of the post region 124 extends vertically through the substrate material 102 and is substantially transverse to the main surface of the upper electrode 122. The lower electrode 126 is formed as a dielectric material 114 adjacent to the opening 112, wherein the main surface of the lower electrode 126 is substantially parallel to the main surface of the upper electrode 122. The material of the upper electrode 122 may be the same as or different from the material of one or more of the post regions 124 and the lower electrode 126. For convenience, the upper electrode 122, the post region 124, and the lower electrode 126 are shown in the figures as individual portions of the gate electrode 120, but it should be understood that in some embodiments, the gate electrode 120 comprises substantially continuous portions of one or more (e.g., a single) conductive material. As used herein, the term “continuous” means and includes material that is substantially without interruption, such as voids, gaps, orifices, or other openings. Therefore, in some embodiments, one or more of the upper electrode 122, the post region 124, and the lower electrode 126 may comprise substantially the same chemical composition and have no easily identifiable physical interface between them. In other embodiments, one or more of the upper electrode 122, the post region 124, and the lower electrode 126 may be formed of and comprise a chemical composition different from one or more other portions of the gate electrode 120.

[0049] The dielectric material 114 can substantially completely surround the gate electrode 120 within the openings 110 and 112, such that individual portions of the gate electrode 120 (e.g., the upper electrode 122, the post region 124, and the lower electrode 126) are electrically and physically isolated from the substrate material 102 by the dielectric material 114. In some embodiments, the dielectric material 114 comprises substantially continuous portions of one or more (e.g., a single) materials. The gate electrode 120 can be formed using conventional techniques (e.g., conformally formed) in the opening 110 ( FIG. 1D ) and opening 112 ( FIG. 1DIn each of the openings 110 and 112. In some embodiments, the gate electrode 120 may substantially fill (e.g., substantially completely fill) each of the openings 110 and 112. In other embodiments, at least some of the post regions 124 of the gate electrode 120 may include one or more additional materials (e.g., insulating material, support structure) within the central portion of the opening 110, such that the post regions 124 act as mechanical support posts, as referenced. FIG. 4C A more detailed description. In FIG. 1E In this configuration, the post region 124 of the gate electrode 120 in the opening 110 is adjacent to the top portion of the lower electrode 126 within the opening 112 (e.g., above said top portion). Therefore, the post region 124 directly contacts the lateral portion of the lower electrode 126, such as... FIG. 1E As shown in the diagram. In other embodiments, at least some of the post regions 124 may extend vertically through the lower electrode 126 and into the lower portion of the substrate material 102. The upper electrode 122 is adjacent to (e.g., above) the top portion of the post region 124 and directly contacts the post region 124. In some embodiments, each of the upper electrode 122, post region 124, and lower electrode 126 of the gate electrode 120 may be formed using a single deposition operation. In other embodiments, one or more individual portions of the gate electrode 120 (e.g., the upper electrode 122) may be formed after one or more other portions of the gate electrode 120 (e.g., the post region 124, the lower electrode 126). Excess material of the upper electrode 122 may be removed, such as... FIG. 1E As shown in the figure, a gate electrode 120 is formed within each of the openings 110 and 112 and adjacent to the upper surface 102a of the substrate material 102 (e.g., above the upper surface 102a).

[0050] like FIG. 1E As shown, the upper electrode 122 of the gate electrode 120 can be formed with a width W 122 (For example, the horizontal dimension in the X direction), and the lower electrode 126 of the gate electrode 120 may be formed to have a width W different from that of the upper electrode 122. 122 Width W 126 For example, the width W of the lower electrode 126 126 It can be relatively larger than the width W of the upper electrode 122. 122 This results in the surface area of ​​the gate electrode 120 within the substrate material 102 being larger than the surface area of ​​the gate electrode 120 outside the substrate material 102 (e.g., adjacent to and covering the upper surface 102a). In other words, W 122 :W 126 The ratio is less than 1.0. As a non-limiting example, the width W of the upper electrode 122 is... 122Width W of the lower electrode 126 126 The ratio can be between about 0.3 and about 0.9, for example, between about 0.4 and about 0.7. Therefore, at least one lateral end of the upper electrode 122 can be laterally offset (e.g., misaligned) from at least one lateral end of the lower electrode 126. In some embodiments, each lateral end of the upper electrode 122 can be laterally offset from each lateral end of the lower electrode 126, such as... FIG. 1E As shown in the figure. In other embodiments, the width W of the upper electrode 122 is... 122 It can be basically equal to the width W of the lower electrode 126 126 This arrangement ensures that the lateral centers of the upper electrode 122 and the lower electrode 126 are substantially laterally aligned with each other, and each lateral end of the upper electrode 122 is substantially laterally aligned with the lateral end of the lower electrode 126 closest to it. The lower electrode 126 may be formed having an opening 112 ( FIG. 1D The height H of the dielectric material 114 extending between the opposing surfaces within the dielectric material 114 126 As a non-limiting example, the height H of the lower electrode 126 126 It can be in the range of about 30nm to about 200nm, for example, about 30nm to about 40nm, about 40nm to about 50nm, about 50nm to about 60nm, about 60nm to about 100nm, or about 100nm to about 200nm.

[0051] The formation of the gate electrode 120 results in the formation of one or more capacitors 130 within the substrate material 102. The capacitors 130 may be characterized as so-called "embedded capacitors" because the lower electrode 126 and the post region 124 of the gate electrode 120 are formed within the substrate material 102 (e.g., below its upper surface 102a). The capacitors 130 may also be characterized as so-called "two-sided capacitors" because the first opposing surface 116 of the substrate material 102 ( FIG. 1D ) and the second opposing surface 118 ( FIG. 1DThe gate electrode 120 is connected to the post region 124 and the lower electrode 126, respectively. Furthermore, the vertical orientation of the post region 124 of the gate electrode 120 relative to the upper surface 102a of the substrate material 102, and the horizontal orientation of the lower electrode 126 of the gate electrode 120 below and isolated from the upper surface 102a of the substrate material 102, result in multidimensional regions (e.g., two-dimensional regions) of the substrate material 102 adjacent to individual regions of the gate electrode 120. This arrangement provides a large surface area between the gate electrode 120 and the substrate material 102 to form the opposing capacitor plates of the capacitor 130. Therefore, in addition to the capacitance region of the upper electrode 122 above the upper surface 102a of the substrate material 102, the capacitor 130 also includes a region 128 (e.g., an additional capacitance region) of the lower electrode 126 below and isolated from the upper surface 102a and extending within the substrate material 102, indicated by a dashed line, such as... FIG. 1E As shown in the figure. In some embodiments, region 128 may include a source / drain region (not shown) formed in the substrate material 102 in a region adjacent to capacitor 130. In other words, compared to conventional electronic devices that include a conventional capacitor (e.g., a flat capacitor) having one electrode (e.g., a single upper electrode) that is outside (e.g., overlying) another electrode in the substrate material and extends in a single direction (e.g., horizontally), the presence of post region 124 and lower electrode 126 and upper electrode 122 provides additional capacitance (e.g., storage node) regions.

[0052] FIG. 1F for FIGS. 1A-1E A perspective view of the electronic device 100. For simplicity, FIG. 1F The upper electrode 122 is not shown in the perspective view. As discussed above, the gate electrode 120 includes individual regions, each comprising an upper electrode 122, a post region 124, and a lower electrode 126, each being a substantially continuous material extending in a horizontal direction (e.g., upper electrode 122, lower electrode 126) and a vertical direction (e.g., post region 124). FIG. 1F As best shown in the perspective view, the lower electrode 126 extends in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). The upper electrode 122 also extends in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). The upper surface of the upper electrode 122 may be substantially parallel to the lower surface of the upper electrode 122, and the upper surface of the lower electrode 126 may be substantially parallel to the lower surface of the lower electrode 126. Furthermore, the upper electrode 122 and the lower electrode 126 may be substantially parallel to each other.

[0053] The gate electrode 120 is electrically and physically isolated from the substrate material 102 via the dielectric material 114. The outer surface (e.g., sidewall) of the post region 124 of the gate electrode 120 may have a wedge-shaped profile, wherein the upper portion of each post region 124 has a larger critical dimension (e.g., width) than its lower portion, such as... FIG. 1F As shown in the illustration. In other embodiments, the post regions 124 have different profiles, such as substantially orthogonal (e.g., substantially rectangular) profiles, disk-shaped profiles, or any other three-dimensional recessed shape. The size of the post regions 124 may be selected depending on the desired electrical performance characteristics of the electronic device 100 containing the capacitor 130. For example, the size (e.g., height, width) of the post regions 124 may be selected in response to the desired surface area of ​​the area of ​​the substrate material 102 between adjacent post regions 124. Each of the post regions 124 may be formed with substantially the same spacing and present substantially the same critical dimension (CD) to each other. The spacing of the post regions 124 may be in the range of about 20 nm to about 200 nm, for example, about 20 nm to about 40 nm, about 40 nm to about 60 nm, about 60 nm to about 100 nm, about 100 nm to about 150 nm, or about 150 nm to about 200 nm. FIG. 1F As most clearly shown, the guide pillar regions 124 are equidistant from each other in the first and second horizontal directions, and the spaces between laterally adjacent guide pillar regions 124 are substantially the same size. However, the CD of the guide pillar regions 124 may differ from the CD of the spaces between the guide pillar regions 124, such as... FIG. 1E The best representation is shown in the image. In other embodiments, at least some of the guide post regions 124 may not be equidistant from each other, and the space between laterally adjacent guide post regions 124 may not be substantially the same size, such that at least some of the space between laterally adjacent guide post regions 124 may be different from each other (e.g., dissimilar). In yet another embodiment, the guide post regions 124 are configured in an alternating (e.g., alternating) arrangement. The first depth D1 may correspond to the distance (e.g., in the Z direction) between the upper surface 102a of the substrate material 102 and the upper surface of the lower electrode 126. In some embodiments, the vertical dimension (e.g., height) of the guide post region 124 may correspond to the first depth D1. As a non-limiting example, the first depth D1 may be in the range of about 200 nm to about 1000 nm (1 μm), for example, in the range of about 200 nm to about 400 nm, about 400 nm to about 600 nm, about 600 nm to about 800 nm, or about 800 nm to about 1000 nm. In some embodiments, the first depth D1 may be approximately 300 nm.

[0054] Although FIGS. 1A-1FThis describes the formation of only one (e.g., a single) doped region 106, but more than one doped region 106 may be formed. For example, two or more doped regions 106 (e.g., multi-level doped regions 106) may be formed in the substrate material 102 of the electronic device 100'. FIGS. 2A-2F The diagram illustrates a method for forming multiple doped regions 106 within a substrate material 102 of an electronic device 100'. As shown, for example in... FIG. 2A In this process, two doped regions 106 can be formed within the substrate material 102. This is as described above regarding... FIG. 1A The description forms a mask material 104 (if present) and doped regions 106. Each of the doped regions 106 may be substantially parallel to each other and separated from each other by undoped regions 108 of the substrate material 102. In response to the placement of the mask material 104, the lateral centers of each of the doped regions 106 may be substantially laterally aligned with each other, such that each lateral end of the doped region 106 is substantially aligned with the lateral end of the other doped region 106 closest to it. In other embodiments, a plurality (e.g., three or more) of doped regions 106 may be formed within the substrate material 102. In embodiments comprising a plurality of regions of doped regions 106, the doped regions 106 may or may not be substantially equidistant from each other. Each of the individual doped regions 106 may be below and isolated from the upper surface 102a of the substrate material 102 and substantially (e.g., completely) surrounded by undoped regions 108. In other words, undoped regions 108 may vertically intersect between adjacent regions of the doped regions 106.

[0055] Opening 110 may be formed to penetrate the undoped region 108 of the substrate material 102 to expose each of the doped regions 106, such as FIG. 2B As shown above. FIG. 1B The described formation forms an opening 110. The opening 110 may be adjacent to (e.g., above) each of the doped regions 106 to expose a desired portion of the individual doped region 106 and may extend through the undoped region 108 of the substrate material 102. The opening 110 may extend through the upper region (e.g., the first doped region) of the doped region 106 to expose a desired portion of the underlying region (e.g., the second doped region) beneath the upper region of the doped region 106, such as... FIG. 2B As shown in the image.

[0056] like FIG. 2C As shown, the sacrificial material 105 that can be removed from the essentially doped region 106 ( FIG. 2BThis forms two or more openings 112. Therefore, the sacrificial material 105 of the horizontally extending portion of each of the doped regions 106 can be substantially removed to expose the horizontally extending surface of the sacrificial material 105 of the individual doped region 106 previously adjacent to the respective opening 112 of the undoped region 108 of the substrate material 102. This can be done as described above for... FIG. 1C The sacrificial material 105 is described as selectively removing the doped region 106.

[0057] In the removal of the doped region 106, the sacrificial material 105 ( FIG. 2B Subsequently, dielectric material 114 may be formed within openings 110 and 112 and above the exposed upper and side surfaces of the substrate material 102, such as... FIG. 2D As shown in the diagram. Dielectric material 114 may be formed as an upper surface 102a adjacent to the substrate material 102 outside the opening 110. Dielectric material 114 may also be formed as an exposed surface and sidewall adjacent to the substrate material 102 within the opening 110 and each of two or more openings 112. In other words, dielectric material 114 may substantially completely cover the exposed surfaces of the substrate material 102 within each of the openings 110 and 112 within the electronic device 100'. See reference... FIG. 1D In more detail, a first opposing surface 116 of the substrate material 102 extending in the vertical direction and a second opposing surface 118 of the substrate material 102 extending in the horizontal direction and orthogonal to the first opposing surface 116 provide a large surface area for the subsequent formation of a capacitor within the substrate material 102. However, in FIG. 2D In some embodiments, two or more portions of the first opposing surface 116 and the second opposing surface 118 may be formed in the substrate material 102. Therefore, additional bilateral (e.g., opposing) regions and additional multidimensional (e.g., two-dimensional) regions may be formed within the substrate material 102 between the opening 110 and two or more openings 112, such as... FIG. 2D As shown in the figure. Further enhancement (e.g., further enlargement) is achieved by forming additional double-sided regions and additional two-dimensional regions within the substrate material 102, resulting in a substrate material 102 having more than one side (e.g., two sides) for forming the capacitor 130. FIG. 2E The available area.

[0058] like FIG. 2E As shown, the conductive material 119 of the gate electrode 120 is formed in the opening 110. FIG. 2D ) and opening 112 ( FIG. 2D In each of the components, capacitor 130 is formed. This can be done as described above for... FIG. 1EThe gate electrode 120 is described as comprising an upper electrode 122, a post region 124, and two or more lower electrodes 126. A dielectric material 114 is formed between the substrate material 102 and the gate electrode 120 such that a substantially continuous portion of the dielectric material 114 substantially completely surrounds the post region 124 and the lower electrodes 126 of the gate electrode 120. Each of the upper electrode 122, the post region 124, and the lower electrodes 126 is electrically and physically isolated from the substrate material 102 by the dielectric material 114.

[0059] FIG. 2E The upper electrode 122 of the gate electrode 120 of the electronic device 100' can be formed to have a width W 122 Furthermore, the lower electrode 126 of the gate electrode 120 can be formed to have a width W 126 Its width is relatively greater than or, alternatively, substantially equal to, the width W of the upper electrode 122. 122 In some embodiments, the individual width W of the corresponding lower electrode 126 126 They can be substantially equal to each other, such that the lateral centers of each of the lower electrodes 126 are substantially laterally aligned with each other, and each lateral end of the lower electrode 126 is substantially laterally aligned with the lateral end of the lower electrode 126 closest to it. In other embodiments, the width W of at least one of the lower electrodes 126 (e.g., the lowermost one) is... 126 The width W can be the same as that of another (e.g., the uppermost one) in the lower electrode 126. 126 Different (e.g., relatively larger). The individual height H of the corresponding lower electrode 126 126 They may or may not be substantially equal to each other.

[0060] The formation of two or more lower electrodes 126 provides a larger surface area between the gate electrode 120 of the capacitor 130 of the electronic device 100' and the substrate material 102. For example, in addition to the capacitance region of the upper electrode 122 above the upper surface 102a of the substrate material 102, the regions 128 of the two or more lower electrodes 126 (e.g., additional capacitance regions) may expand as the number of lower electrodes 126 within the substrate material 102 increases, such as... FIG. 2E As shown in the figure. Therefore, compared to conventional electronic devices that include a conventional capacitor having an electrode that is outside another electrode in the substrate material and extends in a single direction, the presence of the post region 124 and two or more lower electrodes 126 and upper electrodes 122 provides an additional capacitance (e.g., storage node) region.

[0061] FIG. 2F for FIGS. 2A-2E A perspective view of the electronic device at 100'. For simplicity, FIG. 2FThe upper electrode 122 is not shown in the perspective view. As mentioned above... FIG. 1F The gate electrode 120 of the capacitor 130 is described as being configured and arranged. For example, the gate electrode 120 includes an upper electrode 122, a post region 124, and a lower electrode 126, each of which is a substantially continuous material extending in a horizontal direction (e.g., upper electrode 122, lower electrode 126) and a vertical direction (e.g., post region 124). FIG. 2F As best shown in the perspective view, the upper electrode 122 and each of two or more lower electrodes 126 extend in a first horizontal direction (e.g., the X direction) and a second horizontal direction (e.g., the Y direction). Due to the doped region 106 ( FIG. 2A The lower electrodes 126 are formed to be substantially parallel to each other, so that each of the lower electrodes 126 can be substantially parallel to each other and individually parallel to the upper electrode 122. FIG. 2E They are essentially parallel. The gate electrode 120 is electrically and physically isolated from the substrate material 102 by the dielectric material 114.

[0062] like FIG. 2F As shown, the first depth D1 may correspond to the distance between the upper surface 102a of the substrate material 102 and the uppermost (e.g., the first) upper surface of the lower electrode 126. The second depth D2 may correspond to the distance between the upper surface 102a of the substrate material 102 and the uppermost (e.g., the second) upper surface of the lower electrode 126. In some embodiments, the vertical dimension (e.g., height) of the guide post region 124 corresponds to FIG. 2F The second depth D2 in the embodiments. As a non-limiting example, the first depth D1 may be in the range of about 200 nm to about 800 nm, for example, in the range of about 200 nm to about 400 nm, about 400 nm to about 600 nm, or about 600 nm to about 800 nm, and the second depth D2 may be in the range of about 400 nm to about 1000 nm (1 μm), for example, in the range of about 400 nm to about 600 nm, about 600 nm to about 800 nm, or about 800 nm to about 1000 nm. In some embodiments, the first depth D1 may be about 300 nm, and the second depth D2 may be about 600 nm.

[0063] FIGS. 3A-3E The electronic device 100, including capacitor 130, has undergone the various methodological actions described above, as shown in 4A to 4C. For convenience, FIGS. 3A-3E The embodiments of 4A to 4C are described as follows: FIGS. 1A-1F An embodiment of the electronic device 100, differing in that it exhibits an additional gate electrode 120. For example, FIG. 3A for FIG. 1F A top view of the electronic device 100. However,FIGS. 3A-3E The embodiments of 4A to 4C are also applicable. FIGS. 2A-2F An embodiment of the electronic device 100'. For simplicity, FIG. 3A , 3C The upper electrode 122 is not shown in the top view of 3E.

[0064] FIG. 3B The middle shows along FIG. 3A The cross-section of the electronic device 100 of line AA, wherein the seven post regions 124 of the gate electrode 120 are adjacent to each other in the horizontal direction. Although FIG. 3B Seven post regions 124 are described, but there may be more or fewer than seven post regions 124. The gate electrode 120 is electrically and physically isolated from the substrate material 102 through a dielectric material 114. FIG. 3A and 3B As shown, the electronic device 100 includes a first region 132 (e.g., a two-dimensional region) of a substrate material 102, which includes an upper electrode 122 adjacent to a gate electrode 120 of the substrate material 102, and each of a post region 124 and a lower electrode 126 of the gate electrode 120 within the substrate material 102. The electronic device 100 may include a peripheral region 135 laterally adjacent to and at least partially (e.g., substantially completely) surrounding the region of the substrate material 102. In some embodiments, the peripheral region 135 may optionally include one or more regions (e.g., corner regions) adjacent to the first region 132 of the substrate material 102 and additional regions within said one or more regions, such as… FIG. 3A As shown in the diagram. In other words, the first region 132 of the substrate material 102 may have a substantially orthogonal (e.g., substantially rectangular) profile (except for one or more of its corners), which includes an additional region of the peripheral region 135, but other configurations are contemplated. The peripheral region 135 may allow for openings (e.g., opening 110, opening 112, etc.). FIG. 1C The electronic device 100 is structurally supported during the formation of the gate electrode 120. Therefore, the gate electrode 120 (e.g., upper electrode 122, post region 124, lower electrode 126) may exist in the first region 132 of the substrate material 102, but not in the peripheral region 135.

[0065] FIG. 3AThe first region 132 of the substrate material 102 of the electronic device 100 may represent a region similar to (e.g., substantially the same) that of a conventional electronic device. However, compared to a conventional electronic device having a single electrode (e.g., a single upper electrode) extending in a single direction (e.g., horizontally) outside (e.g., overlying) the upper surface of another electrode in the substrate material, the presence of the post region 124 of the gate electrode 120 and the lower electrode 126, along with its upper electrode 122, provides an additional capacitance (e.g., storage node) region. In other words, a conventional electronic device may not include additional electrodes extending horizontally and vertically within the substrate material. In some embodiments, the capacitance region of the electronic device 100 may be approximately twice (e.g., double) the capacitance region of a conventional electronic device, due to the configuration of the capacitors 130 within the substrate material 102 (e.g., embedded capacitors, dual-sided capacitors), which contributes to the additional capacitance region and associated additional storage capacity within a given footprint.

[0066] FIG. 3D The middle shows along FIG. 3C The cross-section of the electronic device 100 of line BB, wherein the seven post regions 124 of the gate electrode 120 are adjacent to each other in the horizontal direction, but there may be more or fewer than seven post regions 124. The gate electrode 120 may be electrically and physically isolated from the substrate material 102 by a dielectric material 114. FIG. 3C As shown, the electronic device 100 includes a second region 134a (e.g., a two-dimensional region) and a third region 134b (e.g., another two-dimensional region) of the substrate material 102. The combined second region 134a and third region 134b present a... FIG. 3A The first region 132 is the same region. One or more of the second region 134a and the third region 134b of the substrate material 102 may be at least partially surrounded by the peripheral region 135. The peripheral region 135 may optionally include one or more regions (e.g., corner regions) adjacent to the third region 134b of the substrate material 102 and additional regions within said one or more regions, such as FIG. 3C As shown in the image. FIG. 3C Implementation examples and FIG. 3A The difference in the embodiments is that the area occupied by the capacitor 130 in the third region 134b can be relatively smaller than that in the first region 132. FIG. 3A The capacitor 130 in the device occupies a smaller area than that of a conventional electronic device. In other words, FIG. 3C and 3DThe gate electrode 120 of capacitor 130 allows for a capacitance region and associated storage capacity similar to (e.g., substantially the same) that of a conventional electronic device within a reduced footprint. In some embodiments, a region of electronic device 100 (e.g., a third region 134b) may be about half the size of a conventional electronic device, but other configurations are contemplated. In other words, the configuration of capacitor 130 within substrate material 102 contributes to a comparable (e.g., similar) capacitance region and associated storage capacity within a reduced footprint, making the second region 134a available for additional circuitry, such as additional capacitor 130 of electronic device 100 or other circuitry.

[0067] FIG. 3E Describe the possible configurations of the post region 124 (e.g., size, shape). For example, the post region 124 of the gate electrode 120 ( FIG. 3B The guide pillars 110 can be formed in one or more rows and columns within the substrate material 102. As discussed above, the substrate material 102 can be patterned to accommodate the placement of the guide pillar area 124. For example, opening 110 ( FIG. 1B The portion of the base material 102 that can be configured (e.g., sizing and shaping) to accommodate the guide post area 124 may be defined, such as... FIG. 1E As shown in the diagram. Furthermore, the guide post region 124 can be separated by an intermediate region of the base material 102 located between its adjacent portions. The region of the base material 102 can be at least partially surrounded by a peripheral region 135, and the peripheral region 135 can optionally include one or more regions adjacent to the region of the base material 102 (e.g., corner regions) and additional regions within said one or more regions, such as… FIG. 3E As shown in the image.

[0068] In some embodiments, the guide post regions 124 may each be formed to include a substantially circular cross-section (e.g., annular) shape, such as FIG. 3E As shown in the lower left portion of the top view. In other embodiments, the guide post region 124 may be formed to include a substantially square cross-sectional shape, such as... FIG. 3E As shown in the upper right portion. In such embodiments, individual portions of the guide pillar region 124 may be separated and partitioned by the intermediate region of the substrate material 102, or alternatively, individual portions of the guide pillar region 124 may be substantially continuous (e.g., unpartitioned) in, for example, a lattice-like structure. In yet another embodiment, the guide pillar region 124 may be formed as including a substantially rectangular cross-sectional shape in the form of elongated rods (e.g., strips), such as... FIG. 3EAs shown in the upper right portion. The elongated rod may be substantially elliptical (e.g., with rounded ends) or substantially rectangular (e.g., with square corners), and may extend in a first horizontal direction (e.g., the X direction) or a second horizontal direction (e.g., the Y direction). Furthermore, the longitudinal axis of such an elongated rod may be oriented at an acute angle (e.g., 45 degrees) relative to the longitudinal axes of one or more rows of guide post areas 124, such as... FIG. 3E As shown in the lower right section. Although FIG. 3E The electronic device 100 is described as including a classification of the shape and size of the guide post area 124, but it is understood that the classification is shown for illustrative purposes only, and any configuration of the electronic device 100 including the pattern of the guide post area 124 may include substantially uniform size and shape.

[0069] Although the above embodiments are described and illustrated as including a lower electrode 126 of a gate electrode 120 that extends continuously in the horizontal direction, in some embodiments, the lower electrode 126 may include a separate portion. FIG. 4B and 4C The middle shows along FIG. 4A The cross-section of the electronic device 100 of line CC, wherein the two post regions 124 of the gate electrode 120 are adjacent to each other in the horizontal direction. For example... FIG. 4A and 4B As shown, the electronic device 100 includes an upper electrode 122, a post region 124, and a lower electrode 126 of a gate electrode 120. For simplicity, FIG. 4A The top view does not show the upper portion of dielectric material 114 and substrate material 102. FIG. 4A and 4B Implementation examples and FIG. 3B The difference in the embodiments is that at least some of the lower electrodes 126 of the gate electrode 120 may be included as separate portions within the substrate material 102. In other words, at least some of the lower electrodes 126 may be separated (e.g., discontinuous) portions. As used herein, the term "separated" means and includes regions or materials defined by one or more different regions or materials. FIG. 4A and 4B As shown, individual portions of the lower electrode 126 may be separated by an intermediate region 136 (e.g., a gap). Individual portions of the lower electrode 126 may include one or more post regions 124 surrounded by dielectric material 114. Although FIG. 4BNot explicitly stated, but at least some of the upper electrodes 122 of the gate electrode 120 may also include individual portions spaced apart from each other. In other words, at least some of the upper electrodes 122 may be separate (e.g., discontinuous) portions. In some embodiments, the post regions 124 of the gate electrode 120 are vertically adjacent to the top portion of the lower electrode 126 (e.g., above said top portion). In other embodiments, at least some of the post regions 124 may extend vertically through the lower electrode 126 and into the lower portion of the substrate material 102, such as... FIG. 4B As shown in the image.

[0070] like FIG. 4B As described above, the upper electrode 122 of the gate electrode 120 may have a width W in a first horizontal direction (e.g., the X direction). 122 Furthermore, the lower electrode 126 of the gate electrode 120 may have a width W in the first horizontal direction. 126 Its width is relatively larger than the width W of the upper electrode 122. 122 For reference FIG. 1E A more detailed description is needed. For example... FIG. 4A As explained in the text, the length L of the lower electrode 126 is... 126 It can also be relatively larger than the length L of the upper electrode 122 in the second horizontal direction (e.g., the Y direction). 122 Therefore, the region of the lower electrode 126 (e.g., a two-dimensional region) can be relatively larger than the region of the upper electrode 122 (e.g., a two-dimensional region), such as... FIG. 4A As shown in the diagram. Therefore, the corresponding regions of the upper electrode 122 and the lower electrode 126 can be adapted to optimize the corresponding regions, provided that at least a portion of each of the upper electrode 122 and the lower electrode 126 is in contact with the post region 124 (e.g., electrical contact, direct physical contact), such as... FIG. 4A and 4B As shown in the figure. For example, the area of ​​the upper electrode 122 can be minimized (e.g., reduced) and the area of ​​the lower electrode 126 can be maximized (e.g., increased) to provide increased capacitance of the gate electrode 120 within a given occupied area.

[0071] In some embodiments, at least some of the lower electrodes 126 may extend beyond the region designated for the capacitor 130. For example, portions of the lower electrodes 126 may extend beyond the lateral region containing the capacitor 130 and into an adjacent region containing additional circuitry of the electronic device 100, provided, for example, that access is available to form such... FIG. 1A The sacrificial material 105 of the doped region 106 described herein is formed as follows: FIG. 1E The lower electrode 126 is described in the text. Although FIG. 4AThe guide post region 124 is described as having a generally circular cross-sectional shape including a corner near the lower electrode 126. However, it is understood that the guide post region 124 may include additional size, shape, and position relative to the lower electrode 126 such that at least a portion of each of the upper electrode 122 and the lower electrode 126 contacts one or more of the guide post regions 124. In other words, the additional electrodes of the guide post region 124 may include alternative sizes and shapes. For example, the guide post region 124 may include an elongated rod (e.g., extending along the lateral edge of the lower electrode 126) near the lateral edge of the lower electrode 126. FIG. 3E ).

[0072] like FIG. 4C As shown, electronic device 100 may include a support structure 138 comprising one or more additional materials (e.g., insulating material, support structure) within the post region 124 of gate electrode 120, such that the post region 124 also functions as a mechanical support post. For example, in addition to providing a capacitor (e.g., memory node) region for the gate electrode 120, at least some of the post regions 124 may also function as mechanical support posts positioned within selected regions of substrate material 102 to provide uniform support when components are stacked. For example, the post region 124 including the support structure 138 may be positioned close to one or more of the central and peripheral regions of the substrate material 102. In other words, the post region 124 including the support structure 138 may be positioned within or near a region of the easily warped substrate material 102.

[0073] At least some of the guide post regions 124 may include a support structure 138 covering the lower electrode 126 (e.g., vertically aligned with it). In some embodiments, such as FIG. 4C As shown, the support structure 138 can be located at the opening 110 ( FIG. 1D Within the central portion of the opening 110. For example, the support structure 138 may substantially completely fill the remainder of the opening 110 (e.g., a substantially cylindrical opening) to extend substantially entirely between the sidewalls of the conductive material 119 of the post region 124. In other embodiments, the support structure 138 may be adjacent (e.g., laterally adjacent) to the side surfaces of the dielectric material 114 such that the conductive material 119 of the post region 124 is located within the central portion of the opening 110. The support structure 138 may or may not be in direct physical contact with the substrate material 102. In embodiments including the support structure 138 in the post region 124, the conductive material 119 of the post region 124 may include one or more materials that are the same as one or more materials of the upper electrode 122 and the lower electrode 126 of the gate electrode 120 to provide a substantially continuous portion of the conductive material 119 within the gate electrode 120, such as FIG. 4CAs shown in the illustration. In other embodiments, at least some of the post regions 124 may include a support structure 138 for the conductive material 119 of the post regions 124 that do not include the gate electrode 120. For example, the mechanically supported post including the support structure 138 may be positioned to at least partially surround (e.g., substantially surround) the area designated for the post regions 124 of the gate electrode 120. For convenience, FIG. 4C The embodiments are described as follows FIG. 4A and 4B An embodiment of the electronic device 100. However, FIG. 4C The embodiments can also be applied to FIGS. 1A-1F Electronic device 100 and FIGS. 2A-2F An embodiment of the electronic device 100'.

[0074] The electronic devices 100, 100' according to embodiments of the present disclosure may include, but are not limited to, 3D electronic devices, such as 3D NAND flash memory devices (e.g., multilayer 3D NAND flash memory devices). However, the electronic devices 100, 100' according to embodiments of the present disclosure may be used in other memory devices having capacitors, which may include one or more of the following: spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), particle orbital memory, and other known memory types.

[0075] Therefore, an electronic device is disclosed. The electronic device includes one or more capacitors adjacent to a substrate material. The one or more capacitors include at least one electrode extending horizontally within the substrate material and an additional electrode extending vertically within the substrate material and contacting the at least one electrode. The at least one electrode is located below and isolated from the upper surface of the substrate material.

[0076] Therefore, an electronic device is disclosed, wherein the electronic device includes a capacitor comprising a gate electrode. Each of the gate electrodes includes an upper electrode adjacent to an upper surface of a substrate material, at least one lower electrode extending horizontally within the substrate material, and a post region extending vertically within the substrate material between the upper electrode and the at least one lower electrode.

[0077] Therefore, a method for forming an electronic device is disclosed, the method comprising forming a sacrificial material extending horizontally within a substrate material. The sacrificial material is located below and isolated from an upper surface of the substrate material. The method includes: forming an opening extending into the sacrificial material; removing the sacrificial material within the opening; and forming a conductive material adjacent to the upper surface of the substrate material and within the opening. The conductive material is configured as a gate electrode of a capacitor.

[0078] The gate electrode 120 of electronic devices 100, 100', comprising an upper electrode 122, a post region 124, and a lower electrode 126, helps to increase the capacitance of capacitor 130 within a given occupied area (e.g., the area occupied by capacitor structure 130). This can provide increased capacitance within a given region (e.g., a two-dimensional region) or allocate a reduced region to capacitor 130. For example, compared to a conventional electronic device having a single electrode outside and overlying the upper surface of a substrate material, the presence of the post region 124 and lower electrode 126 within the substrate material 102, and the upper electrode 122 overlying the substrate material 102, provides an additional capacitance (e.g., a storage node) region. Alternatively, the configuration of the gate electrode 120 of capacitor 130 can allow a capacitance region and associated storage capacity similar to (e.g., substantially the same) as those of a conventional electronic device within a reduced occupied area. The bilateral (e.g., opposing) regions of each of the first opposing surfaces 116 and the second opposing surfaces 118 of the substrate material 102, and the vertical orientation of the post region 124 of the gate electrode 120 and the horizontal orientation of the lower electrode 126 below and isolated from the upper surface 102a of the substrate material 102, alter the configuration of the capacitor 130 of the electronic devices 100, 100'. For example, one or more of the post regions 124 of the gate electrode 120 and the lower electrode 126 provide a larger surface area between the gate electrode 120 of the capacitor 130 and the substrate material 102 for increased capacitance within a given area and / or for reduced footprint to optimize packing density. Therefore, the capacitor 130 can have increased capacitance efficiency per unit area compared to conventional capacitors (e.g., flat capacitors). Thus, the capacitance of the capacitor 130 can be increased without requiring an increased footprint.

[0079] Compared to the embodiments disclosed herein, the gate electrode 120' of a conventional capacitor 130' may not extend in the vertical direction (e.g., the Z direction) and may not extend horizontally within the substrate material 102' in a conventional electronic device. FIG. 5B In order to be with FIG. 3A and 3B Along the same manufacturing stage as conventional electronic devices 10 FIG. 5A A cross-sectional view of line DD. (See diagram below.) FIG. 5A and 5B As shown, a capacitor 130' (e.g., a flat capacitor structure) may be contained within a single region of a gate electrode 120' (e.g., a single upper electrode) that is external to and overlying the substrate material 102' and extends in a horizontal direction. For example, the substrate material 102' may contain a p-doped region 140' and an n-well region 142' within the substrate material 102', such as... FIG. 5BAs shown in the diagram. Dielectric material 114' may be located in a portion adjacent to (e.g., above) each of the p-doped region 140' and the n-well region 142' (e.g., above the upper surface 102a' of the substrate material 102'), and gate electrode 120' may be located above dielectric material 114'. The substrate material 102' may contain source / drain regions (not shown).

[0080] Therefore, the gate electrode 120' of a conventional electronic device 10 comprises a single region (e.g., an electrode) outside and overlying the substrate material 102'. In such devices, a capacitor 130' comprising a single region of the gate electrode 120' extending only in the horizontal direction can present a reduced capacitance (e.g., storage node) region, which can create a requirement for a larger area (e.g., increased footprint) of the capacitor 130' within the conventional electronic device 10. Furthermore, compared to providing more than one (e.g., two or more) opposing surfaces in more than one dimension (e.g., in two dimensions) in electronic devices 100, 100', a single region of the gate electrode 120' provides opposing surfaces of the substrate material 102' with only one (e.g., a single) dimension. For example, the capacitor 130 of the electronic devices 100, 100' according to embodiments of the present disclosure comprises an orthogonal arrangement of bilateral regions of each of the first opposing surface 116 and the second opposing surface 118 of the substrate material 102, such as... FIG. 1D and 2D As shown in the diagram. Furthermore, the capacitor 130 includes the vertical orientation of the post region 124 of the gate electrode 120 below and isolated from the upper surface 102a of the substrate material 102, and the horizontal orientation of the lower electrode 126, as illustrated in the diagram. FIG. 1E and 2E As shown in the figure. This arrangement provides a large surface area between the gate electrode 120 of the capacitor 130 of the electronic devices 100, 100' and the substrate material 102.

[0081] Due to the presence of the post region 124 and lower electrode 126 within the substrate material 102, and the upper electrode 122 covering the substrate material 102, the electronic devices and methods according to embodiments of the present disclosure increase capacitance within a given region and decrease the region allocated to capacitor 130. The sacrificial material 105 forming the doped region 106 within the undoped region 108 of the substrate material 102 according to embodiments of the present disclosure can reduce various processing complexities (e.g., the complexity associated with patterning the substrate material 102) associated with the additional regions (e.g., post region 124, lower electrode 126) forming the gate electrode 120 within the substrate material 102. The increased capacitance (e.g., memory node) region within the substrate material 102 according to embodiments of the present disclosure can help increase the capacitance per area without increasing the amount of occupied area occupied by capacitor 130. Therefore, as FIGS. 1A-1F and FIGS. 2A-2F The methods disclosed herein can facilitate the formation of one or more of the post regions 124 of the gate electrode 120 in the vertical direction and the lower electrodes 126 thereunder in the horizontal direction within the substrate material 102. Such methods also facilitate the removal of the sacrificial material 105 of the doped region 106. FIG. 1A This helps to form the gate electrode 120, thereby improving the capacitance properties within the electronic devices 100, 100'.

[0082] FIG. 6 This illustration shows a partial cross-sectional perspective view of an electronic device 200 (e.g., a microelectronic device, a memory device, such as a 3D NAND flash memory device) that includes an electronic structure 201 (e.g., a microelectronic device structure). The electronic device 200 may be compared with previously referenced... FIGS. 1A-4C The described electronic devices 100 and 100' are essentially similar. For example... FIG. 6 As shown, the electronic structure 201 of the electronic device 200 may include a stepped structure 220 defining contact areas for connecting access lines 206 to conductive structures 205. The electronic structure 201 may include vertical strings 207 of memory cells 203 coupled in series with each other. The vertical strings 207 may (e.g., in the Z direction) extend vertically and orthogonally to the conductive lines and conductive structures 205, such as data lines 202, source layers 204, access lines 206, first select gates 208 (e.g., upper select gate, drain select gate (SGD)), select lines 209, and second select gates 210 (e.g., lower select gate, source select gate (SGS)). The select gates 208 may be horizontally divided (e.g., in the Y direction) into a plurality of blocks 232 horizontally separated (e.g., in the Y direction) by slots 230.

[0083] Vertical conductive contacts 211 can electrically couple components to each other, as shown. For example, select line 209 can be electrically coupled to a first select gate 208, and access line 206 can be electrically coupled to conductive structure 205. Electronic device 200 may also include a control unit 212 positioned below the memory array, which may include at least one of the following: string driver circuitry, through gates, circuitry for selecting gates, circuitry for selecting conductive lines (e.g., data line 202, access line 206), circuitry for amplifying signals, and circuitry for temporarily storing data (e.g., capacitor 130 including electronic devices 100, 100'). FIG. 1E and 2E The control unit 212 may be electrically coupled to, for example, data line 202, source layer 204, access line 206, first select gate 208, and second select gate 210. In some embodiments, the control unit 212 includes CMOS (Complementary Metal-Oxide-Semiconductor) circuitry. In such embodiments, the control unit 212 may be characterized by having an "array-under CMOS" ("CuA") configuration.

[0084] The first selection gate 208 may extend horizontally in a first direction (e.g., the X direction) and may be coupled to a corresponding first group of vertical strings 207 of the memory cell 203 at a first end (e.g., the upper end). The second selection gate 210 may be formed in a substantially flat configuration and may be coupled to the vertical strings 207 at a second opposite end (e.g., the lower end) of the vertical strings 207 of the memory cell 203.

[0085] Data lines 202 (e.g., digital lines, bit lines) may extend horizontally in a second direction (e.g., in the Y direction) at an angle (e.g., perpendicular) to a first direction in which the first select gate 208 extends. Individual data lines 202 may be coupled at a first end (e.g., upper end) of a vertical string 207 of an individual group to an individual group of vertical strings 207 extending in the second direction (e.g., the Y direction). Additional individual groups of vertical strings 207 extending in the first direction (e.g., the X direction) and coupled to individual first select gates 208 may share their specific vertical strings 207 with the individual groups of vertical strings 207 coupled to individual data lines 202. Thus, individual vertical strings 207 of memory cells 203 may be selected at the intersection of individual first select gates 208 and individual data lines 202. Therefore, the first select gate 208 may be used to select memory cells 203 of vertical strings 207 of memory cells 203.

[0086] Conductive structures 205 (e.g., word lines) may extend in a corresponding horizontal plane. The conductive structures 205 may be vertically stacked such that each conductive structure 205 is coupled to at least some of the vertical strings 207 of the memory cells 203, and the vertical strings 207 of the memory cells 203 extend vertically through the stacked structure containing the conductive structures 205. The conductive structures 205 may be coupled to or may form the control gate of the memory cells 203.

[0087] The first select gate 208 and the second select gate 210 are operable to select a vertical string 207 of memory cells 203 inserted between the data line 202 and the source layer 204. Thus, an individual memory cell 203 can be selected and electrically coupled to the data line 202 by operating (e.g., by selecting) the appropriate first select gate 208, second select gate 210, and conductive structure 205 coupled to a particular memory cell 203.

[0088] The stepped structure 220 can be configured to provide an electrical connection between the access line 206 and the conductive structure 205 via vertical conductive contacts 211. In other words, an individual conductive structure 205 can be selected via an access line 206 electrically connected to a corresponding vertical conductive contact 211, which is electrically connected to the conductive structure 205. The data line 202 can be electrically coupled to the vertical string 207 via conductive contact structure 234.

[0089] Includes, for example FIGS. 1A-4C and FIG. 6 One or more of the electronic devices 100, 100', 200 shown may be used in embodiments of the electronic devices disclosed herein. FIG. 7A This is a block diagram of an illustrative electronic device 300 (e.g., a 3D NAND flash memory device) according to embodiments of the present disclosure. The electronic device 300 may include at least one memory cell array 302, such as multiple memory arrays. The electronic device 300 may further include at least one peripheral circuit 304 that inputs data from outside the electronic device 300, thus providing access to at least one memory cell array 302. The electronic device 300 may further include a charge pump circuit 306 for generating an input voltage. The peripheral circuit 304 and the charge pump circuit 306 may include one or more capacitors, such as... FIGS. 1A-4C The embodiment of capacitor 130 in electronic devices 100, 100' shown herein. Peripheral circuitry 304 and charge pump circuitry 306 may be electrically connected to at least one memory cell array 302 by means of capacitor 130. For example, electronic device 300 may include memory cell array 302, which may include complementary metal-oxide-semiconductor (CMOS) regions, such as under-array CMOS (CuA) regions 308 beneath memory cell array 302 (e.g., control unit 212). FIG. 6The memory cell array 302 may include connections to access lines (e.g., access line 206). FIG. 6 )) and digital lines (e.g., bit lines, data lines 202) FIG. 6 )) of memory cells (e.g., memory cell 203) FIG. 6 Furthermore, CuA region 308 may lie beneath memory cell array 302 and include its supporting circuitry, as shown in the reference. FIG. 7B A more detailed description follows. Support circuitry can support one or more additional arrays of memory cells existing in a stacked configuration. For example, an electronic device 300 including a memory cell array 302 with memory cells can be two-dimensional (2D) to present a single layer (e.g., a single level, a single hierarchy) of memory cells, or it can be three-dimensional (3D) to present multiple layers (e.g., multiple levels, multiple tiers) of memory cells. In a stacked configuration, CuA regions 308 can facilitate access to one or more memory cells in each array. For example, CuA regions 308 can facilitate data transfer between memory cells coupled to channels of memory cell array 302, memory cells coupled to channels of additional memory cell array 302 (which are coupled to memory cell array 302), and a controller.

[0090] FIG. 7B for FIG. 7A This is a portion of a schematic diagram of an electronic device 300. In some embodiments, the electronic device 300 may include a control logic region 310 of a CuA region 308 vertically adjacent to the memory cell array 302 of the electronic device 300. The control logic region 310 may be included, for example, within a control unit 212 of the electronic device 200, as referenced above. FIG. 6 As described. Control logic region 310 may include additional logic means and circuitry for controlling various operations of memory cell array 302. The means and circuitry of control logic region 310 may be selected relative to the means and circuitry of memory cell array 302. The means and circuitry of control logic region 310 may differ from the means and circuitry of memory cell array 302.

[0091] As a non-limiting example, the control logic region 310 may include one or more sense amplifiers and page buffers 312, data paths 314, I / O devices 316, and controller logic 318. In some embodiments, the control logic region 310 includes one or more line decoders. In some embodiments, the horizontal area occupied by the devices of the control logic region 310 (e.g., sense amplifiers and page buffers 312, data paths 314, I / O devices 316, and controller logic 318) may be substantially the same as the horizontal area occupied by the memory cell array 302. In other words, the devices of the control logic region 310 may be located in a region corresponding to the area occupied by the memory cell array 302. Therefore, the dies of the control logic region 310 may be stacked vertically adjacent to the memory cell array 302 and may not occupy additional area relative to the memory cell array 302.

[0092] The sense amplifier of the sense amplifier and page buffer 312 can be configured to receive data from a digital line selected by the column decoder (e.g., data line 202) during a read operation. FIG. 6 The sense amplifier receives digital line input and generates digital data values. Therefore, the sense amplifier can be configured and operated to sense (read) data from a memory array (e.g., memory cell array 302). FIG. 7A )) of memory cells (e.g., memory cell 203) FIG. 6 The data is stored in the column decoder. In some embodiments, the column decoder is located within the control logic area 310.

[0093] The page buffer of the sense amplifier and page buffer 312 can be configured to access the memory cell array 302 during various read and write operations. FIG. 7A ) memory cell string (e.g., vertical string 207 ( FIG. 6 )) memory cell 203 ( FIG. 6 The page buffer 312 receives and stores data (e.g., temporarily stores data). It is operatively communicative with data path 314 and I / O device 316, and facilitates increased data transfer between I / O device 316 and the string of memory cells in the memory array. In some embodiments, each page buffer 312 individually comprises a size equal to the size (capacity) of a memory page in which data read from memory cells is temporarily stored before serial output (e.g., to one or more I / O devices 316). Furthermore, the page buffer 312 can be configured to store information of memory pages to be written to memory cell 203. Therefore, the page buffer 312 may contain a relatively large number of volatile storage elements, typically bistable elements or latches, corresponding to the number of memory cells in a memory page.

[0094] Data path 314 can be configured and operated to provide data to electronic device 300.FIG. 7A One or more devices (e.g., logic devices). For example, data path 314 can be configured and operated to move data values ​​from one or more devices (e.g., logic devices) to memory cells 203 of a cell-pillar structure. FIG. 6 Data path 314 may be associated with the memory array and, for example, with I / O devices 316 (e.g., data input / output pads), page buffers 312, controller logic 318, and other devices. For example, data path 314 may be located between a memory bank and a corresponding data input / output terminal (DQ pad).

[0095] I / O device 316 is configurable and operable to program data into memory cell array 302 by applying an appropriate voltage to a digital line selected by a column decoder. FIG. 7A ) memory elements (e.g., memory cell 203) FIG. 6 In some embodiments, I / O device 316 can be used for bidirectional data communication with the host via a data bus and can be coupled to write circuitry configured to write data to a memory array.

[0096] Controller logic 318 may be configured to control one or more operations of memory cell array 302, including, for example, data sensing operations (e.g., read operations) and data programming operations (e.g., write operations). In some embodiments, controller logic 318 is configured to sense changes in external signals and to issue internal signals based on, for example, whether the external signal is a read operation, a write operation, or another signal. For example, controller logic 318 may receive inputs including a chip select signal, a read / write signal (e.g., a write enable signal, an address latch signal), or another signal. In response to receiving a read / write signal, controller logic 318 may send signals (e.g., a read enable signal, a write enable signal) to, for example, a row decoder and / or a column decoder. As described above, the row decoder may be configured to send address signals to word line drivers located within memory cell array 302. The row decoder may be configured and operable to select a specific word line (e.g., access line 206) of the memory array based on the row address signal thus received. FIG. 6 The row decoder can output word line segment commands to the word line driver. The column decoder can be configured and operated to select specific digital lines of the memory array based on the column address selection signal received therefrom.

[0097] The sense amplifier and page buffer 312 may include capacitors (e.g., capacitor 130). FIG. 1E and 2EIn some such embodiments, the sense amplifier and page buffer 312 circuitry may utilize a capacitor 130 comprising a configuration including gate electrode 120 (e.g., upper electrode 122, post region 124, and lower electrode 126) to help increase the size of a given area. FIG. 3A The capacitor within the control logic area 310 may be reduced or its allocation to capacitor 130. FIG. 3C The region is characterized by a higher density and / or reduced area of ​​capacitors 130 within the sense amplifier and page buffer 312. This type of configuration can contribute to the memory array (e.g., memory cell array 302) within a given region. FIG. 7A The structure has a high density. In some embodiments, one or more of the capacitors 130 may be electrically connected to a power supply electrode (e.g., V). CC ) and ground electrode (e.g., V GND Between. In some such embodiments, capacitor 130 may be configured to substantially reduce or substantially eliminate (e.g., filter out) electrical signals (e.g., noise) from the power supply (not shown) in a so-called “noise-free” circuit utilizing capacitor 130. As discussed further in detail above, the use of multiple regions of the gate electrode 120 overlying and within the substrate material 102 provides optimal use of the area, thereby reducing the area allocated to capacitor 130 located between the power supply electrode and the ground electrode and improving the reliability of electronic device 300.

[0098] like FIG. 8 The disclosure also discloses an electronic system 400, which includes electronic devices 100, 100', 200, and 300 according to embodiments of the present disclosure. FIG. 8 This is a simplified block diagram of an electronic system 400 implemented according to one or more embodiments described herein. The electronic system 400 may include, for example, a computer or computer hardware component, a server or other network-connected hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 400 includes at least one memory device 420, which includes electronic devices 100, 100', 200, 300 as previously described. Electronic system 400 may further include at least one processor device 410, such as a microprocessor, to control system functions and request processing within electronic system 400. Processor device 410 and other sub-components of electronic system 400 may include memory cells. Processor device 410 may optionally include one or more memory cell arrays 302 as previously described. FIG. 7A ).

[0099] Various other devices may be coupled to the processor device 410 depending on the function performed by the electronic system 400. For example, an input device 430 may be coupled to the processor device 410 for inputting information into the electronic system 400 by a user, such as a mouse or other pointing device, buttons, switches, keyboards, touchpads, light pens, digitizers and styluses, touchscreens, voice recognition systems, microphones, control panels, or combinations thereof. An output device 440 for outputting information (e.g., visual or audio output) to a user may also be coupled to the processor device 410. The output device 440 may include an LCD display, a SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projector, an audio display, or combinations thereof. The output device 440 may also include a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 430 and the output device 440 may include a single touchscreen device that can be used to input information into the electronic system 400 and output visual information to a user. One or more input devices 430 and output devices 440 may be electrically connected to at least one of the memory device 420 and the processor device 410. At least one memory device 420 and processor device 410 may also be used in a system-on-a-chip (SoC).

[0100] Therefore, a system is disclosed. The system includes a processor operatively coupled to input and output devices, and electronic devices operatively coupled to the processor. The electronic devices include at least one array of memory cells and embedded capacitors adjacent to a substrate material. Each of the embedded capacitors includes a gate electrode having a first region extending in a vertical direction and at least one second region extending in a horizontal direction substantially transverse to the vertical direction. The first region and the at least one second region are substantially continuous.

[0101] Compared to conventional structures, conventional devices, and conventional systems, the electronic devices and systems of this disclosure advantageously facilitate one or more of the following: improved simplicity of components, greater package density, and enhanced miniaturization. Compared to conventional devices (e.g., conventional equipment, conventional microelectronic devices, conventional memory devices) and conventional systems (e.g., conventional electronic systems), the methods of this disclosure facilitate the formation of devices (e.g., equipment, microelectronic devices, memory devices) and systems (e.g., electronic systems) having one or more of the following: improved performance, reliability, and durability; lower cost; increased yield; increased component miniaturization; improved pattern quality; and greater package density.

[0102] The embodiments of this disclosure may be further characterized in the manner described below, but not limited to the manner described below.

[0103] Example 1: An electronic device comprising: one or more capacitors adjacent to a substrate material, the one or more capacitors comprising: at least one electrode extending horizontally within the substrate material, the at least one electrode being located below and isolated from an upper surface of the substrate material; and an additional electrode extending vertically within the substrate material and contacting the at least one electrode.

[0104] Example 2: According to the electronic device of Example 1, one or more capacitors include an upper electrode covering an upper surface of a substrate material, the upper electrode causing an additional electrode to contact a main surface of the upper electrode that is substantially transverse to the longitudinal axis of the additional electrode.

[0105] Example 3: The electronic device according to Example 2, wherein the main surface of the upper electrode is substantially parallel to the main surface of at least one electrode.

[0106] Example 4: An electronic device according to any one of Examples 1 to 3, wherein one or more capacitors are configured as embedded double-sided capacitors.

[0107] Example 5: An electronic device according to any one of Examples 1 to 4, wherein one or more capacitors include a first opposing surface of a substrate material horizontally adjacent to an additional electrode and a second opposing surface of a substrate material vertically adjacent to at least one electrode, the second opposing surface of the substrate material being substantially orthogonal to the first opposing surface of the substrate material.

[0108] Example 6: An electronic device according to any one of Examples 1 to 5, wherein at least one electrode includes a first lower electrode and a second lower electrode, and a portion of the substrate material is located between the first lower electrode and the second lower electrode.

[0109] Example 7: The electronic device according to Example 6, wherein the distance between the upper surface of the substrate material and the first lower electrode is about 300 nm, and the distance between the upper surface of the substrate material and the second lower electrode is about 600 nm.

[0110] Example 8: An electronic device comprising: a capacitor including gate electrodes, each of the gate electrodes including: an upper electrode adjacent to an upper surface of a substrate material; at least one lower electrode extending horizontally within the substrate material; and a post region extending vertically within the substrate material between the upper electrode and the at least one lower electrode.

[0111] Example 9: The electronic device according to Example 8 further includes a dielectric material between a substrate material and a gate electrode, wherein a substantially continuous portion of the dielectric material substantially completely surrounds the post region of the gate electrode and at least one lower electrode, wherein each of the upper electrode, the post region, and at least one lower electrode is electrically and physically isolated from the substrate material by the dielectric material.

[0112] Example 10: The electronic device according to Example 8 or Example 9, wherein the width of at least one lower electrode is relatively greater than the width of the upper electrode in the horizontal direction.

[0113] Example 11: An electronic device according to any one of Examples 8 to 10, wherein a particular gate electrode includes a substantially continuous portion of conductive material for an upper electrode, a post region, and at least one lower electrode.

[0114] Example 12: The electronic device according to Example 11, wherein the substrate material includes silicon and the conductive material of the gate electrode includes tungsten.

[0115] Example 13: An electronic device according to Example 11 or Example 12, wherein at least some of the post regions of the gate electrode include a support structure, the support structure comprising an insulating material adjacent to the conductive material of the gate electrode.

[0116] Example 14: A system comprising: a processor operatively coupled to an input device and an output device; and an electronic device operatively coupled to the processor, the electronic device comprising: at least one memory cell array; and embedded capacitors adjacent to a substrate material, each of the embedded capacitors including a gate electrode having a first region extending in a vertical direction and at least one second region extending in a horizontal direction substantially transverse to the vertical direction, the first region and the at least one second region being substantially continuous.

[0117] Example 15: The system according to Example 14, wherein the first region of the gate electrode includes a substantially circular cross-sectional shape, a substantially square cross-sectional shape, or an elongated substantially rectangular cross-sectional shape.

[0118] Example 16: The system according to Example 14 or Example 15, wherein the upper region of at least one second region of the gate electrode is adjacent to the upper surface of the substrate material, and one or more lower regions of at least one second region are located below and isolated from the upper surface of the substrate material, and the one or more lower regions are separated from each other by the substrate material.

[0119] Example 17: The system according to Example 16, wherein the surface area of ​​one or more lower regions is relatively larger than the surface area of ​​the upper region of at least one second region of the gate electrode.

[0120] Example 18: The system according to any of Examples 14 to 17 further includes an under-array CMOS (CuA) region below at least one memory cell array, wherein the horizontal area of ​​the at least one memory cell array is substantially the same as the horizontal area of ​​the CuA region.

[0121] Example 19: The system according to Example 18, wherein the CuA region includes a page buffer region, and at least some of the embedded capacitors are located within the page buffer region.

[0122] Example 20: A method of forming an electronic device, comprising: forming a sacrificial material extending horizontally within a substrate material, the sacrificial material being below and isolated from an upper surface of the substrate material; forming an opening extending into the sacrificial material; removing the sacrificial material within the opening; and forming a conductive material adjacent to the upper surface of the substrate material and within the opening, the conductive material being configured as a gate electrode of a capacitor.

[0123] Example 21: The method according to Example 20, wherein forming the sacrificial material includes forming a doped region within a substrate material, the doped region being located below and isolated from the upper surface of the substrate material.

[0124] Example 22: The method according to Example 20 or Example 21, wherein forming an opening extending to the sacrificial material includes forming an opening extending vertically between the upper surface of the substrate material and the sacrificial material, and wherein removing the sacrificial material includes forming an additional opening extending horizontally within the substrate material.

[0125] Example 23: The method according to Example 22 further includes forming a substantially continuous portion of dielectric material along the exposed surface of the substrate material within the opening and additional opening and adjacent to the upper surface of the substrate material.

[0126] Example 24: The method according to Example 23, wherein forming a conductive material includes forming a single conductive material adjacent to the dielectric material within the opening and additional opening and adjacent to the upper surface of the substrate material in a single deposition operation.

[0127] Example 25: The method according to any of Examples 22 to 24 further includes removing a portion of the conductive material adjacent to the upper surface of the substrate material to form an upper electrode, the upper electrode having a width relatively smaller than the width of the conductive material in each of the additional openings.

[0128] While certain illustrative embodiments have been described with reference to the figures, those skilled in the art will recognize and understand that the embodiments encompassed by this disclosure are not limited to those explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments encompassed by this disclosure (such as those claimed herein, including legal equivalents). Furthermore, features from one disclosed embodiment may be combined with features from another disclosed embodiment while still being included within the scope of this disclosure.

Claims

1. An electronic device comprising: One or more capacitors are located adjacent to a substrate material, said one or more capacitors comprising: At least one electrode extending horizontally within the substrate material, the at least one electrode being located below and isolated from the upper surface of the substrate material; and Additional electrodes, which extend vertically within the substrate material and directly physically contact the at least one electrode; and An upper electrode is overlaid on the upper surface of the substrate material, the upper electrode having its main surface in direct physical contact with the additional electrode, the main surface being substantially transverse to the longitudinal axis of the additional electrode, and a portion of the substrate material being vertically inserted between the at least one electrode and the upper electrode.

2. The electronic device of claim 1, wherein the main surface of the upper electrode is substantially parallel to the main surface of the at least one electrode.

3. The electronic device according to any one of claims 1 to 2, wherein the one or more capacitors are configured as embedded double-sided capacitors.

4. The electronic device according to any one of claims 1 to 2, wherein the one or more capacitors include a first opposing surface of the substrate material horizontally adjacent to the additional electrode and a second opposing surface of the substrate material vertically adjacent to the at least one electrode, the second opposing surface of the substrate material being substantially orthogonal to the first opposing surface of the substrate material.

5. The electronic device of claim 1, further comprising a dielectric material adjacent to the at least one electrode, the additional electrode and the upper electrode, a portion of the dielectric material extending directly between the upper electrode and the substrate material.

6. The electronic device of claim 5, wherein the at least one electrode is located away from the portion of the dielectric material that extends directly between the upper electrode and the substrate material.

7. The electronic device of claim 5, wherein a plurality of portions of the dielectric material are vertically inserted between the upper electrode and the at least one electrode.

8. The electronic device of claim 1, wherein the at least one electrode comprises a single electrode.

9. The electronic device of claim 1, wherein the at least one electrode comprises two or more electrodes, the heights of which are substantially equal to each other.

10. The electronic device of claim 1, wherein the outermost horizontal boundary of the at least one electrode extends beyond the outermost horizontal boundary of the region containing the additional electrode.

11. The electronic device of claim 10, wherein the outermost horizontal boundary of the upper electrode extends beyond the outermost horizontal boundary of the region containing the additional electrode.

12. The electronic device of claim 1, wherein the surface area of ​​a single electrode of the at least one electrode is relatively larger than the surface area of ​​the upper electrode.

13. The electronic device of claim 1, further comprising a substantially continuous portion of conductive material extending within the at least one electrode, the additional electrode, and the upper electrode.

14. The electronic device of claim 1, wherein the substrate material substantially surrounds each electrode of the at least one electrode on at least two consecutive sides.

15. The electronic device of claim 1, wherein a portion of the additional electrode extends beyond the lower surface of the lowermost electrode of the at least one electrode.

16. The electronic device of claim 1, wherein at least some of the additional electrodes include an insulating support structure within the central portion of the additional electrode.

17. The electronic device of claim 1, wherein a portion of the substrate material is laterally interposed between adjacent additional electrodes.

18. An electronic device comprising: One or more capacitors are located adjacent to a substrate material, said one or more capacitors comprising: At least one electrode extends horizontally within the substrate material, the at least one electrode being located below and isolated from the upper surface of the substrate material. The at least one electrode includes a first lower electrode and a second lower electrode, and a portion of the substrate material is located between the first lower electrode and the second lower electrode; and An additional electrode that extends vertically within the substrate material and contacts the at least one electrode.

19. The electronic device of claim 18, wherein the distance between the upper surface of the substrate material and the first lower electrode is about 300 nm, and the distance between the upper surface of the substrate material and the second lower electrode is about 600 nm.

20. An electronic device comprising: A capacitor comprising gate electrodes, each of which includes: The upper electrode is adjacent to the upper surface of the substrate material; At least one lower electrode, which extends horizontally within the substrate material; and A guide post region that extends vertically within the substrate material between the upper electrode and the at least one lower electrode.

21. The electronic device of claim 20, further comprising a dielectric material between the substrate material and the gate electrode, wherein a substantially continuous portion of the dielectric material substantially completely surrounds the post region of the gate electrode and the at least one lower electrode, wherein each of the upper electrode, the post region, and the at least one lower electrode is electrically and physically isolated from the substrate material by the dielectric material.

22. The electronic device according to claim 20 or claim 21, wherein the width of the at least one lower electrode is relatively greater than the width of the upper electrode in the horizontal direction.

23. The electronic device of claim 20 or claim 21, wherein a particular gate electrode comprises a substantially continuous portion of the conductive material of the upper electrode, the post region, and the at least one lower electrode.

24. The electronic device of claim 23, wherein the substrate material comprises silicon, and the conductive material of the gate electrode comprises tungsten.

25. The electronic device of claim 23, wherein at least some of the post regions of the gate electrode include a support structure, the support structure comprising an insulating material adjacent to the conductive material of the gate electrode.

26. A system comprising: A processor that is operatively coupled to input and output devices; as well as An electronic device operatively coupled to the processor, the electronic device comprising: At least one memory cell array; as well as An embedded capacitor, adjacent to a substrate material, each of the embedded capacitors including a gate electrode having a first region extending in a vertical direction and at least one second region extending in a horizontal direction substantially transverse to the vertical direction, the first region and the at least one second region being substantially continuous.

27. The system of claim 26, wherein the first region of the gate electrode comprises a substantially circular cross-sectional shape, a substantially square cross-sectional shape, or an elongated substantially rectangular cross-sectional shape.

28. The system of claim 26 or claim 27, wherein the upper region of the at least one second region of the gate electrode is adjacent to the upper surface of the substrate material, and one or more lower regions of the at least one second region are located below and isolated from the upper surface of the substrate material, the one or more lower regions being separated from each other by the substrate material.

29. The system of claim 28, wherein the surface area of ​​the one or more lower regions is relatively larger than the surface area of ​​the upper region of the at least one second region of the gate electrode.

30. The system of claim 26 or claim 27, further comprising an under-array CMOS CuA region beneath the at least one memory cell array, wherein the horizontal area of ​​the at least one memory cell array is substantially the same as the horizontal area of ​​the CuA region.

31. The system of claim 30, wherein the CuA region includes a page buffer region, and at least some of the embedded capacitors are located within the page buffer region.

32. A method of forming an electronic device, comprising: A sacrificial material is formed within a substrate material and extends horizontally, the sacrificial material being located below and isolated from the upper surface of the substrate material; Forming an opening that extends into the sacrificial material; Remove the sacrificial material from the opening; as well as A conductive material is formed adjacent to the upper surface of the substrate material and within the opening, the conductive material being configured as the gate electrode of one or more capacitors, the one or more capacitors comprising: At least one electrode extends horizontally within the substrate material, the at least one electrode being located below and isolated from the upper surface of the substrate material; Additional electrodes, which extend vertically within the substrate material and directly physically contact the at least one electrode; and An upper electrode is overlaid on the upper surface of the substrate material, the upper electrode having its main surface in direct physical contact with the additional electrode, the main surface being substantially transverse to the longitudinal axis of the additional electrode, and a portion of the substrate material being vertically inserted between the at least one electrode and the upper electrode.

33. The method of claim 32, wherein forming the sacrificial material comprises forming a doped region within the substrate material, the doped region being located below and isolated from the upper surface of the substrate material.

34. The method of claim 32 or claim 33, wherein forming the opening extending to the sacrificial material comprises forming the opening extending vertically between the upper surface of the base material and the sacrificial material, and wherein removing the sacrificial material comprises forming an additional opening extending horizontally within the base material.

35. The method of claim 34, further comprising forming a substantially continuous portion of dielectric material along the exposed surface of the substrate material within the opening and the additional opening and adjacent to the upper surface of the substrate material.

36. The method of claim 35, wherein forming the conductive material comprises forming a single conductive material in a single deposition operation adjacent to the dielectric material within the opening and the additional opening and adjacent to the upper surface of the substrate material.

37. The method of claim 34, further comprising removing a portion of the conductive material adjacent to the upper surface of the substrate material to form the upper electrode, the upper electrode having a width relatively smaller than the width of the conductive material within each of the additional openings.

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