Method and apparatus for measuring slew rate in a current integrating phase interpolator with programmable bias current

Abstract

The present disclosure relates to techniques for measuring slew rate in a current integrating phase interpolator. An apparatus is described that includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal containing a periodic sawtooth waveform therefrom; a digital-to-analog (D / A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for calculating a difference between a first state of the DCD of the clock signal corresponding to the inverter circuit being set to a high voltage input common mode voltage and a second state of the DCD of the clock signal corresponding to the inverter circuit being set to a low voltage input common mode voltage.

Description

[0001] Related Applications

[0002] This application is a continuation-in-part and claims priority to U.S. Non-Provisional Application No. 17 / 116,875, filed December 9, 2020, entitled “TECHNIQUES FOR MEASURING SLEW RATE IN CURRENT INTEGRATING PHASE INTERPOLATOR.” This U.S. Non-Provisional Application is incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of current integrating phase interpolators, and more specifically, to techniques for measuring slew rate in a current integrating phase interpolator (CIPI). SUMMARY

[0004] According to one aspect of the disclosure, there is provided an apparatus comprising: a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving therefrom a signal containing a periodic sawtooth waveform; a digital-to-analog (D / A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and circuitry for calculating a difference between a first state of the DCD of the clock signal corresponding to the inverter circuit being set to a high voltage of the input common mode voltage and a second state of the DCD of the clock signal corresponding to the inverter circuit being set to a low voltage of the input common mode voltage.

[0005] According to another aspect of the disclosure, there is provided an apparatus comprising: a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving therefrom a signal containing a periodic sawtooth waveform, the inverter circuit further comprising at least one of an AC coupled inverter and a DC coupled inverter, the DC coupled inverter comprising a programmable threshold voltage; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and circuitry for calculating a difference between a first state of the DCD of the clock signal corresponding to the inverter circuit being set to a high voltage of the input common mode voltage and a second state of the DCD of the clock signal corresponding to the inverter circuit being set to a low voltage of the input common mode voltage, and for comparing the calculated difference to a threshold value and adjusting a level of the programmable bias current based on the comparison.

[0006] According to yet another aspect of the disclosure, there is provided a method of measuring slew rate in a current integrating phase interpolator (CIPI) having a programmable bias current, the method comprising the steps of setting a common threshold voltage of an inverter to a low level; measuring a first duty cycle distortion (DCD) of a signal at an output of the inverter corresponding to the low level common threshold voltage; setting the common threshold voltage of the AC coupled inverter to a high level; measuring a second DCD of the signal at the output of the inverter corresponding to the high level common threshold voltage; comparing a difference between the first and second DCDs and a threshold value; and adjusting the programmable bias current of the CIPI based on a result of the comparison. BRIEF DESCRIPTION OF DRAWINGS

[0007] For a more complete understanding of the present disclosure and its features and advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings in which like reference numerals represent like parts, in which:

[0008] FIG. 1A and FIG. 1B According to embodiments described herein, together with the accompanying drawings, there is shown a schematic block diagram of a circuit for measuring slew rate in a current integrating phase interpolator (CIPI);

[0009] FIG. 2 A schematic block diagram of a delay-locked loop (DLL) based clock and data recovery (CDR) circuit is shown, in which embodiments FIG. 1A and FIG. 1B The circuit shown.

[0010] FIG. 3 Operation of an alternating current (AC) coupled inverter is shown, for implementing FIG. 1A and FIG. 1B The circuit shown in

[0011] FIG. 4 Operation of an AC coupled inverter having a common mode level shift towards VSS is shown according to embodiments described herein; FIG. 3 of

[0012] FIG. 5 Operation of an AC coupled inverter having a common mode level shift towards VDD is shown according to embodiments described herein; FIG. 3 of

[0013] FIG. 6 According to embodiments described herein, there is shown a graph showing FIG. 1A and FIG. 1B random walk in a clock period of the circuit of

[0014] FIG. 7 Operation of a current switching inverter is shown, for implementingFIG. 1A and FIG. 1B circuitry shown in FIGS. 1-3;

[0015] FIG. 8 According to embodiments described herein is a schematic block diagram of a digital-to-analog (D / A) converter for setting a common-mode voltage threshold in conjunction with FIG. 1A and FIG. 1B circuitry;

[0016] FIG. 9 According to some embodiments of the disclosure is a schematic diagram of an electrical device in which conversion rate measurements can be implemented in CIPI;

[0017] FIG. 10 According to some embodiments of the disclosure is a block diagram of an example system that can include one or more systems configured to provide conversion rate measurements in CIPI;

[0018] FIG. 11 According to some embodiments of the disclosure is a block diagram of an example radio frequency (RF) device that can include one or more systems configured to provide conversion rate measurements in CIPI; and

[0019] FIG. 12 According to some embodiments of the disclosure is a block diagram showing an example data processing system that can be configured to control the operation of one or more systems configured to provide conversion rate measurements in CIPI. DETAILED DESCRIPTION

[0020] Current integration is a power efficient technique for implementing bit-to-phase conversion or phase interpolation. FIG. 1A and FIG. 1B According to features of embodiments described herein is shown circuitry 100 for implementing a current integration phase interpolator (CIPI) with programmable bias current, which can be used as a building block in a cable de-serializer 200, as shown in FIG. 2 for use in, for example, a transceiver device. The cable de-serializer 200 can include a phase detector 202, a ring filter 204, a bit-to-phase converter 206, which can be implemented using circuitry 100 FIG. 1A and FIG. 1B , and a clock multiplication unit (CMU) 208. It should be appreciated that a phase interpolator that implements a full 2π phase shift typically requires some conversion rate control.

[0021] Referring again to FIG. 1A and FIG. 1BAt the first stage 101 of the circuit 100, a pseudo-differentiated square wave signal, such as represented by waveform 102, is applied as a clock signal at each of CKIP and CKIN, which are used as inputs to current starved (or current switched) inverters INV0 and INV1. PMOS supply 106a supplies a programmable bias current I B , and NMOS supply 106b sinks current I B . When CKIP is low, INV0 directs current I B from VDD to output OUTN. The signal transitions at output OUTN to VDD at a slope of I B / C L , where C L is the dominant capacitance on OUTN. At the same time, when CKIN is high, it causes the signal to transition at output OUTP to VSS at the same rate (I B / C L ). The desired shape of the signal at output OUTN is a sawtooth, as represented by waveform 108. Maintaining constant current over the entire swing range VSWING requires both PMOS supply 106a and NMOS supply 106b to remain saturated. If a margin of 150 mV is allocated on both VDD and VSS with a 1 V supply, VSWING should be less than 700 mV. For the sake of example, assume that the common mode voltage VCM1 on output OUTN is equal to VDD / 2.

[0022] Outputs OUTN and OUTP make up the output of the first stage 101 of the circuit 100 and are applied to a sense amplifier, which is implemented as AC coupled inverters INV2 and INV3 with resistive feedback, respectively. Inverters INV2 and INV3 convert the sawtooth waveform (e.g., waveform 108) applied at inputs IN and IP into a square or rectangular wave at outputs CKOP and CKON, respectively. The lowest jitter level on the clock output CKOP can be achieved by maximizing the slope of the sawtooth waveform to INV2. The optimal slope maximizes VSWING while keeping PMOS supply 106a and NMOS supply 106b saturated; typically, voltage swing trades off margin for phase noise. In certain embodiments, the phase noise of the optimal VSWING should be greater than 0.6 V and the margin less than 0.7 V with VDD at 1.0 V.

[0023] Capacitance C L is typically fixed. Device and parasitic interconnect capacitances are typically large enough that no explicit capacitance needs to be added to C L . Thus, current I B is the primary mechanism to control VSWING. In certain embodiments, I BThe coverage of the sawtooth waveforms should have at least 2: 1 programmable dynamic range to accommodate a frequency octave. It should be noted that in alternative embodiments, I B is fixed, and C L The adjustable value of C

[0024] A circuit is needed to detect the slope of a sawtooth waveform, such as waveform 108, where the frequency of the sawtooth covers a wide range. As previously described, the signals output by the first stage 101 at outputs OUTN and OUTP drive AC coupled inverters with resistive feedback (specifically, INV2 and INV3). According to certain embodiments, the resistive feedback of inverters INV2, INV3 can be broken by switches SW0 and SW2, and a DC voltage from D / A converter 116 can be used to set the common mode voltage at the inputs IN, IP of inverters INV2, INV3 by closing switches SW1 and SW3. The D / A converter 116 changes the common mode voltage by a controlled amount to change the duty cycle distortion at the outputs of amplifiers INV2 and INV3 (i.e., CKOP, CKON, respectively). The outputs of amplifiers INV2 and INV3 (CKOP and CKON, respectively) are input to a MUX 118 of a duty cycle measurement (DCM) circuit 119.

[0025] The output of one of the amplifiers INV2, INV3 is applied to a comparator 120 via MUX 118. A ring oscillator 122 performs a random walk over the period of the square wave to generate a signal CKRO, which is applied as a clock signal to comparator 120 and to each of a pair of counters 124, 126. Counter 124 is configured to count the number of times the COMP signal COMP O goes high; counter 126 is configured to count the number of times the signal CKRO goes high. It will be appreciated that the function performed by ring oscillator 122 can be performed by other elements / circuitry, including, for example, a clock device.

[0026] As will be described in greater detail below, when the common mode of the sawtooth waveforms applied to the AC coupled inverters INV2, INV3 is set to a known voltage below VDD / 2, the duty cycle is narrow Is and wide Os. In operation, the ring oscillator 122 performs a random walk over the period of the square wave, and when the output of comparator 120 is high, counter 124 is incremented. The count values CNTlo[19:0] and CNT2o[19:0] are provided to a finite state machine (FSM) 128. When the output of counter 126 reaches a predetermined value (e.g., 1024), the output of counter 124 is a low threshold estimate of the duty cycle.

[0027] Similarly, when the common mode voltage of the sawtooth waveform applied to the AC coupled inverter is set to a known voltage that exceeds VDD / 2, the duty cycle is wide 1 s and narrow 0 s. As previously described, the ring oscillator 122 performs a random walk over the period of the rectangular waveform, and the counter 124 increments when the output of the comparator 120 is high. The count values CNTlo[19:0] and CNT2o[19:0] are provided to the finite state machine (FSM) 128. When the output of the counter 126 reaches a predetermined value (e.g., 1024), the output of the counter 124 is the estimate of the duty cycle of the high threshold.

[0028] According to features of embodiments described in more detail below, the bias current I B is adjusted to a minimum amount that results in a difference between the output of the counter 124 for the low threshold and the output of the counter 124 for the high threshold, which is less than the target integer threshold.

[0029] FIG. 3 Normal mode of operation of the AC coupled inverter INV2 is shown. As FIG. 3 It is shown that the sawtooth waveform on the output OUTN has a common mode voltage of VCM1 (graph 302). In one embodiment, VCM1 is set to VDD / 2 so that the signal at the output OUTN swings symmetrically about VDD and VSS. The AC coupled inverter INV2 decouples the common mode voltage on the output OUTN (VCM1) from the common mode voltage at the input IN (VCM2) (graph 304). In normal mode of operation, the switch sw0 is closed so that resistive feedback is enabled from the output CKOP of the inverter INV2 to the input IN of the inverter INV2. Through the feedback, the common mode voltage VCM2 is adjusted so that the duty cycle of the signal on the output CKOP approaches 50 / 50 (graph 306).

[0030] The slew rate of the phase interpolator is related to the bias current and the voltage swing, expressed as:

[0031]

[0032] Without voltage clipping, the output swings its full range of voltage in 1 / 4 clock period. The slew rate can be estimated by changing the common mode voltage of the input signal applied to the input IN of the inverter INV2, and then measuring the duty cycle of the resulting rectangular wave output. The duty cycles of two applied common mode voltages VCM2, with a difference of AV between the voltages, are measured. The difference in the measured duty cycles of the two applied common mode voltages VCM2 is used to calculate AT.

[0033] Without voltage clipping, the output swings its full range voltage within the 1st ¼ clock period. The slew rate can be estimated by changing the common mode voltage at which the signal IN is applied to the inverter, and then measuring the duty cycle of the resulting square wave output. The duty cycles of two applied common mode voltages, with a difference of AV between them, are measured. The difference of the measured duty cycles of the two applied common mode voltresses is used to calculate AT.

[0034] An AC coupled inverter, such as inverters INV2, INV3, can be used as a comparator preamplifier with programmable threshold voltage, as long as the signal input to the inverter is a periodic waveform with finite slope (e.g., a sine wave or a triangle wave). According to features of embodiments described herein, resistive feedback around the AC coupled inverter INV2 is stopped by opening switch swO and closing switch swl, to enable a DC voltage to be applied by D / A converter 116.

[0035] According to features of embodiments described herein, the slew rate can be corrected as follows. Changing the common mode voltage VCM2 can shift the DC voltage on the input IN relative to the threshold of inverter INV2. FIG. 4 Operation of the AC coupled inverter INV2 with common mode level shift towards VSS is shown. In FIG. 4 In the example shown, VCM2 is set to VLOW (e.g., 0.4 VDD), and assume the voltage threshold of inverter INV2 is 0.5 VDD. If an ideal sawtooth waveform with 0.6 V swing is applied at the input IN (chart 402), the signal at the output CKOP will have a duty cycle of 67 / 33 (chart 404).

[0036] Those of ordinary skill in the art will recognize that the function of the AC coupled inverter can be performed by other elements / circuits, such as a DC coupled inverter with programmable threshold voltage.

[0037] In an alternative example, assume the threshold voltage of the inverter is set to.25 between the negative peak (0.2 V) and the positive peak (0.8 V) of the sawtooth waveform signal input to the inverter (e.g., 0.35 V). Then the duty cycle of the square wave signal output from the inverter will be.75 / .25, where the swing is 0.6 V. Assuming the square wave signal is sampled 128 samples of the clock using DCM circuit 119 FIG. 1A and FIG. 1B The counter output should ideally be 96.

[0038] Referring again to FIG. 1A and FIG. 1Bwhere the clock select input CKSEL of MUX 118 is set to 0, MUX 118 applies the clock signal at output CKOP to the input of comparator 120. A random walk is implemented in the period of CKOP shown. The output count of counter 126 is incremented at each rising edge of CKRO until it reaches the threshold set by N[3:0]; the total count is FIG. 6 For example, for N = 9, counter 126 counts to 8192, at which point ENRO goes low. Counter 124 is incremented only when CKOP is high. As shown, the input duty cycle distortion (DCD) is 67 / 33, and the expected value in COUNTLOW is 8192 / 3 = 5461 for a -0.1 V common mode voltage shift relative to the inverter threshold. FIG. 6

[0039] Next, as FIG. 5 shown, VCM2 is shifted towards VDD. In FIG. 5 the example shown, VCM2 is set to VHIGH (e.g., 0.6 VDD) (graph 502). If the signal at input IN is an ideal sawtooth with a 0.6 V swing, then the signal at output CKOP will have a duty cycle of 33 / 67 (graph 504).

[0040] In an alternative example, assume that the threshold voltage of the inverter is set to.75 between the negative peak (0.2 V) and the positive peak (0.8 V) of the sawtooth signal input to the inverter (e.g.,.65 V), then the duty cycle of the square wave signal output from the inverter will be.25 / .75, where the swing is 0.6 V. Assuming that the square wave signal is sampled 128 times by DCM circuit 119 FIG. 1A and FIG. 1B , the counter output should ideally be 32.

[0041] Referring again to FIG. 1A and FIG. 1B , when the signal on ENMEAS transitions from low to high, the signals at both RESETB and ENRO go high. At this point, both counters 124, 126 are enabled, as is ring oscillator 122. As FIG. 6 shown, the signal at output CKRO implements a random walk within the period of the signal at output CKOP. The output count of counter 126 is incremented at each rising edge of the signal at output CKRO until it reaches the threshold set by N[3:0]; the total count is ​For example, for N = 9, counter 126 counts to 8192, at which point ENRO goes low. The signal at CKOP output of counter 124 is high. As FIG. 6 shown, where the input duty cycle distortion (DCD) is 33 / 67, at a common mode of 0.1 V relative to the inverter threshold, the expected value in COUNTHIGH = 2 / 3 (8192) = 2731.

[0042] The difference (DIFFCOUNT) between COUNTHIGH and COUNTLOW for this example is 2731, which means that the sawtooth spends about 1 / 3 of its period between the low threshold at VDD - 0.1 V and the high threshold at VDD + 0.1 V.

[0043] FIG. 7 The operation of current switching inverters INV0, INV1 is shown. As FIG. 7 shown, when the voltage at node CKREF is high, the current at node OUTIN is -I B , and the current at node OUTIP is +I B . Conversely, when the voltage at node CKREF is low, the current at node OUTIN is +I B , and the current at node OUTIN is -I B .

[0044] One of the benefits of the architecture described herein is that a high resolution D / A converter is not needed. FIG. 8 An example D / A converter 900 that can be used to implement D / A converters 116 FIG. 1A and FIG. 1B is shown. As FIG. 8 shown, D / A converter 900 has only a few levels and will be used to decide I B . The threshold for deciding I B is set by the target of (|COUNTHIGH - COUNTLOW|). In some embodiments, D / A converter 900 can be self-biased with a voltage reference derived from the power supply.

[0045] According to embodiments described herein, the algorithm that performs a binary search on I B is used to correct the slew rate, where the control word is an unsigned integer ibslewfs[5:0]. Other search techniques, such as scanning I B from low to high or from high to low, can be implemented as an alternative to binary search.

[0046] In one embodiment, the minimum target VSWING is 0.6 VDD to balance the margin and the phase noise. The D / A converter is set with VLOW = 0.4 VDD and VHIGH = 0.6 VDD, referenced to the power supply. The number of ring oscillator cycles measured at each step is When VSWING is 0.6 VDD, the difference between COUNTHIGH and COUNTLOW should be COUNTTHRESH = M / 3. If the swing on the output OUTN is too low, then |COUNTHIGH - COUNTLOW | > COUNTTHRESH. The deviation between the D / A output voltage and the inverter threshold will cause COUNTLOW and COUNTHIGH to drift by M / 3, respectively. However, this difference cancels out this mismatch. An example pseudo code for implementing an algorithm embodiment is as follows:

[0047]

[0048]

[0049] Example Systems and Devices

[0050] Circuit 100 can be implemented in any electronic device or system that can require a distributed measurement of slew rate in CIPI. Some examples of such devices / systems are shown in FIGS. 10-12 .

[0051] In some embodiments, circuit 100 can be implemented in a radio system. A radio system is a system that transmits and receives signals in the form of electromagnetic waves in the radio frequency range of about 3 kilohertz (kHz) to 300 gigahertz (GHz). Radio systems can be used for countless different applications, such as aircraft, automotive and industrial radar, cellular technology, Wi-Fi and other short-range communication technology, and military applications. One example is shown in FIG. 9 , providing a schematic diagram of an electronic device 1000 including an RF transceiver 1010 and a baseband IC (BBIC) 1020, which is coupled to the RF transceiver 1010, for example, using a high-speed serial interface supported by JESD. In some embodiments, portions of circuit 100 can be implemented in device clock circuitry component 1012, while other portions of circuit 100 can be implemented in JESD 1014. In other embodiments, various portions of circuit 100 can be included in other portions of electronic device 1000.

[0052] FIG. 10 A block diagram of an example system 2100, which can include one or more systems configured to measure slew rate in CIPI, is shown in accordance with any of the embodiments disclosed herein. For example, any suitable component of system 2100 can include one or more of circuit 100 and / or electronic device 1000 disclosed herein. Several components are shown in FIG. 10These components are shown as included in system 2100, but any one or more of these components may be omitted or copied, as long as it is suitable for the application. In some embodiments, some or all of the components included in system 2100 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-a-chip (SoC) die.

[0053] Additionally, in various embodiments, system 2100 may not include FIG. 10 The system 2100 may include one or more components shown, but may also include interface circuitry for coupling to those components. For example, the system 2100 may not include the display device 2106, but may include a display device interface circuitry (e.g., connector and driver circuitry) to which the display device 2106 may be coupled. In another set of examples, the system 2100 may not include the audio input device 2118 or the audio output device 2108, but may include an audio input or output device interface circuitry (e.g., connector and support circuitry) to which the audio input device 2118 or the audio output device 2108 may be coupled.

[0054] System 2100 may include processing means 2102 (e.g., one or more processing means). As used herein, the term "processing means" or "processor" may refer to any means or part of a means of processing electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing means 2102 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing means. System 2100 may include memory 2104, which itself may include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 2104 may include memory that shares a die with processing means 2102. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0055] In some embodiments, system 2100 can include a communication chip 2112 (e.g., one or more communication chips). For example, the communication chip 2112 can be configured to manage wireless communications for the transfer of data to and from the system 2100. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0056] The communication chip 2112 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), Bluetooth (including the Bluetooth LE extension), IEEE 802.16 (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project

[0057] In some embodiments, the communication chip 2112 can manage wired communications, such as electronic, optical, or any other appropriate communication protocols (e.g., the Ethernet). As described above, the communication chip 2112 can include multiple communication chips. For example, a first communication chip 2112 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 2112 can be dedicated to longer-range wireless

[0058] The system 2100 can include battery / power supply circuitry 2114. The battery / power supply circuitry 2114 can include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the system 2100 to an energy source separate from the system 2100 (e.g., AC line power).

[0059] The system 2100 can include a display device 2106 (or corresponding interface circuitry, as discussed above). The display device 2106 can include any visual

[0060] The system 2100 can include an audio output device 2108 (or corresponding interface circuitry, as discussed above). The audio output device 2108 can include any device that produces sound, such as a speaker, headphones, or earbuds.

[0061] The system 2100 can include an audio input device 2118 (or corresponding interface circuitry, as discussed above). The audio input device 2118 can include any device that generates a signal representative of sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output).

[0062] The system 2100 can include a GPS device 2116 (or corresponding interface circuitry, as discussed above). The GPS device 2116 can communicate with

[0063] The system 2100 can include another output device 2110 (or corresponding interface circuitry, as discussed above). Examples of the another output device 2110 can include an audio codec, a video codec, a printer, a wired or wireless transceiver for providing information to other devices, or an additional storage device.

[0064] The system 2100 can include another input device 2120 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2120 can include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0065] The system 2100 can have any desired form factor, such as a hand-held or mobile electronic device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electronic device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electronic device. In some embodiments, the system 2100 can be any other electronic device that processes data.

[0066] FIG. 11 A block diagram of an example RF device 2200 according to any of the embodiments disclosed herein can include one or more components with one or more systems configured to provide conversion rate measurements in CIPI. For example, any suitable of the components of the RF device 2200 can include a die including at least one system or portion thereof configured to provide conversion rate measurements in CIPI according to any of the embodiments disclosed herein. In some embodiments, the RF device 2200 can be included within any of the components of the system 2100, as described with reference to FIG. 10 The system 2100 can include another input device 2120 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2120 can include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. FIG. 10 The system 2100 can include another input device 2120 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2120 can include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. FIG. 10 The system 2100 can include another input device 2120 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2120 can include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0067] In general, RF device 2200 can be any device or system that can support wireless transmission and / or reception of signals in the form of electromagnetic waves in the RF range of about 3 kilohertz (kHz) to 300 gigahertz (GHz). In some embodiments, RF device 2200 can be used for wireless communication, for example, in a base station (BS) or user equipment (UE) device of any suitable cellular wireless communication technology, such as GSM, WCDMA, or LTE. In another example, RF device 2200 can be used as or in a BS or UE device of millimeter wave wireless technology, such as fifth generation (5G) wireless (i.e., high frequency / short wavelength spectrum, for example, with frequencies between about 20 GHz and 60 GHz, corresponding to wavelengths between about 5 millimeters and 15 millimeters). In yet another example, RF device 2200 can be used for wireless communication using Wi-Fi technology (e.g., 2.4 GHz frequency band, corresponding to a wavelength of about 12 cm, or 5.8 GHz frequency band, spectrum, corresponding to a wavelength of about 5 cm), for example, in a Wi-Fi enabled device, such as a desktop computer, laptop computer, video game console, smart phone, tablet computer, smart TV, digital audio player, automobile, printer, etc. In some implementations, the Wi-Fi enabled device can be, for example, a node in a smart system to communicate data with other nodes, for example, a smart sensor. In still another example, RF device 2200 can be used for wireless communication using Bluetooth technology (e.g., 2.4 GHz to about 2.485 GHz frequency band, corresponding to a wavelength of about 12 cm). In other embodiments, RF device 2200 can be used to transmit and / or receive RF signals for purposes other than communication, for example, in an automotive radar system, or in a medical application such as magnetic resonance imaging (MRI).

[0068] In various embodiments, RF device 2200 can be included in a frequency-division duplex (FDD) or time-division duplex (TDD) variant of a frequency allocation that can be used in a cellular network. In an FDD system, uplink (i.e., RF signals transmitted from a UE device to a BS) and downlink (i.e., RF signals transmitted from a BS to a UE device) can use separate frequency bands simultaneously. In a TDD system, uplink and downlink can use the same frequency but at different times.

[0069] Several components are in FIG. 11The components are shown as included in RF device 2200, but any one or more of these components may be omitted or copied as appropriate for the application. For example, in some embodiments, RF device 2200 may be an RF device (e.g., an RF transceiver) that supports wireless transmission and reception of RF signals, in which case it may include components referred to herein as the transmit (TX) path and components referred herein as the receive (RX) path. However, in other embodiments, RF device 2200 may be an RF device that only supports wireless reception (e.g., an RF receiver), in which case it may include components of the RX path but not components of the TX path; or RF device 2200 may be an RF device that only supports wireless transmission (e.g., an RF transmitter), in which case it may include components of the TX path but not components of the RX path.

[0070] In some embodiments, some or all of the components included in the RF device 2200 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single die, for example, on a single SoC die.

[0071] Additionally, in various embodiments, the RF device 2200 may not include... FIG. 11 The RF device 2200 may include one or more components shown, but may also include interface circuitry for coupling to those components. For example, the RF device 2200 may not include antenna 2202, but may include antenna interface circuitry (e.g., matching circuitry, connectors, and driver circuitry) to which antenna 2202 can be coupled. In another set of examples, the RF device 2200 may not include digital processing unit 2208 or local oscillator 2206, but may include device interface circuitry (e.g., connectors and support circuitry) to which digital processing unit 2208 or local oscillator 2206 can be coupled.

[0072] like FIG. 11 As shown, the RF device 2200 may include an antenna 2202, a duplexer 2204, a local oscillator 2206, and a digital processing unit 2208. Similarly, as... FIG. 11 As shown, the RF device 2200 may include an RX path, which may include an RX path amplifier 2212, an RX path premix filter 2214, an RX path mixer 2216, an RX path postmix filter 2218, and an ADC 2220. FIG. 11Further, the RF device 2200 may include a TX path, which may include a TX path amplifier 2222, a TX path post-mixing filter 2224, a TX path mixer 2226, a TX path pre-mixing filter 2228, and a DAC 2230. More further, the RF device 2200 may further include an impedance tuner 2232, an RF switch 2234, and control logic 2236. In various embodiments, the RF device 2200 may include... FIG. 11 Examples of any of the components shown are provided. In some embodiments, the RX path amplifier 2212, TX path amplifier 2222, duplexer 2204, and RF switch 2234 may be considered to form, or be part of, the RF front end (FE) of the RF device 2200. In some embodiments, the RX path amplifier 2212, TX path amplifier 2222, duplexer 2204, and RF switch 2234 may be considered to form, or be part of, the RF FE of the RF device 2200. In some embodiments, the RX path mixer 2216 and TX path mixer 2226 (possibly having...) FIG. 11 The pre-mixing filter and post-mixing filter shown and associated therewith can be considered as forming an RF transceiver of RF device 2200, or a part thereof (or an RF receiver or RF transmitter if only the RX path or TX path components are included in RF device 2200, respectively). In some embodiments, RF device 2200 may further include one or more control logic elements / circuits, in FIG. 10 This is shown as control logic 2236, such as an RF FE control interface. In some embodiments, control logic 2236 may be configured to control at least a portion of the operation of any system configured to provide slew rate measurement in CIPI (as described herein) within any component of the RF device 2200. In some embodiments, control logic 2236 may be used to perform other functional controls within the RF device 2200, such as enhancing control of complex RF system environments, supporting implementations of envelope tracking techniques, reducing power dissipation, etc.

[0073] The antenna 2202 can be configured to wirelessly transmit and / or receive RF signals in accordance with any wireless standard or protocol, such as Wi-Fi, LTE, or GSM, as well as any other wireless protocol designated as 3G, 4G, 5G, and beyond. If the RF device 2200 is an FDD transceiver, the antenna 2202 can be configured for simultaneous reception and transmission of communication signals in separate (i.e., non-overlapping and non-contiguous) frequency bands, such as in frequency bands that are separated from each other by, for example, 20 MHz. If the RF device 2200 is a TDD transceiver, the antenna 2202 can be configured for sequential reception and transmission of communication signals in a frequency band in which the TX and RX paths can be the same or overlapping. In some embodiments, the RF device 2200 can be a multi-band RF device, in which case the antenna 2202 can be configured for simultaneous reception of signals having multiple RF components in separate frequency bands and / or configured for simultaneous transmission of signals having multiple RF components in separate frequency bands. In such embodiments, the antenna 2202 can be a single wideband antenna or a plurality of specific-band antennas (i.e., a plurality of antennas, each configured to receive and / or transmit signals in a particular frequency band). In various embodiments, the antenna 2202 can include a plurality of antenna elements, such as a plurality of antenna elements forming a phased antenna array (i.e., a communication system or antenna array in which a plurality of antenna elements and phase shifting can be used to transmit and receive RF signals). Phased antenna arrays can provide advantages such as increased gain, steering capability, and simultaneous communication as compared to single antenna systems. In some embodiments, the RF device 2200 can include more than one antenna 2202 to enable antenna diversity. In some such embodiments, an RF switch 2234 can be deployed to switch between different antennas.

[0074] The output of the antenna 2202 can be coupled to an input of a duplexer 2204. The duplexer 2204 can be any suitable component configured to filter a plurality of signals to permit bidirectional communication on a single path between the duplexer 2204 and the antenna 2202. The duplexer 2204 can be configured to provide RX signals to the RX path of the RF device 2200 and to receive TX signals from the TX path of the RF device 2200.

[0075] The RF device 2200 can include one or more local oscillators 2206 configured to provide local oscillator signals that can be used to downconvert RF signals received by the antenna 2202 and / or upconvert signals to be transmitted by the antenna 2202.

[0076] The RF device 2200 can include a digital processing unit 2208, which can include one or more processing devices. In some embodiments, the digital processing unit 2208 can be implemented as FIG. 11The processing device 2102 shown, of which the digital processing unit is described above (the processing device 2102 can implement, but is not necessarily required to implement, any system configured to provide a slew rate measurement in the CIPI described herein when used as the digital processing unit 2208). The digital processing unit 2208 can be configured to perform various functions related to digital processing of RX and / or TX signals. Examples of such functions include, but are not limited to, decimation / downsampling, error correction, digital downconversion or upconversion, DC offset cancellation, automatic gain control, etc. Although FIG. 10 not shown in the CIPI described herein, but in some embodiments, the RF device 2200 can further include a memory device, e.g., the memory 2104 described with reference to FIG. 11 the digital processing unit 2208. The memory 2104 can implement, but is not necessarily required to implement, any system configured to provide a slew rate measurement in the CIPI described herein when used within or coupled to the RF device 2200.

[0077] Turning to details of the RX path that can be included in the RF device 2200, the RX path amplifier 2212 can include a low noise amplifier (LNA). An input of the RX path amplifier 2212 can be coupled to an antenna port (not shown) of the antenna 2202, e.g., via the duplexer 2204. The RX path amplifier 2212 can amplify RF signals received by the antenna 2202.

[0078] An output of the RX path amplifier 2212 can be coupled to an input of the RX path pre-mix filter 2214, which can be a harmonic or bandpass (e.g., lowpass) filter configured to filter the received RF signals that have been amplified by the RX path amplifier 2212.

[0079] The output of the RX path pre-mix filter 2214 can be coupled to an input of an RX path mixer 2216 (also referred to as a down-converter). The RX path mixer 2216 can include two inputs and one output. A first input can be configured to receive an RX signal indicative of a signal received by the antenna 2202, which can be a current signal (e.g., the first input can receive the output of the RX path pre-mix filter 2214). A second input can be configured to receive a local oscillator signal from one of the local oscillators 2206. The RX path mixer 2216 can then mix the signals received at its two inputs to produce a down-converted RX signal provided at the output of the RX path mixer 2216. As used herein, down-conversion refers to the process of mixing a received RF signal with a local oscillator signal to produce a lower frequency signal. In particular, the RX path mixer (e.g., down-converter) 2216 can be configured to produce sum and / or difference frequencies at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device 2200 can implement a direct-conversion receiver (DCR), also known as a homodyne, synchrodyne, or zero-IF receiver, in which case the RX path mixer 2216 can be configured to demodulate an incoming radio signal using a local oscillator signal whose frequency is equal to or very close to the carrier frequency of the radio signal. In other embodiments, the RF device 2200 can utilize down-conversion to an intermediate frequency (IF). The IF can be used in a superheterodyne radio receiver, in which the received RF signal is shifted to an IF before final detection of the message in the received signal is accomplished. Conversion to an IF can be useful for several reasons. For example, when several stages of filtering are used, they can all be set to a fixed frequency, which makes them easier to construct and tune. In some embodiments, the RX path mixer 2216 can include several such IF conversion stages.

[0080] Although in FIG. 11A single RX path mixer 2216 is shown in the RX path, but in some embodiments, the RX path mixer 2216 can be implemented as a quadrature downconverter, in which case it would include a first RX path mixer and a second RX path mixer. The first RX path mixer can be configured to perform downconversion to produce an in-phase (I) downconverted RX signal by mixing an RX signal received by the antenna 2202 with an in-phase component of a local oscillator signal provided by the local oscillator 2206. The second RX path mixer can be configured to perform downconversion to produce a quadrature (Q) downconverted RX signal by mixing the RX signal received by the antenna 2202 with a quadrature component of the local oscillator signal (the quadrature component being a component that is offset in phase by 90 degrees from the in-phase component of the local oscillator signal). The output of the first RX path mixer can be provided to an I signal path, and the output of the second RX path mixer can be provided to a Q signal path, which can be offset in phase from the I signal path by substantially 90 degrees.

[0081] Optionally, the output of the RX path mixer 2216 can be coupled to an RX path post-mixing filter 2218, which can be a low pass filter. In the case where the RX path mixer 2216 is implemented as a quadrature mixer with first and second mixers as described above, the in-phase and quadrature components provided at the output of the first and second mixers, respectively, can be coupled to respective separate first and second RX path post-mixing filters included in the filter 2218.

[0082] The ADC 2220 can be configured to convert the mixed RX signal from the RX path mixer 2216 from the analog domain to the digital domain. The ADC 2220 can be a quadrature ADC, similar to the RX path quadrature mixer 2216, which can include two ADCs configured to digitize the downconverted RX path signals separated in in-phase and quadrature components. The output of the ADC 2220 can be provided to the digital processing unit 2208, which is configured to perform various functions related to the digital processing of the RX signal, such that information encoded in the RX signal can be extracted.

[0083] Turning to the details of the TX path that can be included in the RF device 2200, a digital signal (TX signal) to be transmitted later by the antenna 2202 can be provided from the digital processing unit 2208 to a DAC 2230. Similar to the ADC 2220, the DAC 2230 can include two DACs configured to convert digital I and Q path TX signal components, respectively, to analog form.

[0084] Optionally, the output of the DAC 2230 can be coupled to a TX path pre-mix filter 2228, which can be a bandpass (e.g., lowpass) filter (or a pair of bandpass (e.g., lowpass) filters in the case of quadrature processing), configured to filter out signal components outside of the desired frequency band from the analog TX signal output by the DAC 2230. The digital TX signal can then be provided to a TX path mixer 2226, which can also be referred to as an upconverter. Similar to the RX path mixer 2216, the TX path mixer 2226 can include a pair of TX path mixers for in-phase and quadrature components. Similar to the first RX path mixer and the second RX path mixer that can be included in the RX path, each TX path mixer of the TX path mixer 2226 can include two inputs and one output. The first input can receive the TX signal component converted to analog form by the corresponding DAC 2230 that is to be upconverted to generate the RF signal to be transmitted. The first TX path mixer can produce an in-phase (I) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2230 with an in-phase component of a TX path local oscillator signal provided from a local oscillator 2206 (which can include a plurality of different local oscillators in various embodiments, or be configured to provide different local oscillator frequencies to the mixers 2216 in the RX path and the mixers 2226 in the TX path). The second TX path mixer can produce a quadrature-phase (Q) upconverted signal by mixing the transmit signal component converted to analog form by the DAC 2230 with a quadrature component of the TX path local oscillator signal. The output of the second TX path mixer can be summed with the output of the first TX path mixer to produce the real RF signal. The second input of each TX path mixer can be coupled to the local oscillator 2206.

[0085] Optionally, the RF device 2200 can include a TX path post-mix filter 2224 configured to filter the output of the TX path mixer 2226.

[0086] The TX path amplifier 2222 can be a power amplifier (PA) configured to amplify the upconverted RF signal before providing it to the antenna 2202 for transmission.

[0087] In various embodiments, any of the RX path pre-mix filters 2214, the RX path post-mix filters 2218, the TX post-mix filters 2224, and the TX pre-mix filters 2228 can be implemented as RF filters. In some embodiments, the RF filters can be implemented as multiple RF filters or filter banks. A filter bank can include multiple RF filters that can be coupled to a switch, such as the RF switch 2234, configured to selectively turn on and off any of the multiple RF filters (e.g., to activate any of the RF filters) in order to achieve the desired filtering characteristics of the filter bank (i.e., to program the filter bank). For example, when the RF device 2200 is a BS or a UE device or is included therein, such a filter bank can be used to switch between different RF frequency ranges. In another example, such a filter bank can be programmed to suppress TX leakage over different duplex distances.

[0088] The impedance tuner 2232 can include any suitable circuitry configured to match the input and output impedances of different RF circuitry to minimize signal loss in the RF device 2200. For example, the impedance tuner 2232 can include an antenna impedance tuner. It can be particularly advantageous to be able to tune the impedance of the antenna 2202, as the impedance of the antenna is a function of the environment in which the RF device 2200 is located, e.g., the impedance of the antenna varies depending on whether the antenna is held in a hand, placed on a car roof, etc.

[0089] As described above, the RF switch 2234 can be a device configured to route high frequency signals through a transmission path, e.g., to enable the RF device 2200 to transmit and / or receive signals. For example, the RF switch 2234 can be configured to selectively switch between multiple instances of any of the components shown, e.g., to enable the desired behavior and characteristics of the RF device 2200. For example, in some embodiments, the RF switch can be used to switch between different antennas 2202. In other embodiments, the RF switch can be used to switch between multiple RF filters of the RF device 2200 (e.g., by selectively turning on and off the RF filters). Generally, an RF system will include multiple such RF switches. FIG. 11

[0090] The RF device 2200 provides a simplified version, and in other embodiments can include components not shown in FIG. 22, such as one or more of the following: a power amplifier, a low noise amplifier, a frequency synthesizer, and / or one or more components of the transmit and / or receive chains. Example Data Processing System ​other components are specifically illustrated. For example, the RX path of the RF device 2200 can include a current-voltage amplifier between the RX path mixer 2216 and the ADC 2220, which can be configured to amplify the down-converted signal and convert the down-converted signal to a voltage signal. In another example, the RX path of the RF device 2200 can include a balun for generating a balanced signal. In yet another example, the RF device 2200 can further include a clock generator, which may, for example, include a suitable PLL configured to receive a reference clock signal and use it to generate different clock signals that can then be used to time the operation of the ADC 2220, the DAC 2230, and / or can also be used by the local oscillator 2206 to generate a local oscillator signal to be used in the RX path or TX path. One or more systems configured to provide conversion rate measurements in CIPIs described herein can be included to provide conversion rate measurements in CIPIs for operation of one or more of these components.

[0091] FIG. 12

[0092] FIG. 11 According to some embodiments of the disclosure, a block diagram showing an example data processing system 2300 that can be configured to control the operation of one or more systems configured to provide conversion rate measurements in CIPIs is provided. For example, the data processing system 2300 can be configured to implement or control portions of the circuit 100 and / or electronic device 1000 as described herein. In some embodiments, the data processing system 2300 can be configured to implement FIG. 12 the control logic 2236 shown.

[0093] As FIG. 12 shown, the data processing system 2300 can include at least one processor 2302, such as a hardware processor 2302 coupled to memory elements 2304 by a system bus 2306. As such, the data processing system can store program code within memory elements 2304. Further, the processor 2302 can execute the program code accessed from the memory elements 2304 via the system bus 2306. In one aspect, the data processing system can be implemented as a computer that is suitable for storing and / or executing program code. It should be appreciated, however, that the data processing system 2300 can be implemented in the form of any system including a processor and memory that enables the processor to perform the functions described in the present disclosure.

[0094] In some embodiments, the processor 2302 can execute software or an algorithm to perform the activities discussed in this disclosure, particularly those related to providing a conversion rate measurement in a CIPI, as described herein. The processor 2302 can include any combination of hardware, software, or firmware providing programmable logic, including but not limited to a microprocessor, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific IC (ASIC), or a virtual machine processor. The processor 2302 can be communicatively coupled to the memory element 2304, for example, in a direct memory access (DMA) configuration, such that the processor 2302 can read from or write to the memory element 2304.

[0095] In general, the memory element 2304 can include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash, read only memory (ROM), optical media, virtual memory areas, magnetic or tape memory, or any other suitable technology. Unless otherwise specified, any memory element discussed herein is to be interpreted as encompassed within the broad term "memory." Information measured, processed, tracked, or transmitted to or from the data processing system 2300 can be provided in any database, register, control list, cache, or storage structure, all of which can be referenced at any suitable time range. Any such storage options can be included within the broad term "memory" used herein. Similarly, any possible processing elements, modules, and machines described herein are to be interpreted as encompassed within the broad term "processor." Each element shown in the present figure, for example, any element of the circuit 100 and / or the electronic device 1000, can also include suitable interfaces for receiving, transmitting, and / or otherwise communicating data or information in a network environment, so that they can communicate with, for example, the data processing system 2300.

[0096] In certain example implementations, mechanisms for implementing conversion rate measurements in a CIPI as outlined herein can be implemented by logic encoded in one or more tangible media (e.g., embedded logic provided in an ASIC, memory or software logic like an instruction set, possibly comprising object code and source code, executed by a processor or other similar machine, etc.). In some of these instances, memory elements, such as the memory element 2304, can include a non-transitory medium that can be embedded in a chip or chip set, for example, the ASIC, and / or various other circuitry to facilitate the writing and the reading of information to, from, and / or by software and / or hardware configurations. FIG. 12The memory element 2304 shown herein can store data or information used for the operations described herein. This includes memory elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. A processor can execute any type of instructions associated with data or information to implement the operations detailed herein. In one example, a processor, such as... FIG. 12 The processor 2302 shown can transition an element or article of manufacture (e.g., data) from one state or thing to another. In another instance, the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0097] Memory element 2304 may include one or more physical memory devices (such as local memory 2308) and one or more mass storage devices 2310. Local memory may refer to RAM or other non-persistent memory devices that are typically used during the actual execution of the program code. Mass storage devices may be implemented as hard disk drives or other persistent data storage devices. Processing system 2300 may also include one or more cache memories (not shown) that provide temporary storage for at least some program code to reduce the number of times program code must be retrieved from mass storage device 2310 during execution.

[0098] like FIG. 12 As shown, memory element 2304 can store application 2318. In various embodiments, application 2318 can be stored in local memory 2308, one or more mass storage devices 2310, or separately from local memory and mass storage devices. It should be understood that data processing system 2300 can further execute an operating system (…). FIG. 12 (Not shown in the image), the operating system can facilitate the execution of application 2318. Application 2318, implemented as executable program code, can be executed by data processing system 2300, for example, by processor 2302. In response to executing the application, data processing system 2300 can be configured to perform one or more operational or method steps described herein.

[0099] Optionally, input / output (I / O) devices 2312 and 2314 described as input device 2312 and output device 2314 can be coupled to data processing system. Examples of input devices can include, but are not limited to, keyboard, pointing devices such as mice, and the like. Examples of output devices can include, but are not limited to, monitors or displays, speakers, or the like. In some embodiments, output device 2314 can be any type of screen display such as a plasma display, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator such as a dial, a barometer, or an LED. In some implementations, the system can include a driver (not shown) for output device 2314. Input and / or output devices 2312, 2314 can be coupled to data processing system either directly or through intervening I / O controllers.

[0100] In embodiments, input and output devices can be implemented as a combined input / output device (shown in phantom in FIG. 23 around input device 2312 and output device 2314). An example of such a combined device is a touch-sensitive display, sometimes also referred to as a "touchscreen display" or simply "touchscreen." In such embodiments, input to the device can be provided by moving a physical object, such as a stylus or a user's finger, on or near the touchscreen display. Examples

[0101] Optionally, a network adapter 2316 can also be coupled to data processing system to enable it to become coupled to other systems, computer systems, remote network devices, and / or remote storage devices through intervening private or public networks. The network adapter can comprise a data receiver for receiving data that is transmitted by the systems, devices, and / or networks to data processing system 2300, and a data transmitter for transmitting data from data processing system 2300 to the systems, devices, and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that can be used with data processing system 2300.

[0102] Variants and Embodiments

[0103] ​Example 1 is an apparatus comprising a current integrating phase interpolator core having a programmable bias current; an AC coupled inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal comprising a periodic sawtooth waveform therefrom; a digital-to-analog (D / A) converter for setting an input common mode voltage of the AC coupled inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the AC coupled inverter circuit; and a circuit for calculating a difference in the DCD of the clock signal when the input common mode voltage of the inverter circuit is set to a high voltage and the input common mode voltage of the inverter circuit is set to a low voltage.

[0104] In Example 2, the apparatus of Example 1 can further comprise a circuit for comparing the calculated difference to a threshold value and adjusting a level of the programmable bias current based on the comparison.

[0105] In Example 3, the apparatus of any of Examples 1-2 can further comprise increasing the level of the programmable bias current if the calculated difference is greater than the threshold value.

[0106] In Example 4, the apparatus of any of Examples 1-3 can further comprise decreasing the level of the programmable bias current if the calculated difference is less than the threshold value.

[0107] In Example 5, the apparatus of any of Examples 1-4 can comprise the inverter circuit further comprising an inverter having an input and an output; and a resistor coupled between the input and the output via a first switch, the resistor for providing direct current (DC) feedback from the output to the input when the first switch is closed.

[0108] In Example 6, the apparatus of any of Examples 1-5 can further comprise the inverter circuit further comprising a second switch for selectively coupling the D / A converter to the input of the inverter when the first switch is open and the second switch is closed.

[0109] In Example 7, the apparatus of any of Examples 1-6 can further comprise the DCM circuit comprising a clock circuit for performing a random walk in a sample period of the clock signal output from the inverter circuit.

[0110] In Example 8, the apparatus of any of Examples 1-7 can further comprise the DCM circuit comprising a comparator having an input comprising a buffered version of the clock signal output from the inverter circuit.

[0111] In Example 9, the apparatus of any of Examples 1-8 can further comprise a clock circuit for generating a clock signal for the comparator.

[0112] In Example 10, the apparatus of any of Examples 1-9 can further include DCM circuitry including a counter that is incremented when the output of the comparator is high.

[0113] In Example 11, the apparatus of any of Examples 1-10 can further include DCM circuitry including a counter that is incremented at each sampling edge of a clock signal generated by clock circuitry.

[0114] In Example 12, the apparatus of any of Examples 1-11 can further include current- integrating phase interpolator core including a current-switched inverter.

[0115] Example 13 is an apparatus comprising a current-integrating phase interpolator core having a programmable bias current; inverter circuitry coupled to an output of the current-integrating phase interpolator core for receiving a signal including a periodic sawtooth waveform therefrom, the inverter circuitry further including an inverter having an input and an output and a switch for selectively coupling a digital-to-analog (D / A) converter to the input of the inverter, for setting an input common-mode voltage of the inverter circuitry to one of a high voltage and a low voltage; duty cycle measurement (DCM) circuitry for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuitry; and circuitry for calculating a difference in the DCD of the clock signal when the input common-mode voltage of the inverter circuitry is set to the high voltage and the input common-mode voltage of the inverter circuitry is set to the low voltage, and comparing the calculated difference to a threshold value and adjusting a level of the programmable bias current based on the comparison.

[0116] In Example 14, the apparatus of Example 13 can further include increasing the level of the programmable bias current if the calculated difference is greater than the threshold value.

[0117] In Example 15, the apparatus of any of Examples 13-14 can further include decreasing the level of the programmable bias current if the calculated difference is less than the threshold value.

[0118] In Example 16, the apparatus of any of Examples 13-15 can further include clock circuitry for performing a random walk in a sampling period of the clock signal output from the inverter circuitry; and a comparator having an input including a buffered version of the clock signal output from the inverter circuitry.

[0119] In Example 17, the apparatus of any of Examples 13-16 can further include clock circuitry generating a clock signal for the comparator.

[0120] In Example 18, the apparatus of any of Examples 13-17 can further include DCM circuitry including a first counter that increments when the output of the comparator is high, and a second counter that increments at each sampling edge of a clock signal generated by the clock circuitry.

[0121] Example 19 is a method of measuring slew rate in a current integral phase interpolator (CIPI) having a programmable bias current, the method comprising: setting a common threshold voltage of an inverter to a low level; measuring a first duty cycle distortion (DCD) of a signal at an output of the inverter corresponding to the low level common threshold voltage; setting a common threshold voltage of an AC coupled inverter to a high level; measuring a second DCD of the signal at an output of the inverter corresponding to the high level common threshold voltage; comparing a difference between the first and second DCDs and a threshold value; and adjusting the programmable bias current of the CIPI based on a result of the comparison.

[0122] In Example 20, the method of Example 19 can further include adjusting, the adjusting including increasing a level of the programmable bias current if the difference is greater than the threshold value and decreasing the level of the programmable bias current if the difference is less than the threshold value.

[0123] ​

[0124] While embodiments of the disclosure are described above with reference to the example implementations shown herein, those skilled in the art will recognize that the various teachings described above can be applied to a variety of other implementations.

[0125] In the discussion of the above embodiments, components of the system, such as combiners / adders, flip-flops, multiplexers, and / or other components can be readily substituted, replaced, or otherwise modified to accommodate the needs of a particular circuitry. Moreover, it should be noted that the use of complementary electronics, hardware, software, etc. provides equally viable options for implementing the teachings of the present disclosure, which relate to providing slew rate measurements in a CIPI.

[0126] As described herein, the various systems for implementing slew rate measurements in a CIPI can include electronic circuitry for performing the functions described herein. In some cases, one or more components of the system can be provided by a processor specifically configured to perform the functions described herein. For example, the processor can include one or more application specific components, or can include programmable logic gates configured to perform the functions described herein. The circuitry can operate in the analog domain, the digital domain, or the mixed signal domain. In some cases, the processor can be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer readable storage medium.

[0127] In some embodiments, any number of the circuits of the present figures can be implemented on a board of an associated electronic device. The board can be a general-purpose circuit board or a single-purpose circuit board that can house various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board can provide the electrical connections by which the other components of the system can communicate electrically. Any suitable processors, including DSPs, microprocessors, support chips, etc., computer-readable non-transitory memory elements, etc. can be suitably coupled to the board as appropriate to the particular configuration, processing demands, computer designs, etc. Other components, such as external storage, additional sensors, controllers for audio / video displays, and peripheral devices can be attached to the board as plug-in cards, via cables, or integrated onto the board itself. In various embodiments, the functionality described herein can be implemented in analog form as software or firmware running in one or more configurable (e.g., programmable) elements arranged in a structural arrangement to support these functions. The software or firmware providing the analog can be provided on a non-transitory computer-readable storage medium including instructions to permit a processor to perform these functions.

[0128] In some embodiments, the circuits of the present figures can be implemented as independent modules (e.g., devices with relevant components and circuitry configured to perform particular applications or functions) or as plug-in modules in a specific application hardware of an electronic device. Note that particular embodiments of the present disclosure can be readily included in a single chip implementation, such as a system on chip (SOC) package. An SOC represents an integrated circuit that combines

[0129] All specifications, dimensions and relationships (e.g., the number of components or portions of such devices and systems shown in the present figures for providing a rate of conversion measurement in CIPI, etc.) outlined herein are for example and instructional purposes only. Such information can vary considerably without departing from the spirit or scope of the present disclosure or the appended claims. These specifications are intended to be illustrative only and should not be construed as limiting. In the foregoing description, exemplary embodiments have been described with reference to particular processor and / or component arrangements. Various modifications and changes can be made to such embodiments without departing from the scope of the appended claims. The description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0130] Note that in the numerous examples provided herein, interactions can be described in terms of two, three, four, or more electrical components. However, this has only been for purposes of simplifying the figures and the concepts. It is understood that each of the systems can include any number of electrical components. Along these lines, any of the components, modules, and elements depicted in the accompanying drawings / figures can also be combined in various possible configurations and

[0131] Moreover, the functionality associated with providing a conversion rate measurement in the CIPI referenced herein is only illustrative of some possible functionality that can be executed by or within the systems illustrated in the present figures. In some cases, some of these operations can be deleted or removed and in other cases, additional operations can be added or modified. Additionally, the timing of these operations can be altered substantially. The preceding operational flows have been offered for purposes of example and discussion. Substantial flexibility is provided by the embodiments described herein in that any suitable arrangements, schedules, configurations, and timing mechanisms can be resorted to without departing from the teachings hereof.

[0132] Note that all of the optional features of the devices described above can also be implemented with respect to the methods or processes described herein, and the details in the examples can be used anywhere in one or more embodiments.

[0133] Many other changes, substitutions, variations, alterations, and modifications can be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended claims.

Claims

1. An apparatus comprising: The core of the current integral phase interpolator features a programmable bias current; An inverter circuit, coupled to the output of the current integrating phase interpolator core, is used to receive from it a signal containing a periodic sawtooth waveform. A digital-to-analog (D / A) converter for setting the input common-mode voltage of the inverter circuit; Duty cycle measurement (DCM) circuit, used to measure the duty cycle distortion (DCD) of the clock signal output from the inverter circuit; as well as A circuit for calculating the difference between a first state of the DCD of the clock signal and a second state of the DCD of the clock signal, the first state corresponding to the input common-mode voltage when the inverter circuit is set to high voltage and the second state corresponding to the input common-mode voltage when the inverter circuit is set to low voltage.

2. The device of claim 1, further comprising circuitry for comparing the calculated difference with a threshold and adjusting the level of the programmable bias current based on the comparison.

3. The device of claim 2, wherein if the calculated difference is greater than the threshold, the level of the programmable bias current is increased.

4. The device of claim 2, wherein if the calculated difference is less than the threshold, the level of the programmable bias current is reduced.

5. The device according to claim 1, wherein the inverter circuit further comprises: An inverter has both input and output; as well as A resistor, coupled between the input and the output of the inverter via a first switch, is used to provide DC feedback from the output to the input when the first switch is closed.

6. The device of claim 5, wherein the inverter circuit further includes a second switch for selectively coupling a D / A converter to the input of the inverter when the first switch is open and the second switch is closed.

7. The device of claim 1, wherein the DCM circuit includes a clock circuit system for performing a random walk during a sampling period of the clock signal output from the inverter circuit.

8. The device of claim 1, wherein the inverter circuit comprises at least one AC-coupled inverter.

9. The device of claim 1, wherein the inverter circuit includes at least one DC-coupled inverter, the at least one DC-coupled inverter including a programmable threshold voltage.

10. The device according to claim 1, wherein the clock signal comprises a rectangular wave signal.

11. The device of claim 1, wherein the DCM circuit comprises: A counter that increments when the comparator's output is high; as well as A counter that increments at each sampling edge of the clock signal generated by the clock circuit system.

12. The device according to claim 1, wherein the current integrating phase interpolator core includes a current switching inverter.

13. An apparatus comprising: The core of the current integral phase interpolator features a programmable bias current; An inverter circuit, coupled to the output of the current integral phase interpolator core for receiving a signal containing a periodic sawtooth waveform therefrom, the inverter circuit further comprising at least one of an AC-coupled inverter and a DC-coupled inverter, the DC-coupled inverter including a programmable threshold voltage. A duty cycle measurement (DCM) circuit is used to measure the duty cycle distortion of the clock signal output from the inverter circuit. as well as The circuit is configured to calculate the difference between a first state of duty cycle distortion of the clock signal and a second state of duty cycle distortion of the clock signal, the first state corresponding to a high input common-mode voltage of the inverter circuit and the second state corresponding to a low input common-mode voltage of the inverter circuit, and to compare the calculated difference with a threshold and adjust the level of the programmable bias current based on the comparison.

14. The device of claim 13, wherein if the calculated difference is greater than the threshold, the level of the programmable bias current is increased.

15. The device of claim 13, wherein if the calculated difference is less than the threshold, the level of the programmable bias current is reduced.

16. The device of claim 13, wherein the DCM circuit includes a clock circuit for performing a random walk during a sampling period of the clock signal output from the inverter circuit.

17. A method for measuring the conversion rate in a current integral phase interpolator (CIPI) with a programmable bias current, the method comprising the steps of: Set the common threshold voltage of the inverter to a low level; Measure the first duty cycle distortion of the signal at the output of the inverter corresponding to the low-level common threshold voltage; Set the common threshold voltage of the inverter to a high level; Measure the second duty cycle distortion of the signal at the output of the inverter corresponding to the high-level common threshold voltage; The difference between the first duty cycle distortion and the second duty cycle distortion is compared with a threshold. as well as The programmable bias current of the CIPI is adjusted based on the results of the comparison.

18. The method of claim 17, wherein the adjustment includes increasing the level of the programmable bias current if the difference is greater than the threshold, and the adjustment includes decreasing the level of the programmable bias current if the difference is less than the threshold.

19. The method of claim 17, further comprising, prior to the comparison, calculating the difference between the first duty cycle distortion and the second duty cycle distortion.

20. The method of claim 17, further comprising: A random walk is performed during the sampling period of the clock signal output from the inverter circuit.

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