Semiconductor manufacturing apparatus and method of manufacturing semiconductor device

Abstract

Provided is an etching apparatus or etching method that improves the yield of processing in etching of a film composed of SiO2. As a means thereof, a semiconductor manufacturing apparatus is used, which has: a guide inlet that guides a processing gas composed of steam of each of hydrogen fluoride and alcohol into a processing chamber inside a processing vessel; a sample stage that is disposed in the processing chamber and on which a wafer that is a processing target is loaded on an upper surface; and an electrode that is disposed inside the sample stage and to which direct current power that forms an electric field of a first layer formed on the upper surface of the wafer by the processing gas is applied when etching processing is performed on the first film formed on the upper surface of the wafer.

Description

Technical Field

[0001] This invention relates to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor apparatus, and particularly to a vapor etching apparatus that does not use plasma and a manufacturing method using the same. Background Technology

[0002] In the manufacture of semiconductor devices, which involves processing a film (e.g., a silicon oxide (SiO2) film) on a sample of a semiconductor wafer to form a circuit structure, the demand for higher precision processing techniques increases with the miniaturization of semiconductor devices. In recent years, as processing equipment for processing SiO2 films, the development of so-called vapor etching apparatuses has been underway. These apparatuses use a processing gas instead of plasma to supply vapors of a specific substance to the surface of the SiO2 film, causing the atoms or molecules of that substance to react with the SiO2 film.

[0003] For example, in the vapor etching of SiO2 films, as described in Non-Patent Document 1, an etching apparatus using a mixture of hydrofluoric acid (HF) and alcohol is proposed. Furthermore, Patent Document 1 (JP Patent Application Publication No. 2015-161493) proposes a vapor etching apparatus using a mixture of HF and alcohol.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: JP Japanese Patent Application Publication No. 2005-161493

[0007] Non-patent literature

[0008] Non-patent document 1: Chun Su Lee et al., "Modeling and Characterization of Gas-Phase Ethihng of Thermal Oxide and TEOS Oxide Using Anthdrous HF and CH3OH", J. Electrochem. Soc., vol. 143, No. 3 pp. 1099-1103 (1996) Summary of the Invention

[0009] The problem that the invention aims to solve

[0010] In etching using a vapor mixture of HF and alcohol, it is known that maintaining the wafer temperature within a suitable range during etching is effective in order to achieve the desired etching rate. Additionally, the pressure within the processing chamber can be cited as another parameter affecting the etching rate. However, parameters such as temperature and pressure within the processing chamber are generally difficult to change at high speeds. Therefore, in the past, in vapor etching using a mixed gas as vapor and etching SiO2 as the target, a so-called continuous etching method was employed, where the etching amount monotonically increases over time.

[0011] On the other hand, in recent years, there has been a growing demand for high-precision etching in semiconductor device manufacturing, such as atomic-level etching of SiO2, known as ALE (Atomic Layer Etching). Regarding the ALE problem targeting SiO2, the technology described in Patent Document 1 suffers from the inability to precisely adjust the etching amount (etching rate) per unit time to within the desired range, resulting in a low yield.

[0012] The purpose of this invention is to provide a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor apparatus, which can etch films containing SiO2 with high precision, especially in atomic-level etching, thereby improving the yield of the processed product.

[0013] Other purposes and new features will become apparent from the description in this specification and from the accompanying drawings.

[0014] Methods for solving problems

[0015] If we were to briefly describe the outline of a representative scheme among the embodiments disclosed in this application, it would be as follows.

[0016] A representative embodiment of a semiconductor manufacturing apparatus includes: a processing container; an inlet that introduces a processing gas containing vapors of hydrogen fluoride and an alcohol into a processing chamber inside the processing container; a sample stage disposed in the processing chamber, the upper surface of which is loaded with a wafer to be processed; and an electrode disposed inside the sample stage, which, during etching of a first film formed on the upper surface of the wafer, is subjected to direct current power to form an electric field on a first layer formed on the upper surface of the wafer by the processing gas.

[0017] The effects of the invention

[0018] According to representative implementation methods, the performance of semiconductor manufacturing equipment can be improved. In particular, it enables high-precision etching of SiO2. Attached Figure Description

[0019] Figure 1This is a longitudinal cross-sectional view schematically illustrating the structure of an etching apparatus as a semiconductor manufacturing apparatus according to an embodiment of the present invention.

[0020] Figure 2 It is Figure 1 The overall structure of the etching apparatus shown is illustrated in a block diagram, which connects the blocks representing the functions of each other.

[0021] Figure 3 It means to utilize Figure 1 A schematic diagram of the structure of the upper surface of the wafer and the processing chamber above it in the etching process of the etching apparatus shown.

[0022] Figure 4 It means to utilize Figure 1 A schematic diagram of the structure of the upper surface of the wafer and the processing chamber above it in the etching process of the etching apparatus shown.

[0023] Figure 5 It is a graph showing the relationship between time and etching amount in the etching process.

[0024] Figure 6 It means to utilize Figure 1 A graph showing the relationship between time and etching amount in the etching process of the etching apparatus shown.

[0025] Figure 7 This is a longitudinal cross-sectional view illustrating the structure of an etching apparatus as a semiconductor manufacturing apparatus according to a modified example 1 of the embodiments of the present invention.

[0026] Figure 8 It indicates composition Figure 7 A top view of the sample stage of the etching apparatus shown.

[0027] Figure 9 It means to use Figure 7 The graph shows the variation of the etching rate of the SiO2 film on the upper surface of a wafer processed by an etching apparatus as a semiconductor manufacturing device, as shown in the modified example, relative to the position of the wafer in the radial direction.

[0028] Figure 10 This is a longitudinal cross-sectional view illustrating the structure of an etching apparatus as a semiconductor manufacturing apparatus according to a modified example 1 of the embodiments of the present invention.

[0029] Figure 11 It indicates composition Figure 10 A top view of the sample stage of the etching apparatus shown.

[0030] Figure 12 It is a symbolic representation of use Figure 10The graph shows the variation of the etching rate of the SiO2 film on the upper surface of a wafer processed by an etching apparatus as a semiconductor manufacturing device, as shown in the modified example, relative to the position of the wafer in the radial direction.

[0031] Figure 13 This is a longitudinal cross-sectional view illustrating the structure of an etching apparatus as a semiconductor manufacturing apparatus according to Modified Example 3 of the present invention.

[0032] Figure 14 This is a longitudinal cross-sectional view illustrating the structure of an etching apparatus as a semiconductor manufacturing apparatus according to Modified Example 3 of the present invention.

[0033] Figure 15 This is a schematic diagram showing the structure of the upper surface of the wafer and the processing chamber above it during the etching process using the etching apparatus of the comparative example. Detailed Implementation

[0034] The embodiments of the present invention will now be described in detail based on the accompanying drawings. Furthermore, throughout the drawings used to explain the embodiments, components with the same function are labeled with the same reference numerals, and repeated descriptions are omitted. Additionally, in the embodiments, descriptions of the same or identical parts are generally not repeated except where necessary.

[0035] (Implementation Method)

[0036] The following describes an etching apparatus and etching method for etching a SiO2 film, the object to be processed, pre-formed on the upper surface of a semiconductor wafer (hereinafter simply referred to as a wafer), as a process in manufacturing semiconductor devices. In this etching apparatus and etching method, so-called vapor etching is performed, using vapor containing hydrogen fluoride (HF, hydrofluoric acid) and alcohol X (CxHyOH) as the constituent gas mixture for the process. This embodiment provides a semiconductor manufacturing apparatus or a method for manufacturing a semiconductor device that can precisely control the etching rate (speed) of SiO2.

[0037] <Details on where there is room for improvement>

[0038] As a process for processing SiO2 films, there is a so-called vapor etching method, which does not use plasma. In this method, the vapor of a specific substance is provided to the surface of the SiO2 film as a processing gas, so that the atoms or molecules of that substance react with SiO2.

[0039] For example, in vapor etching of SiO2, consider etching using a mixture of HF and alcohol. In HF and alcohol vapor etching, the HF and alcohol X mixed in the gas phase liquefy at the wafer surface. In the liquid phase at the wafer surface, HF and alcohol X are ionized into negative ions HF2, as shown in Formula 1 below. -and positive ions XH + .

[0040] 2HF+X→HF2 - +XH + …(1)

[0041] On the other hand, at the interface between the liquid phase and the etched object, i.e., the SiO2 film, the negative ions HF2 - The bond between silicon atoms (Si) and oxygen atoms (O) in SiO2 is broken to produce silicon tetrafluoride (SiF4) and water (H2O). Additionally, this chemical reaction requires protons (H). + However, the protons originate from XH in the liquid phase. + Provided. As a result, the reaction shown in Equation 2 is advanced on this interface.

[0042] SiO2+2HF2 - +2XH + →SiF4+2H2O+2X…(2)

[0043] If we summarize this reaction, it becomes the reaction formula 3 below.

[0044] SiO2+4HF+2X→SiF4+H2O+2X…(3)

[0045] If the reaction products SiF4 and H2O are continuously vented using a vacuum pump or similar means, the reaction proceeds unidirectionally from left to right in Equation 3, resulting in the etching of SiO2. To carry out this reaction in a vacuum chamber, etching must be performed below the saturated vapor pressure of SiF4 or H2O. Specifically, to efficiently advance the reaction in Equation 1, the pressure within the processing chamber is preferably near the saturated vapor pressure of HF or alcohol X. For example, efficient etching can be achieved when etching is performed at pressures ranging from tens to hundreds of Pa.

[0046] In etching using vapors of a mixture of HF and alcohol X, maintaining the wafer temperature within a suitable range during etching is effective in order to keep the etching rate within a desired range. For example, by placing the wafer on a sample stage positioned within the processing chamber and keeping the temperature of the sample stage appropriately low, the proportion (adhesion coefficient) of vapor particles such as HF or alcohol X adhering to the wafer increases. As a result, a portion of the vapors of the substance supplied to the wafer surface in the chamber that adheres to the wafer surface combines with each other to form droplets, thereby forming a liquid (liquid phase) layer containing the aforementioned components on the wafer surface.

[0047] exist Figure 15 This indicates the state. Figure 15This is a schematic diagram showing the structure of the upper surface of the wafer and the processing chamber above it during the etching process using the etching apparatus of the comparative example. Figure 15 In the diagram, a white triangle represents hydrogen fluoride (HF) in its vapor state, a white square represents alcohol X in its gaseous state, and a negatively charged triangle represents the negatively charged ion HF2 in its liquid state. - The positive ions XH in the liquid phase are shown in shaded squares. + .

[0048] like Figure 15 As shown, in region 1A, a silicon oxide (SiO2) film is pre-formed on the wafer surface. Furthermore, vapors containing hydrogen fluoride (HF) and alcohol X are supplied to the chamber on the SiO2 film 4a. In region 1B on the upper surface of the SiO2 film 4a, these substances (hydrogen fluoride and alcohol) form a liquid phase layer as a liquid phase, and in region 1C within the chamber above this liquid phase layer, these substances (hydrogen fluoride and alcohol) form a vapor phase layer as a gas phase. In this state, in the liquid phase layer in contact with the SiO2 film 4a, the negative ions HF2 act as an etchant. - The total number of layers is greater than that of the vapor layer, and as a result, the etching rate of SiO2 increases.

[0049] Other parameters that affect the etching rate under these conditions include the pressure inside the processing chamber. The HF2 etching rate can be increased by increasing the pressure inside the processing chamber where the HF vapor is supplied. - The generation rate. However, parameters such as temperature and pressure are difficult to change in a short time in response to changes in processing conditions, i.e., it is difficult to respond at a high speed. Therefore, in steam etching that uses a mixed gas as steam to etch SiO2, the so-called continuous etching, in which the etching amount monotonically increases with time, is considered.

[0050] On the other hand, in the so-called ALE (Atomic Layer Etching) that etches SiO2 at the atomic level, if a mixture of HF and alcohol as described in Patent Document 1 is used for etching, the amount of etching per unit time (etching rate) cannot be adjusted to the desired range with high precision, which impairs the yield of the processed product.

[0051] Thus, in vapor etching without plasma, it is not possible to etch films containing SiO2 with high precision, especially in atomic-level etching, and there is room for improvement in terms of improving the yield.

[0052] <Structure of the etching apparatus in this embodiment>

[0053] The following uses Figures 1-6This embodiment will be explained below. Figure 1 This is a schematic longitudinal cross-sectional view illustrating the structure of the etching apparatus as a semiconductor manufacturing apparatus according to this embodiment. Especially in Figure 1 The image shows an etching apparatus that applies a DC electric field to a wafer to etch SiO2.

[0054] like Figure 1 As shown, the etching apparatus 100 of this embodiment includes, inside a vacuum container (processing container) 1, a processing chamber 30 serving as a depressurized space; and an electrode 5 disposed within the processing chamber 30 and positioned above the upper surface of the wafer 4, serving as a sample stage (platform). When the wafer 4 is placed on the electrode 5, the electrode 5 and the wafer 4 are in physical contact. The vacuum container 1, which is at least partially cylindrical, has a circular top plate 1a at its upper part, which serves as a cover member to airtightly seal the interior, and a gas inlet 2 at its lower part, above the processing chamber. The gas inlet 2 includes a gas inlet hole 32 that serves as a gas path, penetrating the top plate 1a and the gas inlet 2 in the vertical direction. Here, "at least a portion" of the vacuum container 1 refers to the portion of the vacuum container 1 that surrounds the processing chamber 30 above the electrode 5 when viewed from above.

[0055] A mixed gas containing HF and alcohol X is introduced into the processing chamber 30 as the processing gas. Alcohol X, as referred to in this application, generally refers to a substance characterized by the chemical formula CxHyOH, in which hydrogen atoms of hydrocarbons, such as isopropanol, ethanol, and methanol, are replaced with hydroxyl groups.

[0056] Furthermore, at the lower part of the vacuum container 1, an exhaust port 31 with a through hole for discharging particles such as gases or reaction products from the processing chamber 30 to the outside of the processing chamber 30 is provided, connecting the inside and outside of the processing chamber 30. Below the exhaust port 31, a vacuum exhaust pump, such as a turbomolecular pump or a rotary pump, is provided and connected to the outlet of the exhaust port 31 through a pipe. By operating the vacuum exhaust pump, the interior of the processing chamber 30 is vented, thereby reducing the pressure.

[0057] In the lower part of the processing chamber 30, which has a cylindrical shape in at least a portion, an electrode 5 disposed in the central part, viewed from above, has a cylindrical shape. The electrode 5 has a conductive component, such as a circular plate or a cylindrical metal, inside it. A DC voltage source 6 is electrically connected to this conductive component. The DC voltage source 6 is preferably a bipolar power source with a built-in function or polarity switch capable of switching the polarity of the DC voltage in its terminals, but is not limited to this.

[0058] Furthermore, at least one infrared lamp (IR lamp) assembly 3 is provided inside the vacuum container 1, which is arranged in a ring around the gas inlet 2 above the processing chamber 30. The infrared lamp assembly 3 has an annular space arranged around the gas inlet 32 ​​and the center of the electrode 5 when viewed from above the vacuum container 1. In addition, the infrared lamp assembly 3 has at least one infrared lamp 3a arranged concentrically or spirally around the vertical axis of the gas inlet 32 ​​or the cylindrical electrode 5 within this space. In addition, the infrared lamp assembly 3 has an annular window member 3b, which is disposed between the infrared lamp 3a and the processing chamber 30 and forms the top surface of the processing chamber 30, and is made of a quartz or other component that transmits infrared rays radiated from the infrared lamp 3a. In addition, the infrared lamp assembly 3 includes: a cylindrical partition wall surrounding the gas inlet 2 above the inner periphery of the window member 3b; and a reflector plate, which, although not shown, is disposed above the infrared lamp 3a inside the annular space and reflects the infrared light radiated by the infrared lamp 3a below into the processing chamber 30 below.

[0059] Infrared lamp 3a is electrically connected to a DC power supply (not shown) and is powered to irradiate wafer 4 with infrared radiation radiated from infrared lamp 3a. Residue and reaction products on wafer 4 are removed due to the heating caused by radiation. That is, infrared lamp 3a is used to remove residue and reaction products on wafer 4 after etching of wafer 4 by etching apparatus 100.

[0060] Furthermore, a SiO2-containing film of the material to be etched is formed in contact with the upper surface of the wafer 4. In addition, in the etching of SiO2 in this embodiment, the wafer 4 is irradiated by an infrared lamp 3a for the purpose of removing reaction products, but in this etching method, the infrared lamp is not an essential structure.

[0061] The etching apparatus 100 of this embodiment is a vapor etching apparatus that provides a vapor of a specific substance as a processing gas to the surface of the SiO2 film and causes the atoms or molecules of that substance to react with the SiO2 film. Plasma is not used during etching. That is, the etching apparatus 100 does not perform plasma etching. In other words, the etching apparatus 100 does not include a plasma generating device (plasma generating unit).

[0062] Next, an explanation Figure 1The etching apparatus 100 shown in the figure is used to etch a wafer 4 on which a SiO2 film has been pre-formed on its upper surface. In this embodiment, a mixed gas containing hydrogen fluoride (HF) and methanol (CH3OH) vapor is supplied to the processing chamber 30 as the processing gas. The flow rates of HF and CH3OH are adjusted to 500 mL / min and 250 mL / min, respectively. Furthermore, by balancing the amount or rate of the processing gas introduced into the processing chamber 30 from the gas introduction section 2 with the amount or rate of the exhaust gas from the processing chamber 30 regulated by the operation of the vacuum exhaust pump, the pressure inside the processing chamber 30 is adjusted to a value of 10 Pa to 1000 Pa.

[0063] Electrode 5 has an internal coolant flow path connected to a cooler (not shown) for temperature regulation of the coolant. Before and during the processing of wafer 4, the temperature of electrode 5 and wafer 4, which is held above its upper surface, is regulated to -50 to -10°C by the coolant supplied and circulated from the cooler within the coolant flow path. Furthermore, the optimal processing temperature of wafer 4 depends on the pressure value within the processing chamber 30. As described above, a conductive component connected to a DC voltage source 6, which serves as a bipolar power supply, is disposed inside electrode 5. During the processing of wafer 4, a voltage V is applied to this conductive component. DC = ±200V voltage.

[0064] On the upper surface of a silicon (Si) wafer 4, a film comprising SiO2 is formed with a thickness within a given error range of 500 nm, serving as the film to be processed (etched material). This film is a thermally oxidized film. Using such a wafer 4, the inventors of this invention measured the etching rate when a mixed gas containing HF and CH3OH vapors was supplied to the processing chamber 30 to etch the SiO2 film. In this measurement of the etching rate of the wafer 4, the inventors of this invention calculated the etching rate of the SiO2 film as the average value of values ​​detected at five locations near the center of the wafer 4.

[0065] The detected etching rate of SiO2 in V DC At 0V, it reaches 60nm / min. On the other hand, let V be... DC The etching rate of SiO2 increases to approximately 80 nm / min at +200V, while at V... DC At -200V, the etching rate of SiO2 decreases to around 50nm / min. Furthermore, it is anticipated that further increasing the bias voltage would increase both the etching rate and the suppression effect.

[0066] use Figure 2The overall structure, including the structure for providing and discharging the processing gas of the etching apparatus 100 of this embodiment, will be described. Figure 2 It is Figure 1 The overall structure of the etching apparatus shown is schematically illustrated as a block diagram in which blocks representing functions are connected to each other. Additionally, in Figure 2 In China, for Figure 1 A portion of the structure shown is omitted from the illustration.

[0067] like Figure 2 As shown, the etching apparatus of this embodiment includes a hydrogen fluoride (HF) supplier 20 that provides steam as a processing gas and a flow regulator 21 thereof. The HF supplier 20 has a structure that provides HF under high-pressure gas conditions based on a storage unit such as a gas tank that internally stores HF or a commonly used gas cylinder. The flow regulator 21 widely uses a mass flow controller for gases.

[0068] Furthermore, the etching apparatus of this embodiment includes an alcohol X supplier 22 and a flow regulator 23. The alcohol X supplier 22 is a supplier that provides alcohol X via forced vaporization or in a liquid state, together with an alcohol X storage section. The flow regulator 23 is, for example, a flow regulator with the same structure as the flow regulator 21.

[0069] Regarding the processing gas, the gases from suppliers 20 and 22, whose flow rates are regulated by flow regulators 21 and 23, are combined into a single flow path and connected to the vacuum container 1 to supply the internal processing chamber 30 as vapor. However, the aforementioned structure for supplying the processing gas is not limited to using... Figure 2 The structure described above.

[0070] The etching apparatus of this embodiment includes a vacuum container 24 and a vacuum exhaust pump 25 connected to and communicating with an exhaust port 31. The vacuum container 24 is equivalent to... Figure 1 The vacuum container 1 is shown. The feeder 20 is connected to the vacuum container 24 via the flow regulator 21, the feeder 22 is connected to the vacuum container 24 via the flow regulator 23, and the vacuum container 24 is connected to the vacuum exhaust pump 25.

[0071] Vacuum container 24 is connected to cooler 26, which provides and circulates coolant at a temperature set within a given range to the coolant flow path disposed inside electrode 5. Here, coolant from cooler 26 is supplied to the coolant flow path when the wafer 4 is placed on and held on the upper surface of electrode 5, or during the processing of wafer 4. As a result, the temperature of electrode 5 and the wafer 4 held thereon are cooled to a temperature suitable for processing. By cooling in this way, the adhesion rate of the mixed gas can be increased.

[0072] Furthermore, the electrode 5 located inside the vacuum container 24 is connected to a DC power supply 28 with a polarity determination circuit via a controller (DC power supply controller, control unit) 27. The polarity of the voltage applied to the electrode 5 from the DC power supply 28 can be controlled by the controller 27.

[0073] The devices in the various modifications described later also include the aforementioned components such as a gas feeder, flow regulator, exhaust pump, or temperature regulator for the sample stage supporting the wafer 4.

[0074] Next, use Figure 3 as well as Figure 4 This section will explain the structure of the upper surface of wafer 4 during the etching process of the SiO2 film implemented in this embodiment. Figure 3 as well as Figure 4 It means to utilize Figure 1 This is a schematic diagram of the structure of the upper surface of the wafer and the processing chamber above it in the etching process of the etching apparatus shown. (As used...) Figure 15 As explained, HF and alcohol X, supplied as vapor within the processing chamber 30, form a liquid phase layer on the upper surface of the SiO2 film on the wafer 4. Within this liquid phase layer, HF and alcohol X are ionized into positive and negative ions, respectively, forming negative ions HF2, which act as an etchant for SiO2. - .

[0075] exist Figure 3 The diagram shows the state of the upper surface of the wafer 4 when the polarity of the terminal of the DC voltage source 6, which is electrically connected to a conductive component within the electrode 5, is set such that the polarity of both the component and the electrode 5 is positive. Figure 3 To the right, a large arrow indicates the direction of the electric field. Figure 3 In this process, a positive electric field (a potential difference distribution where the potential is high on the electrode 5 side and low inside the processing chamber 30 above the wafer 4) is formed by applying a voltage to the conductive components within the electrode 5 to control the negative ions HF2. - The attraction that causes it to move towards the lower electrode 5, thereby generating negative ions HF2. - Downward within the liquid phase layer, so that it approaches the upper surface of the SiO2 film 4a of wafer 4.

[0076] On the other hand, in the positive ion XH + The repulsive force acting away from electrode 5, positive ions XH +The particles move upwards within the liquid phase layer in a direction away from the upper surface of the SiO2 film 4a on the wafer 4. That is, when an electric field is applied to the wafer 4 in a positive direction (a positive electric field that creates a relatively high potential for the conductive components within the electrode 5), negative ions HF2, acting as an etchant, segregate at the interface between the SiO2 film 4a on the wafer 4 and the liquid phase layer above it. - As a result, the etching rate of SiO2 increases compared to the case where no electric field is applied.

[0077] Figure 4 and Figure 3 Conversely, the example shows the state of the upper surface of the wafer 4 when the polarity of the terminal of the DC voltage source 6, which is electrically connected to a conductive component within electrode 5, is set such that the polarity of both the component and electrode 5 is negative. Figure 4 To the right, a large arrow indicates the direction of the electric field. (Example) Figure 4 As shown, when the electric field formed on the upper surface of wafer 4 is in the negative direction, for negative ions HF2 - Between electrode 5 and electrode XH, a repulsive force is exerted. + Between electrode 5 and electrode 6, attraction plays a role. That is, assuming that when the electric field is applied in the negative direction, at the interface between the upper surface of the SiO2 film 4a on wafer 4 and the lower surface of the liquid phase layer, segregation does not directly contribute to the etching of positive ions XH. + As a result, the etching rate of SiO2 is reduced compared to the case where no electric field is applied.

[0078] <Effects of this implementation method>

[0079] The following uses Figure 5 as well as Figure 6 This will illustrate the effects of this implementation method.

[0080] Figure 5 as well as Figure 6 This is a graph showing the relationship between time and etching amount in the etching process. For example... Figure 5 As shown, it can be seen that the voltage (bias voltage) V applied to electrode 5 DC When V is positive DC >0), with V DC Compared to the case where the bias voltage is 0, the etching rate increases. Conversely, it can be seen that when the bias voltage is negative (V... DC When the value is less than 0, the etching rate decreases. Here, the magnitude of the etching rate increases correspondingly to the magnitude of the applied positive bias voltage.

[0081] On the other hand, Figure 6The diagram illustrates the change in the etching amount of the SiO2 film when the magnitude of the bias voltage varies with time. For example, the bias voltage is set to V during the time interval 0 < t < t1. DC When V = -V0 (a negative fixed value), as mentioned above, the etching progress of SiO2 is suppressed. Next, let V be the value for the time interval t1 < t < t2. DC When the bias voltage is +V0 (a positive fixed value), the etching of SiO2 progresses. Thus, by varying the bias voltage over time, the progress and suppression of etching can be controlled. Utilizing this effect, high-precision etching control of SiO2 can be achieved. Therefore, the etching apparatus 100 of this embodiment can also include a control unit that varies the magnitude or polarity of the DC power supplied to the electrode 5 according to the elapsed time during the processing of the wafer 4.

[0082] Thus, in this embodiment, in an etching apparatus that does not use plasma, the etching progress can be controlled by controlling the voltage applied to the electrodes within the sample stage where the wafer is placed. Therefore, in vapor etching, films containing SiO2 can be etched with high precision. That is, the performance of the semiconductor manufacturing apparatus can be improved. Furthermore, especially in atomic-level etching, the yield of the processed material can be improved. In other words, the aforementioned improvement is eliminated.

[0083] <Variation Example 1>

[0084] use Figure 7 Let me illustrate a variation of this embodiment, Example 1. Figure 7 This is a schematic longitudinal cross-sectional view illustrating the structure of the etching apparatus in this modified example. Figure 8 It indicates composition Figure 7 The image shows a top view of the sample stage of the etching apparatus. In this modified etching apparatus 600, the sample stage holding the wafer 4 on its upper surface has multiple conductive components, i.e., electrodes, arranged concentrically about the radial direction of its cylindrical shape, which is similar to... Figure 1 The etching apparatus 100 shown is different. In the following description, the designations and... Figures 1-6 The structures of the same reference numerals as those in the embodiments described herein are omitted unless necessary.

[0085] The etching apparatus 600 in this modification, like the etching apparatus 100, includes a vacuum container 1, a processing chamber 30, a gas inlet section 2 with a gas inlet hole 32, an infrared lamp assembly 3, and an exhaust port 31 disposed on the bottom surface of the vacuum container 1. In this modification, a first multi-electrode 10 is provided, which is disposed below the gas inlet hole 32 in the lower part of the processing chamber 30, and has a cylindrical or circular plate shape. The first multi-electrode 10 has multiple conductive components disposed at different radial positions or regions along its radial direction. Each of the multiple conductive components is electrically connected to a DC voltage source 6.

[0086] For the components constituting the multiple conductive systems of the first multi-electrode 10, in Figure 8 The top view is shown in the image. Figure 8 It is a schematic representation Figure 7 A diagram showing the structure of the upper surface of the first multi-electrode 10, or a cross-section of a specific vertical direction viewed from above, particularly illustrating the arrangement of components of multiple conductive systems. For example... Figure 8 As shown, the first multi-electrode 10 includes: an inner electrode 7, which is disposed at the center of the cylindrical or circular plate shape of the first multi-electrode 10 in the radial direction, has a circular plate or cylindrical shape, and is conductive; an outer electrode 8, which is spaced apart from the inner electrode 7 on the outer periphery of the inner electrode 7 and surrounds the inner electrode 7, has an annular shape, and is conductive; and an insulator 9, which is disposed between the two electrodes disposed at a distance apart in the radial direction, is made of a dielectric material that electrically insulates these electrodes, and is annular in shape.

[0087] In the first multi-electrode 10, an insulator 9 is embedded and connected between the inner electrode 7 and the outer electrode 8. Furthermore, for the DC voltage source 6 in this example, one of its terminals is electrically connected to the inner electrode 7, allowing a DC voltage to be applied to the inner electrode 7. Additionally, the other terminal of the DC voltage source 6, along with a ground electrode (not shown), is electrically connected to the outer electrode 8 and is set to a ground potential. Thus, the potential of the inner electrode 7, connected to one terminal of the DC voltage source 6 (which is a bipolar power source), can change between positive and negative. Furthermore, the relative magnitude of the potential of the inner electrode 7 with respect to the outer electrode 8 can be changed.

[0088] In this modified example, the inner electrode 7, the outer electrode 8, and the insulator 9 are preferably circular or cylindrical, and they are preferably arranged concentrically. However, the shapes of the inner electrode 7, the outer electrode 8, and the insulator 9, as well as the shape of the first multi-electrode 10 formed by them, are not limited to circular plates or cylindrical shapes.

[0089] Next, an explanation Figure 7 as well as Figure 8The etching apparatus 600 shown depicts a process of etching a wafer 4 on which a SiO2-containing film has been pre-formed on its upper surface. In this modified example of the etching apparatus 600, the conditions for processing the wafer 4 are the same as in... Figures 1-6 The conditions used in the etching apparatus 100, which is a semiconductor manufacturing apparatus, are the same as those in the embodiment shown.

[0090] In the etching apparatus 600 of this modified example, a mixed gas containing vapors of HF and alcohol X is provided in the processing chamber 30. With the wafer 4 disposed on the upper surface of the first multi-electrode 10 within the processing chamber 30 and held there, a voltage V is applied to the inner electrode 7 from a DC voltage source 6, which serves as a bipolar power supply. DC =+200V or -200V, and perform etching on the SiO2 film on the upper surface of wafer 4. The results of the etching rate measured at 13 points on a 300mm wafer at this time are explained.

[0091] Furthermore, in this variant example, such as Figure 8 As shown, the radius of the inner circular electrode 7, viewed from above the center of the first multi-electrode 10, is set to r1 = 100 mm, the radius of the outer periphery of the annular insulator 9 is set to r2 = 150 mm, and the radius up to the outer periphery of the outer electrode 8 is set to r3 = 200 mm.

[0092] The voltage V applied to the inner electrode 7 is set to... DC At +200V, the etching rate of the SiO2 film at the center of the wafer 4, which is supported on the upper surface of the first multi-electrode 10 and held therein, is approximately 80 nm / min, while at the outer periphery (edge) of the wafer 4, the etching rate is approximately 65 nm / min. On the other hand, when V is set to... DC At -200V, the etching rate is approximately 50 nm / min at the center of wafer 4 and approximately 55 nm / min at the edge. Similar to the above embodiment, the etching rate of the SiO2 film on the upper surface of wafer 4 can be further increased or suppressed by further increasing the bias voltage provided to the first multi-electrode 10.

[0093] Figure 9 It is a schematic representation of the use Figure 7 The diagram illustrates the variation of the etching rate of the SiO2 film on the upper surface of a wafer, processed by an etching apparatus as part of a semiconductor manufacturing apparatus, relative to the radial direction of the wafer, in the modified example shown. Figure 9 In the diagram, the position of the center of the wafer 4 is represented as O, and the positions of the outer periphery of the inner electrode 7, the insulator 9, and the outer electrode 8 in the radial direction are represented as r2, r2′, and rG, respectively.

[0094] The bias voltage provided to the inner electrode 7 is V. DC When >0, HF2 is located in the liquid phase layer containing particles of mixed gas on the SiO2 film on the inner electrode 7, within the range of -r2 < r < +r2 in the radial direction shown by the horizontal axis. - The amount of segregation increases. Therefore, the etching rate is related to V. DC The value of ≤0 is relatively larger compared to the case where the value is larger. On the other hand, on the surface of the SiO2 film above the outer electrode 8, which is set to ground potential and positioned radially at r2′<r<rG、-rG<r<-r2′, the etching rate is smaller than that on the inner electrode 7 because the bias voltage is DC = 0. As a result, Figure 9 As shown in the graph with the solid line in the middle, the etch rate distribution of the SiO2 film on wafer 4 is a so-called mountain-shaped distribution with the horizontal axis O as the center of wafer 4, which is large and small at the periphery.

[0095] On the other hand, the bias voltage is V DC The etch rate distribution when <0 is as follows Figure 9 As shown in the diagram with a dotted line, similar to the V mentioned above. DC Conversely, when the value is greater than 0, a valley-shaped rate distribution is shown, indicating a lower etching rate at the center compared to the etching rate on the SiO2 film on the outer electrode 8. Accordingly, according to this modified example, by variably adjusting the value and polarity of the voltage applied to the inner electrode 7 with multiple values ​​between positive and negative, the etching rate can be achieved in a free shape between a mountain-shaped and a valley-shaped configuration. Furthermore, when the radius of the wafer 4 is larger than the radius of the inner electrode 7, the distribution, including the magnitude of the etching rate and the ratio of the rate value relative to the center, can be effectively adjusted, particularly at the outer periphery (edge) of the wafer 4.

[0096] <Variation Example 2>

[0097] use Figure 10 as well as Figure 11 Let's illustrate a variation of this embodiment, Example 2. Figure 10 This is a schematic longitudinal cross-sectional view illustrating the structure of the etching apparatus in this modified example. Figure 11 It indicates composition Figure 10 A top view of the sample stage of the etching apparatus shown. Figure 10 as well as Figure 11 As shown, in the etching apparatus 800 of this modified example, the sample stage holding the wafer 4 on its upper surface has three or more conductive components, i.e., electrodes, arranged concentrically with respect to the radial direction of its cylindrical shape. In this respect, it is similar to... Figure 1 as well as Figure 7 The etching apparatus shown is different. In the following description, for those marked with [specific markings], the [specific markings] will be different. Figures 1-6 The structures of the same reference numerals as those in the embodiments described herein are omitted unless necessary.

[0098] The etching apparatus 800 in this variation and Figure 1 The etching apparatus 100 shown or Figure 7 The etching apparatus 600 shown also includes a vacuum container 1, a gas inlet 2, an infrared lamp assembly 3, and an exhaust port 31 disposed on the bottom surface of the vacuum container 1. Furthermore, in this modified example, instead of... Figure 7 The first multi-electrode 10 includes a second multi-electrode 14. The second multi-electrode 14 includes a central electrode 11, which is electrically insulated from each other by a plurality of annular insulators 9. Furthermore, the second multi-electrode 14 includes a first intermediate electrode 12 and a second intermediate electrode 13, both concentrically arranged around the central axis of the central electrode 11 and having annular shapes, respectively. Additionally, the second multi-electrode 14 includes an outer electrode 8, which is annularly arranged surrounding the first intermediate electrode 12 and the second intermediate electrode 13 and electrically grounded.

[0099] The center electrode 11, the first intermediate electrode 12, and the second intermediate electrode 13 are electrically connected to different DC voltage sources 15, 16, and 17, respectively. Specifically, the center electrode 11 is connected to a terminal of DC voltage source 15, the first intermediate electrode 12 is connected to a terminal of DC voltage source 16, and the second intermediate electrode 13 is connected to a terminal of DC voltage source 17. Independently regulated voltages are applied to the center electrode 11, the first intermediate electrode 12, and the second intermediate electrode 13 from DC voltage sources 15, 16, and 17, respectively. Figure 10 The second multi-electrode 14 shown has four electrodes that are mutually insulated and concentrically arranged in multiple configurations. However, the number of electrodes is not limited to this modification; it can be composed of any number of electrodes, more than three, and the same function and effect as this modification can be obtained. In addition, these electrodes have a circular plate, cylindrical, or annular shape, but the shape of the electrodes is not limited to this modification.

[0100] Figure 12 It is a symbolic representation of use Figure 10 The diagram illustrates the variation of the etching rate of the SiO2 film on the upper surface of a wafer, processed by an etching apparatus as part of a semiconductor manufacturing device, relative to the radial direction of the wafer, in the modified example shown. Figure 12 In this context, the position r along the radial direction, shown as a variable on the horizontal axis, is characterized as follows. That is, in... Figure 12In this context, the radial positions r of the outer periphery of the center electrode 11, the first intermediate electrode 12, the second intermediate electrode 13 and the outer electrode 8 are respectively set as r4, r5, r6 and rG. The radial positions of the inner periphery (outer periphery of the insulator 9) of the first intermediate electrode 12, the second intermediate electrode 13 and the outer electrode 8, which have an annular shape when viewed from above, are respectively set as r4′, r5′ and r6′.

[0101] In this modified example, for example, V is applied to the center electrode 11, the first intermediate electrode 12, and the second intermediate electrode 13 from DC voltage sources 15, 16, and 17 respectively. DC =+V4、V DC =-V5 and V DC When the voltage is equal to +V6, the etchant HF2 in the liquid phase layer on the surface of the SiO2 film on wafer 4... - The amount of segregation increases or decreases according to the magnitude (potential difference) of the electric field formed by the applied bias voltage. Accordingly, compared to the case of the outer electrode 8 with voltage 0 (potential set to 0), a larger value is taken at positions where r is smaller than r4, a smaller value is taken at positions where r is r4′~r5, and a larger value is taken at positions where r is r5′~r6. Furthermore, the regions between these radially oriented positions r are above the insulator 9, and the voltage at these locations is substantially proportional to the dielectric constant of the material constituting the insulator 9 and the potential difference between the electrodes sandwiching the insulator 9. Therefore, in Figure 2 In this context, the segregation also increases or decreases linearly on both the positive and negative sides of the coordinate O that serves as the center, between r4 and r4′, between r5 and r5′, and between r6 and r6′.

[0102] Furthermore, when |V4| > |V6|, the HF2 at the center electrode 11 is higher than that at the location on the second intermediate electrode 13. - The segregation is greater, therefore the etching rate at the center of wafer 4 becomes greater. Thus, according to this modification, when the second multi-electrode 14 has multiple electrodes divided into radially spaced and insulated portions, the desired etching rate distribution within the plane of wafer 4 can be achieved by adjusting the voltage supplied to these electrodes and the potential formed by that voltage. However, if the number of electrodes is increased and the radially spaced portions occupied by these electrodes are excessively subdivided, it becomes difficult to achieve accurate negative ion HF2 emission. - The concentration distribution is such that the number of electrodes is appropriate to be at most a few dozen. By using this variation, even when there are differences in the etching rate distribution between the inner and outer peripheries of the wafer surface, uniformity within the wafer surface can be controlled.

[0103] <Variation Example 3>

[0104] Next, use Figure 13 To illustrate another variation of the present invention, see Example 3. Figure 13 This is a schematic longitudinal cross-sectional view illustrating the structure of the etching apparatus as a semiconductor manufacturing apparatus according to this variation. In this variation, the parts labeled with... Figures 1-12 The structures of the same reference numerals in the accompanying drawings as those in the illustrated embodiments and variations are omitted from description unless necessary.

[0105] Figure 13 In this modified example, the structural features of the etching apparatus 1000, which is a semiconductor manufacturing apparatus, are similar to those described above. Figure 1 The etching apparatus 100 of the embodiment shown Figure 7 The etching apparatus 600 shown in Modified Example 1 and Figure 10 The etching apparatus 800 of the modified example 2 shown differs in that it has a pair of parallel plate-type electrodes, on the upper surface of the sample stage for loading the wafer 4 of the electrode 5 or the first multiple electrode 10, the second multiple electrode 14, etc., in the processing chamber 30, with other electrode plates arranged opposite to and substantially parallel to the upper surface. That is, in this embodiment, the processing chamber 30 has an upper plate electrode 18 and a lower plate electrode 19, which have a circular or cylindrical shape, and are arranged at a position substantially consistent from above on their respective vertical central axes, with a given gap between the upper and lower surfaces, and the lower and upper surfaces are parallel or approximately considered to be parallel.

[0106] In this variation, these electrodes are configured to be electrically connected to different terminals of the DC voltage source 6 that are given other polarities, thereby creating a potential difference between the electrodes. Furthermore, in this variation, the upper and lower electrodes form a potential that requires a potential difference to be created between them; the potential or polarity used for this is not limited to the examples described above.

[0107] A lower plate electrode 19 and an upper plate electrode 18 on the lower plate electrode 19 are disposed within the processing chamber 30. The upper plate electrode 18 and the lower plate electrode 19 are located at the overlapping part when viewed from above.

[0108] A wafer 4 is disposed on the flat upper surface of the lower plate electrode 19. When the potential formed on the lower surface of the upper plate electrode 18 by the DC power supplied to it is higher than the potential on the upper surface of the lower plate electrode 19, the electric field formed between them becomes downward, attracting positively charged ions downward toward the upper surface of the wafer 4, thus promoting the etching of the SiO2 film formed on the surface of the wafer 4. Conversely, when the potential on the lower surface of the upper plate electrode 18 is lower than the potential on the upper surface of the lower plate electrode 19, the electric field becomes upward, suppressing the etching of the SiO2 film on the wafer 4. Thus, according to this modified example, by adjusting the potential or polarity formed by the power supplied to the group of parallel plate electrodes holding the wafer on one surface, or the magnitude of the potential difference between these parallel plate electrodes, the etching rate of the SiO2 film on the surface of the wafer 4 can be adjusted to a desired range.

[0109] The pairs of parallel plate-type electrodes arranged in the processing chamber 30 are not limited to Figure 13 Only one is shown. For example, multiple units can be arranged in the vertical or horizontal direction within a single processing chamber 30 inside the vacuum container 1. For example, as shown... Figure 14 As shown in the etching apparatus 1100, pairs of parallel plate-type electrodes are arranged inside the vacuum container 1 with gaps between them in the vertical direction, and it has: multiple pairs ( Figure 14 The upper plate electrode 18 and the lower plate electrode 19 (3 ​​in total); and the DC voltage source 6 electrically connected to them.

[0110] Figure 14 This is a longitudinal cross-sectional view schematically illustrating the structure of an etching apparatus as a semiconductor manufacturing apparatus according to Modified Example 3 of the present invention. Figure 14 In the illustrated variation, wafers 4 can be etched in a so-called batch process. In this batch process, multiple wafers 4 are placed in a processing chamber 30, and the SiO2 films on the upper surfaces of these multiple wafers 4 are etched in parallel while they are held on the upper surfaces of multiple lower plate electrodes 19. The power supplied from the DC voltage sources 6 connected to the parallel plate electrodes can be variably adjusted according to the different circuit patterns or SiO2 film specifications in the multiple wafers 4. As a result, different conditions such as the electric field formed during the processing of the wafers 4 or the bias potential formed on the lower plate electrodes 19 can be achieved, thereby realizing different etching rates for different wafers 4 in the batch process. Here, the optimal processed shape of each wafer 4 can also be obtained by using appropriate processing conditions.

[0111] The invention made by the inventors of the present invention has been specifically described above based on its implementation methods, but the present invention is not limited to the described implementation methods and various modifications can be made without departing from its spirit.

[0112] Industrial availability

[0113] This invention can be widely used in semiconductor manufacturing apparatus and methods for manufacturing semiconductor apparatus.

[0114] Explanation of reference numerals in the attached figures

[0115] 1. Vacuum container

[0116] 2 Gas Inlet Section

[0117] 3 Infrared lights

[0118] 4 chips

[0119] 5 electrodes

[0120] 6. DC voltage source.

Claims

1. A semiconductor manufacturing apparatus, characterized in that, have: Handling containers; An inlet is provided for introducing a processing gas containing vapors of hydrogen fluoride and alcohol into the processing chamber inside the processing container. A sample stage, which is disposed in the processing chamber, has a wafer of the object to be processed mounted on its upper surface; and An electrode, disposed inside the sample stage, is subjected to a DC power that forms an electric field on the first layer formed on the upper surface of the wafer by the processing gas when etching the first film formed on the upper surface of the wafer without using plasma. and The first control unit switches the value or polarity of the voltage output by the power source providing the DC power.

2. The semiconductor manufacturing apparatus according to claim 1, characterized in that, The first film comprises silicon oxide. The electric field is formed in the first layer of the liquid phase on the upper surface of the first membrane, which is formed by the vapors of the hydrogen fluoride and the alcohol constituting the gas for the process, by a direct current power supplied to the electrode.

3. The semiconductor manufacturing apparatus according to claim 1, characterized in that, The electrode comprises: a plurality of electrodes, including an inner electrode located in a region on the central side of the sample stage when viewed from above; and an outer electrode surrounding the inner electrode on its outer periphery. One of the plurality of electrodes is connected to a ground electrode and is set to a ground potential.

4. The semiconductor manufacturing apparatus according to claim 1, characterized in that, The semiconductor manufacturing apparatus includes: The second control unit causes the magnitude or polarity of the voltage of the DC power supplied to the electrodes to vary according to the passage of time during the processing of the wafer.

5. A method for manufacturing a semiconductor device, comprising: placing a wafer of a processing target on the upper surface of a sample stage in a processing chamber disposed inside a processing container; providing a processing gas containing vapors of hydrogen fluoride and an alcohol to the processing chamber; and etching a first film pre-formed on the upper surface of the wafer without using plasma; the method for manufacturing the semiconductor device is characterized in that... In the etching process, a DC power is applied to the electrodes disposed inside the sample stage, and the voltage value or polarity of the DC power applied to the electrodes is switched to form an electric field in the first layer on the upper surface of the wafer by the gas used in the process.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, A first film comprising the processed object of silicon oxide is formed on the upper surface of the wafer. In the etching process, the DC power is applied to the electrode, and an electric field is formed in the first layer of the liquid phase formed on the surface of the first film by the gas used in the process.

7. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The electrode comprises: a plurality of electrodes, including an inner electrode disposed in a region on the central side of the sample stage when viewed from above; and an outer electrode surrounding the inner electrode on its outer periphery. One of the plurality of electrodes is connected to a ground electrode and is set to a ground potential.

8. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The magnitude or polarity of the DC power supplied to the electrodes varies according to the passage of time during the processing of the wafer.

Images