Optical detector

Abstract

The solid-state image sensor (100) has at least two or more APDs (31) formed on a substrate (110). When viewed from above, a first region (32) is arranged outside the APDs (31). Adjacent APDs (31), adjacent first regions (32), and adjacent APDs (31) and first regions (32) are separated by a separation region (13). A first voltage (V21) is applied to the fourth semiconductor layer (21) of the APD (31), and a second voltage (V22) is applied to the fifth semiconductor layer (22) of the first region (32). The first voltage (V21) is higher than the second voltage (V22).

Description

Technical Field

[0001] The present disclosure relates to a photodetector, and more particularly to a photodetector such as a solid-state image sensor capable of detecting weak light. Background Art

[0002] In recent years, highly sensitive photodetectors have been used in various fields such as medical, communication, biotechnology, chemistry, monitoring, vehicle-mounted, and radiation detection. For example, in order to improve the sensitivity of solid-state image sensors such as CMOS (Complementary Metal Oxide Semiconductor) image sensors, a structure using an avalanche photodiode (hereinafter referred to as APD) has been proposed (for example, refer to Patent Document 1).

[0003] An APD is a photodiode that multiplies signal charges generated by photoelectric conversion using avalanche breakdown, thereby improving the detection sensitivity to light.

[0004] A solid-state image sensor has also been proposed that can generate an image with high resolution using minute incident light by arranging APDs in an array (for example, refer to Patent Document 2).

[0005] Patent Document 1: U.S. Patent No. 9,178,100 Specification

[0006] Patent Document 2: International Publication No. 2017 / 043068 Summary of the Invention

[0007] -Technical Problem to be Solved by the Invention-

[0008] In the structure disclosed in Patent Document 2, an APD is formed below a pixel circuit, and the APDs are connected by the same N-type semiconductor layer. Therefore, the current and charge at the pixel array terminal are affected by adjacent pixels, and this influence spreads to the inside of the pixel array. In particular, the end of the APD pixel array sometimes inadvertently becomes a high electric field. That is, at the end of the APD pixel array, it is necessary to improve the withstand voltage and reduce the leakage current by alleviating the electric field.

[0009] Therefore, the present disclosure provides a photodetector that can operate stably by alleviating the electric field concentration at the end of the pixel array section.

[0010] -Technical Solution for Solving the Technical Problem-

[0011] The photodetector according to one aspect of the present disclosure is a photodetector in which at least two or more avalanche photodiodes (APDs) are formed on a semiconductor substrate, and is characterized in that: when viewed from above, a first region is disposed outside the APDs, and adjacent APDs, adjacent first regions, and adjacent APDs and the first region are separated by a separation region; the APD is composed of a first semiconductor layer of a second conductivity type included in the semiconductor substrate and a fourth semiconductor layer of a first conductivity type in contact with the first semiconductor layer; the first region is composed of the first semiconductor layer and a fifth semiconductor layer of a first conductivity type in contact with the first semiconductor layer; a first voltage is applied to the fourth semiconductor layer of the APD, and a second voltage is applied to the fifth semiconductor layer of the first region, and the first voltage is higher than the second voltage.

[0012] - Effects of the Invention -

[0013] According to the present disclosure, a photodetector that can operate stably by alleviating the electric field concentration at the end of the pixel array unit is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a top view of a solid-state image sensor according to a first embodiment;

[0015] Figure 2 is a top view of a pixel array unit;

[0016] Figure 3 is along Figure 2 a schematic cross-sectional view taken along line III-III;

[0017] Figure 4 is along Figure 3 a potential distribution diagram along lines A-A and B-B;

[0018] Figure 5 is along Figure 3 a potential distribution diagram along line C-C;

[0019] Figure 6 is a schematic cross-sectional view of a pixel array unit according to Modification 1;

[0020] Figure 7 is along Figure 6 an impurity concentration distribution diagram along lines D-D and E-E;

[0021] Figure 8 is along Figure 6 a potential distribution diagram along lines D-D and E-E;

[0022] Figure 9It is a schematic cross-sectional view of the pixel array section related to Modification 2;

[0023] Figure 10 It is Figure 9 the impurity concentration distribution diagram along the F - F line and G - G line of;

[0024] Figure 11 It is a top view of the pixel array section related to the second embodiment;

[0025] Figure 12 It is a diagram showing the circuit structure of the solid-state image sensor related to the second embodiment;

[0026] Figure 13 It is an example of the driving timing diagram of the pixel circuit;

[0027] Figure 14 It is along Figure 11 the schematic cross-sectional view taken along the XIV - XIV line of;

[0028] Figure 15 It is the impurity concentration distribution diagram of each part of the pixel array section;

[0029] Figure 16A It is a top view of the pixel array section related to Modification 3;

[0030] Figure 16B It is a top view of another pixel array section related to Modification 3;

[0031] Figure 17 It is a top view of the pixel array section and the electric field relaxation region related to Modification 4;

[0032] Figure 18 It is along Figure 17 the schematic cross-sectional view taken along the XVIII - XVIII line of;

[0033] Figure 19 It is a top view of another pixel array section and the electric field relaxation region related to Modification 4;

[0034] Figure 20 It is along Figure 19 the schematic cross-sectional view taken along the XX - XX line of;

[0035] Figure 21 It is along Figure 19 the schematic cross-sectional view taken along the XXI - XXI line of;

[0036] Figure 22 It is a schematic diagram of the structure of the distance measurement system related to the third embodiment;

[0037] Figure 23 It is a schematic cross-sectional view of another pixel array section. Detailed Embodiments

[0038] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The following description of the preferred embodiments is illustrative only in nature and is not intended to limit the present disclosure, its application, or its use in any way.

[0039] (First Embodiment)

[0040] [Structure of Solid-State Image Sensor and Pixel Array Section]

[0041] Figure 1 is a top view showing the solid-state image sensor according to this embodiment, Figure 2 is a top view showing the pixel array section, Figure 3 is a schematic cross-sectional view taken along line III-III of Figure 2 . It should be noted that for ease of explanation, in Figures 1 to 3 , illustrations and descriptions of contact holes, interlayer insulating layers, and wirings inside the solid-state image sensor 100 are omitted. In Figure 2 , the number of APDs 31 included in the pixel array section 120 is different from the actual number. At least two or more APDs 31 are sufficient.

[0042] It should be noted that in the following description, the thickness direction of the semiconductor substrate 110 (hereinafter simply referred to as the substrate 110) is sometimes referred to as the Z direction, and the two directions orthogonal to each other in the plane perpendicular to the Z direction are respectively referred to as the X direction and the Y direction. "Top view" means observing from the Z direction. In the Z direction, the second main surface S2 side on which the back electrode 40 (refer to Figure 3 ) is arranged is sometimes referred to as the lower side or the bottom, and the opposite side, i.e., the first main surface S1 side, is referred to as the upper side or the top.

[0043] As Figure 1 shows, the solid-state image sensor 100 includes a pixel array section 120, a first peripheral circuit section 130, and a second peripheral circuit section 140, which are respectively formed on the first main surface S1 of the substrate 110 (refer to Figure 3 ). It should be noted that the solid-state image sensor 100 is an example of a light detector.

[0044] The first peripheral circuit section 130 includes a readout circuit 131 (refer to Figure 12 ) for reading out signals from each pixel of the pixel array section 120 (refer to Figure 12 ), a horizontal scanning circuit 132 (refer to Figure 12 ), a buffer amplifier 133 (refer to Figure 12 ), etc. The second peripheral circuit section 140 includes a vertical scanning circuit 141 (refer to Figure 12 ), etc.

[0045] As Figure 2 shown, the pixel array unit 120 is composed of an APD array 30 and a first region 32 disposed outside the APD array 30. The APD array 30 is composed of a plurality of APDs 31 arranged in an array. The plurality of APDs 31 are arranged in a matrix along the X direction and the Y direction, respectively.

[0046] Specifically, as Figure 2 shown, the first region 32 is arranged so as to surround the outside of the APD array 30. When the pixel array unit 120 includes a plurality of APD arrays 30, the first region 32 is also arranged outside each APD array 30. Separation regions 13 are respectively formed between adjacent APDs 31, between adjacent first regions 32, and between adjacent APDs 31 and the first region 32. As described below, the APD 31 constitutes the light detection unit 201 of the pixel (see Figure 12 ). On the other hand, the first region 32 is provided to enable the APD 31 to operate with high photon detection efficiency, and it itself may not contribute to light detection.

[0047] In the present specification, avalanche multiplication includes both linear multiplication and Geiger multiplication. In particular, in the case of the Geiger multiplication mode, a quenching element (not shown) for stopping Geiger multiplication may also be provided. In this case, a resistor, a capacitor, a transistor, or the like can be used as the quenching element, and the type of the element is not limited. It should be noted that the linear multiplication mode in the present specification refers to "the operating mode of an APD in which the reverse bias voltage applied to the APD is below the avalanche breakdown voltage and charge multiplication is caused by impact ionization". The Geiger multiplication mode refers to "the operating mode of an APD in which a reverse bias voltage above the avalanche breakdown voltage is at least temporarily applied to the APD to make it operate".

[0048] In particular, the structure according to the present disclosure can be used for components such as an MPPC (Multi-Pixel Photon Counter) or an SPAD (Single Photon Avalanche Diode).

[0049] In the present embodiment, it is preferable that the APD 31 operates in the Geiger multiplication mode and the first region 32 operates in the linear multiplication mode, but it is not limited to this operating mode. That is, the APD 31 can operate in the linear multiplication mode, or the first region 32 can operate in the Geiger multiplication mode.

[0050] In particular, when the first region 32 operates in Geiger multiplication mode, a resistor (not shown) is preferably connected in series with the first region 32 to limit the amount of current flowing through the first region 32. The resistance value at this time is, for example, 100 Ω or more. However, the first region 32 does not necessarily have to be quenched, and a steady current may also flow through it.

[0051] The quenching elements of the APD 31 and the first region 32 may also use different types of elements. For example, it also includes structures such as the APD 31 being connected to a transistor and the first region 32 being connected to a resistor.

[0052] As Figure 3 shown, the substrate 110 is composed of a first semiconductor layer 10 and a second semiconductor layer 11. The first semiconductor layer 10 is a p-type single-crystal silicon substrate, at least a part of which can be formed by epitaxial growth method, and the second semiconductor layer 11 is a p-type epitaxial layer formed on the upper surface of the first semiconductor layer 10. The p-type impurity concentration of the second semiconductor layer 11 is set to be lower than the p-type impurity concentration of the first semiconductor layer 10.

[0053] It should be noted that in the specification of this application, as the conductivity type of each semiconductor layer, the n-type is sometimes referred to as the "first conductivity type" and the p-type is referred to as the "second conductivity type". However, it should be noted that in some exactly opposite cases, for example, there is a case where the n-type is referred to as the "second conductivity type". In the specification of this application, the impurity concentration refers to the effective impurity concentration. In the case where there are two different conductivity type impurities in the same region, the impurity concentration refers to the difference between the two.

[0054] The APD 31 is mainly composed of a first semiconductor layer 10 and a fourth semiconductor layer 21. The fourth semiconductor layer 21 is an n-type semiconductor layer, which is formed by introducing n-type impurities from the first main surface S1 into the interior of the substrate 110 by ion implantation or the like using a resist mask pattern (not shown). An avalanche multiplication region 33 is formed at and near the junction interface between the first semiconductor layer 10 and the fourth semiconductor layer 21.

[0055] It should be noted that in Figure 3 , the first semiconductor layer 10 becomes a semiconductor substrate or an integrated structure in which the semiconductor substrate and the p-type epitaxial layer become one body. However, the solid-state image sensor 100 of this embodiment is not limited to forming an avalanche multiplication region between the first semiconductor layer 10 and the semiconductor substrate. As shown in Figure 23 illustrated later, both the n-type region and the p-type region for forming the avalanche multiplication region can also be formed by implantation. The solid-state image sensor 100 of this embodiment is not limited to the PN junction structure of the APD 31, and the present invention can also be used for general structures such as the through type and the PIN type. In particular, Figure 3The first semiconductor layer 10 is denoted as a region, but there may also be spatial concentration variations. For example, in a PIN type, the P-type concentration is high on the side of the second main surface S2, and the concentration is low on the side of the first main surface S1. The end of the avalanche multiplication region 33 of the APD 31 located on the side of the second main surface S2 may also extend to the vicinity of the first main surface S1.

[0056] Regarding Figure 3 For example, assume a structure in which the p-type impurity concentration of the first semiconductor layer 10 is the same or gradually increases from the side of the first main surface S1 toward the side of the second main surface S2, and assume that the width of the avalanche multiplication region 33 of the APD 31 in the thickness direction of the substrate is relatively short, 2 μm or less. By adopting this structure, the breakdown voltage can be reduced. The absolute value of the breakdown voltage is usually 50 V or less. Since the width of the separation region 13 can be reduced to about the width of the avalanche multiplication region, there is an effect of being able to reduce the separation width and achieve miniaturization.

[0057] The first region 32 is mainly composed of the first semiconductor layer 10 and the fifth semiconductor layer 22. The fifth semiconductor layer 22 is an n-type semiconductor layer, which is formed by the same method as the method for forming the fourth semiconductor layer 21. An avalanche multiplication region 34 is formed at and near the bonding interface between the first semiconductor layer 10 and the fifth semiconductor layer 22. In the present embodiment, an example in which the fourth semiconductor layer 21 and the fifth semiconductor layer 22 are formed simultaneously in the manufacturing process of the solid-state image sensor 100 is shown. Therefore, the n-type impurity concentration of the fourth semiconductor layer 21 and the n-type impurity concentration of the fifth semiconductor layer 22 may be the same, but they do not necessarily have to be formed in the same process, so they may also have different concentrations.

[0058] It should be noted that in the present application specification, "the same" or "equal" means that the comparison objects are the same or equal to each other including deviations in the manufacturing process, etc., and does not mean that the comparison objects are the same or equal to each other in a strict sense.

[0059] The separation region 13 is composed of the third semiconductor layer 12. The third semiconductor layer 12 is a p-type semiconductor layer, which is formed by introducing p-type impurities from the first main surface S1 into the interior of the substrate 110 by ion implantation or the like using a resist mask pattern (not shown).

[0060] In the present embodiment, the p-type impurity concentration of the first semiconductor layer 10 is 1×10 16 cm -3 ~1×10 18 cm -3 or so, and the p-type impurity concentration of the second semiconductor layer 11 is 1×10 14 cm -3 ~1×10 17 cm-3 or so, the p-type impurity concentration of the third semiconductor layer 12 is 1×10 15 cm -3 ~1×10 18 cm -3 or so.

[0061] The p-type impurity concentration of the second semiconductor layer 11 is set to be lower than the p-type impurity concentration of the first semiconductor layer 10.

[0062] The n-type impurity concentrations of the fourth semiconductor layer 21 and the fifth semiconductor layer 22 are 5×10 16 cm -3 ~1×10 19 cm -3 or so. However, the impurity concentrations of the first semiconductor layer to the fifth semiconductor layer 10 to 12, 21, 22 can be appropriately changed according to the specifications of the solid-state image sensor 100, the performance required for the APD 31, the performance required for the first region 32, and the like.

[0063] The back electrode 40 is formed on the second main surface S2 of the substrate 110 and is applied with a prescribed voltage, which is a voltage Vrev of a prescribed magnitude in the present embodiment. The second main surface S2 faces the first main surface S1 in the Z direction. It should be noted that the voltage Vrev is a negative voltage. The value of the voltage Vrev can be variable, adjustable, or a fixed value. The back electrode 40 preferably uses a metal having ohmic contact with the first semiconductor layer 10.

[0064] The separation region 13 is depleted. Specifically, the separation region 13 is depleted from the junction interface between the separation region 13 and the fourth semiconductor layer 21 or the junction interface between the separation region 13 and the fifth semiconductor layer 22 to a region at a prescribed distance. It should be noted that this distance depends on the p-type impurity concentration of the separation region 13 and the n-type impurity concentration of the fourth semiconductor layer 21 or the fifth semiconductor layer 22, and changes according to the above-mentioned impurity concentrations.

[0065] Since the separation region 13 is depleted, and a separation barrier (refer to Figure 5), so that electrical separation is achieved between adjacent APDs 31. In other words, the signals of each APD 31 can be output separately without mixing the signals of each APD 31. In particular, by depleting the separation region 13, the lateral electric field between the APD 31 and the separation region 13 can be alleviated, the separation region 13 can be reduced, and the pixel can be miniaturized. It is not necessary to apply a fixed voltage to the separation region 13 from the first main surface S1 side or to form an insulating separation region such as a Shallow Trench Isolation (STI) structure for electrically separating between the respective APDs 31. Therefore, it is not necessary to arrange contact holes for electrical connection thereto in the separation region 13, nor is it necessary to form trenches extending from the surface of the separation region 13, that is, the first main surface S1, toward the inside of the substrate 110.

[0066] It should be noted that it is not necessary for the entire separation region 13 to be depleted. For example, the intersection portion (refer to Figure 2 ) between the separation region 13 extending in the X direction and the separation region 13 extending in the Y direction may not be depleted at the center.

[0067] A reverse bias voltage is applied to the APD 31 and the first region 32 via wirings and contact holes (not shown). Specifically, in the APD 31, a voltage V21 (first voltage V21) is applied to the fourth semiconductor layer 21, and in the first region 32, a voltage V22 (second voltage V22) is applied to the fifth semiconductor layer 22. The wiring for applying the voltage V21 is a different wiring from the wiring for applying the voltage V22, and these wirings are electrically separated from each other.

[0068] Figure 4 Shows the potential distributions along the Figure 3 A - A line and B - B line of Figure 5 Shows the potential distribution along the Figure 3 C - C line of Figure 4 In Figure 4 The potential distributions shown are distributions in the Z direction, in other words, distributions in the depth direction starting from the first main surface S1 of the substrate 110, Figure 5 The potential distributions shown are distributions in the X direction, in other words, distributions in a direction parallel to the first main surface S1 of the substrate 110.

[0069] In Figure 4 、 Figure 5 And the potential distributions shown later, the numbers in the figure correspond to Figure 2 、 Figure 3 The APD 31, the first region 32, the avalanche multiplication regions 33, 34, and the separation region 13 shown in

[0070] As Figure 4 shown, in the APD 31 and the first region 32, the potential distribution in the Z direction is different. Specifically, the slope of the potential across the PN junction boundary of the APD 31 is greater than the slope of the potential across the PN junction boundary of the first region 32. This is because the first reverse bias voltage V1 applied to the PN junction of the APD 31 is set to be higher than the second reverse bias voltage V2 applied to the PN junction of the first region 32. Here, the first reverse bias voltage V1 and the second reverse bias voltage V2 are represented by the following equations (1) and (2).

[0071] |V1| = V21 + |Vrev|...(1)

[0072] |V2| = V22 + |Vrev|...(2)

[0073] It should be noted that the first reverse bias voltage V1 and the second reverse bias voltage V2 are zero or positive voltages.

[0074] Since the slope of the potential is equivalent to the electric field strength, it can be said that the electric field applied to the avalanche multiplication region 33 of the APD 31 is higher than the electric field applied to the avalanche multiplication region 34 of the first region 32.

[0075] Since the n-type impurity concentrations of the fourth semiconductor layer 21 and the fifth semiconductor layer 22 are the same, when the first reverse bias voltage V1 and the second reverse bias voltage V2 are the same value, in the APD 31 and the first region 32, the p-type depletion layer ends extending to the first semiconductor layer 10 and the second semiconductor layer 11 are as Figure 3 shown by the dashed line LP2 in, located at positions at the same distance from the PN junction boundary. On the other hand, when the first reverse bias voltage V1 is higher than the second reverse bias voltage V2, the p-type depletion layer ends are as shown by the dashed line LP1, and are located at positions farther from the PN junction boundary around the first region 32 than around the APD 31. That is, the depletion layer extending to the first semiconductor layer 10 is wider around the first region 32 than around the APD 31.

[0076] As Figure 5 shown, the separation barrier is equivalent to the potential difference between the potential of the separation region 13 and the potential of the APD 31. Since a separation barrier is formed in the separation region 13, the signal charges accumulated in the fourth semiconductor layer 21 of the APD 31 can be prevented from flowing into the adjacent APD 31 and the first region 32 across the separation region 13. In this way, for example, color mixing between pixels can be prevented.

[0077] The separation barrier is determined by the impurity distribution in the separation region 13, the impurity distributions of the fourth semiconductor layer 21 and the fifth semiconductor layer 22 disposed around the separation region 13, and the voltage conditions applied to the pixel array unit 120. For example, the separation barrier also varies according to the voltage Vrev applied to the back electrode 40, the value of the first reverse bias V1, and the value of the second reverse bias V2. It should be noted that it is preferable that the width and p-type impurity concentration of the separation region 13 surrounding one APD 31 are constant.

[0078] Since the width and p-type impurity concentration of the separation region 13 are determined based on the constraint relationship between the height of the separation barrier and the electric field inside the separation region 13, in the separation region 13 surrounding one APD 31, when the width and p-type impurity concentration of the separation region 13 are made constant, it is easy to maintain the electrical characteristics of the APD 31. The first region 32 functions to keep the same separation characteristics between the APD 31 adjacent to the first region 32 and the APD 31 adjacent only to the APD 31.

[0079] As Figure 5 shown, the difference between the first reverse bias V1 and the second reverse bias V2 is set to be smaller than the potential difference between the potential of the separation region 13 and the potential of the first region 32.

[0080] [Optical detection operation of the solid-state image sensor]

[0081] The light incident from the first main surface S1 is absorbed by the first semiconductor layer 10 of the APD 31 to cause photoelectric conversion, generating carriers, namely electron-hole pairs. The electrons among the generated carriers drift toward the first main surface S1 side along the potential gradient and reach the avalanche multiplication region 33. On the other hand, the holes among the generated carriers are not multiplied but are discharged to the back electrode 40.

[0082] Here, when the absolute value of the voltage Vrev applied to the back electrode 40 is set to be larger than the absolute value of the breakdown voltage of the APD 31, the electrons flowing into the avalanche multiplication region 33 will generate avalanche multiplication through impact ionization. In this way, multiple signal electrons can be generated, and even weak light that is usually buried in noise and cannot be detected can be detected. That is, the photon detection efficiency of the solid-state image sensor 100 can be greatly improved.

[0083] On the other hand, it is preferable to set the voltage Vrev to a level that ensures that the first region 32 is not broken down, so that the first region 32 does not perform optical detection.

[0084] It should be noted that in this application specification, the breakdown voltage refers to the voltage at which the carrier multiplication rate in the avalanche multiplication region increases sharply when the voltage applied to the APD 31 is changed.

[0085] [Effect, etc.]

[0086] As described above, in the solid-state image sensor (light detector) 100 according to the present embodiment, at least two or more APDs 31 are formed on the substrate 110, and adjacent APDs 31 are separated by the separation region 13.

[0087] The first region 32 is arranged outside the APD array 30 composed of a plurality of APDs 31.

[0088] The APD urchased by the substrate 110 includes a p-type first semiconductor layer 10 and an n-type fourth semiconductor layer 21 in contact with the first semiconductor layer 10. An avalanche multiplication region 33 is formed near the interface between the first semiconductor layer 10 and the fourth semiconductor layer 21.

[0089] The first region 32 is composed of the first semiconductor layer 10 and an n-type fifth semiconductor layer 22 in contact with the first semiconductor layer 10. An avalanche multiplication region 34 is formed near the interface between the first semiconductor layer 10 and the fifth semiconductor layer 22.

[0090] In the solid-state image sensor 100, the electric field applied to the avalanche multiplication region 33 of the APD 31, that is, the PN junction of the APD 31, is higher than the electric field applied to the avalanche multiplication region 34 of the first region 32, that is, the PN junction of the first region 32.

[0091] By providing the separation region 13 between adjacent APDs 31, each APD 31 can operate independently. Mixing of colors between pixels can also be prevented.

[0092] By making the electric field applied to the PN junction of the APD 31 higher than the electric field applied to the PN junction of the first region 32, electric field concentration can be alleviated at the peripheral portion of the pixel array unit 120 (hereinafter referred to as the end portion of the pixel array unit 120), thereby realizing a stable light detection operation, that is, realizing the stable operation of the APD 31. This will be further described.

[0093] First, consider the case where the pixel array unit 120 is composed of a plurality of APDs 31 and the separation region 13 provided between the plurality of APDs 31. In this case, a high electric field may exist at the end portion of the pixel array unit 120.

[0094] The inventors found that in a structure where the separation region 13 is depleted, one APD31 affects the electric potential of adjacent APD31s, reducing the lateral electric field at the end of the APD31, thereby enabling the reduction of electric field concentration. However, in the pixels located at the end of the pixel array section 120, since there is no APD31 adjacent to one end, the lateral electric field at this end of the APD31 cannot be reduced, and there is a tendency for the electric field to be higher than the internal electric field of the pixel array section 120. In addition, at the end of the pixel array section 120, the bottom of the n-type semiconductor layer of the APD31 is angular, so there is a tendency for the electric field to be higher than the internal electric field of the pixel array section 120 (see Figure 3 ). These problems do not occur in a structure such as that in Patent Document 1 where the separation region is not depleted.

[0095] The formation process of the fourth semiconductor layer 21 sometimes causes the electric field at the end of the pixel array section 120 to become higher. As described above, the fourth semiconductor layer 21 is formed by introducing n-type impurities into the interior of the substrate 110 by means of ion implantation or the like. The resist mask pattern used at this time is a pattern in which a plurality of opening patterns corresponding to the outer shape of the APD31 are arranged in an array. In such an array pattern, compared with the internal opening patterns, the shape of the opening patterns in the peripheral part is likely to be distorted, which is well known in the manufacturing process of semiconductor devices. For example, when the opening pattern in the peripheral part is conical, the n-type impurities may sometimes be formed wider or narrower than the mask opening pattern at the peripheral part of the APD31.

[0096] When this occurs, at the end of the pixel array section 120, the depletion layer width becomes narrower, or the internal electric field of the PN junction becomes higher. As a result, the electric field at the end of the pixel array section 120 becomes higher.

[0097] When the electric field at the end of the pixel array section 120 becomes higher, it is impossible to sufficiently increase the electric field applied to the avalanche multiplication region 33 inside the pixel array section 120, making it difficult for avalanche multiplication to occur, and the photon detection efficiency of the APD31 may decrease.

[0098] To solve the above problems, for example, it is considered to reduce the impurity concentration of the fourth semiconductor layer 21 in the APD31 located at the end of the pixel array section 120, thereby reducing the electric field in this part. However, in this case, in the separation region around the APD31 located at the end of the pixel array section 120, it may be impossible to ensure the separation barrier due to the expanded depletion layer.

[0099] On the other hand, according to the present embodiment, by disposing a first region 32 where the electric field applied to the PN junction is lower than that of the APD 31 outside the APD 31, it is possible to suppress the electric field concentration at the end of the pixel array unit 120 without reducing the area of the avalanche multiplication region 33 of the APD 31. In this way, it is possible to suppress the reduction of the photon detection efficiency of the APD 31, and thus it is possible to realize the stable operation of the APD 31 and even the solid-state image sensor 100.

[0100] The separation region 13 is depleted at least from the surface in contact with the APD 31, that is, from the bonding interface between the fourth semiconductor layer 21 and the fifth semiconductor layer 22 to a region at a predetermined distance.

[0101] The separation region 13 is depleted in this way and forms a separation barrier as described above, whereby electrical separation between adjacent APDs 31 can be achieved. By performing electrical separation between the APDs 31 in the depleted separation region 13, it is possible to reduce the pixel arrangement pitch in the pixel array unit 120, and thus it is possible to achieve high integration of the pixel array unit 120.

[0102] No contact hole connected to the separation region 13 is disposed in the separation region 13, and no trench extending from the surface of the separation region 13 toward the inside is formed.

[0103] Since the separation region 13 is depleted and a separation barrier is formed, there is no need to form such a contact hole or trench, and since no contact hole or trench is provided, there is no need to widen the width of the separation region 13. In this way, it is possible to further reduce the pixel arrangement pitch in the pixel array unit 120, and thus it is possible to further achieve high integration of the pixel array unit 120.

[0104] The first reverse bias voltage V1 applied to the APD 31 is higher than the second reverse bias voltage V2 applied to the first region 32.

[0105] By adopting this method, even if the impurity concentration distribution of the APD 31 is the same as that of the first region 32, it is possible to make the electric field in the avalanche multiplication region 33 of the APD 31 higher than the electric field in the avalanche multiplication region 34 of the first region 32, so as to achieve the above effects. It is also possible to form the fourth semiconductor layer 21 of the APD 31 and the fifth semiconductor layer 22 of the first region 32 simultaneously, thereby suppressing an increase in the manufacturing cost of the solid-state image sensor 100. Since the voltages applied to the APD 31 and the first region 32 from the back electrode 40 can be the same, there is no need to increase the power supply for driving the solid-state image sensor 100, and the structure of the back electrode 40 can be simplified. In this way, an increase in the manufacturing cost of the solid-state image sensor 100 can also be suppressed.

[0106] It should be noted that, as described below, in order to multiply the hole avalanche generated by photoelectric conversion into signal charge, the polarities of the first reverse bias voltage V1 and the second reverse bias voltage V2 must be reversed. Therefore, taking this into consideration, the aforementioned effect can be achieved by making the absolute value of the first reverse bias voltage V1 applied to the APD 31 greater than the absolute value of the second reverse bias voltage V2 applied to the first region 32.

[0107] The difference between the first reverse bias voltage V1 and the second reverse bias voltage V2 is set to be smaller than the potential difference between the separation region 13 and the first region 32 .

[0108] As described above, by making the second reverse bias voltage V2 applied to the first region 32 lower than the first reverse bias voltage V1 applied to the APD 31 , the electric field applied to the avalanche multiplication region 34 of the first region 32 can be reduced.

[0109] However, the relationship between the first reverse bias voltage V1 and the second reverse bias voltage V2 is limited by the electrical isolation characteristics between the APDs 31. Figure 5 It can be seen that when the difference between the first reverse bias voltage V1 and the second reverse bias voltage V2 is approximately equal to the separation barrier, it becomes difficult to achieve electrical separation between the APD 31 and the first region 32. Therefore, by setting the relationship between the first reverse bias voltage V1 and the second reverse bias voltage V2 as described above, electrical separation between the APD 31 can be ensured, and the electric field applied to the avalanche multiplication region 34 of the first region 32 can be reduced.

[0110] It should be noted that, as described above, the first region 32 does not contribute to light detection. When the solid-state image sensor 100 performs light detection, the multiplication rate of the first region 32 is lower than the multiplication rate of the APD 31 , and in particular, avalanche breakdown may not occur.

[0111] That is, the first region 32 can also be said to have a PN junction structure composed of the p-type first semiconductor layer 10 and the n-type fifth semiconductor layer 22 in contact with the first semiconductor layer 10 .

[0112] Therefore, the solid-state image sensor (photodetector) 100 according to this embodiment can be said to have the following structure. The solid-state image sensor 100 includes at least one APD 31 and at least one PN junction structure 32 formed on a substrate 110. Adjacent APDs 31 and adjacent APDs 31 and PN junction structures 32 are separated by isolation regions 13. When viewed from above, the PN junction structures 32 are arranged outside the APDs 31.

[0113] The APD31 is composed of a p-type first semiconductor layer 10 included in a substrate 110 and an n-type fourth semiconductor layer 21 in contact with the first semiconductor layer 10. An avalanche multiplication region 33 is formed near the interface between the first semiconductor layer 10 and the fourth semiconductor layer 21.

[0114] The PN junction structure 32 is composed of the first semiconductor layer 10 and an n-type fifth semiconductor layer 22 in contact with the first semiconductor layer 10. A PN junction region 34 is formed near the interface between the first semiconductor layer 10 and the fifth semiconductor layer 22.

[0115] In the solid-state image sensor 100, the electric field applied to the PN junction of the APD31 is higher than the electric field applied to the PN junction of the PN junction structure 32. In other words, a voltage V21 (first voltage V21) is applied to the fourth semiconductor layer 21 of the APD31, a voltage V22 (second voltage V22) is applied to the fifth semiconductor layer 22 of the first region 32, and a voltage Vrev is applied to the first semiconductor layer 10. It can be seen from Equation (1) and Equation (2) that the voltage V21 is higher than the voltage V22.

[0116] It should be noted that the method of making the electric field applied to the PN junction of the APD31 higher than the electric field applied to the PN junction of the first region 32 or higher than the electric field applied to the PN junction of the PN junction structure 32 is not limited to the method shown in this embodiment, and other methods can be appropriately adopted. In Modification Example 1 and Modification Example 2 shown below, specific methods will be described.

[0117] <Modification Example 1>

[0118] Figure 6 It is a schematic cross-sectional view showing a pixel array unit according to this modification example. Figure 7 Shows Figure 6 The impurity concentration distributions along the D - D line and the E - E line, Figure 8 Shows Figure 6 The potential distributions along the D - D line and the E - E line. It should be noted that, Figure 6 Is equivalent to Figure 3 The figure.

[0119] It should be noted that in Figure 7 , the impurity concentration distributions along the D - D line and the impurity concentration distributions along the E - E line are shown together, and in Figure 8 , the potential distributions along the D - D line and the potential distributions along the E - E line are shown together. Figure 7 The impurity concentration distributions shown in Figure 8 The potential distributions shown in are respectively distributions in the depth direction starting from the first main surface S1 of the substrate 110.

[0120] In Figure 7In the impurity concentration distributions shown later, the numbers in the figures correspond to the symbols of the respective semiconductor layers in the solid-state image sensor 100. For example, in Figure 7 the impurity concentration distribution indicated by the solid line is labeled with the number 21, which means that this distribution is the impurity concentration distribution of the fourth semiconductor layer 21.

[0121] In Figures 6 to 8 each of the drawings shown later, the same symbols are assigned to the same parts as in the first embodiment, and detailed descriptions thereof are omitted.

[0122] As Figure 6 , Figure 7 shown, the difference between the solid-state image sensor 100 shown in this modified example and the solid-state image sensor 100 shown in the first embodiment is that the impurity concentration of the fifth semiconductor layer 22a in the first region 32 is lower than the impurity concentration of the fourth semiconductor layer 21 of the APD 31.

[0123] By adopting this method, the depletion layer extends more toward the first semiconductor layer 10 around the first region 32 than around the APD 31. As a result, as Figure 8 shown, it is possible to make the electric field applied to the avalanche multiplication region 33 of the APD 31 higher than the electric field applied to the avalanche multiplication region 34 of the first region 32. In this way, the same effect as that of the structure shown in the first embodiment can be achieved. That is, the electric field concentration at the end of the pixel array unit 120 can be alleviated, thereby realizing the stable operation of the APD 31 and even the solid-state image sensor 100. Since the first reverse bias voltage V1 and the second reverse bias voltage V2 can have the same value, the number of power supplies can be reduced, and thus an increase in the cost of the solid-state image sensor 100 can be suppressed.

[0124] It should be noted that in this modified example, in order to make the electric field applied to the PN junction of the APD 31 higher than the electric field applied to the PN junction of the first region 32, the impurity concentration of the fifth semiconductor layer 22a is made lower than the impurity concentration of the fourth semiconductor layer 21. However, for example, the impurity concentration of the first semiconductor layer 10 around the first region 32 can also be made lower than the impurity concentration of the first semiconductor layer 10 around the APD 31. In this way, of course, the same effect as that of the structure shown in this modified example can be achieved.

[0125] Not limited thereto, by appropriately adjusting the impurity concentrations of the fourth semiconductor layer 21 and the fifth semiconductor layer 22a, and the first semiconductor layer 10 around the APD 31 and the first semiconductor layer 10 around the first region 32, respectively, the absolute value of the breakdown voltage of the first region 32 can be made greater than the absolute value of the breakdown voltage of the APD 31. In this way, the electric field applied to the PN junction of the APD 31 can also be made higher than the electric field applied to the PN junction of the first region 32. The electric field concentration at the end of the pixel array section 120 can be alleviated, thereby realizing the stable operation of the APD 31 and even the solid-state image sensor 100.

[0126] <Modification Example 2>

[0127] Figure 9 It is a cross-sectional schematic view of the pixel array section according to this modification example. Figure 10 Shows the impurity concentration distributions along Figure 9 the F-F line and the G-G line. It should be noted that Figure 9 is a diagram corresponding to Figure 3 the equivalent.

[0128] It should be noted that in Figure 10 both the impurity concentration distribution along the F-F line and the impurity concentration distribution along the G-G line are shown. Figure 10 The shown impurity concentration distribution is the distribution in the depth direction starting from the first main surface S1 of the substrate 110.

[0129] As Figure 9 shown, the difference between the solid-state image sensor 100 shown in this modification example and the solid-state image sensor 100 shown in the first embodiment is that a sixth semiconductor layer 23 is formed at a portion below the fifth semiconductor layer 22 of the first region 32 and connected to the fifth semiconductor layer 22.

[0130] As Figure 9 shown, the sixth semiconductor layer 23 is a carrier compensation layer in which n-type impurities of the same degree as p-type impurities are introduced into the first semiconductor layer 10. Therefore, in the sixth semiconductor layer 23, the effective p-type impurity concentration is reduced, and the PN junction boundary of the first region 32 is located at a position deeper inside the substrate 110 than the PN junction boundary of the APD 31. As described above, the fifth semiconductor layer 22 and the sixth semiconductor layer 23 are continuous, so in Figure 10 the n-type impurity concentration distributions of the fifth semiconductor layer 22 and the sixth semiconductor layer 23 are shown as a single curve. The range of the sixth semiconductor layer 23 is given on the horizontal axis.

[0131] By positioning the PN junction boundary of the first region 32 deeper inside the substrate 110 than the PN junction boundary of the APD 31, it is possible to suppress variations in the separation characteristics of the separation region 13 and to make the electric field applied to the PN junction of the APD 31 higher than the electric field applied to the PN junction of the first region 32. This will be further explained.

[0132] As described above, when forming the fourth semiconductor layer 21 and the fifth semiconductor layer 22, a resist mask pattern (not shown) is used. On the other hand, as shown in Modification 1, when the impurity concentrations of the fourth semiconductor layer 21 and the fifth semiconductor layer 22 are different, the resist mask patterns for introducing n-type impurities into the APD 31 and the first region 32 are mostly formed separately.

[0133] In this case, due to the influence of mask misalignment in the photolithography process for forming the resist mask pattern, etc., the effective impurity concentration of the separation region 13 in contact with the fourth semiconductor layer 21 and the fifth semiconductor layer 22 accidentally changes, and the separation region 13 becomes a high electric field, making it possible to not obtain the desired separation characteristics.

[0134] In this modification, the resist mask pattern for forming the fourth semiconductor layer 21 and the fifth semiconductor layer 22 and the resist mask pattern for forming the sixth semiconductor layer 23 are also formed separately.

[0135] However, according to this modification, the concentration of the n-type impurity introduced to form the sixth semiconductor layer 23 is lower than the n-type impurity concentrations of the fourth semiconductor layer 21 and the fifth semiconductor layer 22, and is introduced to a position deeper than the separation region 13. In this way, the influence on the electric field and separation barrier in the separation region 13 can be reduced, thereby suppressing variations in the separation characteristics of the separation region 13. Similar to the cases shown in the first embodiment and Modification 1, the electric field concentration at the end of the pixel array unit 120 can be alleviated, thereby realizing the stable operation of the APD 31 and even the solid-state image sensor 100.

[0136] In the solid-state image sensor 100 shown in this modification and Modification 1, the absolute value of the breakdown voltage of the first region 32 is greater than the absolute value of the breakdown voltage of the APD 31. Furthermore, the difference between the absolute value of the breakdown voltage of the first region 32 and the absolute value of the breakdown voltage of the APD 31 is set to be greater than the difference between the first reverse bias V1 and the absolute value of the breakdown voltage of the APD 31, i.e., the remaining bias voltage.

[0137] By making the absolute value of the voltage Vrev applied to the back electrode 40 greater than the absolute value of the breakdown voltage of the APD 31, as described above, electrons among the carriers after photoelectric conversion will generate avalanche multiplication in the APD 31.

[0138] On the other hand, in the first region 32, it is preferable that avalanche breakdown does not occur during the light detection operation. When avalanche breakdown occurs in the first region 32, even if its output signal is not utilized, a large current will flow in the first region 32, resulting in an unexpected increase in the power consumption of the solid-state image sensor 100. Since the first region 32 generates heat, it affects the characteristics of the APD 31 and the separation characteristics of the separation region 13, leading to a reduction in the performance of the solid-state image sensor 100.

[0139] On the other hand, by specifying the difference between the absolute value of the breakdown voltage of the first region 32 and the absolute value of the breakdown voltage of the APD 31 as described above, it is possible to ensure that avalanche breakdown does not occur in the first region 32 when the solid-state image sensor 100 performs the light detection operation. In this way, heat generation and an unnecessary increase in power consumption can be suppressed, enabling the solid-state image sensor 100 to operate stably.

[0140] (Second Embodiment)

[0141] [Planar Structure of Pixel Array Section]

[0142] Figure 11 is a top view of the pixel array unit according to the present embodiment.

[0143] The solid-state image sensor 100 shown in the present embodiment is different from the solid-state image sensor 100 shown in the first embodiment in that the pixel array section 120 includes a pixel circuit region 150.

[0144] As Figure 11 shown, the pixel circuit region 150 is provided corresponding to each APD 31. The APD 31 and the pixel circuit region 150 are alternately arranged along the Y direction, and the first region 32 is arranged outside them. Separation regions 13 are respectively formed between adjacent APD 31 and the pixel circuit region 150, between adjacent first regions 32 and the pixel circuit region 150, and between adjacent APD 31 and the first region 32. Separation regions 13 are also respectively formed between adjacent APD 31 and between adjacent first regions 32. By providing the separation regions 13, adjacent APD 31 and adjacent pixel circuit regions 150 are electrically separated, which is the same as the case shown in the first embodiment.

[0145] As described below, pixel circuits are formed inside the pixel circuit region 150 (see Figure 14 ). In Figure 11 the example shown, a pixel circuit region 150 is provided for each APD 31, but one pixel circuit region 150 may also be provided corresponding to multiple APD 31. The specific structure of the pixel circuit region 150 will be described below.

[0146] [Circuit Structure and Operation of Solid-State Imaging Device]

[0147] Figure 12 The circuit structure of the solid-state image sensor according to this embodiment is shown, Figure 13 and an example of the driving timing chart of the pixel circuit is shown.

[0148] As Figure 12 shown, the solid-state image sensor 100 has a readout circuit 131, a horizontal scanning circuit 132, a buffer amplifier 133, and a vertical scanning circuit 141 on the periphery of the pixel array section 120. The readout circuit 131, the horizontal scanning circuit 132, and the buffer amplifier 133 correspond to Figure 1 the first peripheral circuit section 130 shown, and the vertical scanning circuit 141 corresponds to the second peripheral circuit section 140.

[0149] In the pixel array section 120, a light detection section 201, a transfer transistor 202, a reset transistor 203, a source follower transistor 204, a selection transistor 205, and a floating diffusion capacitor 206 are provided for each pixel.

[0150] The light detection section 201 corresponds to Figure 2 the APD 31 shown. The transfer transistor 202, the reset transistor 203, the source follower transistor 204, the selection transistor 205, and the floating diffusion capacitor 206 correspond to the pixel circuit, and they are formed in Figure 11 the pixel circuit region 150 shown. It should be noted that Figure 12 the pixel circuit shown is merely an example, and other structures can be appropriately adopted according to the specifications of the solid-state image sensor 100, etc.

[0151] The transfer transistor 202 transfers the charge output from the light detection section 201 to the floating diffusion capacitor 206, and the floating diffusion capacitor 206 accumulates the charge. The reset transistor 203 restores the potential of the floating diffusion capacitor 206 to a specified potential. The potential of the floating diffusion capacitor 206 corresponding to the accumulated charge amount is input to the gate of the source follower transistor 204, and the source follower transistor 204 outputs an amplified signal. The selection transistor 205 transfers the amplified signal output from the source follower transistor 204 to the vertical signal line 208 connected to the readout circuit 131.

[0152] Next, the operation of the solid-state image sensor 100 will also be described with reference to Figure 13 .

[0153] During the reset period ( Figure 13During the period I) shown, signals are respectively input from the vertical scanning circuit 141 to the gates of the reset transistor 203 and the transfer transistor 202, and the reset transistor 203 and the transfer transistor 202 respectively become conductive states.

[0154] The drain of the reset transistor 203 is connected to the horizontal signal line 207 connected to the vertical scanning circuit 141. When the reset transistor 203 becomes conductive, the potential of the floating diffusion capacitor 206 is reset to the drain potential of the reset transistor 203. Since the transfer transistor 202 connected to the floating diffusion capacitor 206 is also in a conductive state, the photodetection unit 201 is also reset to the drain potential of the reset transistor 203.

[0155] Next, the reset transistor 203 and the transfer transistor 202 are respectively made non-conductive, and a signal is input from the vertical scanning circuit 141 to the gate of the selection transistor 205 to make the selection transistor 205 conductive. The potential of the floating diffusion region just after reset is transmitted to the readout circuit 131 via the source follower transistor 204, the selection transistor 205, and the vertical signal line 208, and is stored as a first signal in a memory (not shown) or the like. The memory or the like is mostly provided in the readout circuit 131 (clamping period: Figure 13 the period II) shown.

[0156] After the reset period ends, when light is incident on the photodetection unit 201, electrons generated by photoelectric conversion undergo avalanche multiplication and are accumulated in the photodetection unit 201. Specifically, they are accumulated in Figure 3 the fourth semiconductor layer 21 shown. The period during which electrons are accumulated after light is incident on the photodetection unit 201 is the exposure time, which is equivalent to Figure 13 the sum of the period II and the period III shown.

[0157] After the exposure period ends, the transfer transistor 202 is made conductive again to transfer the electrons accumulated in the photodetection unit 201 to the floating diffusion capacitor 206 (transfer period: Figure 13 the period IV) shown.

[0158] Next, the transfer transistor 202 is made non-conductive, and the selection transistor 205 is made conductive to transmit the potential of the floating diffusion region in the state where electrons are accumulated as a second signal to the readout circuit 131 via the source follower transistor 204, the selection transistor 205, and the vertical signal line 208. The difference between the second signal and the first signal obtained during the clamping period is taken to generate a pixel signal (readout period: Figure 13 the period V) shown.

[0159] Note that most pixel signals are generated within the readout circuit 131. In this case, the pixel signals are delivered by the horizontal scanning circuit 132 to the buffer amplifier 133 and further output to the outside of the solid-state image sensor 100. However, the generation of pixel signals can also be performed outside the solid-state image sensor 100.

[0160] By taking the difference between the first signal and the second signal, noise components such as kTC noise can be removed from the pixel signal, thereby obtaining a high-quality signal.

[0161] In particular, when the APD 31 operates in Geiger multiplication mode, the reset transistor 203 is turned on during period I to apply the voltage V21 to the APD 31, and the reset transistor 203 is turned off during exposure periods II and III to disconnect the power supply from the APD 31. In this way, the APD 31 becomes a floating state, and the charges generated by avalanche multiplication are accumulated in the capacitor connected to the cathode of the APD 31, thereby relaxing the reverse bias applied to the multiplication region of the APD 31 and stopping the avalanche multiplication. That is to say, the APD 31 of the present disclosure is at least temporarily connected only to the capacitor during optical detection, and the connected capacitor becomes the quenching element of the APD 31. The capacitor here includes PN junction capacitors, wiring capacitors, edge capacitors of series transistors, etc. in the multiplication region and separation region 13 of the APD 31. It is also possible to adopt the following structure: connect a quenching resistor (not shown) to the first region 32, quench the APD 31 with a capacitor, and quench the first region 32 with a resistor. The quenching resistor here includes wiring resistors, contact resistors, polysilicon resistors, etc.

[0162] In Figure 11 a structure is shown in which the readout circuit 131 is provided on the same substrate as the APD 31 and the first region 32, but the readout circuit 131 can also be provided on another semiconductor substrate and wafer-bonded. In this case, the substrate voltage of the semiconductor substrate on which the readout circuit 131 is provided can also be different from the substrate voltage Vrev of the semiconductor substrate on which the APD 31 and the first region 32 are provided. In this case, the reverse bias applied to the well of the readout circuit 131 is reduced, thereby reducing the current.

[0163] [Cross-sectional structure of pixel array section]

[0164] Figure 14 is a schematic cross-sectional view taken along line XIV-XIV of Figure 11 and shows the impurity concentration distribution of each part of the pixel array section. Figure 15 The impurity concentration distribution shown is the distribution in the Z direction. In Figure 15 Figure 15 ​In this figure, the impurity concentration distributions of the APD 31, the first region 32, and the pixel circuit region 150 are shown together.

[0165] In Figure 14 the pixel array section 120 shown, the APD 31 and the first region 32 have the same structure as that shown in Modification 1, and their respective impurity concentration distributions are also the same as those Figure 7 shown. Therefore, the absolute value of the breakdown voltage of the first region 32 is greater than the absolute value of the breakdown voltage of the APD 31.

[0166] On the other hand, in the pixel circuit region 150, an N-well 26 is formed as a circuit well. A p-type ninth semiconductor layer 15 is formed inside the N-well 26, and on the ninth semiconductor layer 15, Figure 12 the transfer transistor 202 shown is formed. The transfer transistor 202 is an N-channel transistor, and the ninth semiconductor layer 15 functions as its P-well. It should be noted that the reset transistor 203, the source follower transistor 204, the selection transistor 205, and the floating diffusion capacitor 206 are also respectively formed in the pixel circuit region 150 and are not shown.

[0167] The N-well 26 is composed of an n-type seventh semiconductor layer 24 and an n-type eighth semiconductor layer 25 in contact with the seventh semiconductor layer 24. The n-type impurity concentration of the eighth semiconductor layer 25 is set to be lower than the n-type impurity concentration of the seventh semiconductor layer 24. From Figure 14 and Figure 15 it can be seen that, with the first main surface S1 as a reference, the depth of the fifth semiconductor layer 22 is set to be the same as the depth of the seventh semiconductor layer 24. The n-type impurity concentration of the fifth semiconductor layer 22 is set to be the same as the n-type impurity concentration of the seventh semiconductor layer 24. A well voltage V23 is applied to the N-well 26.

[0168] In the solid-state image sensor 100 shown in this embodiment, by providing the eighth semiconductor layer 25 in the N-well 26, the p-type depletion layer end LP3 becomes wider below the N-well 26 (see Figure 14 ). The potential gradient in the Z direction from the eighth semiconductor layer 25 to the first semiconductor layer 10 is smaller than the potential gradient in the Z direction from the fourth semiconductor layer 21 of the APD 31 to the first semiconductor layer 10. Therefore, the absolute value of the breakdown voltage between the N-well 26 and the first semiconductor layer 10 is greater than the absolute value of the breakdown voltage of the APD 31.

[0169] By adopting this method, it is possible to suppress breakdown between the N-well 26 and the first semiconductor layer 10 during the light detection operation. It is possible to suppress punchthrough between the ninth semiconductor layer 15, the N-well 26, and the first semiconductor layer 10.

[0170] In the pixel circuit, in order for each transistor to operate, the well voltage V23 applied to the N-well 26 needs to be around the driving power supply voltage of the transistor. Regardless of the magnitude of the voltage Vrev applied to the back electrode 40, each transistor needs to operate.

[0171] Therefore, when the above-mentioned breakdown and punch-through occur, the pixel circuit cannot operate properly, and thus light detection cannot be performed.

[0172] On the other hand, according to the present embodiment, by making the N-well 26 have the above structure, the above-mentioned breakdown and punch-through can be suppressed from occurring, so that the pixel circuit can operate properly and the light detection operation can be stably performed.

[0173] It should be noted that in addition to Figure 14 the structure shown, it is also possible to make the absolute value of the breakdown voltage between the N-well 26 and the first semiconductor layer 10 greater than the absolute value of the breakdown voltage of the APD 31. For example, the N-well 26 can be formed only by the seventh semiconductor layer 24. In this case, the depth of the seventh semiconductor layer 24 can also reach Figure 14 the lower surface of the eighth semiconductor layer 25 shown. By adopting this method, the distance between the lower surface of the N-well 26 and the isolation region 13 can be ensured, and thus the influence of the N-well 26 on the electrical characteristics of the isolation region 13 can be reduced. It should be noted that this also applies to Figure 14 the structure shown.

[0174] In this case, it is preferable that the depth of the N-well 26 is the same as the depth of the fifth semiconductor layer 22 in the first region 32. That is, preferably in the Z direction, the PN junction boundary between the seventh semiconductor layer 24 forming the N-well 26 and the first semiconductor layer 10, and the PN junction boundary between the fifth semiconductor layer 22 and the first semiconductor layer 10 are located at the same position. It is preferable that the n-type impurity concentration of the seventh semiconductor layer 24 is the same as the n-type impurity concentration of the fifth semiconductor layer 22.

[0175] By adopting this method, the absolute value of the breakdown voltage between the N-well 26 and the first semiconductor layer 10 can be made greater than the absolute value of the breakdown voltage of the APD 31. In this way, breakdown in the first region 32 and the N-well 26 can be suppressed, and punch-through in the pixel circuit region 150 can be suppressed.

[0176] Since the fifth semiconductor layer 22 and the N-well 26 can be formed simultaneously in the manufacturing process of the solid-state image sensor 100, an increase in the manufacturing cost of the solid-state image sensor 100 can be suppressed. This also applies to Figure 14 the structure shown.

[0177] <Modification Example 3>

[0178] Figure 16AIt is a top view of the pixel array section according to this modification example. Figure 16B It is a top view of another pixel array section.

[0179] Figure 16A and Figure 16B The difference between the pixel array section 120 shown in and the pixel array sections 120 shown in the first embodiment and the second embodiment is that: the first regions 32 are integrated and are arranged in a frame shape so as to surround the APD 31 when viewed from above. Figure 16B The difference between the pixel array section 120 shown in and the pixel array section 120 shown in the second embodiment is that: the pixel circuit region 150 is arranged to be shared by two adjacent APDs 31.

[0180] When the same voltage is applied to the plurality of first regions 32 respectively, the separation region 13 may not be provided between the first regions 32. Therefore, as Figure 16A and Figure 16B shown, the first regions 32 may also be integrally formed.

[0181] When it is also possible to make the well voltage V23 applied to the N well 26 the same between pixels in the pixel circuit region 150, there is no need to provide the separation region 13 between the pixel circuit regions 150 of adjacent pixels, and the pixel circuit regions 150 can be integrated. By adopting this method, the effective occupation area ratio of the pixel circuit region 150 can be reduced within the pixel array section 120, and thus the occupation area ratio of the APD 31 can be increased. In this way, the photon detection efficiency of the solid-state image sensor 100 can be improved.

[0182] It should be noted that in Figure 16A and Figure 16B , an example in which the frame-shaped first region 32 surrounds the peripheries of four APDs 31 is shown, but it is not particularly limited thereto. For example, it may also be that one APD 31 is surrounded by the frame-shaped first region 32.

[0183] Of course, the structures shown in the first embodiment, Modification Example 1, and Modification Example 2 can be applied as the structures of the APD 31 and the first region 32.

[0184] <Modification Example 4>

[0185] Figure 17 It is a top view of the pixel array section and the electric field relaxation region according to this modification example. Figure 18 is along Figure 17 The schematic cross-sectional view taken along line XVIII - XVIII.

[0186] The solid-state image sensor 100 shown in this modified example is different from the solid-state image sensors 100 shown in the first and second embodiments in that an electric field relaxation region 50 is provided outside the pixel array section 120, and the first region 32 is composed of a frame-shaped region 32a, a dummy APD 32b, and a dummy pixel circuit region 32c. Therefore, by providing these components, as described above, the APD 31 and the pixel circuit can operate stably.

[0187] It should be noted that, in Figure 17 the example shown, considering the periodicity of the patterns in the pixel array section 120, the first region 32 having different planar patterns is formed. For example, a frame-shaped region 32a is provided in the outer peripheral portion of the pixel array section 120. A dummy pixel circuit region 32c extending in the X direction is provided between the dummy APD 32b and the APD 31 adjacent to it in the Y direction and closer to the inside than it.

[0188] As Figure 18 shown, in the frame-shaped region 32a located at the outermost periphery of the pixel array section 120, an n-type tenth semiconductor layer 27 is provided between the fifth semiconductor layer 22 and the first semiconductor layer 10.

[0189] The tenth semiconductor layer 27 is formed simultaneously with the eighth semiconductor layer 25 of the N well 26. That is, the n-type impurity concentration of the tenth semiconductor layer 27 is the same as the n-type impurity concentration of the eighth semiconductor layer 25. In this case, the n-type impurity concentration of the tenth semiconductor layer 27 is set to be lower than the n-type impurity concentration of the fifth semiconductor layer 22. The tenth semiconductor layer 27 extends in a protruding manner toward the outside of the pixel array section 120, in other words, toward the side opposite to the adjacent APD 31, near the bonding surface with the first semiconductor layer 10.

[0190] In the photolithography process of the N well 26 for forming the pixel circuit region 150, a resist mask pattern (not shown) is formed. On the other hand, as Figure 17 shown, since the pixel circuit region 150 is a pattern that extends elongately in the X direction, the above-mentioned resist mask pattern is also an opening pattern that extends elongately in the X direction, and stress is applied in the X direction during pattern formation, and the shape may be unstable. As shown in this modified example, since the frame-shaped region 32a is provided near the X-direction end of the resist mask pattern of the N well 26 for forming the pixel circuit region 150, the stress in the X direction applied to this resist mask pattern is relaxed, thereby suppressing pattern distortion. In this way, the area and depth of the N well 26 are stable, the characteristic deviation of the circuits in the pixel circuit region 150 can be suppressed, and the performance of the solid-state image sensor 100 can be stabilized.

[0191] By providing the tenth semiconductor layer 27 in the frame-shaped region 32a located at the outermost periphery of the pixel array section 120, it is possible to further alleviate the electric field concentration at the ends of the pixel array section 120. In the tenth semiconductor layer 27, the corners surrounded by the dashed circles are the parts where electric field concentration is likely to occur. However, by reducing the n-type impurity concentration of the tenth semiconductor layer 27, it is possible to further alleviate the electric field concentration at these parts. Since the tenth semiconductor layer 27 is located deeper inside the substrate 110 than the fifth semiconductor layer 22, the influence of the electric field concentration at the above-mentioned corners is difficult to be transmitted to the separation region 13 and the electric field alleviation region 50. In this way, the separation characteristics between the APDs 31 and the effect of alleviating the electric field concentration at the ends of the pixel array section 120 are maintained.

[0192] Same as Figure 2 the first region 32 shown, when viewed from above, the size of the dummy APD 32b is the same as that of the APD 31, and the impurity distribution is also the same as that of the APD 31. However, the dummy APD 32b does not contribute to light detection. As Figure 17 shown, by providing a plurality of dummy APDs 32b between the frame-shaped region 32a and the APD 31, it is possible to maintain the periodicity of the plurality of APDs 31 arranged in an array. In this way, the stress on the resist mask pattern applied to the fourth semiconductor layer 21 for forming the APD 31 located at the outermost periphery of the APD array 30 is alleviated, so that pattern distortion can be suppressed. In this way, the area and depth of the fourth semiconductor layer 21 are stable, the characteristic deviation of the APD 31 can be suppressed, and thus the performance of the solid-state image sensor 100 can be stabilized.

[0193] The dummy pixel circuit region 32c is composed of an n-type seventh semiconductor layer 24 and a p-type ninth semiconductor layer 15a formed inside thereof. However, a transistor may not be formed in the dummy pixel circuit region 32c. The impurity concentration of the ninth semiconductor layer 15a is lower than that of the ninth semiconductor layer 15 and is the same as the impurity concentration of the second semiconductor layer 11. As Figure 17 shown, by providing the dummy pixel circuit region 32c between the dummy APD 32b and the APD 31 adjacent to it along the Y direction and inside it, it is possible to maintain the periodicity of the plurality of pixel circuit regions 150 arranged alternately with the APD 31 along the Y direction. In this way, the stress in the Y direction applied to the resist mask pattern of the N well 26 for forming the pixel circuit region 150 is alleviated, so that pattern distortion can be suppressed. In this way, the area and depth of the N well 26 are stable, the characteristic deviation of the circuits in the pixel circuit region 150 can be suppressed, and thus the performance of the solid-state image sensor 100 can be stabilized.

[0194] However, the arrangement of the first region 32 does not always need to adopt Figure 17The layout shown can be appropriately changed within the range that can ensure the planar shape of the APD 31, the planar shape of the pixel circuit region 150, and the stability of the APD 31 and the pixel circuit. For example, the shape of the frame-shaped region 32a can be changed to an array shape, or the dummy pixel circuit region 32c having the same pattern as the pixel circuit region 150 can be omitted.

[0195] It should be noted that, of course, a reverse bias can also be applied to the frame-shaped region 32a, the plurality of dummy APDs 32b, and the dummy pixel circuit region 32c through wirings or contact holes (not shown).

[0196] As Figure 17 , Figure 18 As shown, an electric field relaxation region 50 is provided outside the pixel array unit 120 so as to surround the pixel array unit 120. The electric field relaxation region 50 is composed of a second semiconductor layer 11, and STI 51 is formed on most of its surface, that is, on the side of the first main surface S1. The STI 51 is an insulating structure formed by forming a groove inside the substrate 110 from the first main surface S1 and burying an insulator such as a silicon oxide film therein.

[0197] As described above, by providing the electric field relaxation region 50, the width of the depletion layer (not shown) extending outside the frame-shaped region 32a can be further expanded. Since the p-type impurity concentration of the second semiconductor layer 11 is lower than the p-type impurity concentration of the first semiconductor layer 10, the depletion layer easily expands along the X direction and the Y direction.

[0198] In this way, compared with the cases shown in the first embodiment and the second embodiment, the electric field concentration at the end of the pixel array unit 120 can be alleviated, and thus the stability of the light detection operation of the APD 31 and even the solid-state image sensor 100 can be further improved.

[0199] It should be noted that no silicide is formed on the surface of the electric field relaxation region 50. In the first peripheral circuit unit 130 and the second peripheral circuit unit 140, in order to improve the performance of the transistor, a method widely used is to form a silicide on the surfaces of the gate, source, and drain of the transistor. For this purpose, a general self-aligned silicide technology can be used. It should be noted that a silicide is a compound of silicon and a metal, and its resistivity is lower than that of silicon.

[0200] On the other hand, when a silicide is formed on the surface of the electric field relaxation region 50, carrier generation and recombination are likely to occur on the surface, the leakage current flowing into the first region 32 increases, and unnecessary power consumption increase and heat generation in the solid-state image sensor 100 will be caused. To prevent this from happening, no silicide is formed on the surface of the electric field relaxation region 50. For the same reason, it is preferable to cover the surface of the electric field relaxation region 50 with the STI 51. In this way, it is also possible to suppress the increase in the leakage current flowing into the first region 32, thereby suppressing the increase in heat generation and power consumption.

[0201] As Figure 17 shown, it is preferable to provide a p-type eleventh semiconductor layer 14 outside the electric field relaxation region 50. In this way, it is possible to prevent the depletion layer extending to the electric field relaxation region 50 from reaching the first peripheral circuit portion 130 and the second peripheral circuit portion 140 and affecting their respective internal circuits.

[0202] Figure 19 is a top view of another pixel array portion and an electric field relaxation region according to this modification example, Figure 20 is along Figure 19 XX-XX line of the sectional schematic view taken, Figure 21 is along Figure 19 XXI-XXI line of the sectional schematic view taken.

[0203] As Figure 19 shown, on the inner peripheral side of the frame-shaped region 32a surrounding the pixel array portion 120, there is the above-mentioned dummy pixel circuit region 32c. The n-type tenth semiconductor layer 27 is formed integrally in such a manner as to be in contact with the lower surfaces of the n-type seventh semiconductor layer 24 provided in the dummy pixel circuit region 32c and the fifth semiconductor layer 22 of the frame-shaped region 32a, respectively.

[0204] By integrally forming the tenth semiconductor layer 27 so as to straddle the seventh semiconductor layer 24 and the fifth semiconductor layer 22, the shape of the resist mask pattern (not shown) for forming the tenth semiconductor layer 27 can be stabilized. When the tenth semiconductor layer 27 is separated below the seventh semiconductor layer 24 provided in the dummy pixel circuit region 32c and below the fifth semiconductor layer 22, it is necessary to form the resist mask pattern in a long line shape, so pattern distortion is likely to occur. To prevent this, as described above, the n-type tenth semiconductor layer 27 is integrally formed.

[0205] As Figure 21 shown, on the outer peripheral side of the pixel circuit region 150, specifically at the end in the X direction, when viewed from above, the end of the eighth semiconductor layer 25 is located at a position more inward than the end of the seventh semiconductor layer 24.

[0206] Different voltages are applied to the pixel circuit region 150 and the frame-shaped region 32a outside thereof, respectively. On the other hand, since the resist mask pattern (not shown) for forming the eighth semiconductor layer 25 is an opening pattern with a relatively large area, shape distortion is likely to occur.

[0207] Therefore, as Figure 21 shown, on the first main surface S1 side, a separation region 13 is formed between the pixel circuit region 150 and the frame-shaped region 32a. On the other hand, by positioning the end portion of the eighth semiconductor layer 25 at a position more inward than the end portion of the seventh semiconductor layer 24, a separation barrier in the separation region 13 can be stably formed, so that the separation characteristics between the pixel circuit region 150 and the first region 32 including the frame-shaped region 32a can be set to a desired value.

[0208] It should be noted that, in this modification example, an example in which multiple columns of dummy APDs 32b are arranged in the Y direction is shown. However, depending on the arrangement of the APDs 31 and the pixel circuit region 150 within the pixel array unit 120, multiple columns of dummy APDs 32b can be arranged in the X direction outside the pixel array unit 120.

[0209] (Third Embodiment)

[0210] Figure 22 is a structural schematic diagram of the distance measurement system according to this embodiment. The distance measurement system 1000 includes a light emitting unit 1100, a light receiving unit 1200, a control unit 1300, and an output unit 1400.

[0211] The light emitting unit 1100 is composed of a light emitting device such as a light emitting diode, generates pulsed light according to a control signal from the control unit 1300, and irradiates the measurement object.

[0212] The light receiving unit 1200 is the solid-state image sensor 100 disclosed in this application specification, and receives the pulsed light reflected by the measurement object by the light receiving unit 1200.

[0213] The control unit 1300 is composed of a CPU (Central Processing Unit), etc., and controls the light emitting unit 1100 and the light receiving unit 1200 to work synchronously. The control unit 1300 measures the time from when the pulsed light is reflected by the measurement object and returns to the light receiving unit 1200 based on the control signal for the light emitting unit 1100 and the output signal from the light receiving unit 1200, and thereby calculates the distance to the measurement object.

[0214] The output unit 1400 outputs the distance to the measurement object calculated by the control unit 1300 in the form of numerical data or an image. The output unit 1400 is usually composed of a display, such as a liquid crystal display or an organic EL display.

[0215] The distance measurement system 1000 shown in this embodiment is a so-called TOF (Time Of Flite) distance measurement system.

[0216] According to this embodiment, by using the solid-state image sensor 100 including the APD 31, detection can be performed even in the case of weak reflected light. Since the conduction time of the transfer transistor 202 can be arbitrarily set, false detection of the distance due to background light can be prevented, and the distance to the measurement object can be obtained with high precision.

[0217] (Other embodiments)

[0218] It is also possible to appropriately combine the respective constituent elements shown in the respective embodiments and the respective modification examples to form a new embodiment. For example, the tenth semiconductor layer 27 shown in the modification example 4 may be provided in the first region 32 shown in the first embodiment, the second embodiment, or the modification examples 1 to 3.

[0219] The structure of the solid-state image sensor 100, particularly the structure of the pixel array portion 120, is not limited to the above structure, and other structures can be appropriately adopted. For example, as Figure 23 shown, a p-type twelfth semiconductor layer 16 may be provided in contact with the fourth semiconductor layer 21 and the fifth semiconductor layer 22 below the fourth semiconductor layer 21 of the APD 31 and below the fifth semiconductor layer 22 of the first region 32. The twelfth semiconductor layer 16 is formed by introducing p-type impurities into the inside of the substrate 110 by ion implantation or the like using a resist mask pattern (not shown).

[0220] By making the pixel array portion 120 have the Figure 23 shown structure, the breakdown voltage of the APD 31 can be reduced. It should be noted that the impurity concentration of the twelfth semiconductor layer 16 below the fifth semiconductor layer 22 in the first region 32 may be lower than the impurity concentration of the twelfth semiconductor layer 16 below the fourth semiconductor layer 21 of the APD 31. In this way, the absolute value of the breakdown voltage of the first region 32 can be increased. In Figure 23 , a diagram is drawn showing that the depletion layer end is located at the lower part of the twelfth semiconductor layer 16, but it may also be a so-called punch-through type APD in which the depletion layer end extends to the second main surface S2 side.

[0221] It should be noted that holes generated by photoelectric conversion may also be subjected to avalanche multiplication as signal charges. In this case, the conductivity types of the respective semiconductor layers shown in the respective embodiments and the respective modification examples, such as the first semiconductor layer to the twelfth semiconductor layers 10 to 12, 14 to 16, 21 to 25, 26, 27, are of course appropriately changed.

[0222] In the description of the present application, the case where light is incident from the first main surface S1 of the substrate 110 has been described as an example. However, light may also be incident from the second main surface S2 of the substrate 110. In this case, the back electrode 40 uses a transparent electrode such as indium tin oxide (ITO), for example. Of course, the polarities of the voltage applied to the back electrode 40, the first reverse bias voltage V1, and the second reverse bias voltage V2 also change.

[0223] It should be noted that in the description of the present application, the solid-state image sensor 100 has been described as an example. However, the present disclosure can also be implemented as a light detector (in other words, a photosensor) that does not capture images other than a solid-state image sensor. In this case, the APD 31 included in the pixel array unit 120 may also be one.

[0224] -Industrial Applicability-

[0225] The light detector of the present disclosure can achieve stable operation by alleviating the electric field concentration at the end of the pixel array unit, and thus is useful for application to a solid-state image sensor used in a distance measurement system or the like.

[0226] -Symbol Explanation-

[0227] 10 First semiconductor layer (p-type silicon substrate)

[0228] 11 Second semiconductor layer (p-type epitaxial layer)

[0229] 12 Third semiconductor layer

[0230] 13 Separation region

[0231] 14 Eleventh semiconductor layer

[0232] 15, 15a Ninth semiconductor layer (P well)

[0233] 16 Twelfth semiconductor layer

[0234] 21 Fourth semiconductor layer

[0235] 22, 22a Fifth semiconductor layer

[0236] 23 Sixth semiconductor layer

[0237] 24 Seventh semiconductor layer

[0238] 25 Eighth semiconductor layer

[0239] 26 N well (circuit well)

[0240] 27 Tenth semiconductor layer

[0241] 30 APD (avalanche photodiode) array

[0242] 31 APD

[0243] 32 First region (PN junction structure)

[0244] 32a Frame-shaped region

[0245] 32b dummy APD

[0246] 32c dummy pixel circuit region

[0247] 33 Avalanche multiplication region of APD

[0248] 34 Avalanche multiplication region of the first region (PN junction region of the PN junction structure of the first region)

[0249] 40 Back electrode

[0250] 50 Electric field relaxation region

[0251] 51 STI (Shallow Trench Isolation)

[0252] 100 Solid-state image sensor (photodetector)

[0253] 110 Substrate (semiconductor substrate)

[0254] 120 Pixel array section

[0255] 121 Pixel

[0256] 130 First peripheral circuit section

[0257] 131 Readout circuit

[0258] 132 Horizontal scanning circuit

[0259] 133 Buffer amplifier

[0260] 140 Second peripheral circuit section

[0261] 141 Vertical scanning circuit

[0262] 150 Pixel circuit region

[0263] 201 Photodetection section (APD)

[0264] 202 Transfer transistor

[0265] 203 Reset transistor

[0266] 204 Source follower transistor

[0267] 205 Selection transistor

[0268] 206 Floating diffusion capacitor

[0269] 207 Horizontal signal line

[0270] 208 Vertical signal line

[0271] 1000 Distance measurement system

[0272] 1100 Light emitting part

[0273] 1200 Light receiving part

[0274] 1300 Control part

[0275] 1400 Output part

[0276] S1 First main surface of the substrate

[0277] S2 Second main surface of the substrate

Claims

1. An optical detector having two or more avalanche photodiodes (APDs) formed on a semiconductor substrate, characterized in that: When viewed from above, a first region is disposed outside the APD. The adjacent APDs, adjacent first regions, and adjacent APDs and first regions are separated by separation regions. The APD is composed of a first semiconductor layer of a second conductivity type contained in the semiconductor substrate and a fourth semiconductor layer of a first conductivity type in contact with the first semiconductor layer. The first region is composed of the first semiconductor layer and a fifth semiconductor layer of a first conductivity type in contact with the first semiconductor layer. A first voltage is applied to the fourth semiconductor layer of the APD, and a second voltage is applied to the fifth semiconductor layer of the first region. The first voltage is higher than the second voltage. At least a part of the separation region is depleted in the first main surface of the semiconductor substrate. No contact hole connected to the separation region is disposed in the separation region, and no trench extending from the surface of the separation region toward the inside is formed. The difference between the first reverse bias voltage applied to the APD and the second reverse bias voltage applied to the first region is less than the potential difference between the separation region and the first region.

2. The optical detector according to claim 1, wherein: The difference between the first reverse bias voltage and the second reverse bias voltage is greater than the remaining bias voltage, which is the difference between the absolute value of the voltage applied to the APD during operation of the APD and the absolute value of the breakdown voltage of the APD.

3. The optical detector according to claim 1, characterized in that: The absolute value of the breakdown voltage of the first region is greater than the absolute value of the breakdown voltage of the APD.

4. The optical detector according to claim 3, wherein: The PN junction boundary of the first region is located at a position deeper inside the semiconductor substrate than the PN junction boundary of the APD.

5. The optical detector according to claim 3, wherein: The difference between the absolute value of the breakdown voltage of the first region and the absolute value of the breakdown voltage of the APD is greater than the remaining bias voltage, which is the difference between the absolute value of the voltage applied to the APD during operation of the APD and the absolute value of the breakdown voltage of the APD.

6. The optical detector according to claim 1, wherein: The photodetector further includes a pixel circuit region having a circuit well. The absolute value of the breakdown voltage between the circuit well and the first semiconductor layer is greater than the absolute value of the breakdown voltage of the APD.

7. The optical detector according to claim 6, characterized in that: The breakdown voltage of the first region and the breakdown voltage between the circuit well and the first semiconductor layer are the same.

8. The optical detector according to claim 6, wherein: The circuit well is composed of a seventh semiconductor layer of a first conductivity type formed in the semiconductor substrate and an eighth semiconductor layer of a first conductivity type in contact with the seventh semiconductor layer. The impurity concentration of the fifth semiconductor layer is the same as the impurity concentration of the seventh semiconductor layer. Based on the first main surface of the semiconductor substrate, the depth of the fifth semiconductor layer is the same as the depth of the seventh semiconductor layer.

9. The optical detector according to claim 1, wherein: When viewed from above, the first region surrounds one or more of the APDs and is formed in a frame shape.

10. The optical detector according to claim 1, wherein: The first region further has a tenth semiconductor layer of a first conductivity type, which extends in a protruding manner toward the side opposite to the adjacent APD near the bonding surface with the first semiconductor layer.

11. The optical detector according to claim 1, wherein: An electric field relaxation region is further provided outside the first region. The impurity concentration in the electric field relaxation region is lower than that in the first semiconductor layer, and no silicide is formed on the surface of the electric field relaxation region.

12. The optical detector according to claim 11, wherein: Most of the surface of the electric field relaxation region is covered by a shallow trench isolation (STI) structure.

13. The optical detector according to claim 1, characterized in that: The APD operates in Geiger multiplication mode, and the APD is connected only to the capacitor at least temporarily during optical detection.

14. The optical detector according to claim 13, wherein: The first region is connected in series with the resistor.

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