A method, apparatus, device and medium for determining pulse frequency

Abstract

Embodiments of the present application disclose a pulse frequency determination method, device, equipment and medium. The method comprises: obtaining a clock frequency of a reference clock; counting a first count value of the reference clock and a second count value of a to-be-measured signal within a set time length; and determining a pulse frequency of the to-be-measured signal according to the clock frequency, the first count value and the second count value. Embodiments of the present application trigger two kinds of counters to count through a reference clock, obtain two groups of count values, and determine the pulse frequency of the to-be-measured signal in combination with the clock frequency of the reference clock, thereby solving the problem of abnormal data of an internal counter of an FPGA and improving the accuracy of pulse frequency measurement of the to-be-measured signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of ultrafast lasers, and particularly relates to a pulse frequency determination method and device, equipment and medium. BACKGROUND

[0002] In the working process of an ultrafast laser, it is necessary to detect whether a seed source is normal in real time. A common detection method is to measure whether the output frequency of the seed source is normal, and therefore it is necessary to accurately and stably measure the frequency of the seed source.

[0003] The prior art uses two groups of counters to count simultaneously. One group of counters is triggered by a relatively stable clock to record a period of time as a reference time. The other group of counters is triggered by a to-be-detected frequency as a clock to calculate the number of rising edges, i.e., the number of pulse periods, in a period of time. Then, the frequency of the to-be-detected signal is calculated through a formula.

[0004] However, the to-be-detected signal as the trigger clock of the second group of counters may appear unstable, because the to-be-detected signal is an optical signal emitted by the seed source, which is converted into an electrical signal by an optical-electrical sensor. In the conversion and transmission process, glitches are very likely to occur. If the to-be-detected signal is directly used as the trigger clock of the counter, when the seed source signal appears glitches in the conversion and transmission process, it is equivalent to that the trigger clock of the second group of counters appears glitches. When the clock has glitches, the internal counter of the field programmable gate array (FPGA) may appear abnormal, and the calculated frequency is incorrect. SUMMARY

[0005] The present application provides a pulse frequency determination method, device, equipment and medium to solve the problem that the to-be-detected signal appears glitches, causing the internal counter of the FPGA to appear abnormal, thereby improving the accuracy of the to-be-detected signal frequency measurement.

[0006] According to an aspect of the present application, a pulse frequency determination method is provided, comprising:

[0007] obtaining a clock frequency of a reference clock;

[0008] counting a first count value of the reference clock and a second count value of a to-be-detected signal in a set time length;

[0009] determining a pulse frequency of the to-be-detected signal according to the clock frequency, the first count value and the second count value.

[0010] According to another aspect of the present application, a pulse frequency determination device is provided, comprising:

[0011] a clock frequency acquisition module configured to acquire a clock frequency of a reference clock;

[0012] a count value statistics module configured to count a first count value of the reference clock and a second count value of a to-be-tested signal within a set time length;

[0013] a pulse frequency determination module configured to determine a pulse frequency of the to-be-tested signal according to the clock frequency, the first count value and the second count value.

[0014] According to another aspect of the present application, an electronic device is provided, which comprises:

[0015] at least one processor; and

[0016] a memory in communication connection with the at least one processor; wherein

[0017] the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the pulse frequency determination method according to any one of the embodiments of the present application.

[0018] According to another aspect of the present application, a computer readable storage medium is provided, which stores computer instructions for enabling a processor to execute the pulse frequency determination method according to any one of the embodiments of the present application.

[0019] The technical solution of the embodiments of the present application acquires the clock frequency of the reference clock, counts the first count value of the reference clock and the second count value of the to-be-tested signal within the set time length, and determines the pulse frequency of the to-be-tested signal according to the clock frequency, the first count value and the second count value. The embodiments of the present application count by two kinds of counters triggered by one reference clock to obtain two groups of count values, and determine the pulse frequency of the to-be-tested signal by combining the clock frequency of the reference clock, thereby solving the problem of abnormal data of the internal counter of the FPGA and improving the accuracy of the frequency measurement of the to-be-tested signal.

[0020] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to make the technical solution in the embodiments of the present application clearer, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0022] Figure 1 The flow chart of the pulse frequency determination method provided in the embodiments of the present application is shown in FIG. 1.

[0023] Figure 2 The implementation schematic diagram of the reference clock used to beat the to-be-measured signal is shown in FIG. 2.

[0024] Figure 3 The implementation schematic flow chart of the pulse frequency determination method provided in the embodiments of the present application is shown in FIG. 3.

[0025] Figure 4 The structural schematic diagram of the pulse frequency determination device provided in the embodiments of the present application is shown in FIG. 4.

[0026] Figure 5 The structural schematic diagram of the electronic device implementing the pulse frequency determination method in the embodiments of the present application is shown in FIG. 5. DETAILED DESCRIPTION

[0027] In order to make the technical solution in the embodiments of the present application clearer, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0028] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0029] Figure 1A flowchart of a pulse frequency determination method provided by an embodiment of the present application, the embodiment can be applied to a case of determining a pulse frequency of a to-be-measured signal, the method can be executed by a pulse frequency determination apparatus, and can be generally integrated in an electronic device having a pulse frequency determination function, such as a server, a mobile terminal, or a server cluster. As shown in Figure 1 the method specifically includes the following steps: as shown in Figure 1 the method includes:

[0030] S110, obtaining a clock frequency of a reference clock.

[0031] The clock frequency is used to describe the number of pulses generated by a periodic pulse signal in a unit of time. The reference clock can be selected according to user requirements, for example, it can be a clock signal generated by a quartz crystal oscillator, and the reference clock is a stable clock source.

[0032] S120, counting a first count value of the reference clock and a second count value of the to-be-measured signal in a set time length.

[0033] The first count value and the second count value are count values obtained by simultaneously counting by two groups of counters, and the trigger clock of the two groups of counters is a stable reference clock. The first count value can be a value counted by a first group of counters on the number of periods required in the set time length. The second count value can be a value counted by a second group of counters on the number of rising edges of the to-be-measured signal in the set time length. Of course, each rising edge of the to-be-measured signal can be understood as a pulse period. The set time length can be adjusted according to the required measurement frequency accuracy, which is not limited by the embodiment of the present application, for example, it can be 1 millisecond. For example, if the set time length is 1 millisecond and the reference clock frequency is 100 megahertz, the first group of counters needs to count a total of 100,000 periods.

[0034] Specifically, the first group of counters and the second group of counters count simultaneously, the first group of counters continuously counts until the maximum count value of the set time length is reached, the first count value (the maximum count value) of the reference clock is counted, and at the same time, the value counted by the second group of counters on the number of rising edges of the to-be-measured signal is counted.

[0035] In this embodiment, a stable reference clock is used as the trigger clock of the counter, which solves the unstable factors of the to-be-measured signal in the prior art, prevents the to-be-measured signal counter from being abnormal, and makes the measurement result of the pulse frequency more stable and accurate.

[0036] Optionally, counting the second count value of the to-be-measured signal in the set time length includes:

[0037] The number of rising edges of the to-be-measured signal in the set time length is counted based on the reference clock to obtain the second count value.

[0038] Wherein, the rising edge refers to the moment (time) when the digital level changes from low level (digital "0") to high level (digital "1").

[0039] The embodiment of the present application can count the number of rising edges of the to-be-tested signal in the set time length by using the stable reference clock to tap the to-be-tested signal twice, and the number of rising edges of the to-be-tested signal can be determined by tapping twice, so that the number of rising edges of the to-be-tested signal can be counted to obtain the second count value.

[0040] Optionally, the number of rising edges of the to-be-tested signal in the set time length is counted based on the reference clock to obtain the second count value, and the method comprises the following steps of:

[0041] The to-be-tested signal is tapped based on the reference clock to obtain a first tapped signal;

[0042] The first tapped signal is tapped based on the reference clock to obtain a second tapped signal;

[0043] The number of rising edges of the to-be-tested signal in the set time length is counted according to the first tapped signal and the second tapped signal to obtain the second count value.

[0044] Wherein, the first tapped signal can be a signal obtained by sampling the to-be-tested signal by using the reference clock. The second tapped signal can be a signal obtained by sampling the first tapped signal by using the reference clock.

[0045] Specifically, the signal point at the previous moment of the to-be-tested signal is sampled at the rising edge of the reference clock, and the first tapped signal is obtained after sampling is completed. The signal point at the previous moment of the first tapped signal is sampled at the rising edge of the reference clock, and the second tapped signal is obtained after sampling is completed. The first tapped signal and the second tapped signal are used as the condition for determining the rising edge of the to-be-tested signal, and the value of the number of rising edges of the to-be-tested signal in the set time length is used as the second count value.

[0046] In the embodiment, the sampling is triggered at the rising edge of the reference clock, and no sampling is performed during the non-rising edge period, so that one cycle of error may exist at each of the beginning and the end, and a total of two cycles of error exist. When the first count value is larger, the influence of the two cycles of error is smaller. Therefore, if the error is to be reduced, the clock frequency of the reference clock can be increased, that is, the error time is reduced. The set time length can also be increased, that is, the proportion of the error is reduced.

[0047] Optionally, the number of rising edges of the to-be-tested signal in the set time length is counted according to the first tapped signal and the second tapped signal to obtain the second count value, and the method comprises the following steps of:

[0048] acquiring the level values of the first and second beat signals when the signal of the reference clock is at a rising edge within a set time length;

[0049] when the first beat signal is at a high level and the second beat signal is at a low level, adding 1 to the second count value.

[0050] Specifically, the level values of the first and second beat signals are acquired when the signal of the reference clock is at a rising edge within a set time length to determine the rising edge of the to-be-tested signal, and when the first beat signal is at a high level and the second beat signal is at a low level, it is determined that the rising edge of the to-be-tested signal, and the second count value is added by 1.

[0051] S130, determining the pulse frequency of the to-be-tested signal according to the clock frequency, the first count value and the second count value.

[0052] wherein the pulse frequency is the number of effective discharges on the discharge gap within a unit time.

[0053] Specifically, the first count value is the value counted by the first group of counters for the number of required periods within a set time length, which can be calculated by the following formula: the first count value*reference clock period. The second count value represents the pulse period of the to-be-tested signal within the set time length, and one pulse period can be calculated by the following formula: set time length / second count value. Therefore, the pulse frequency of the to-be-tested signal can be calculated by the following formula: second count value / set time length, so that the pulse frequency=second count value / (first count value*reference clock period) can be obtained, and then according to the reference clock frequency equal to 1 / reference clock period, the pulse frequency of the to-be-tested signal can be determined.

[0054] Optionally, the pulse frequency of the to-be-tested signal is determined according to the clock frequency, the first count value and the second count value, and is calculated according to the following formula:

[0055] Pulse frequency=(second count value*clock frequency) / first count value.

[0056] It should be noted that the second count value in the pulse frequency of the to-be-tested signal is the value of the second count value stored when the first count value reaches the maximum first count value of the set time length. For example, the set time is 1 millisecond, and the reference clock period is 10 nanoseconds, so the maximum first count value is 100000-1. The first count value in the pulse frequency of the to-be-tested signal is the maximum first count value.

[0057] The technical scheme of the embodiment of the present application comprises the following steps: obtaining a clock frequency of a reference clock; counting a first count value of the reference clock and a second count value of a to-be-measured signal within a set time length; and determining a pulse frequency of the to-be-measured signal according to the clock frequency, the first count value and the second count value. The embodiment of the present application counts two kinds of counters triggered by one reference clock to obtain two sets of count values, and determines the pulse frequency of the to-be-measured signal by combining the clock frequency of the reference clock, thereby solving the problem of abnormal data of the internal counter of the FPGA and improving the accuracy of the frequency measurement of the to-be-measured signal.

[0058] Exemplarily, Figure 2 An implementation schematic diagram of the present application is provided for the reference clock to beat the to-be-measured signal. As shown in the figure, Figure 2 The reference clock is a stable clock source, and the reference clock is used to beat the to-be-measured signal twice. The first beat signal is a signal sampled by the reference clock on the to-be-measured signal, and the second beat signal is a signal sampled by the reference clock on the first beat signal. The dashed line represents the rising edge of the reference clock, and the sampling of the to-be-measured signal is triggered at the rising edge of the reference clock. The first group of counters records the number of periods of the reference clock within the set time length, and the second group of counters records the number of rising edges of the to-be-measured signal. When the first beat signal is high and the second beat signal is low, it is determined that the rising edge of the to-be-measured signal appears.

[0059] Exemplarily, Figure 3 An implementation schematic flow chart of the determination method of the pulse frequency is provided for the embodiment of the present application. As shown in the figure, Figure 3 The first group of counters and the second group of counters count at the same time. First, the first group of counters counts continuously, for example, the first group of counters performs the add 1 operation, and when the first count value reaches the maximum first count value of the set time length, the first group of counters clears the first count value. When it is detected that beat 1 is high and beat 2 is low, that is, the rising edge of the to-be-measured signal appears, the second count value is added by 1, and when the first count value reaches the maximum value, the second count value at this time is stored and can be recorded as data. Then, the second group of counters also clears the second count value. Thereafter, the first group of counters counts again, and when the first count value reaches the maximum first count value, the value of data is updated. It should be noted that the trigger clock of all the counters is the reference clock, and the pulse frequency of the to-be-measured signal can be obtained according to the following formula: pulse frequency of the to-be-measured signal = data * reference clock frequency / maximum first count value.

[0060] Figure 4 A structural schematic diagram of a determination device of the pulse frequency is provided for the embodiment of the present application.

[0061] As shown in the figure, Figure 4 The device comprises:

[0062] The clock frequency acquisition module 210 is configured to acquire a clock frequency of a reference clock;

[0063] The count value statistics module 220 is configured to count a first count value of the reference clock and a second count value of a to-be-tested signal within a set time length.

[0064] The pulse frequency determination module 230 is configured to determine a pulse frequency of the to-be-tested signal according to the clock frequency, the first count value and the second count value.

[0065] Optionally, the count value statistics module 220 comprises:

[0066] The second count value obtaining unit is configured to count a number of rising edges of the to-be-tested signal within the set time length based on the reference clock, and obtain the second count value.

[0067] Optionally, the second count value obtaining unit comprises:

[0068] The first beat signal obtaining sub-unit is configured to beat the to-be-tested signal based on the reference clock, and obtain a first beat signal.

[0069] The second beat signal obtaining sub-unit is configured to beat the first beat signal based on the reference clock, and obtain a second beat signal.

[0070] The second count value obtaining sub-unit is configured to count the number of rising edges of the to-be-tested signal within the set time length according to the first beat signal and the second beat signal, and obtain the second count value.

[0071] Optionally, the second count value obtaining sub-unit is further configured to:

[0072] Within the set time length, when a signal of the reference clock is at a rising edge, a level value of the first beat signal and the second beat signal is acquired.

[0073] When the first beat signal is at a high level and the second beat signal is at a low level, the second count value is accumulated by 1.

[0074] Optionally, the pulse frequency determination module 230 is further configured to calculate according to the following formula:

[0075] Pulse frequency=(second count value*clock frequency) / first count value.

[0076] The pulse frequency determination device provided by the embodiment of the present application can execute the pulse frequency determination method provided by any of the embodiments of the present application, and has the corresponding function modules and beneficial effects of the execution method.

[0077] Figure 5A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0078] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0079] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0080] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as determining the method pulse frequency.

[0081] In some embodiments, the determination of the method pulse frequency can be implemented as a computer program tangibly embodied in a computer readable storage medium, e.g., storage unit 18. In some embodiments, parts or all of the computer program can be loaded and / or installed onto electronic device 10 via, e.g., ROM 12 and / or communication unit 19. When the computer program is loaded onto RAM 13 and executed by processor 11, one or more steps of the determination of the method pulse frequency as described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the determination of the method pulse frequency by other means, e.g., with the aid of firmware.

[0082] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (PLD), a computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0083] Computer programs used to implement the methods of the present application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program running on the processor implements the functions / operations specified in the flowcharts and / or the block diagrams. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0084] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable storage medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of a machine-readable storage medium will include one or more lines of a program of instructions in a transitory signal, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0085] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0086] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0087] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0088] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, each step described in the present application can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0089] The above detailed description does not constitute a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method of determining the pulse frequency, characterized in that, The method comprises the following steps: acquiring a clock frequency of a reference clock; counting a first count value of the reference clock and a second count value of a to-be-tested signal within a set time length; wherein the first count value is a value counted by a first group of counters for a required period number within the set time length, and the set time length is calculated by the following formula: the first count value * a period of the reference clock; determining a pulse frequency of the to-be-tested signal according to the clock frequency, the first count value and the second count value; the counting of the second count value of the to-be-tested signal within the set time length comprises the following steps: triggering sampling of a signal point of a previous time of the to-be-tested signal at a rising edge of the reference clock to obtain a first beat signal; triggering sampling of a signal point of a previous time of the first beat signal at a rising edge of the reference clock to obtain a second beat signal; counting a number of rising edges of the to-be-tested signal within the set time length according to the first beat signal and the second beat signal to obtain the second count value; the counting of the number of rising edges of the to-be-tested signal within the set time length according to the first beat signal and the second beat signal to obtain the second count value comprises the following steps: acquiring a level value of the first beat signal and the second beat signal when a signal of the reference clock is at a rising edge within the set time length; when the first beat signal is at a high level and the second beat signal is at a low level, the second count value is accumulated by 1.

2. The method of claim 1, wherein, the determination of the pulse frequency of the to-be-tested signal according to the clock frequency, the first count value and the second count value is calculated according to the following formula: pulse frequency = (the second count value * the clock frequency) / the first count value.

3. A pulse frequency determination device, characterized by The method comprises the following steps: a clock frequency acquisition module is configured to acquire a clock frequency of a reference clock; a count value counting module is configured to count a first count value of the reference clock and a second count value of a to-be-tested signal within a set time length; wherein the first count value is a value counted by a first group of counters for a required period number within the set time length, and the set time length is calculated by the following formula: the first count value * a period of the reference clock; a pulse frequency determination module is configured to determine a pulse frequency of the to-be-tested signal according to the clock frequency, the first count value and the second count value; the count value counting module comprises: a second count value obtaining unit is configured to count a number of rising edges of the to-be-tested signal within the set time length based on the reference clock to obtain the second count value; the second count value obtaining unit comprises: a first beat signal obtaining sub-unit is configured to trigger sampling of a signal point of a previous time of the to-be-tested signal at a rising edge of the reference clock to obtain a first beat signal; a second beat signal obtaining sub-unit is configured to trigger sampling of a signal point of a previous time of the first beat signal at a rising edge of the reference clock to obtain a second beat signal; a second count value obtaining sub-unit is configured to count a number of rising edges of the to-be-tested signal within the set time length according to the first beat signal and the second beat signal to obtain the second count value; the second count value obtaining sub-unit is further configured to: Within the set time length, when a signal of the reference clock is at a rising edge, a level value of the first beat signal and the second beat signal is acquired; When the first beat signal is at a high level and the second beat signal is at a low level, the second count value is accumulated by 1.

4. An electronic device, comprising: The electronic device comprises: at least one processor; and a memory connected with the at least one processor in communication; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the pulse frequency determination method in any one of claims 1-2.

5. A computer readable storage medium, characterized in that, The computer readable storage medium stores computer instructions for enabling the processor to implement the pulse frequency determination method in any one of claims 1-2 when executed.

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