Low-Voltage Fuse Trimming Circuit Applied to High-Voltage Analog Integrated Circuits

Abstract

The present invention belongs to the field of high-voltage analog integrated circuits, and discloses a low-voltage fuse trimming circuit applied to high-voltage analog integrated circuits, which includes a P-type DMOS transistor DP1, an N-type DMOS transistor DN1, a current mirror, a pull-down unit, a first N-type MOS transistor MN1, a first diode D1, a resistor R1, a fuse F1, an inverter INV1, an AND gate AND1, a bias current input terminal IBIAS, a high-voltage power supply voltage terminal VDDH, a low-voltage power supply voltage terminal VREG, and a ground terminal GND. A fuse status indication output terminal DOUT is provided at the output terminal of the inverter INV1; a programming control input terminal W_EN is provided at the first input terminal of the AND gate AND1, and a fuse status indication input terminal DIN is provided at the second input terminal of the AND gate AND1. Through a new power supply switching circuit, sufficient programming current can be directly obtained from an external power supply during fuse programming. At the same time, it can be switched to internal low-voltage power supply during normal operation to avoid damage to the low-voltage fuse trimming circuit caused by external high voltage.

Description

Technical Field

[0001] The present invention belongs to the field of high - voltage analog integrated circuits, and relates to a low - voltage fuse trimming circuit applied to high - voltage analog integrated circuits. Background Art

[0002] Due to the influence of manufacturing process fluctuations and packaging stress, integrated circuits often need to be calibrated after packaging. Among them, fuse programming, as a trimming technology with simple structure, easy implementation, and low power consumption, is widely used in analog integrated circuits. The supply voltage of analog integrated circuits applied in fields such as automotive and industrial fluctuates between several volts and dozens of volts. However, limited by the gate - source voltage of MOS transistors in most semiconductor processes, the fuse programming circuit containing logic devices mostly operates at low voltage.

[0003] Currently, in high - voltage analog integrated circuits, the low - voltage power supply inside the chip is usually generated by an internal voltage - regulating circuit, and its driving ability is limited and cannot provide the large current of dozens of milliamperes required for fuse programming. Therefore, when programming the fuse, the fuse circuit needs to be connected to an external voltage to obtain current. At this time, adjusting the external supply voltage to low voltage can ensure that the fuse circuit will not be damaged. When the chip is working normally, the external supply voltage fluctuates between several volts and dozens of volts. Therefore, the fuse circuit needs to work at the low voltage generated inside the chip. However, based on the power supply switching during fuse programming and normal operation, the existing fuse trimming circuits cannot effectively ensure that they will not be damaged when the chip supply voltage is high while the fuse is being programmed normally. Summary of the Invention

[0004] The purpose of the present invention is to overcome the above - mentioned disadvantages of the prior art and provide a low - voltage fuse trimming circuit applied to high - voltage analog integrated circuits.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A low - voltage fuse trimming circuit applied to high - voltage analog integrated circuits includes a P - type DMOS transistor DP1, an N - type DMOS transistor DN1, a current mirror, a pull - down unit, a first N - type MOS transistor MN1, a first diode D1, a resistor R1, a fuse F1, an inverter INV1, an AND gate AND1, a bias current input terminal IBIAS, a high - voltage supply voltage terminal VDDH, a low - voltage supply voltage terminal VREG, and a ground terminal GND;

[0007] The first terminal of the current mirror is connected to the bias current input terminal IBIAS, and the second terminal of the current mirror is connected to the source of the N-type DMOS transistor DN1; the first terminal of the pull-down unit, the source of the first N-type MOS transistor MN1, the ground terminal of the inverter INV1, and the ground terminal of the AND gate AND1 are all connected to the ground terminal GND; the second terminal of the pull-down unit, the drain of the first N-type MOS transistor MN1, and the input terminal of the inverter INV1 are all connected to the first terminal of the fuse F1; the gate of the first N-type MOS transistor MN1 and the output terminal of the AND gate AND1 are both connected to the gate of the N-type DMOS transistor DN1; the drain of the P-type DMOS transistor DP1 and the second terminal of the fuse F1 are both connected to the negative terminal of the first diode D1; the source of the P-type DMOS transistor DP1 and the second terminal of the resistor R1 are both connected to the high-voltage power supply voltage terminal VDDH; the positive terminal of the first diode D1, the power supply terminal of the inverter INV1, and the power supply terminal of the AND gate AND1 are all connected to the low-voltage power supply voltage terminal VREG; a fuse status indication output terminal DOUT is provided at the output terminal of the inverter INV1; a programming control input terminal W_EN is provided at the first input terminal of the AND gate AND1, and a fuse status indication input terminal DIN is provided at the second input terminal of the AND gate AND1;

[0008] Among them, the pull-down unit is used to provide active pull-down. When the fuse F1 is blown, the input terminal of the inverter INV is pulled down to low; when the fuse F1 is not blown, the input terminal of the inverter INV is pulled high.

[0009] Optionally, the first diode D1 is a Zener diode.

[0010] Optionally, a second diode D2 is further included; the positive terminal of the second diode D2 is connected to the gate of the P-type DMOS transistor DP1, the first terminal of the resistor R1, and the drain of the N-type DMOS transistor DN1; the negative terminal of the second diode D2 is connected to the high-voltage power supply voltage terminal VDDH.

[0011] Optionally, the second diode D2 is a Zener diode.

[0012] Optionally, the width-to-length ratio of the first N-type MOS transistor MN1 is: 1000 to 3000; the width-to-length ratio of the P-type DMOS transistor DP1 is: 1000 to 3000.

[0013] Optionally, the pull-down unit includes a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, and a fourth N-type MOS transistor MN4; the gates of the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, the fourth N-type MOS transistor MN4, and the drain of the fourth N-type MOS transistor MN4 are all connected to the first end of the fuse F1, the drain of the second N-type MOS transistor MN2 is connected to the source of the third N-type MOS transistor MN3, the drain of the third N-type MOS transistor MN3 is connected to the source of the fourth N-type MOS transistor MN4; the source of the second N-type MOS transistor MN2 is connected to the ground terminal GND.

[0014] Optionally, the width-to-length ratios of the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, and the fourth N-type MOS transistor MN4 are: 0.001 to 0.002.

[0015] Optionally, the resistance value of the fuse F1 is: 50 to 200 Ω.

[0016] Optionally, the current mirror includes a fifth N-type MOS transistor MN5 and a sixth N-type MOS transistor MN6;

[0017] The drain of the fifth N-type MOS transistor MN5, the gate of the fifth N-type MOS transistor MN5, and the gate of the sixth N-type MOS transistor MN6 are all connected to the bias current input terminal IBIAS; the sources of the fifth N-type MOS transistor MN5 and the sixth N-type MOS transistor MN6 are both connected to the ground terminal GND, and the drain of the sixth N-type MOS transistor MN6 is connected to the source of the N-type DMOS transistor DN1.

[0018] Optionally, when performing fuse programming, the difference between the input voltage values of the high-voltage power supply voltage terminal VDDH and the low-voltage power supply voltage terminal VREG is within 0.3 V.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention is applied to a low-voltage fuse trimming circuit for high-voltage analog integrated circuits. By designing a new power supply switching circuit, through a digitally controlled N-type DMOS transistor DN1 and a current-controlled P-type DMOS transistor DP1, according to the working mode of the fuse F1, the power supply of the fuse circuit is switched between an external power supply and an internal power supply, so as to directly obtain sufficient programming current from the external power supply during fuse programming, and at the same time, the fuse trimming circuit can be switched to the internal low-voltage power supply during normal operation to avoid damage to the fuse trimming circuit caused by external high voltage.

[0021] Further, it further includes a second diode D2, and the positive terminal of the second diode D2 is connected to the gate of the P-type DMOS transistor DP1, the first terminal of the resistor R1, and the drain of the N-type DMOS transistor DN1; the negative terminal of the second diode D2 is connected to the high-voltage power supply voltage terminal VDDH. The gate of the P-type DMOS transistor DP1 is protected by the second diode D2. If the source-gate voltage of the P-type DMOS transistor DP1 is too high, the second diode D2 breaks down, stabilizing the gate-source voltage of the P-type DMOS transistor DP1 back to a low voltage, thereby preventing the gate of the P-type DMOS transistor DP1 from being broken down by high voltage.

[0022] Further, when performing fuse programming, the input voltage values of the high-voltage power supply voltage terminal VDDH and the low-voltage power supply voltage terminal VREG are approximately the same, ensuring that while providing a large current for fuse programming, high-voltage breakdown damage will not occur to the fuse circuit trimming. Brief Description of the Drawings

[0023] Figure 1 It is a topology diagram of a low-voltage fuse trimming circuit applied to a high-voltage analog integrated circuit according to the present invention. Detailed Embodiment

[0024] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or devices.

[0026] The present invention will be further described in detail below in conjunction with the drawings:

[0027] See Figure 1, in an embodiment of the present invention, a low-voltage fuse trimming circuit applied to a high-voltage analog integrated circuit is provided, including a P-type DMOS transistor DP1, an N-type DMOS transistor DN1, a current mirror, a pull-down unit, a first N-type MOS transistor MN1, a first diode D1, a resistor R1, a fuse F1, an inverter INV1, an AND gate AND1, a bias current input terminal IBIAS, a high-voltage power supply voltage terminal VDDH, a low-voltage power supply voltage terminal VREG, and a ground terminal GND; the first terminal of the current mirror is connected to the bias current input terminal IBIAS, and the second terminal of the current mirror is connected to the source of the N-type DMOS transistor DN1; the first terminal of the pull-down unit, the source of the first N-type MOS transistor MN1, the ground terminal of the inverter INV1, and the ground terminal of the AND gate AND1 are all connected to the ground terminal GND; the second terminal of the pull-down unit, the drain of the first N-type MOS transistor MN1, and the input terminal of the inverter INV1 are all connected to the first terminal of the fuse F1; the gate of the first N-type MOS transistor MN1 and the output terminal of the AND gate AND1 are both connected to the gate of the N-type DMOS transistor DN1; the drain of the P-type DMOS transistor DP1 and the second terminal of the fuse F1 are both connected to the negative terminal of the first diode D1; the source of the P-type DMOS transistor DP1 and the second terminal of the resistor R1 are both connected to the high-voltage power supply voltage terminal VDDH; the positive terminal of the first diode D1, the power supply terminal of the inverter INV1, and the power supply terminal of the AND gate AND1 are all connected to the low-voltage power supply voltage terminal VREG; a fuse status indication output terminal DOUT is provided at the output terminal of the inverter INV1; a programming control input terminal W_EN is provided at the first input terminal of the AND gate AND1, and a fuse status indication input terminal DIN is provided at the second input terminal of the AND gate AND1.

[0028] Among them, the pull-down unit is used to provide active pull-down. When the fuse F1 is blown, the input terminal of the inverter INV is pulled down to low; when the fuse F1 is not blown, the input terminal of the inverter INV is pulled up. Specifically, the pull-down unit provides an active weak pull-down effect. When reading the value of the fuse F1, if the fuse F1 is blown, the input terminal of the inverter INV is weakly pulled down to low; if the fuse F1 is not blown, the pull-down unit is connected to the power supply as a resistor with a very large resistance, maintaining a very small operating current and pulling up the input terminal of the inverter INV. Therefore, the low-power operation of the fuse circuit is achieved through the pull-down unit.

[0029] In a possible implementation, the low-voltage fuse trimming circuit applied to the high-voltage analog integrated circuit further includes a second diode D2; the positive terminal of the second diode D2 is connected to the gate of the P-type DMOS transistor DP1, the first terminal of the resistor R1, and the drain of the N-type DMOS transistor DN1; the negative terminal of the second diode D2 is connected to the high-voltage power supply voltage terminal VDDH. The gate of the P-type DMOS transistor DP1 is protected by the second diode D2. If the source-gate voltage of the P-type DMOS transistor DP1 is too high, the second diode D2 breaks down, stabilizing the gate-source voltage of the P-type DMOS transistor DP1 back to a low voltage, thereby preventing the gate of the P-type DMOS transistor DP1 from being broken down by high voltage.

[0030] Optionally, both the second diode D2 and the first diode D1 are Zener diodes. The characteristic of a Zener diode is that before reverse conduction and breakdown, the current at both ends remains basically unchanged. When the Zener diode is connected to the circuit, if the power supply voltage fluctuates or other reasons cause the voltage at each point in the circuit to change, the voltage across the load will remain basically unchanged.

[0031] In a possible implementation, the width-to-length ratio of the first N-type MOS transistor MN1 is: 1000 - 3000; the width-to-length ratio of the P-type DMOS transistor DP1 is: 1000 - 3000.

[0032] In a possible implementation, the pull-down unit includes a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, and a fourth N-type MOS transistor MN4; the gates of the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, the fourth N-type MOS transistor MN4, and the drain of the fourth N-type MOS transistor MN4 are all connected to the first terminal of the fuse F1, the drain of the second N-type MOS transistor MN2 is connected to the source of the third N-type MOS transistor MN3, and the drain of the third N-type MOS transistor MN3 is connected to the source of the fourth N-type MOS transistor MN4; the source of the second N-type MOS transistor MN2 is connected to the ground terminal GND.

[0033] In a possible implementation, the width-to-length ratio of the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, and the fourth N-type MOS transistor MN4 is: 0.001 - 0.002, and the resistance value of the fuse F1 is: 50 - 200 Ω. The second N-type MOS transistor MN2, the third N-type MOS transistor MN3, and the fourth N-type MOS transistor MN4 form a large resistor. In comparison, the resistance value of the fuse F1 is relatively small.

[0034] In an actual circuit, there are many current sources. Usually, the method of device matching is applied. Only one reference current source is used as the input to provide a bias voltage for multiple current sources, or directly provide multiple constant currents. The structure composed of these matching devices is called a current mirror, which is a special case of a constant current source circuit. Its controlled current is equal to the input reference current, that is, the input-output current transfer ratio is equal to 1. Its characteristic is that the output current is a replication of the input current in a certain proportion. In the design of traditional voltage-mode operational amplifiers, current mirrors are used to generate bias currents and as active loads.

[0035] In a possible implementation, the current mirror includes a fifth N-type MOS transistor MN5 and a sixth N-type MOS transistor MN6; the drain of the fifth N-type MOS transistor MN5, the gate of the fifth N-type MOS transistor MN5, and the gate of the sixth N-type MOS transistor MN6 are all connected to the bias current input terminal IBIAS; the source of the fifth N-type MOS transistor MN5 and the source of the sixth N-type MOS transistor MN6 are both connected to the ground terminal GND, and the drain of the sixth N-type MOS transistor MN6 is connected to the source of the N-type DMOS transistor DN1.

[0036] The working principle of the low-voltage fuse trimming circuit of the present invention applied to high-voltage analog integrated circuits is introduced as follows:

[0037] When performing fuse programming, the voltage of the high-voltage power supply voltage terminal VDDH is adjusted to a voltage value approximately equal to the voltage of the low-voltage power supply voltage terminal VREG, for example, the difference between the two is within 0.3V, so as to facilitate providing a large current for fuse programming without causing high-voltage breakdown damage to the fuse circuit. Then, the programming control input terminal W_EN is set to logic high. If the input of the fuse status indication input terminal DIN is logic high, the output of the AND gate AND1 is logic high, and the gate of the N-type DMOS transistor DN1 is pulled up to the voltage of the low-voltage power supply voltage terminal VREG, and the N-type DMOS transistor DN1 conducts. The current generated by the sixth N-type MOS transistor MN6 and the fifth N-type MOS transistor MN5 as a current mirror thus flows through the resistor R1 to generate a voltage drop. This voltage drop is high enough to cause the gate-source voltage of the P-type DMOS transistor DP1 to be much greater than the threshold voltage of the P-type DMOS transistor DP1, and the P-type DMOS transistor DP1 thus conducts. At the same time, the gate of the first N-type MOS transistor MN1 is also pulled up to the voltage of the low-voltage power supply voltage terminal VREG, and the first N-type MOS transistor MN1 conducts. Since the width-to-length ratios of the first N-type MOS transistor MN1 and the P-type DMOS transistor DP1 are set large enough, a large current flows through the fuse F1, and the fuse F1 is heated by the large current and blown, and the fuse programming is completed. If the input of the fuse status indication input terminal DIN is logic low, the above process will not occur, and the status of the fuse F1 will not change.

[0038] During normal operation, the input of the programming control input terminal W_EN is logic low, the output of the AND gate AND1 is logic low, the N-type DMOS transistor DN1 and the first N-type MOS transistor MN1 are in the off state, no current flows through the resistor R1, the gate-source voltage of the P-type DMOS transistor DP1 is 0, and the P-type DMOS transistor DP1 is turned off. The first diode D1 is forward-biased and conducts to supply power to the fuse F1. The second N-type MOS transistor MN2, the third N-type MOS transistor MN3, and the fourth N-type MOS transistor MN4 are all inverse ratio transistors with a very small aspect ratio, so the three form a large resistor. If the fuse F1 is not blown, due to the very small resistance value of the fuse F1, the resistance value of the resistor formed by the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, and the fourth N-type MOS transistor MN4 is very large, so the input level of the inverter INV1 is high, and the output of the fuse status indicator output terminal DOUT is logic low. If the fuse F1 is blown, there is no path from the input terminal of the inverter INV1 to the power supply, and it is pulled down to ground by the resistor formed by the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, and the fourth N-type MOS transistor MN4. The output of the fuse status indicator output terminal DOUT of the inverter INV1 is logic high.

[0039] During fuse programming, if the input of the fuse status indicator input terminal DIN is logic high, the fuse F1 is blown, and after that, when the fuse F1 operates normally, the output of the fuse status indicator output terminal DOUT is logic high; if the input of the fuse status indicator input terminal DIN is logic low, the fuse F1 is not blown, and after that, when the fuse F1 operates normally, the output of the fuse status indicator output terminal DOUT is logic low. Therefore, the value output by the fuse status indicator output terminal DOUT after the fuse F1 is programmed is always the input of the fuse status indicator input terminal DIN. Generally, the fuse F1 is not blown when leaving the factory, so the default output of the fuse status indicator output terminal DOUT is logic low.

[0040] The second diode D2 is responsible for protecting the gate of the P-type DMOS transistor DP1. If the source-gate voltage of the P-type DMOS transistor DP1 is too high, the second diode D2 breaks down, stabilizing the gate-source voltage of the P-type DMOS transistor DP1 back to a low voltage, thereby preventing the gate of the P-type DMOS transistor DP1 from being broken down by high voltage. The first diode D1 is used to prevent a large current flowing out from the high-voltage power supply voltage terminal VDDH during fuse programming from being injected into the low-voltage power supply voltage terminal VREG.

[0041] When the chip is not programmed, since the P-type DMOS transistor DP1 is turned off, the high-voltage power supply voltage terminal VDDH will not be connected to the fuse circuit, which can ensure that the fuse circuit is not damaged by high voltage.

[0042] In summary, the low-voltage fuse trimming circuit of the present invention applied to high-voltage analog integrated circuits can switch the power supply of the fuse circuit between an external power supply and an internal power supply according to the working mode of the fuse F1 through a newly designed power supply switching circuit, which consists of a digitally controlled first N-type MOS transistor MN1 and a current-controlled P-type DMOS transistor DP1. Thus, sufficient programming current can be directly obtained from the external power supply during fuse programming, and at the same time, the fuse trimming circuit can be switched to the internal low-voltage power supply during normal operation to avoid damage to the fuse trimming circuit caused by the external high voltage.

[0043] The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A low-voltage fuse trimming circuit applied to high-voltage analog integrated circuits, characterized in that, It includes a P-type DMOS transistor DP1, an N-type DMOS transistor DN1, a current mirror, a pull-down unit, a first N-type MOS transistor MN1, a first diode D1, a resistor R1, a fuse F1, an inverter INV1, an AND gate AND1, a bias current input terminal IBIAS, a high-voltage power supply voltage terminal VDDH, a low-voltage power supply voltage terminal VREG, and a ground terminal GND; The first terminal of the current mirror is connected to the bias current input terminal IBIAS, and the second terminal of the current mirror is connected to the source of the N-type DMOS transistor DN1; the first terminal of the pull-down unit, the source of the first N-type MOS transistor MN1, the ground terminal of the inverter INV1, and the ground terminal of the AND gate AND1 are all connected to the ground terminal GND; the second terminal of the pull-down unit, the drain of the first N-type MOS transistor MN1, and the input terminal of the inverter INV1 are all connected to the first terminal of the fuse F1; the gate of the first N-type MOS transistor MN1 and the output terminal of the AND gate AND1 are both connected to the gate of the N-type DMOS transistor DN1; the drain of the P-type DMOS transistor DP1 and the second terminal of the fuse F1 are both connected to the negative terminal of the first diode D1; the source of the P-type DMOS transistor DP1 and the second terminal of the resistor R1 are both connected to the high-voltage power supply voltage terminal VDDH; the positive terminal of the first diode D1, the power supply terminal of the inverter INV1, and the power supply terminal of the AND gate AND1 are all connected to the low-voltage power supply voltage terminal VREG; a fuse status indication output terminal DOUT is provided at the output terminal of the inverter INV1; a programming control input terminal W_EN is provided at the first input terminal of the AND gate AND1, and a fuse status indication input terminal DIN is provided at the second input terminal of the AND gate AND1; Among them, the pull-down unit is used to provide active pull-down. When the fuse F1 is blown, it pulls down the input terminal of the inverter INV to low; when the fuse F1 is not blown, it pulls up the input terminal of the inverter INV; It further includes a second diode D2; the positive terminal of the second diode D2 is connected to the gate of the P-type DMOS transistor DP1, the first terminal of the resistor R1, and the drain of the N-type DMOS transistor DN1; the negative terminal of the second diode D2 is connected to the high-voltage power supply voltage terminal VDDH; The current mirror includes a fifth N-type MOS transistor MN5 and a sixth N-type MOS transistor MN6; The drain, gate of the fifth N-type MOS transistor MN5, and the gate of the sixth N-type MOS transistor MN6 are all connected to the bias current input terminal IBIAS; the source of the fifth N-type MOS transistor MN5 and the source of the sixth N-type MOS transistor MN6 are both connected to the ground terminal GND, and the drain of the sixth N-type MOS transistor MN6 is connected to the source of the N-type DMOS transistor DN1.

2. The low-voltage fuse trimming circuit applied to a high-voltage analog integrated circuit according to claim 1, wherein The first diode D1 is a Zener diode.

3. The low-voltage fuse trimming circuit applied to high-voltage analog integrated circuits according to claim 1, characterized in that, The second diode D2 is a Zener diode.

4. The low-voltage fuse trimming circuit applied to a high-voltage analog integrated circuit according to claim 1, wherein The width-to-length ratio of the first N-type MOS transistor MN1 is: 1000 to 3000; the width-to-length ratio of the P-type DMOS transistor DP1 is: 1000 to 3000.

5. The low-voltage fuse trimming circuit applied to high-voltage analog integrated circuits according to claim 1, wherein The pull-down unit includes a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, and a fourth N-type MOS transistor MN4; the gates of the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, the gate of the fourth N-type MOS transistor MN4, and the drain of the fourth N-type MOS transistor MN4 are all connected to the first end of the fuse F1, the drain of the second N-type MOS transistor MN2 is connected to the source of the third N-type MOS transistor MN3, and the drain of the third N-type MOS transistor MN3 is connected to the source of the fourth N-type MOS transistor MN4; the source of the second N-type MOS transistor MN2 is connected to the ground terminal GND.

6. The low-voltage fuse trimming circuit applied to a high-voltage analog integrated circuit according to claim 5, wherein The width-to-length ratios of the second N-type MOS transistor MN2, the third N-type MOS transistor MN3, and the fourth N-type MOS transistor MN4 are: 0.001 to 0.

002.

7. The low-voltage fuse trimming circuit applied to a high-voltage analog integrated circuit according to claim 1, wherein The resistance value of the fuse F1 is: 50 to 200 Ω.

8. The low-voltage fuse trimming circuit applied to a high-voltage analog integrated circuit according to claim 1, wherein When performing fuse programming, the difference between the input voltage values of the high-voltage power supply voltage terminal VDDH and the low-voltage power supply voltage terminal VREG is within 0.3 V.

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