Storage device and operating method thereof

Abstract

The present invention provides a memory device and an operating method thereof, the memory device comprising: a memory device including a plurality of planes and a plurality of pairs of cache buffers and data buffers; and a memory controller configured to control the memory device to transfer first data and second data from the first plane and the second plane to the respective first cache buffers and the second cache buffers, and to control the first cache buffer and the second cache buffer to transfer the first data and the second data to the memory controller. While the first data is being transferred from the first cache buffer to the memory controller, in response to a read request for third data from a host, the memory controller transmits a cache read command to the memory device, so that the memory device reads the third data after the first data is completely transferred to the memory controller and before the second data is transferred from the second cache buffer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0172469, filed on December 10, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to an electronic device, and more particularly, to a storage device and an operating method thereof. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are categorized as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices store data only when power is supplied and lose the stored data when power is interrupted. Volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0006] Non-volatile memory devices are memory devices that do not lose data even when power is interrupted. Non-volatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0007] Various embodiments of the present disclosure provide a memory device for performing an improved read operation and a method of operating the memory device.

[0008] According to one aspect of the present disclosure, a storage device is provided, comprising: a memory device including a plurality of planes and a plurality of pairs of cache buffers and data buffers, the plurality of planes including a plurality of storage blocks storing data, the plurality of pairs being respectively connected to the plurality of planes; and a memory controller configured to control the memory device to transfer first data and second data from the first plane and the second plane to respective first cache buffers and second cache buffers, and configured to control the first cache buffer and the second cache buffer to transfer the first data to the memory controller when the first data and the second data are stored in the first cache buffer and the second cache buffer, wherein while the first data is transferred from the first cache buffer to the memory controller, in response to a read request for third data from a host, the memory controller is further configured to transfer a cache read command to the memory device, so that after the first data is completely transferred from the first cache buffer to the memory controller and before the second data is transferred from the second cache buffer to the memory controller, the memory device reads the third data corresponding to the read request.

[0009] According to another aspect of the present disclosure, a memory device is provided, comprising: a memory device including a plurality of planes and a plurality of page buffers respectively corresponding to the plurality of planes; and a memory controller configured to control the memory device to perform a garbage collection operation of moving valid data included in each of the plurality of planes and a read operation of reading host data corresponding to a read request received from a host, wherein when the memory controller receives a read request for at least one plane from the host while the garbage collection operation is being performed on the plurality of planes, the memory controller is further configured to control the memory device to perform a cache read operation on the at least one plane in response to the read request for the at least one plane.

[0010] According to another aspect of the present disclosure, a storage system is provided, comprising: a memory device including a plurality of planes, the plurality of planes corresponding to a plurality of circuits, respectively, each circuit including a first buffer and a second buffer; and a controller configured to control the memory device to: perform a GC operation of moving garbage collection (GC) data stored in the plane through the second buffer in the circuit; in a case where the GC data is buffered in the second buffer in the circuit, read data from a selected plane in the plane to the first buffer in the circuit corresponding to the selected plane according to a cache read scheme, and provide the read data from the first buffer to the controller through the second buffer in the corresponding circuit according to the cache read scheme as long as the GC data is cleared from the second buffer in the corresponding circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings; however, the embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0012] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may be present. The same reference numerals refer to the same elements throughout.

[0013] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0014] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0015] Figure 3 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0016] Figure 4 is a diagram illustrating a garbage collection operation according to an embodiment of the present disclosure.

[0017] Figure 5 is a diagram illustrating a cache read operation according to an embodiment of the present disclosure.

[0018] Figure 6 is a diagram illustrating a memory device including a plurality of planes and a plurality of page buffers according to an embodiment of the present disclosure.

[0019] Figure 7 is a diagram illustrating a cache buffer and a data buffer according to an embodiment of the present disclosure.

[0020] Figure 8 is a diagram illustrating a method for processing a read request received during a garbage collection operation according to some methods that have been proposed.

[0021] Figure 9 is a diagram illustrating a method for processing a read request received during a garbage collection operation according to an embodiment of the present disclosure.

[0022] Figure 10 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0023] Figure 11 is a diagram illustrating a memory controller according to another embodiment of the present disclosure.

[0024] Figure 12 is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0025] Figure 13 is a diagram illustrating a solid state drive (SSD) according to an embodiment of the present disclosure.

[0026] Figure 14 is a diagram illustrating a user system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] For the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are illustrative only. Embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0028] The present disclosure is applicable to various variations and different shapes, and therefore is described in detail only with reference to specific examples. However, these examples are not limited to specific forms and apply to all variations, equivalent materials, and alternatives. For better understanding, the included drawings are shown in an enlarged form. When describing the embodiments, descriptions of technologies known in the art and not directly related to the present disclosure are omitted. This is to further clarify the main points of the present disclosure without confusion.

[0029] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure.

[0030] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0031] Reference Figure 1 , the memory device 1000 may include a memory device 100 and a memory controller 200 .

[0032] The storage device 1000 may be a device for storing data under the control of a host 2000 such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a display device, a tablet PC, or an in-vehicle infotainment device.

[0033] The storage device 1000 may be manufactured as any of various types of storage devices according to a host interface as a communication scheme with the host 2000. For example, the storage device 1000 may be implemented using any of various types of storage devices such as a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro MMC (micro-MMC), a secure digital (SD) card, a mini SD card, a micro SD card, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a compact flash (CF) card, a smart media card (SMC), a memory stick, etc.

[0034] The memory device 1000 may be implemented in any of various package types. For example, the memory device 1000 may be implemented in any of the following package types: package on package (POP), system-in-package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0035] The memory device 100 may store data or use stored data. The memory device 100 may operate under the control of the memory controller 200. In addition, the memory device 100 may include a plurality of memory dies, and each of the plurality of memory dies may include a memory cell array including a plurality of memory cells for storing data.

[0036] Each of the memory cells may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0037] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells, and one memory block may include multiple pages. A page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100.

[0038] The memory device 100 may be implemented as a double data rate synchronous dynamic random access memory (DDR SDRAM), a fourth generation low power double data rate (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a perpendicular NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for ease of description, the case where the memory device 100 is a NAND flash memory is described.

[0039] The memory device 100 may receive a command and an address from the memory controller 200. The memory device 100 may access an area selected by the received address in the memory cell array. When the memory device 100 accesses the selected area, it may indicate that the memory device 100 performs an operation corresponding to the received command on the selected area. For example, the memory device 100 may perform a write operation (program operation), a read operation, and an erase operation. A program operation may be an operation in which the memory device 100 records data in an area selected by an address. A read operation may indicate an operation in which the memory device 100 reads data from an area selected by an address. An erase operation may indicate an operation in which the memory device 100 erases data stored in an area selected by an address.

[0040] The memory controller 200 may control all operations of the memory device 1000. Specifically, when power is applied to the memory device 1000, the memory controller 200 may execute instructions, such as firmware (FW). The FW may include a host interface layer (HIL), which receives requests input from the host 2000 or outputs responses to the host 2000, a flash translation layer (FTL), which manages operations between the interface of the host 2000 and the interface of the memory device 100, and a flash interface layer (FIL), which provides commands to the memory device 100 or receives responses from the memory device 100.

[0041] The memory controller 200 may receive data and a logical address (LA) from the host 2000 and convert the LA into a physical address (PA) indicating an address of a memory cell included in the memory device 100 where data is to be stored. The LA may be a logical block address (LBA), and the PA may be a physical block address (PBA).

[0042] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. in response to a request from the host 2000. In a program operation, the memory controller 200 may provide a program command, a PBA, and data to the memory device 100. In a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. In an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0043] The memory controller 200 may control the memory device 100 to autonomously perform a program operation, a read operation, or an erase operation regardless of any request from the host 2000. For example, the memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation for performing background operations such as wear leveling, garbage collection, or read reclamation.

[0044] According to an embodiment of the present disclosure, the memory controller 200 can control the memory device 100 to perform a garbage collection operation regardless of any request from the host 2000. The garbage collection operation can be an operation that collects only valid data from the data stored in the victim block, moves the collected valid data to another free block, and erases invalid data to obtain a free block. For example, the garbage collection operation can be configured with the following operations: a garbage read operation that collects valid data stored in the victim block included in the memory device 100, a garbage program operation that programs the collected valid data into the target block, and a garbage erase operation that erases the victim block.

[0045] Furthermore, according to an embodiment of the present disclosure, when the memory controller 200 receives a read request from the host 2000 during garbage collection regardless of any request from the host 2000, the memory controller 200 may control the memory device 100 to prioritize a read operation corresponding to the received read request. Furthermore, the memory controller 200 may control the memory device 100 to perform a cache read operation in response to the read request received during the garbage collection operation.

[0046] The host 2000 may communicate with the storage device 1000 using at least one of various communication standards or interfaces such as Universal Serial Bus (USB), Serial AT Attachment (SATA), High-Speed ​​Interchip (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0047] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0048] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0049] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. The plurality of memory blocks BLK1 to BLKz are connected to a page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells connected to the same word line may correspond to a single page. Therefore, a single memory block may include multiple pages.

[0050] Each of the memory cells included in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0051] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region in the memory cell array 110 under the control of the control logic 130. That is, the peripheral circuit 120 drives the memory cell array 110 under the control of the control logic 130. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0052] Specifically, the peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0053] The row decoder 121 may be connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row lines RL may further include a pipe select line.

[0054] The row decoder 121 may operate under the control of the control logic 130. The row decoder 121 may receive a row address RADD from the control logic 130. Specifically, the row decoder 121 may decode the row address RADD. The row decoder 121 may select at least one memory block from the memory blocks BLK1 to BLKz based on the decoded address. Furthermore, the row decoder 121 may select at least one word line of the selected memory block based on the decoded address, and apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0055] For example, in a program operation, the row decoder 121 may apply a program voltage to a selected word line and apply a program pass voltage having a level different from (e.g., lower than) the program voltage to unselected word lines. In a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and apply a verification pass voltage higher than the verification voltage to unselected word lines. In a read operation, the row decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage higher than the read voltage to unselected word lines.

[0056] In an embodiment, an erase operation of the memory device 100 may be performed in units of memory blocks. In the erase operation, the row decoder 121 may select a memory block according to a decoded address. In the erase operation, the row decoder 121 may apply a reference (e.g., ground) voltage to a word line connected to the selected memory block.

[0057] The voltage generator 122 may operate under the control of the control logic 130. Specifically, the voltage generator 122 may generate a plurality of voltages under the control of the control logic 130 by using an external power supply voltage supplied to the memory device 100. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. under the control of the control logic 130. That is, the voltage generator 122 may generate various operation voltages Vop for program operations, read operations, and erase operations in response to the operation signal OPSIG.

[0058] In an embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory cell array 110.

[0059] In an embodiment, the voltage generator 122 may generate a plurality of voltages by using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving the internal power supply voltage, and generate the plurality of voltages by selectively activating the plurality of pumping capacitors under the control of the control logic 130. In addition, the generated plurality of voltages may be supplied to the memory cell array 110 through the row decoder 121.

[0060] The page buffer group 123 may include first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn may be connected to the memory cell array 110 via first to nth bit lines BL1 to BLn, respectively. Furthermore, the first to nth bit lines BL1 to BLn may operate under the control of the control logic 130. Specifically, the first to nth bit lines BL1 to BLn may operate in response to a page buffer control signal PBSIGNALS. For example, in a read operation or a verify operation, the first to nth page buffers PB1 to PBn may temporarily store data received via the first to nth bit lines BL1 to BLn, or sense the voltage or current of the bit lines BL1 to BLn.

[0061] Specifically, in a programming operation, when a programming voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn can transmit data DATA received through the input / output circuit 125 to the selected memory cells through the first to nth bit lines BL1 to BLn. The memory cells in the selected page can be programmed according to the transmitted data DATA. The memory cells connected to the bit lines to which a program enable voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a program inhibit voltage (e.g., a power supply voltage) is applied can be maintained.

[0062] In a program verification operation, the first to nth page buffers PB1 to PBn may read page data from selected memory cells through the first to nth bit lines BL1 to BLn.

[0063] In a read operation, the first to nth page buffers PB1 to PBn may read data DATA from memory cells in a selected page through the first to nth bit lines BL1 to BLn under the control of the column decoder 124 and output the read data DATA to the input / output circuit 125 .

[0064] In an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn.

[0065] The column decoder 124 may communicate data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may communicate data with the first to nth page buffers PB1 to PBn through the data lines DL or with the input / output circuit 125 through the column lines CL.

[0066] The input / output circuit 125 may transfer a command CMD and an address ADDR received from the memory controller 200 to the control logic 130 , or exchange data DATA with the column decoder 124 .

[0067] In a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit VRYBIT signal and output a pass signal PASS or a fail signal FAIL by comparing the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current.

[0068] The control logic 130 may control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR.

[0069] Furthermore, the control logic 130 may determine whether the verification operation has passed or failed in response to the pass signal PASS or the fail signal FAIL. Furthermore, the control logic 130 may control the page buffer group 123 to temporarily store verification information including the pass signal PASS or the fail signal FAIL in the page buffer group 123. Specifically, the control logic 130 may determine the programming state of the memory cell in response to the pass signal PASS or the fail signal FAIL. For example, when the memory cell operates as a triple-level cell (TLC), the control logic 130 may determine whether the programming state of the memory cell is the erased state E or one of the first to seventh programming states P1 to P7.

[0070] Figure 3 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0071] Reference Figure 3, in a memory block BLKi, a plurality of word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of strings ST connected between bit lines BL1 to BLn and a source line SL. The bit lines BL1 to BLn may be connected to the strings ST, respectively, and the source line SL may be connected to the strings ST in common. The strings ST may be configured identically to one another, and thus the string ST connected to the first bit line BL1 will be described in detail as an example.

[0072] The string ST may include a source select transistor SST, a plurality of memory cells MC1 to MC16, and a drain select transistor DST connected in series between a source line SL and a first bit line BL1. At least one source select transistor SST and at least one drain select transistor DST may be included in one string ST, and one string ST may include a greater number of memory cells than the number of memory cells MC1 to MC16 shown in the drawing.

[0073] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. The memory cells MC1 to MC16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST can be connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings ST can be connected to the drain select line DSL. The gates of the memory cells MC1 to MC16 can be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST can be referred to as a physical page PPG. Therefore, a physical page PPG corresponding to the number of word lines WL1 to WL16 can be included in the memory block BLKi.

[0074] Each of the memory cells may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0075] An SLC can store one bit of data. One physical page PPG of an SLC can store one logical page (LPG) of data. One LPG of data can include a number of data bits corresponding to the number of cells included in one physical page PPG.

[0076] MLC, TLC, and QLC can store two or more bits of data. One physical page PPG can store two or more LPG data.

[0077] In a non-volatile memory device, data stored in a memory cell cannot be rewritten and updated. Therefore, whenever data stored in the memory device 100 is updated or modified, the previously existing data may become old data or invalid data, and the data stored in a newly opened block may become new data or valid data. Alternatively, when an error occurs due to an unknown reason while an internal operation such as a program operation, a read operation, or an erase operation is being performed, the data stored in the corresponding area is unreliable, so as a method of managing bad blocks where errors occur, a garbage collection operation may be performed. Hereinafter, reference will be made to Figure 4 Describes garbage collection operations.

[0078] Figure 4 is a diagram illustrating a garbage collection operation according to an embodiment of the present disclosure.

[0079] Reference Figure 4 , a diagram showing a garbage collection operation performed in the memory device 1000. The garbage collection operation may be an operation of collecting only valid data from among data stored in a sacrifice block, moving the collected valid data to another free block, and erasing invalid data to obtain a free block. For example, the garbage collection operation may be configured with the following operations: a garbage read operation of collecting valid data stored in a sacrifice block included in the memory device 100, a garbage program operation of programming the collected valid data in a target block, and a garbage erase operation of erasing the sacrifice block. Invalid data may refer to data that cannot be used due to updating or moving data, and valid data may be the latest data or normal data that can be used.

[0080] The memory device 1000 may refer to the valid page table VPT to detect the page status (e.g., valid page status, invalid page status, etc.) of each of the plurality of page PGs included in each of the plurality of memory blocks BLK in the memory device 100. The valid page table VPT may include page status information (information for checking whether a page is a valid page) of each of the plurality of page PGs, so that the memory controller 200 may detect the page status (e.g., valid page status, invalid page status, etc.) of each of the plurality of page PGs.

[0081] Furthermore, the memory controller 200 may move the detected multiple valid pages to an open block. For example, each of the first memory block BLK1 and the second memory block BLK2 may include at least one valid page. In addition, the third memory block BLK3 may be an open block or a target block to which the valid pages are to be moved. Specifically, the memory controller 200 may control the memory device 100 to move the valid pages stored in the first memory block BLK1 and the second memory block BLK2 to the third memory block BLK3.

[0082] Furthermore, the memory controller 200 may erase the first memory block BLK1 and the second memory block BLK2. The memory controller 200 may obtain two free blocks by erasing the first memory block BLK1 and the second memory block BLK2, and obtain data storage space by erasing invalid data. Furthermore, the memory controller 200 may organize valid pages and invalid pages by performing address reset.

[0083] The memory controller 200 moves valid pages distributed and stored in the first and second memory blocks BLK1 and BLK2 to the third memory block BLK3. Therefore, a free block and a memory space corresponding to a space of an area storing invalid pages can be obtained.

[0084] Figure 5 is a diagram illustrating a cache read operation according to an embodiment of the present disclosure.

[0085] Reference Figure 5 , a plurality of pages included in the memory cell array 100 can be sequentially read to the page buffer group 123. Specifically, the memory device 100 reads data stored in the memory cell array 110 under the control of the memory controller 200. Memory cells connected to the same word line may correspond to one page, and the memory device 100 may read the stored data in units of one page. For example, the memory device 100 may read the Nth page and read the (N+1)th page.

[0086] The memory device 100 can perform a cache read operation of reading the next page data while outputting a specific page data by using the page buffer group 123. Specifically, the memory device 100 can read the Nth page data stored in the Nth page to the page buffer group 123 while outputting the (N-1)th page data temporarily stored in the page buffer group 123. Then, when the (N-1)th page data is completely output, the memory device 100 can output the Nth page data temporarily stored in the page buffer group 123. The memory device 100 can read the (N+1)th page data stored in the (N+1)th page to the page buffer group 123 while outputting the Nth page data temporarily stored in the page buffer group 123.

[0087] That is, while a specific page of data is output, the next page of data is input (or read) to the page buffer group 123 , and thus the memory device 100 can reduce a read time for reading data stored in all pages.

[0088] Figure 6is a diagram illustrating a memory device including a plurality of planes and a plurality of page buffers according to an embodiment of the present disclosure.

[0089] Reference Figure 6 , shows a memory device 100 including a memory cell array 110 , a page buffer group 123 , and a control logic 130 .

[0090] The memory cell array 110 and the page buffer group 123 can be divided into a plurality of planes and a plurality of page buffer circuits (also referred to as page buffers) connected to each other through bit lines BL. That is, each of the plurality of planes and each of the plurality of page buffer circuits can form a pair to operate as a plane unit. For example, the first plane 110a and the first page buffer circuit 123a can form a pair to operate as a plane unit, the second plane 110b and the second page buffer circuit 123b can form a pair to operate as a plane unit, the third plane 110c and the third page buffer circuit 123c can form a pair to operate as a plane unit, and the fourth plane 110d and the fourth page buffer circuit 123d can form a pair to operate as a plane unit. The plurality of planes and the plurality of page buffer circuits included in the memory device 100 can be divided into a plurality of corresponding pairs, and each pair can be independently operated as a plane unit.

[0091] The control logic 130 may control the peripheral circuit including the page buffer group 123 to independently perform a read operation on the memory cells included in each of the plurality of planes. For example, the control logic 130 may control the peripheral circuit to perform a read operation on each of the first to fourth planes 110a to 110d.

[0092] Furthermore, the control logic 130 may control the peripheral circuit to independently perform a read operation on each plane. Data read from each plane is temporarily stored in a page buffer circuit corresponding to each plane, so that a read operation may be independently performed on each plane.

[0093] Figure 7 is a diagram illustrating a cache buffer and a data buffer according to an embodiment of the present disclosure.

[0094] Reference Figure 7 , shows the first page buffer circuit 123a among the plurality of page buffer circuits included in the page buffer group 123. Figure 7 Only the first page buffer circuit 123a is shown in FIG. Figure 6 The second to fourth page buffer circuits 123b to 123d shown in FIG. Figure 7The first page buffer circuit 123 a may include a cache buffer 1231 and a data buffer 1233 .

[0095] The first page buffer circuit 123a can be connected to the memory cell array 110 through the bit line BL. In a read operation, the first page buffer circuit 123a can operate under the control of the control logic 130. Specifically, the first page buffer circuit 123a can operate in response to the page buffer control signal PBSIGNALS. The first page buffer circuit 123a can exchange data with the column decoder 124 through the data line DL.

[0096] In an embodiment of the present disclosure, the cache buffer 1231 and the data buffer 1233 included in the first page buffer circuit 123 a may temporarily store data stored in memory cells connected to the bit lines BL.

[0097] The cache buffer 1231 can temporarily store valid data or host data and output the temporarily stored valid data or temporarily stored host data to a data line. Specifically, the cache buffer 1231 can be connected to the data line DL and output the data to the outside. According to an embodiment of the present disclosure, the valid data or host data temporarily stored in the cache buffer 1231 can be output to the data line DL, and the output data can be transmitted to the memory controller 200 through the input / output circuit 125.

[0098] When data is output through cache buffer 1231, data buffer 1233 can temporarily store subsequent data. Specifically, one end of data buffer 1233 can be connected to bit line BL, and the other end of data buffer 1233 can be connected to cache buffer 1231. Data buffer 1233 can sense data stored in memory cell array 110 through bit line BL and temporarily store the sensed data. While outputting valid data or host data, data buffer 1233 can temporarily store subsequent data. Because data buffer 1233 is not directly connected to data line DL, data stored in data buffer 1233 can be moved to cache buffer 1231 and then output.

[0099] The memory device 100 can perform reference operations by using the page buffer group 123. Figure 5Specifically, the memory device 100 can perform a cache read operation by using the cache buffer 1231 and the data buffer 1233 included in the first page buffer group 123a. For example, while valid data is output from the cache buffer 1231 to the data line DL, the memory device 100 can perform a cache read operation of reading subsequent data to the data buffer 1233.

[0100] According to an embodiment of the present disclosure, while transmitting valid data to the memory controller 200 through the data line DL, host data corresponding to the host request is read to the data buffer 1233 and output preferentially, so that the memory device 100 can reduce the read time according to the read request of the host 2000.

[0101] Figure 8 is a diagram illustrating a conventional method for processing a read request received during a garbage collection operation.

[0102] Reference Figure 8 In some methods that have been proposed, when a storage device receives a read request from a host while performing a garbage collection operation, the storage device processes the read request.

[0103] according to Figure 8 In the illustrated embodiment, the memory controller 200′ may transmit a GC CMD command to cause the memory device 100′ to perform a garbage collection operation regardless of any request from the host. Specifically, the memory controller 200′ may transmit the GC CMD command to collect valid data GC Data in the memory cell array 110′ divided into a plurality of planes (e.g., first to fourth planes P1 to P4).

[0104] according to Figure 8 In the illustrated embodiment, the memory device 100′ may read valid data from a victim block included in each of the plurality of planes in response to a command GC CMD received from the memory controller 200′. Specifically, the memory device 100′ may temporarily store the valid data GC Data in a page buffer circuit corresponding to each of the plurality of planes in the page buffer group 123′ in response to the command GC CMD received from the memory controller 200′.

[0105] Furthermore, the memory device 100' can transmit valid data GC Data from each of the page buffer circuits corresponding to the multiple planes to the memory controller 200'. Specifically, each page buffer circuit can randomly output valid data under the control of the memory controller 200' or the control logic. For example, valid data can be output from the page buffer circuit corresponding to the third plane to the channel CH, valid data can be output from the page buffer circuit corresponding to the second plane to the channel CH, valid data can be output from the page buffer circuit corresponding to the fourth plane to the channel CH, and valid data can be output from the page buffer circuit corresponding to the first plane to the channel CH.

[0106] according to Figure 8 In the illustrated embodiment, when the memory controller 200' receives a first read request from the host (e.g., at a first time t1) while valid data is being transferred from the page buffer circuit corresponding to the third plane to the memory controller 200', the memory controller 200' may transmit a first read command RD CMD1 to the memory device 100' in response to the host's first read request after outputting the valid data stored in the multiple planes to the channel CH. Specifically, the memory controller 200' may transmit the first read command RD CMD1 to the memory device 100' after an internal operation (e.g., a garbage collection operation) in the page buffer group 123' of the memory device 100' has completed.

[0107] In addition, after all valid data is output from the page buffer circuits corresponding to the first to fourth planes, the memory device 100' may perform a first read operation in response to the first read command RD CMD1. Specifically, the memory device 100' may read the data RD1 Data corresponding to the first read command RD CMD1 into the page buffer group 123'. In addition, when the memory device 100' receives a second read request from the host (e.g., at a second time t2) while reading the data corresponding to the first read command RD CMD1 into the page buffer group 123', after the read operation corresponding to the first read command RD CMD1 is completed, the memory controller 200' may transmit a second read command RD CMD2 to the memory device 100'. When the read operation corresponding to the first read command RD CMD1 is completed, the memory device 100' may perform a read operation corresponding to the second read command RD CMD2.

[0108] That is to say, according to Figure 8The embodiment shown processes a read request received from the host only after performing internal operations (eg, garbage collection operations) regardless of any request from the host. Therefore, the read request received from the host may be delayed due to the internal operations.

[0109] Figure 9 is a diagram illustrating a method for processing a read request received during a garbage collection operation according to an embodiment of the present disclosure.

[0110] Reference Figure 9 , shows a method in which the storage device 1000 processes a read request when the storage device 1000 receives a read request from the host 2000 while performing a garbage collection operation.

[0111] According to an embodiment of the present disclosure, the memory controller 200 may transmit a command GC CMD to cause the memory device 100 to perform a garbage collection operation regardless of any request from the host. Specifically, the memory controller 200 may transmit a command GC CMD to collect valid data GC Data in the memory cell array 110 divided into a plurality of planes (e.g., first to fourth planes P1 to P4).

[0112] According to an embodiment of the present disclosure, the memory device 100 may read valid data from a victim block included in each of the plurality of planes in response to a command GC CMD received from the memory controller 200. Specifically, the memory device 100 may temporarily store the valid data GC Data in a cache buffer 1231 corresponding to each of the plurality of planes in the page buffer group 123 in response to the command GC CMD received from the memory controller 200.

[0113] Furthermore, the memory device 100 may transmit valid data GC Data from the cache buffer 1231 corresponding to each of the plurality of planes to the memory controller 200. Specifically, each cache buffer may randomly output valid data under the control of the memory controller 200 or the control logic 130. For example, valid data may be output from the cache buffer 1231 corresponding to the second plane to the channel CH, valid data may be output from the cache buffer 1231 corresponding to the third plane to the channel CH, valid data may be output from the cache buffer 1231 corresponding to the fourth plane to the channel CH, and valid data may be output from the cache buffer 1231 corresponding to the first plane to the channel CH.

[0114] When the memory controller 200 receives a first read request for the second plane from the host 2000 while transmitting valid data in the cache buffer 1231 corresponding to the second plane or the third plane to the memory controller 200, the memory controller 200 may transmit a first read command RD CMD1 to the memory device 100 in response to the first read request from the host 2000. The memory controller 200 may control the memory device 100 to perform a cache read operation in response to the first read request. Specifically, the memory device 100 may read the first host data RD1Data(P2) stored in the second plane to the data buffer 1233 in response to the first read command RD CMD1. In addition, the memory controller 200 may check whether the valid data GCData(P2) has been output from the cache buffer 1231 corresponding to the second plane. When valid data GC Data (P2) is output from the cache buffer 1231 corresponding to the second plane P2, the memory controller 200 may control the memory device 100 to move the first host data RD1 Data (P2) temporarily stored in the data buffer 1233 corresponding to the second plane P2 to the cache buffer 1231 corresponding to the second plane P2. Specifically, the memory controller 200 may transmit a command 3Fh to the memory device 100, the command 3Fh being used to control the memory device 100 to move the first host data RD1 Data (P2) stored in the data buffer 1233 within the page buffer circuit 123b corresponding to the second plane P2 to the cache buffer 1231. In response to the command 3Fh received from the memory controller 200, the memory device 100 may move the first host data RD1 Data (P2) stored in the data buffer 1233 within the page buffer circuit 123b corresponding to the second plane P2 to the cache buffer 1231. The first host data RD1 Data( P2 ) moved to the cache buffer 1231 corresponding to the second plane P2 may be provided to the memory controller 200 through the channel CH.

[0115] In addition, the memory controller 200 may control the memory device 100 to output valid data from the cache buffer 1231 corresponding to other planes (eg, the first plane and the fourth plane) to the channel CH.

[0116] When a second read request for any plane among the plurality of planes is received from the host 2000 before the valid data GC Data(P1) is output from the cache buffer 1231 to the channel CH, the memory controller 200 may control the memory device 100 to perform a read operation corresponding to the second read request. Specifically, the memory controller 200 may control the memory device 100 to perform the read operation corresponding to the second read request by transmitting a second read command RD(Pi)CMD2 corresponding to the second read request to the memory device 100.

[0117] According to an embodiment of the present disclosure, when the memory controller 200 receives a read request from the host 2000 while valid data is being output from the cache buffers 1231 corresponding to a plurality of planes, the memory controller 200 may control the memory device 100 to prioritize the read request received from the host 2000. For example, this may be the case where valid data is temporarily stored in each of the cache buffers 1231 corresponding to the first to fourth planes, and all valid data has not yet been transferred from the cache buffers 1231 to the memory controller 200. When the memory controller 200 receives a read request for the third plane from the host 2000, the memory controller 200 may control the memory device 100 to transfer the valid data stored in the cache buffer 1231 corresponding to the third plane to the memory controller 200. The memory controller 200 may control the memory device 100 to read the host data from the third plane to the data buffer 1233 corresponding to the third plane. Moreover, when the cache buffer 1231 corresponding to the third plane outputs valid data to the memory controller 200 and therefore the cache buffer 1231 is empty, the memory controller 200 can control the memory device 100 to move the host data temporarily stored in the data buffer 1233 corresponding to the third plane to the cache buffer 1231 corresponding to the third plane.

[0118] Figure 10 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0119] Reference Figure 10 , the memory controller 200 may include a garbage collection controller 210 , a read operation controller 220 , and a scheduler 230 .

[0120] The garbage collection controller 210 may control the memory device 100 to perform a garbage collection operation on each of a plurality of planes included in the memory device 100. Specifically, the garbage collection controller 210 may control the memory device 100 to autonomously perform a program operation, a read operation, or an erase operation regardless of any request from the host 2000. For example, the garbage collection operation may be configured with the following operations: a garbage read operation to collect valid data stored in a victim block included in the memory device 100, a garbage program operation to program the collected valid data in a target block, and a garbage erase operation to erase the victim block. In some embodiments, the garbage collection controller 210 may control the memory device 100 to collect valid data included in each of the planes in the memory device 100 with reference to a valid page table (VPT).

[0121] Specifically, the garbage collection controller 210 can control the memory device 100 to temporarily store the valid data included in each of the multiple planes in a page buffer in sequence, and randomly output the temporarily stored valid data to the data line. For example, the garbage collection controller 210 can transmit a garbage read operation command to the first to fourth planes to perform a garbage read operation to collect the valid data included in the first to fourth planes respectively. In addition, the memory device 100 can temporarily store the valid data included in each plane in sequence in the page buffer corresponding to each plane under the control of the garbage collection controller 210. After the memory device 100 temporarily stores the valid data corresponding to each plane in the page buffer corresponding to each plane, the memory device 100 can transmit the valid data to the memory controller 200 by using the cache buffer 1231 corresponding to each plane.

[0122] The read operation controller 220 can control the memory device 100 to perform a cache read operation. The cache read operation can be an operation that temporarily stores data in at least two buffers. Specifically, while data is temporarily stored in the cache buffer 1231, the read operation controller 220 can control the memory device 100 to sense subsequent data and load the subsequent data into the data buffer 1233. Furthermore, the read operation controller 220 can control the memory device 100 to first output the data temporarily stored in the cache buffer 1231 and then move the subsequent data temporarily stored in the data buffer 1233 to the cache buffer 1231.

[0123] For example, when the read operation controller 220 receives a read request from the host 2000 in a state where valid data is temporarily stored in the cache buffers 1231 corresponding to the plurality of planes, respectively, the read operation controller 220 may control the memory device 100 to sense host data from the selected plane in response to the read request and load the sensed host data into the data buffer 1233 corresponding to the selected plane. Furthermore, the read operation controller 220 may control the memory device 100 to output the valid data temporarily stored in the cache buffer 1231 corresponding to the selected plane and then move the host data temporarily stored in the data buffer 1233 to the cache buffer 1231 corresponding to the selected plane.

[0124] The scheduler 230 can determine the output order of data output from the page buffers. Specifically, the scheduler 230 can determine the output order of valid data and host data output from the page buffers corresponding to the first to fourth planes, respectively. For example, when the scheduler 230 receives a read request for the first plane from the host 2000 while valid data included in each of the first to fourth planes is temporarily stored in the cache buffers 1231 corresponding to the first to fourth planes, respectively, the scheduler 230 can determine the output order so that the host data corresponding to the first plane is output earlier than the valid data corresponding to the second to fourth planes.

[0125] Furthermore, in order to prioritize read requests received from the host 2000, the scheduler 230 may determine an output order such that valid data in the plane corresponding to the read request is output earlier than valid data corresponding to other planes. For example, when the scheduler 230 receives a read request for the first plane from the host 2000 while valid data included in each of the first to fourth planes is temporarily stored in the cache buffer 1231 corresponding to the first to fourth planes, the scheduler 230 may determine an output order such that valid data corresponding to the first plane is output earlier than valid data corresponding to the second to fourth planes.

[0126] Figure 11 is a diagram illustrating a memory controller according to another embodiment of the present disclosure.

[0127] Reference Figure 11 , the memory controller 1300 may include a processor 1310 , a RAM 1320 , an ECC circuit 1330 , a ROM 1360 , a host interface 1370 , and a flash memory interface 1380 . Figure 11 The memory controller 1300 shown may be Figure 1 or Figure 10 An embodiment of a memory controller 200 is shown.

[0128] The processor 1310 can communicate with the host 2000 by using the host interface 1370 and perform logical operations to control the operation of the memory controller 1300. For example, the processor 1310 can load program commands, data files, data structures, etc. based on a request received from the host 2000 or an external device, and perform various operations or generate commands and addresses. For example, the processor 1310 can generate various commands for program operations, read operations, erase operations, suspend operations, and parameter setting operations.

[0129] Furthermore, the processor 1310 may perform the function of a flash translation layer (FTL). The processor 1310 may convert a logical block address (LBA) provided by the host 2000 into a physical block address (PBA) through the FTL. The FTL may receive an input LBA and convert the LBA into a PBA using a mapping table. There are several address mapping methods for the FTL depending on the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

[0130] Also, the processor 1310 may generate a command without any request from the host 2000. For example, the processor 1310 may generate a command for background operations such as wear leveling of the memory device 100 and garbage collection of the memory device 100.

[0131] The RAM 1320 may be used as a buffer memory, a working memory, or a cache memory of the processor 1310. Also, the RAM 1320 may store codes and commands executed by the processor 1310. The RAM 1320 may store data processed by the processor 1310. Also, the RAM 1320 may be implemented as a static RAM (SRAM) or a dynamic RAM (DRAM).

[0132] The ECC circuit 1330 can detect errors in programming operations or read operations and correct the detected errors. Specifically, the ECC circuit 1330 can perform error correction operations based on error correction codes (ECC). Moreover, the ECC circuit 1330 can perform ECC encoding based on the data to be written to the memory device 100. The data to which the ECC encoding is performed can be transmitted to the memory device 100 via the flash memory interface 1380. Furthermore, the ECC circuit 1330 can perform ECC decoding on the data received from the memory device 100 via the flash memory interface 1380.

[0133] ROM 1360 may be used as a storage unit for storing various information required for the operation of memory controller 1300. Specifically, ROM 1360 may include a mapping table, and physical-to-logical address information and logical-to-physical address information may be stored in the mapping table. Furthermore, ROM 1360 may be controlled by processor 1310.

[0134] The host interface 1370 may include a protocol for exchanging data between the host 2000 and the memory controller 1300. Specifically, the host interface 1370 may communicate with the host 2000 through at least one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a proprietary protocol.

[0135] The flash interface 1380 may communicate with the memory device 100 by using a communication protocol under the control of the processor 1310. Specifically, the flash interface 1380 may communicate commands, addresses, and data with the memory device 100 through a channel. For example, the flash interface 1380 may include a NAND interface.

[0136] Figure 12 is a diagram illustrating a memory card system according to an embodiment of the present disclosure.

[0137] Reference Figure 12 , the memory card system 3000 includes a memory controller 3100 , a memory device 3200 , and a connector 3300 .

[0138] The memory controller 3100 may be connected to the memory device 3200. The memory controller 3100 may access the memory device 3200. For example, the memory controller 3100 may control read operations, write operations, erase operations, and background operations on the memory device 3200. The memory controller 3100 may provide an interface between the memory device 3200 and the host. Furthermore, the memory controller 3100 may drive firmware for controlling the memory device 3200.

[0139] For example, the memory controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0140] The memory controller 3100 may communicate with an external device through the connector 3300. The memory controller 3100 may communicate with an external device (e.g., a host) according to a specific communication protocol. The memory controller 3100 may communicate with an external device through at least one of various communication protocols such as Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WiFi, Bluetooth, and NVMe.

[0141] The memory device 3200 may be implemented using various nonvolatile memory devices such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0142] The memory controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the memory controller 3100 and the memory device 3200 may constitute memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), Compact Flash (CF) cards, Smart Media Cards (SM and SMC), Memory Sticks, Multimedia Cards (MMC, RS-MMC, Micro MMC, and eMMC), SD cards (SD, Mini SD, Micro SD, and SDHC), and Universal Flash Storage (UFS).

[0143] Figure 13 is a diagram illustrating a solid state drive (SSD) according to an embodiment of the present disclosure.

[0144] Reference Figure 13 , an SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges a signal SIG with the host 4100 via a signal connector 4001 and receives power PWR via a power connector 4002. The SSD 4200 includes an SSD controller 4210, a plurality of flash memories 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0145] In an embodiment, the SSD controller 4210 may be used as a reference Figure 1The memory controller 200 described above. The SSD controller 4210 may control the plurality of flash memories 4221 to 422n in response to a signal SIG received from the host 4100. The signal SIG may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal SIG may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), MultiMedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0146] The auxiliary power supply 4230 can be connected to the host 4100 via the power connector 4002. The auxiliary power supply 4230 can receive power PWR input from the host 4100 and be charged using the power PWR. When the power supply from the host 4100 is unstable, the auxiliary power supply 4230 can provide power to the SSD 4200. The auxiliary power supply 4230 can be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 can be located on the motherboard and provide auxiliary power to the SSD 4200.

[0147] The buffer memory 4240 can operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 can temporarily store data received from the host 4100 or data received from the plurality of flash memories 4221 to 422n, or temporarily store metadata (e.g., a mapping table) of the flash memories 4221 to 422n. The buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0148] Figure 14 is a diagram illustrating a user system according to an embodiment of the present disclosure.

[0149] Reference Figure 14 , the user system 5000 includes an application processor 5100 , a memory module 5200 , a network module 5300 , a storage module 5400 and a user interface 5500 .

[0150] The application processor 5100 may drive components, an operating system (OS), user programs, etc. included in the user system 5000. The application processor 5100 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 5000. The application processor 5100 may be provided as a system on chip (SoC).

[0151] The memory module 5200 can operate as a main memory, working memory, buffer memory, or cache memory of the user system 5000. The memory module 5200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. The application processor 5100 and the memory module 5200 may be packaged based on a package-on-package (PoP) and provided as one semiconductor package.

[0152] The network module 5300 can communicate with external devices. The network module 5300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi. The network module 5300 may be included in the application processor 5100.

[0153] The storage module 5400 can store data. For example, the storage module 5400 can store data received from the application processor 5100. Alternatively, the storage module 5400 can transmit the data stored therein to the application processor 5100. The storage module 5400 can be implemented using a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory with a three-dimensional structure. The storage module 5400 can be configured as a removable drive, such as a memory card or an external drive of the user system 5000.

[0154] The storage module 5400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be connected to the reference Figure 1 The memory device 100 described in the foregoing description operates identically. The memory module 5400 may be configured similarly to the memory device 100 described in the foregoing description. Figure 1 The described memory device 1000 operates identically.

[0155] The user interface 5500 may include an interface for inputting data or commands to the application processor 5100 or outputting data to an external device. The user interface 5500 may include user input interfaces such as a keyboard, a keypad, buttons, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 5500 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0156] According to the present disclosure, a memory device for performing an improved read operation and an operating method of the memory device are provided.

[0157] Although the present disclosure has been shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0158] In the above embodiments, all steps may be selectively performed or some or all steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples to facilitate understanding of the present disclosure, and the present disclosure is not limited thereto. In other words, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0159] Embodiments of the present disclosure have been described in the accompanying drawings and the specification. Although specific terms are used herein, these are only for the purpose of describing embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure. Further, it should be noted that, as will be appreciated by those skilled in the art based on the present disclosure, the present disclosure may be implemented in various ways by replacement, change, and modification, as long as they fall within the scope of the appended claims.

Claims

1. A storage device comprising: a memory device comprising a plurality of planes including a plurality of memory blocks storing data and a plurality of pairs of a cache buffer and a data buffer, the plurality of planes comprising a plurality of memory blocks storing data, the plurality of pairs being coupled to the plurality of planes, respectively; as well as a memory controller that controls the memory device to transfer first data and second data from a first plane and a second plane to respective first and second cache buffers, and when the first and second data are stored in the first and second cache buffers, controls the first and second cache buffers to transfer the first data to the memory controller, wherein while the first data is transferred from the first cache buffer to the memory controller, in response to a read request for third data from a host, the memory controller further transmits a cache read command to the memory device, so that after the first data is completely transferred from the first cache buffer to the memory controller and before the second data is transferred from the second cache buffer to the memory controller, the memory device reads the third data corresponding to the read request, The storage device performs a cache read operation in response to the cache read command, the cache read operation storing data in at least two buffers including the data buffer and the cache buffer, and The cache read operation outputs the first page data from the cache buffer to the data line when reading the second page data into the data buffer, and then moves the second page data stored in the data buffer to the cache buffer and then outputs it to the data line.

2. The storage device according to claim 1, wherein the cache buffer stores data stored in the memory device before transmitting the data to the memory controller, and The data buffer is connected to the cache buffer, and the data buffer stores the stored data before transferring the data stored in the memory device to the cache buffer.

3. The memory device according to claim 1, wherein in response to the cache read command, the memory device reads the third data from a third plane to a third data buffer coupled to the third plane, and simultaneously transfers the data stored in the third cache buffer to the memory controller.

4. The memory device according to claim 3, wherein when the data stored in the third cache buffer is transferred from the third cache buffer to the memory controller, the memory controller controls the memory device to transfer the third data from the third data buffer to the third cache buffer. The storage device according to claim 1 , wherein the first data and the second data are valid data for a garbage collection operation.

6. The memory device according to claim 1, wherein the memory controller comprises: a garbage collection controller that controls the memory device to perform a garbage collection operation that obtains a free block in each of the plurality of planes; a read operation controller that controls the memory device to perform the cache read operation by using the cache buffer and the data buffer; as well as A scheduler determines an output order of valid data and host data output from page buffers respectively including a plurality of pairs of the cache buffer and the data buffer.

7. The memory device according to claim 6, wherein the garbage collection controller controls the memory device to temporarily store valid data included in each of the plurality of planes in sequence in the page buffer and randomly output the valid data from the page buffer to the data line.

8. The storage device of claim 6, wherein when the scheduler receives a read request for the third data from the host while transmitting the first data to the memory controller, the scheduler determines the output order so that the third data is transmitted earlier than the second data. 9 . The storage device according to claim 8 , wherein the scheduler determines the output order so that valid data stored in the third cache buffer is output earlier than the third data.

10. A storage device comprising: A memory device comprising a plurality of planes and a plurality of page buffers respectively corresponding to the plurality of planes; as well as a memory controller that controls the memory device to perform a garbage collection operation of moving valid data included in each of the plurality of planes and a read operation of reading host data corresponding to a read request received from a host, wherein when the memory controller receives a read request for at least one plane from the host while the garbage collection operation is being performed on the plurality of planes, the memory controller further controls the memory device to perform a cache read operation on the at least one plane in response to the read request for the at least one plane, The cache read operation is to store data in each of the page buffers, each of the page buffers including: a cache buffer that temporarily stores the valid data or the host data and outputs the temporarily stored valid data or the temporarily stored host data to a data line; as well as A data buffer temporarily stores the host data to output the host data to the cache buffer while the cache buffer outputs the valid data.

11. The memory device according to claim 10, wherein when the memory controller receives a read request for the at least one plane before the valid data is output from the cache buffer corresponding to the at least one plane to the data line, the memory controller controls the memory device to output the valid data from the cache buffer corresponding to the at least one plane to the data line, and then outputs host data corresponding to the read request for the at least one plane to the data line through the data buffer and the cache buffer.

12. The memory device of claim 11 , wherein the memory controller controls the memory device to output the valid data from the cache buffer corresponding to the at least one plane to the data line, and then move host data corresponding to a read request for the at least one plane from the data buffer to the cache buffer.

13. The memory device according to claim 10 , wherein when the memory controller receives a read request for the at least one plane while reading the valid data to the cache buffers respectively corresponding to the plurality of planes, the memory controller controls the memory device to output the valid data corresponding to the at least one plane from the cache buffer corresponding to the at least one plane to the data line, and then outputs host data corresponding to the read request for the at least one plane to the data line through the data buffer and the cache buffer corresponding to the at least one plane.

14. The memory device of claim 13 , wherein the memory controller controls the memory device to output host data corresponding to a read request for the at least one plane to the data line before outputting valid data corresponding to other planes among the plurality of planes except the at least one plane to the data line.

15. The memory device according to claim 10, wherein the memory controller comprises: a garbage collection controller that controls the memory device to perform the garbage collection operation on each of the plurality of planes; a read operation controller that controls the memory device to perform the cache read operation of reading the host data from the at least one plane by using at least two buffers included in a page buffer corresponding to the at least one plane; as well as A scheduler determines an output order of the valid data and the host data output from the page buffers respectively corresponding to the plurality of planes.

16. The memory device of claim 15, wherein the garbage collection controller controls the memory device to temporarily store valid data from the plurality of planes in respective page buffers during the garbage collection operation and randomly output the temporarily stored valid data to the data lines. 17 . The storage device according to claim 15 , wherein the scheduler determines the output order so that valid data corresponding to the at least one plane is output earlier than valid data corresponding to other planes other than the at least one plane among the plurality of planes.

18. The storage device of claim 15, wherein the scheduler determines the output order so that host data from the at least one plane is output earlier than valid data corresponding to other planes among the plurality of planes except the at least one plane.

19. A storage system comprising: A memory device comprising a plurality of planes, the plurality of planes respectively corresponding to a plurality of circuits, each circuit comprising a first buffer and a second buffer; as well as A controller controls the memory device to: performing a GC operation of moving garbage collected data (GC data) stored in the plane through the second buffer in the circuit, In a case where the GC data is buffered in the second buffer in the circuit, reading data from a selected one of the planes to a first buffer in the circuit corresponding to the selected plane according to a cache read scheme, and providing read data from the first buffer to the controller through the second buffer in the corresponding circuit as soon as the GC data is flushed from the second buffer in the corresponding circuit according to the cache read scheme, The cache read scheme outputs read data from the first buffer to the data line when reading the GC data to the second buffer, and then moves the GC data stored in the second buffer to the first buffer and then outputs it to the data line.

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