Memory Diagnosis Method, Device, System, Chip and Medium

Abstract

The present application provides a memory diagnosis method, apparatus, system, chip and medium. The method includes: assigning values to P flip-flops on a scan chain; sending a first signal to a first flip-flop group to cause the first flip-flop group to write data to be written to a target address of a memory, where the first flip-flop group includes flip-flops on the scan chain respectively connected to an enable port, an address port and a write data port of the memory; setting the working mode of the scan chain to a capture mode and sending a second signal to a second flip-flop group to cause the second flip-flop group to read data from the target address, where the second flip-flop group includes flip-flops on the scan chain respectively connected to the enable port, the address port and a read data port of the memory, and the flip-flops in the first flip-flop group and the second flip-flop group are completely different; obtaining the data read from the target address, and diagnosing the memory according to the data read from the target address and the data to be written. The present application can improve the diagnosis efficiency of the memory.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular, to a memory diagnosis method, apparatus, system, chip, and medium. Background Art

[0002] With the improvement of manufacturing processes, the complexity of memories has increased accordingly, and thus the diagnosis of memories has become more and more complex.

[0003] In existing memory diagnosis technologies, first, a plurality of scannable flip-flops are connected in series to form a scan chain; then, a certain number of flip-flops on the scan chain are selected and connected to the enable port, address port, read data port, and write data port of the memory. When diagnosing the memory, first, the scan chain is set to the shift mode, and all flip-flops on the scan chain are assigned values by shifting; after the shifting is completed, the scan chain is set to the capture mode to transfer the values of the flip-flops connected to the enable port, address port, and write data port to the memory, that is, a write operation is performed on the memory. Then, the scan chain is set to the shift mode again, and all flip-flops on the scan chain are assigned values by shifting; after the shifting is completed, the scan chain is set to the capture mode to transfer the values of the flip-flops connected to the enable port and address port to the memory, where the value transferred by the flip-flop connected to the address port is the read address. Further, read data is read from the read address through the read data port, that is, a read operation is performed on the memory. Then, the scan chain is set to the shift mode, and the values of all flip-flops on the scan chain are shifted out to obtain the above-mentioned read data, and the write data and read data corresponding to the above-mentioned read address are compared to diagnose the memory, that is, a comparison operation is performed.

[0004] However, in the prior art, when diagnosing a memory, three steps of a write operation, a read operation, and a comparison operation need to be performed. Each time the above-mentioned operation is performed, the scan chain needs to perform a shift operation, so the scan chain needs to be shifted three times, and the shift operation takes a long time, resulting in a low diagnosis efficiency of the memory. Summary of the Invention

[0005] The present application provides a memory diagnosis method, apparatus, system, chip, and medium, which can improve the diagnosis efficiency of the memory.

[0006] In a first aspect, the present application provides a memory diagnosis method. The scan chain is composed of P flip-flops connected in series. Among them, some or all of the flip-flops on the scan chain are divided into multiple flip-flop groups. Each flip-flop group is respectively connected to multiple ports of the memory, and the host computer is connected to the scan chain. The method is applied to the host computer and includes: assigning values to the P flip-flops on the scan chain; setting the working mode of the scan chain to the capture mode, and sending a first signal to the first flip-flop group to enable the first flip-flop group to write the data to be written to the target address of the memory. The first flip-flop group includes the flip-flops on the scan chain that are respectively connected to the enable port, address port, and write data port of the memory; sending a second signal to the second flip-flop group to enable the second flip-flop group to read data from the target address. The second flip-flop group includes the flip-flops on the scan chain that are respectively connected to the enable port, address port, and read data port of the memory. The flip-flops in the first flip-flop group and the second flip-flop group are completely different; obtaining the data read from the target address, and diagnosing the memory according to the data read from the target address and the data to be written.

[0007] Through this method, the number of scan chain shifts can be reduced, the diagnosis time of the memory can be shortened, and thus the diagnosis efficiency of the memory can be improved.

[0008] Optionally, sending the first signal to the first flip-flop group includes: sending the first signal to the first flip-flop group according to the count value of the counter; sending the second signal to the second flip-flop group includes: sending the second signal to the second flip-flop group according to the count value of the counter.

[0009] Through this method, read and write operations on the memory can be performed according to the count value of the counter, and thus the number of read and write operations on the memory can be controlled.

[0010] Optionally, sending the first signal to the first flip-flop group according to the count value of the counter includes: when the count value of the counter is a preset value, sending the first signal to the first flip-flop group; sending the second signal to the second flip-flop group according to the count value of the counter includes: when the count value of the counter is a preset value, sending the second signal to the second flip-flop group.

[0011] Through this method, single-cycle read and write operations on the memory can be realized.

[0012] Optionally, sending the first signal to the first flip-flop group according to the count value of the counter includes: when the count value of the counter is a preset value, sending the first signal to the first flip-flop group; sending the second signal to the second flip-flop group according to the count value of the counter includes: when the count value of the counter is the preset value plus M, sending the second signal to the second flip-flop group, where M is an integer greater than or equal to 1.

[0013] By this method, when the count value of the counter reaches a preset value, a first signal is sent to the first trigger group, and when the count value of the counter reaches the preset value plus M (where M is an integer greater than or equal to 1), a second signal is sent to the second trigger group, enabling continuous read operations or continuous write operations on the memory, and the number and order of read or write operations on the memory can be set, improving the flexibility and operability of memory diagnosis.

[0014] Optionally, the memory, scan chain, and counter are integrated on a single chip; wherein, each time the clock signal of the chip reaches a rising clock edge, the count value of the counter is incremented by one.

[0015] By this method, the memory, scan chain, and counter are integrated on a single chip, eliminating the need for additional scan chain or counter circuits outside the chip, thereby simplifying the memory diagnostic circuit; each time the clock signal of the chip reaches a rising clock edge, the count value of the counter is incremented by one, ensuring that the change in the count value of the counter is synchronized with the clock signal of the chip without the need for clock signal synchronization processing, simplifying the diagnostic method and improving diagnostic efficiency.

[0016] Optionally, the number of bits of the counter is N (where N is a positive integer), and correspondingly, the scan chain includes 2 N trigger groups.

[0017] By this method, 2 N consecutive read operations, write operations, and simultaneous read and write operations can be performed on the memory.

[0018] Next, a memory diagnosis method, device, equipment, system, chip, storage medium, and program product will be provided. Their effects can be referred to the effects corresponding to the above image recognition method and will not be elaborated here.

[0019] In a second aspect, the present application provides a memory diagnosis method. The scan chain is composed of P flip-flops connected in series. Among them, some or all of the flip-flops on the scan chain are divided into multiple trigger groups, each trigger group is respectively connected to multiple ports of the memory, and the host computer is connected to the scan chain. The method is applied to a chip integrated with a memory and a scan chain, and the method includes:

[0020] P flip - flops on the scan chain obtain data from the host computer in a shift manner; the first flip - flop group receives a first signal and writes the data to be written to the target address of the memory. The first flip - flop group includes the flip - flops on the scan chain that are respectively connected to the enable port, address port, and write - data port of the memory; the second flip - flop group receives a second signal, reads data from the target address, and shifts out the data read from the target address in a shift manner. The second flip - flop group includes the flip - flops on the scan chain that are respectively connected to the enable port, address port, and read - data port of the memory. The flip - flops in the first flip - flop group and the second flip - flop group are completely different; wherein, the data read from the target address and the data to be written are used to diagnose the memory.

[0021] In a third aspect, the present application provides a memory diagnosis device, which includes:

[0022] An assignment module, configured to assign values to P flip - flops on the scan chain in a shift manner;

[0023] A first sending module, configured to set the working mode of the scan chain to the capture mode and send a first signal to the first flip - flop group, so that the first flip - flop group writes the data to be written to the target address of the memory. The first flip - flop group includes the flip - flops on the scan chain that are respectively connected to the enable port, address port, and write - data port of the memory;

[0024] A second sending module, configured to send a second signal to the second flip - flop group, so that the second flip - flop group reads data from the target address. The second flip - flop group includes the flip - flops on the scan chain that are respectively connected to the enable port, address port, and read - data port of the memory. The first flip - flop group and the second flip - flop group are different;

[0025] An acquisition module, configured to obtain the data read from the target address in a shift manner and diagnose the memory according to the data read from the target address and the data to be written.

[0026] Optionally, the first sending module is specifically configured to send a first signal to the first flip - flop group according to the count value of the counter; the second sending module is specifically configured to send a second signal to the second flip - flop group according to the count value of the counter.

[0027] Optionally, the first sending module is specifically configured to send a first signal to the first flip - flop group when the count value of the counter is a preset value; the second sending module is specifically configured to send a second signal to the second flip - flop group when the count value of the counter is a preset value.

[0028] Optionally, the first sending module is specifically configured to send a first signal to the first trigger group when the count value of the counter reaches a preset value; the second sending module is specifically configured to send a second signal to the second trigger group when the count value of the counter reaches the preset value plus M, where M is an integer greater than or equal to 1.

[0029] Optionally, the memory, the scan chain, and the counter are integrated on a single chip; wherein, when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one.

[0030] Optionally, the number of bits of the counter is N, where N is a positive integer. Correspondingly, there are 2 N trigger groups on the scan chain.

[0031] In a fourth aspect, the present application provides a host computer, including at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method of any one of the first aspects.

[0032] In a fifth aspect, the present application provides a chip, including: a memory and a scan chain composed of P triggers connected in series, wherein some or all of the triggers on the scan chain are divided into multiple trigger groups, each trigger group is respectively connected to multiple ports of the memory, and the host computer is connected to the scan chain; the P triggers on the scan chain are used to obtain the assignments of multiple triggers by the host computer in the shift direction; the first trigger group is used to receive the first signal and write the data to be written to the target address of the memory, and the first trigger group includes the triggers on the scan chain respectively connected to the enable port, the address port, and the write data port of the memory; the second trigger group is used to receive the second signal and read the data from the target address, and the second trigger group includes the triggers on the scan chain respectively connected to the enable port, the address port, and the read data port of the memory, and the first trigger group and the second trigger group are different; wherein, the data read from the target address and the data to be written are used to diagnose the memory.

[0033] Optionally, it further includes: a counter; wherein, when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one.

[0034] Optionally, the number of bits of the counter is N, where N is a positive integer. Correspondingly, there are 2 N trigger groups on the scan chain.

[0035] In a sixth aspect, the present application provides a memory diagnosis system, including the host computer as in the fourth aspect and the chip as in the fifth aspect.

[0036] In a seventh aspect, the present application provides a computer-readable storage medium storing computer-executable instructions, which are used to implement the memory diagnosis method as in the first aspect when executed by a processor.

[0037] The memory diagnosis method, device, system, chip and medium provided by the present application assign values to P flip-flops on a scan chain; send a first signal to a first flip-flop group to cause the first flip-flop group to write data to be written to a target address of a memory, where the first flip-flop group includes flip-flops on the scan chain respectively connected to the enable port, address port and write data port of the memory; send a second signal to a second flip-flop group to cause the second flip-flop group to read data from the target address, where the second flip-flop group includes flip-flops on the scan chain respectively connected to the enable port, address port and read data port of the memory, and the flip-flops in the first flip-flop group and the second flip-flop group are completely different; obtain the data read from the target address, and diagnose the memory according to the data read from the target address and the data to be written, that is, assign values to all flip-flops on the scan chain by shifting, and realize the write data and read data operations of the memory by grouping and time-sharing controlling the obtained flip-flops on the scan chain, and then shift out the values of the flip-flops on the scan chain by shifting, so that the host computer can obtain the data read from the target address, and diagnose the memory according to the data read from the target address and the data to be written, thereby reducing the number of scan chain shifts, shortening the time for reading and writing the memory, and improving the memory diagnosis efficiency. Description of the Drawings

[0038] Figure 1 It is a schematic diagram of an application scenario of the memory diagnosis method provided by the present application;

[0039] Figure 2 It is a schematic flowchart of the memory diagnosis method provided by the present application;

[0040] Figure 3 It is another schematic flowchart of the memory diagnosis method provided by the present application;

[0041] Figure 4 It is still another schematic flowchart of the memory diagnosis method provided by the present application;

[0042] Figure 5 It is a schematic structural diagram of the memory diagnosis device provided by the present application;

[0043] Figure 6 It is a schematic diagram of a host computer provided by the present application;

[0044] Figure 7 It is a schematic diagram of a chip provided by the present application.

[0045] Through the above-mentioned drawings, specific embodiments of the present disclosure have been shown, and will be described in more detail hereinafter. These drawings and the written description are not intended to limit the scope of the concept of the present disclosure in any way, but to illustrate the concept of the present disclosure to those skilled in the art by reference to specific embodiments. Detailed Description of the Embodiments

[0046] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0047] A memory is a memory component used to store programs and various data information. To ensure the reliability of the programs and data, the functionality of the memory must be ensured. Therefore, it is necessary to diagnose the memory to determine whether there are any faults. In the existing memory diagnosis technology, first, a plurality of scannable flip-flops are connected in series to form a scan chain; then, a certain number of flip-flops on the scan chain are multiplexed and connected to the enable port, address port, read data port, and write data port of the memory. When diagnosing the memory, first, the scan chain is set to the shift mode, and all the flip-flops on the scan chain are assigned values by shifting; after the shifting is completed, the scan chain is set to the capture mode to transfer the values of the flip-flops connected to the enable port, address port, and write data port to the memory for a write operation on the memory; then, the scan chain is set to the shift mode again, and all the flip-flops on the scan chain are assigned values by shifting; after the shifting is completed, the scan chain is set to the capture mode again to transfer the values of the flip-flops connected to the enable port and address port to the memory. Further, data is read from the corresponding address through the read data port, that is, a read operation is performed on the memory, where the address of the read operation is the same as that of the above-mentioned write operation; then, the scan chain is set to the shift mode to shift out the values of all the flip-flops on the scan chain, and thus the data read out by the above-mentioned read operation is obtained and compared with the data written by the above-mentioned write operation to diagnose the memory.

[0048] It can be seen that the existing technology requires three shift operations and two capture operations to complete one diagnosis. Among them, the shift operation takes a long time, resulting in low memory diagnosis efficiency.

[0049] The main idea of this application is to divide the flip - flops on the reused scan chain into multiple different flip - flop groups. The flip - flops in different flip - flop groups are respectively connected to the corresponding memory ports, namely the enable port, address port, read data port, and write data port. The host computer controls the working modes of all flip - flops. First, the host computer sets the scan chain to enter the shift mode and assigns values to all flip - flops on the scan chain. Then, it sets the first flip - flop group to enter the capture mode so that it can transfer the values to the memory for a write operation on the memory. The first flip - flop group is the flip - flop connected to the memory enable port, address port, read data port, and write data port. Next, it sets the second flip - flop group to enter the capture mode so that it can transfer the values to the memory. The second flip - flop group is the flip - flop group on the scan chain that is connected to the memory enable port, address port, read data port, and write data port and is different from the first flip - flop group. Further, data is read from the corresponding address through the read data port, that is, a read operation is performed on the memory, where the address of the read operation is the same as that of the above - mentioned write operation. Then, the scan chain is set to enter the shift mode, and the values of all flip - flops on the scan chain are shifted out, thereby obtaining the data read out by the above - mentioned read operation and comparing it with the data written by the above - mentioned write operation to diagnose the memory. Thus, only two shift operations and one capture operation are required to complete one diagnosis, which can shorten the diagnosis time and improve the diagnosis efficiency.

[0050] Figure 1 It is a schematic diagram of an application scenario of the memory diagnosis method provided by this application. As Figure 1 shown, this memory diagnosis method can be applied to a scenario composed of a host computer 11, a memory 12, and a scan chain 13.

[0051] Among them, the host computer 11 is connected to the scan chain 13, and the host computer 11 is connected to any flip - flop group on the scan chain 13; the host computer 11 is connected to the flip - flop at the starting position in the scan chain 13 (i.e., the flip - flop at the scan input end). For example, as Figure 1 shown, flip - flop 1 and flip - flop X are respectively the flip - flops at the starting position and the ending position of the scan chain 13, and the host computer 11 is connected to flip - flop 1 and flip - flop X. The enable port, address port, write data port, and read data port of the memory 12 are respectively connected to the flip - flops on the scan chain 13.

[0052] The host computer 11 can control the working mode of the scan chain 13 and also the working mode of each flip - flop group on the scan chain 13.

[0053] Taking a single diagnosis as an example, first, when the host computer 11 sets the scan chain 13 to enter the scan mode, data is shifted in through the scan input port 131 of the scan chain 13 to assign values to all the flip-flops on the scan chain 13. Then, the host computer 11 sets the first flip-flop group 133 on the scan chain 133 to enter the capture mode, enabling the first flip-flop group 133 to communicate with the corresponding interface of the memory 12 it is connected to and perform a write data operation on the memory. Then the host computer 11 controls the second flip-flop group 134 on the scan chain 13 to enter the capture mode, enabling the second flip-flop group 134 to communicate with the corresponding interface of the memory 12 it is connected to and perform a read data operation on the memory 12. Finally, the host computer 11 sets the scan chain 13 to enter the shift mode, shifts out the data of each flip-flop on the scan chain 13 from the scan output port 132, and diagnoses the memory based on the data shifted in from the scan input port 131 and the data shifted out from the scan output port 132.

[0054] It can be understood that Figure 1 This is only a schematic diagram of an application scenario of the memory diagnosis method provided by this application, but it does not mean that the memory diagnosis method of the scan chain provided by this application can only be applied to this scenario.

[0055] Figure 2 This is a schematic flowchart of a memory diagnosis method provided by this application. The execution entity of this memory diagnosis method is the host computer, and the host computer is connected to the scan input end and the scan output end of the scan chain. The scan chain is composed of P flip-flops connected in series. Among them, some or all of the flip-flops on the scan chain are divided into multiple flip-flop groups. Specifically, N flip-flops on the scan chain can be divided into multiple flip-flop groups, where N is less than P (that is, some flip-flops on the scan chain can be divided into multiple flip-flop groups), or P flip-flops on the scan chain are divided into multiple flip-flop groups (that is, all flip-flops on the scan chain can be divided into multiple flip-flop groups). Each flip-flop group is respectively connected to multiple ports of the memory, as Figure 2 shown, and the method includes the following steps:

[0056] Step S201: The host computer assigns values to the P flip-flops on the scan chain.

[0057] A possible implementation method for the host computer to assign values to the P flip-flops on the scan chain is:

[0058] a1: The host computer sets the working mode of the scan chain to the shift mode.

[0059] For example, assume that scan_en is the control port for the scan chain working mode. When scan_en is 1, the working mode of the scan chain is the shift mode; when scan_en is 0, the working mode of the scan chain is the capture mode. Then, when the host computer sets scan_en to 1, the scan chain enters the shift mode. Assume that scan_en is the control port for the scan chain working mode. When scan_en is 0, the working mode of the scan chain is the shift mode; when scan_en is 1, the working mode of the scan chain is the capture mode. Then, when the host computer sets scan_en to 0, the scan chain enters the shift mode.

[0060] a2. The host computer sequentially inputs data through the scan input ports of the scan chain, so that the scan chain assigns values to P flip-flops on the scan chain through shifting.

[0061] For example, reference can be made to Figure 1 , the host computer sequentially inputs data through the scan input port 131 of the scan chain, so that the scan chain assigns values to X flip-flops on the scan chain through shifting.

[0062] Step S202. The host computer sets the working mode of the scan chain to the capture mode and sends a first signal to the first flip-flop group on the scan chain, so that the first flip-flop group writes the data to be written to the target address of the memory.

[0063] Among them, the first flip-flop group includes at least one group of flip-flops on the scan chain that are respectively connected to the enable port, address port, and write data port of the memory.

[0064] Optionally, the first flip-flop group may further include flip-flops on the scan chain that are connected to the read data port of the memory.

[0065] The first signal is used to enable the first flip-flop group to write the data to be written to the target address of the memory.

[0066] Optionally, the memory and the scan chain are integrated on one chip.

[0067] A possible implementation for the host computer to send a first signal to the first flip-flop group on the scan chain so that the first flip-flop group writes the data to be written to the target address of the memory is:

[0068] b1. The host computer sets the first flip-flop group to enter the capture mode.

[0069] For example, assume that scan_en_1 is the control port for the working mode of the first flip-flop group. When scan_en_1 is 0, the working mode of the first flip-flop group is the capture mode. The host computer sets scan_en_1 to 0, and the first flip-flop group then enters the capture mode.

[0070] b2. The first trigger group transfers the values of the triggers respectively connected to the enable port, address port, and write data port of the memory to the memory, i.e., performs a write operation on the memory.

[0071] For example, assume that when the value of the enable port of the memory is 1, the memory is in the write data mode; when the value of the enable port is 0, the memory is in the read data mode. Then the first group of triggers transfers 1, the target address, and the data to be written to the enable port, address port, and write data port of the memory respectively.

[0072] Step S203. The host computer sends a second signal to the second trigger group to enable the second trigger group to read data from the target address.

[0073] Among them, the second trigger group includes the triggers respectively connected to the enable port, address port, and read data port of the memory on the scan chain, and the triggers in the first trigger group and the second trigger group are completely different.

[0074] The second signal is used to enable the second trigger group to read data from the target address.

[0075] A possible implementation for the host computer to send a second signal to the second trigger group to enable the second trigger group to read data from the target address is as follows:

[0076] c1. The host computer sets the second trigger group to enter the capture mode.

[0077] For example, assume that scan_en_2 is the control port for the working mode of the second trigger group. When scan_en_2 is 0, the working mode of the second trigger group is the capture mode. Then when the host computer sets scan_en_2 to 0, the second trigger group enters the capture mode. Assume that scan_en_2 is the control port for the working mode of the second trigger group. When scan_en_2 is 1, the working mode of the second trigger group is the capture mode. The host computer sets scan_en_2 to 1, and the second trigger group then enters the capture mode.

[0078] c2. The second trigger group transfers the values of the triggers respectively connected to the enable port and address port of the memory to the memory.

[0079] c3. The trigger in the second trigger group connected to the read data port of the memory obtains data from this port, and this data is the data stored at the target address.

[0080] Combined with c2 and c3 for explanation, for example, assume that when the value of the enable port of the memory is 1, the memory is in the write data mode; when the value of the enable port is 0, the memory is in the read data mode. Then the first group of triggers transfers 0 and the target address to the enable port and address port of the memory respectively, and obtains the data to be read out from the read data port of the memory.

[0081] Step S204: The host computer obtains the data read from the target address and diagnoses the memory according to the data read from the target address and the data to be written.

[0082] A possible implementation for the host computer to obtain the data read from the target address is as follows:

[0083] d1. The host computer sets the working mode of the scan chain to the shift mode.

[0084] For example, assume that scan_en is the control port for the working mode of the scan chain. When scan_en is 1, the working mode of the scan chain is the shift mode; when scan_en is 0, the working mode of the scan chain is the capture mode. Then, when the host computer sets scan_en to 1, the scan chain enters the shift mode. Assume that scan_en is the control port for the working mode of the scan chain. When scan_en is 0, the working mode of the scan chain is the shift mode; when scan_en is 1, the working mode of the scan chain is the capture mode. Then, when the host computer sets scan_en to 0, the scan chain enters the shift mode.

[0085] d2. The host computer obtains the data read from the target address from the data shifted out from the shift output port of the scan chain.

[0086] A possible implementation for the host computer to diagnose the memory according to the data read from the target address and the data to be written is as follows: Compare the data read from the target address with the data to be written. If the data read from the target address is the same as the data to be written, it is diagnosed that the target address of the memory is normal; if the data read from the target address is different from the data to be written, it is diagnosed that there is an abnormality in the target address of the memory.

[0087] This application assigns values to P flip-flops on the scan chain; sets the working mode of the scan chain to the capture mode, and sends a first signal to the first flip-flop group to enable the first flip-flop group to write the data to be written to the target address of the memory. The first flip-flop group includes flip-flops on the scan chain that are respectively connected to the enable port, address port, and write data port of the memory; sends a second signal to the second flip-flop group to enable the second flip-flop group to read data from the target address. The second flip-flop group includes flip-flops on the scan chain that are respectively connected to the enable port, address port, and read data port of the memory. The flip-flops in the first flip-flop group and the second flip-flop group are completely different; obtains the data read from the target address, and diagnoses the memory according to the data read from the target address and the data to be written, that is, assigns values to all flip-flops on the scan chain by shifting, and controls the flip-flops obtained on the scan chain in groups and time-sharing to implement the write data and read data operations on the memory. Then, shifts the values of the flip-flops on the scan chain out to enable the host computer to obtain the data read from the target address, and diagnoses the memory according to the data read from the target address and the data to be written. Furthermore, compared with the prior art, the number of scan chain shifts is reduced, the time for reading and writing the memory is shortened, and the memory diagnosis efficiency is improved.

[0088] Figure 3 Another flowchart of the memory diagnosis method provided by this application. The execution subject of this memory diagnosis method is the host computer, and the host computer is connected to the scan input end and scan output end of the scan chain. The scan chain is composed of P flip-flops connected in series. Among them, some or all of the flip-flops on the scan chain are divided into multiple flip-flop groups, and each flip-flop group is respectively connected to multiple ports of the memory, and the host computer is connected to the scan chain. As Figure 3 shown, the method includes the following steps:

[0089] Step S301: The host computer assigns values to P flip-flops on the scan chain.

[0090] For the specific content of step S301, refer to the content of step S201, which will not be elaborated here.

[0091] Step S302: The host computer sets the working mode of the scan chain to the capture mode, and sends a first signal to the first flip-flop group according to the count value of the counter, so that the first flip-flop group writes the data to be written to the target address of the memory.

[0092] Among them, the first flip-flop group includes flip-flops on the scan chain that are respectively connected to the enable port, address port, and write data port of the memory.

[0093] The counter can be integrated with the memory and the scan chain on a single chip, or can be set in the host computer or set independently. When the counter is integrated with the memory and the scan chain on a single chip or set independently, the counter is connected to the host computer. Integrating the memory, the scan chain and the counter on a single chip, without the need to additionally set up a scan chain or a counter circuit outside the chip, can simplify the memory diagnostic circuit; when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one, enabling the change of the count value of the counter to be consistent with the clock signal of the chip, without the need to perform synchronization processing on the clock signal, simplifying the diagnostic method and improving the diagnostic efficiency.

[0094] Optionally, if the counter is integrated with the memory and the scan chain on a single chip, when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one; if the counter is set in the host computer or set independently, when the clock signal of the memory reaches each rising clock edge, the count value of the counter is incremented by one.

[0095] Optionally, the number of bits of the counter is N, where N is a positive integer. Correspondingly, there are 2 N trigger groups on the scan chain. This method can achieve 2 N consecutive read operations or write operations on the memory. If the memory itself supports single-cycle read and write operations, that is, the read and write enables can be opened simultaneously, and the value of the write data port before the rising edge of the clock signal will be read out by the read data port after the rising edge of the clock signal, then this method can also achieve 2 N consecutive read and write operations on the memory.

[0096] Step S303: The host computer sends a second signal to the second trigger group according to the count value of the counter, so that the second trigger group reads data from the target address.

[0097] Among them, the second trigger group includes the triggers on the scan chain that are respectively connected to the enable port, the address port and the read data port of the memory, and the triggers in the first trigger group and the second trigger group are completely different.

[0098] The following is an explanation in combination with Step S302 and Step S303.

[0099] A possible implementation method for the host computer to send a first signal to the first trigger group and a second signal to the second trigger group according to the count value of the counter is: when the count value of the counter is the first preset value, the host computer sends a first signal to the first trigger group; when the count value of the counter is the second preset value, the host computer sends a second signal to the second trigger group, and the first preset value and the second preset value may be the same or different.

[0100] For example, when the memory supports single-cycle read and write operations, assuming the number of bits of the counter is 2, when the count value of the counter is 00, the host computer sends a first signal to the first trigger group and a second signal to the second trigger group, controlling both the first trigger group and the second trigger group to enter the capture mode. Then, at the rising edge of the clock signal, the data to be written corresponding to the first trigger group is written to the target address of the memory. Subsequently, at the falling edge of the clock signal, the second trigger group reads the data from the target address, thereby realizing the single-cycle read and write operation on the memory, that is, performing read and write operations on the memory simultaneously.

[0101] Another possible implementation for the host computer to send a first signal to the first trigger group according to the count value of the counter and send a second signal to the second trigger group according to the count value of the counter is: when the count value of the counter is N, the host computer sends a first signal to the first trigger group; when the count value of the counter is N + M, the host computer sends a second signal to the second trigger group, where M is an integer greater than or equal to 1. By this method, when the count value of the counter is the preset value N, a first signal is sent to the first trigger group, and when the count value of the counter is the preset value N + M, a second signal is sent to the second trigger group, with M being an integer greater than or equal to 1, which can realize continuous read operations or continuous write operations on the memory, and can set the number and order of read or write operations on the memory, improving the flexibility and operability of memory diagnosis.

[0102] For example, assuming the number of bits of the counter is 2, when the count values of the counter are 00 and 01, the host computer sends a first signal to the first trigger group to enable the first trigger group to write the data to be written to the target address of the memory; when the count value of the counter is 2, that is, the count values are 10 and 11, the host computer sends a second signal to the second trigger group to enable the second trigger group to read the data from the target address, thereby realizing two consecutive write operations on the memory followed by two consecutive read operations.

[0103] Step S304: The host computer obtains the data read from the target address and diagnoses the memory based on the data read from the target address and the data to be written.

[0104] For the specific content of step S304, refer to step S204.

[0105] In this application, the host computer assigns values to P flip-flops on the scan chain, sends a first signal to the first flip-flop group according to the count value of the counter, so that the first flip-flop group writes the data to be written into the target address of the memory, sends a second signal to the second flip-flop group according to the count value of the counter, so that the second flip-flop group reads data from the target address, obtains the data read from the target address, and diagnoses the memory according to the data read from the target address and the data to be written. Not only does it reduce the number of scan chain shifts, shorten the memory diagnosis time, and improve the diagnosis efficiency; but also by setting a counter, it autonomously determines the number and order of read operations, write operations, and simultaneous read and write operations according to the technical value of the counter, improving the flexibility of memory diagnosis.

[0106] Figure 4 FIG. 4 is another flowchart of the memory diagnosis method provided by this application. The execution subject of this memory diagnosis method can be a chip integrated with a memory and a scan chain. The scan chain is composed of P flip-flops connected in series. Among them, some or all of the flip-flops on the scan chain are divided into multiple flip-flop groups, and each flip-flop group is respectively connected to multiple ports of the memory. The host computer is connected to the scan chain, as Figure 4 shown. The method includes the following steps:

[0107] Step S401: The P flip-flops on the scan chain obtain data from the host computer in a shifting manner.

[0108] Step S402: The first flip-flop group on the scan chain receives the first signal and writes the data to be written into the target address of the memory.

[0109] Among them, the first flip-flop group includes the flip-flops on the scan chain that are respectively connected to the enable port, address port, and write data port of the memory.

[0110] A possible implementation manner for the first flip-flop group on the scan chain to receive the first signal and write the data to be written into the target address of the memory is: the first flip-flop group on the scan chain receives the first signal and passes the values of the flip-flops in the first flip-flop group connected to the memory ports to the corresponding ports.

[0111] Step S403: The second flip-flop group on the scan chain receives the second signal and reads data from the target address.

[0112] Among them, the second flip-flop group includes the flip-flops on the scan chain that are respectively connected to the enable port, address port, and read data port of the memory. The flip-flops in the first flip-flop group and the second flip-flop group are completely different.

[0113] The second trigger group on the scan chain receives a second signal. A possible implementation of reading data from a target address is as follows: The second trigger group passes the values of the triggers respectively connected to the enable port and the address port of the memory to the memory. The trigger in the second trigger group connected to the read data port of the memory obtains data from this port, and this data is the data stored at the target address.

[0114] Step S404: The scan chain shifts out the data read from the target address.

[0115] Among them, the data read from the target address and the data to be written are used to diagnose the memory.

[0116] In this application, P triggers on the scan chain obtain data from the host computer through shifting. The first trigger group on the scan chain receives a first signal and writes the data to be written into the target address of the memory. The second trigger group on the scan chain receives a second signal and reads data from the target address. The scan chain shifts out the data read from the target address, realizing the assignment of the triggers on the scan chain and the read and write operations on the memory. Shifting out the data read from the target address reduces the difficulty of diagnosing the memory based on the data read from the target address and the data to be written.

[0117] Figure 5 FIG. is a schematic structural diagram of a memory diagnosis device provided by this application, as Figure 5 shown, the memory diagnosis device includes:

[0118] An assignment module 51, configured to assign values to P triggers on the scan chain through shifting.

[0119] A first sending module 52, configured to set the working mode of the scan chain to the capture mode and send a first signal to the first trigger group, so that the first trigger group writes the data to be written into the target address of the memory.

[0120] Among them, the first trigger group includes the triggers on the scan chain respectively connected to the enable port, the address port, and the write data port of the memory.

[0121] A second sending module 53, configured to send a second signal to the second trigger group, so that the second trigger group reads data from the target address.

[0122] Among them, the second trigger group includes the triggers on the scan chain respectively connected to the enable port, the address port, and the read data port of the memory, and the first trigger group and the second trigger group are different.

[0123] An acquisition module 54, configured to acquire data read from a target address in a shifting manner, and diagnose a memory according to the data read from the target address and data to be written.

[0124] Optionally, a first sending module 52, specifically configured to send a first signal to a first trigger group according to a count value of a counter.

[0125] A second sending module 53, specifically configured to send a second signal to a second trigger group according to a count value of the counter.

[0126] Optionally, the first sending module is specifically configured to send a first signal to the first trigger group when the count value of the counter is a preset value.

[0127] The second sending module is specifically configured to send a second signal to the second trigger group when the count value of the counter is the preset value.

[0128] Optionally, the first sending module is specifically configured to send a first signal to the first trigger group when the count value of the counter is the preset value.

[0129] The second sending module is specifically configured to send a second signal to the second trigger group when the count value of the counter is the preset value plus M, where M is an integer greater than or equal to 1.

[0130] Optionally, the memory, the scan chain, and the counter are integrated on a single chip.

[0131] Wherein, when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one.

[0132] Optionally, the number of bits of the counter is N, where N is a positive integer. Correspondingly, there are 2 N trigger groups on the scan chain.

[0133] Figure 5 The memory diagnosis device in the illustrated embodiment can be used to implement the technical solutions of the above method embodiment, and its implementation principle and technical effects are similar, and will not be elaborated here.

[0134] Figure 6 The figure is a schematic diagram of a host computer provided by this application. As Figure 6 shown, the host computer includes at least one processor 61; and a memory 62 communicatively connected to the at least one processor 61.

[0135] Wherein, the memory 62 stores instructions executable by the at least one processor 61, and the instructions are executed by the at least one processor 61 so that the at least one processor 61 can execute Figure 2 or Figure 3 the methods in the illustrated embodiments.

[0136] Optionally, the host computer further includes: a transceiver 63 for communicating with other devices.

[0137] Figure 6 The host computer in the illustrated embodiment can be used to execute the technical solutions of the above method embodiments. The implementation principles and technical effects are similar and will not be elaborated here.

[0138] Figure 7 A schematic diagram of a chip provided by the present application includes: a memory 71 and a scan chain 72 composed of P flip - flops connected in series. The scan chain is composed of P flip - flops connected in series. Among them, some or all of the flip - flops on the scan chain are divided into multiple flip - flop groups. Each flip - flop group is respectively connected to multiple ports of the memory, and the host computer is connected to the scan chain.

[0139] The P flip - flops on the scan chain 72 are used to obtain data from the host computer in a shift manner.

[0140] The first flip - flop group 721 on the scan chain is used to receive the first signal and write the data to be written to the target address of the memory.

[0141] Among them, the first flip - flop group includes the flip - flops on the scan chain that are respectively connected to the enable port, address port, and write - data port of the memory.

[0142] The second flip - flop group 722 on the scan chain 72 is used to receive the second signal and read data from the target address.

[0143] Among them, the second flip - flop group includes the flip - flops on the scan chain that are respectively connected to the enable port, address port, and read - data port of the memory. The first flip - flop group and the second flip - flop group are different.

[0144] The data read from the target address and the data to be written are used to diagnose the memory.

[0145] Optionally, it further includes: a counter 73. Wherein, when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one.

[0146] Optionally, the number of bits of the counter is N, N is a positive integer. Correspondingly, there are 2 N flip - flop groups on the scan chain.

[0147] Figure 7 The chip in the illustrated embodiment can be used to execute the technical solutions of the above method embodiments. The implementation principles and technical effects are similar and will not be elaborated here.

[0148] The present application provides a memory diagnosis system, including the host computer as shown in Figure 6 the illustrated embodiment, and the chip as shown in Figure 7 the illustrated embodiment.

[0149] The present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the memory diagnosis method in the embodiments as Figure 2 or Figure 3 shown in the embodiments.

[0150] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above division of each functional module is used as an example. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can refer to the corresponding process in the foregoing method embodiments, and will not be elaborated here.

[0151] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory diagnosis method, characterized in that, the scan chain is composed of P flip - flops connected in series. Among them, some or all of the flip - flops on the scan chain are divided into multiple flip - flop groups. Each flip - flop group is respectively connected to multiple ports of the memory. The host computer is connected to the scan chain. The method is applied to the host computer, and the method includes: Assign values to the P flip - flops on the scan chain; Set the working mode of the scan chain to the capture mode, and send a first signal to the first flip - flop group according to the count value of the counter, so that the first flip - flop group writes the data to be written into the target address of the memory. The first flip - flop group includes the flip - flops on the scan chain that are respectively connected to the enable port, address port, and write data port of the memory; Send a second signal to the second flip - flop group according to the count value of the counter, so that the second flip - flop group reads data from the target address. The second flip - flop group includes the flip - flops on the scan chain that are respectively connected to the enable port, address port, and read data port of the memory. The flip - flops in the first flip - flop group and the second flip - flop group are completely different; Obtain the data read from the target address, and diagnose the memory according to the data read from the target address and the data to be written.

2. The method according to claim 1, characterized in that, the step of sending the first signal to the first flip - flop group according to the count value of the counter includes: When the count value of the counter is a preset value, send the first signal to the first flip - flop group; the step of sending the second signal to the second flip - flop group according to the count value of the counter includes: When the count value of the counter is a preset value, send the second signal to the second flip - flop group.

3. The method according to claim 1, characterized in that, the step of sending the first signal to the first flip - flop group according to the count value of the counter includes: When the count value of the counter is a preset value, send the first signal to the first flip - flop group; the step of sending the second signal to the second flip - flop group according to the count value of the counter includes: When the count value of the counter is the preset value plus M, send the second signal to the second flip - flop group, where M is an integer greater than or equal to 1.

4. The method according to any one of claims 1 - 3, characterized in that, the memory, the scan chain, and the counter are integrated on a chip; wherein, when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one.

5. The method according to any one of claims 1 - 3, characterized in that, The number of bits of the counter is N, where N is a positive integer. Correspondingly, there are 2 N trigger groups on the scan chain.

6. A memory diagnosis method, characterized in that, the scan chain is composed of P flip - flops connected in series. Among them, some or all of the flip - flops on the scan chain are divided into multiple flip - flop groups. Each flip - flop group is respectively connected to multiple ports of the memory. The host computer is connected to the scan chain. The method is applied to a chip integrated with the memory, the scan chain, and the counter. The method includes: The P flip - flops on the scan chain obtain data from the host computer through a shift method; The first trigger group receives a first signal and writes the data to be written to the target address of the memory. The first trigger group includes the triggers on the scan chain that are respectively connected to the enable port, address port, and write data port of the memory. The second trigger group receives a second signal, reads data from the target address, and shifts out the data read from the target address. The second trigger group includes the triggers on the scan chain that are respectively connected to the enable port, address port, and read data port of the memory. The triggers in the first trigger group and the second trigger group are completely different. Wherein, the data read from the target address and the data to be written are used to diagnose the memory. Wherein, when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one.

7. A memory diagnostic device Characterized in that The device includes: An assignment module for assigning values to all the triggers on the scan chain in a shift manner. A first sending module for setting the working mode of the scan chain to the capture mode and sending a first signal to the first trigger group according to the count value of the counter, so that the first trigger group writes the data to be written to the target address of the memory. The first trigger group includes the triggers on the scan chain that are respectively connected to the enable port, address port, and write data port of the memory. A second sending module for sending a second signal to the second trigger group according to the count value of the counter, so that the second trigger group reads data from the target address. The second trigger group includes the triggers on the scan chain that are respectively connected to the enable port, address port, and read data port of the memory. The first trigger group and the second trigger group are different. An acquisition module for acquiring the data read from the target address in a shift manner and diagnosing the memory according to the data read from the target address and the data to be written.

8. A host computer Characterized in that It includes: At least one processor; And a memory communicatively connected to the at least one processor. Wherein, The memory stores instructions executable by the at least one processor. The instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1 to 5.

9. A chip Characterized in that It includes: A memory and a scan chain composed of P triggers connected in series. Wherein, some or all of the triggers on the scan chain are divided into multiple trigger groups, each trigger group is respectively connected to multiple ports of the memory, and the host computer is connected to the scan chain. The P triggers on the scan chain are used to acquire the values assigned to the multiple triggers by the host computer in the shift direction. The first trigger group is used to receive a first signal and write the data to be written to the target address of the memory. The first trigger group includes the triggers respectively connected through the enable port, address port, and write data port of the memory. The second trigger group is used to receive a second signal and read data from the target address. The second trigger group includes triggers respectively connected through the enable port, address port, and read data port of the memory, and the first trigger group is different from the second trigger group; Wherein, the data read from the target address and the data to be written are used to diagnose the memory; It further includes: a counter; Wherein, when the clock signal of the chip reaches each rising clock edge, the count value of the counter is incremented by one.

10. The chip according to claim 9, wherein, The number of bits of the counter is N, where N is a positive integer. Correspondingly, there are 2 N trigger groups on the scan chain.

11. A memory diagnostic system, wherein, includes: The host computer according to claim 8, and the chip according to claim 9 or 10.

12. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the memory diagnostic method according to any one of claims 1 to 5.

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