Semiconductor structure and method for forming the same
By first etching the grooves in the fork-shaped nanosheet device and forming a sacrificial layer therein, the problems of high process difficulty and insufficient channel control capability of the gate structure are solved, and a more efficient semiconductor structure performance improvement is achieved.
Patent Information
- Application Number
- CN202011452915.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-11
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2040-12-11
AI Technical Summary
The performance of fork sheet devices has not yet reached the best state, the process is difficult and the gate structure lacks channel control capabilities, resulting in limited performance improvement.
Before forming the isolation structure, the first fin layer on both sides of the first opening is etched and removed, grooves are formed, and a sacrificial layer is formed therein, expanding part of the distance of the fin structure. The subsequently formed first gate structure can be surrounded on all sides. The first fin layer enhances the control capability of the channel.
It reduces process difficulty, improves the performance and integration of semiconductor structures, and achieves better electrical isolation and channel control.
Smart Images
Figure CN114628255B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] The FinFET (FinFET) architecture is a mainstay in today's semiconductor industry. However, as devices continue to shrink, the FinFET structure becomes unable to provide sufficient electrostatic control and drive current when the channel length reaches a certain value. Therefore, the nanosheet structure has been introduced. Compared to the FinFET, the characteristics of the nanosheet provide superior channel control capabilities. At the same time, the excellent three-dimensional distribution of the channel optimizes the effective drive current per unit area.
[0003] As semiconductor device sizes continue to shrink, further reductions in cell height will require smaller spacing between NMOS and PMOS devices within standard cells. However, for FinFETs and nanosheets, the process limits the spacing between these NMOS and PMOS devices. In order to expand the scalability of these devices, an innovative architecture called a forksheet device has been proposed. The forksheet can be considered a natural extension of the nanosheet. Compared to the nanosheet, the channel of the forksheet is controlled by a fork-shaped gate structure, which is achieved by introducing a "dielectric wall" between the NMOS and PMOS devices before gate patterning. The wall physically isolates the NMOS gate trench from the PMOS gate trench, thereby significantly reducing the spacing between NMOS and PMOS, giving the forksheet better scalability in terms of area and performance.
[0004] However, the performance of forksheet devices still needs to be improved. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce the process difficulty during the formation process and is conducive to improving the performance of the semiconductor structure.
[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming a fin structure on the first region and the second region respectively, with a first opening between adjacent first regions and second regions, the fin structure comprising a bottom region and a top region located on the bottom region, the top region comprising a first fin layer and a second fin layer alternately stacked along a normal direction of a substrate surface, the fin structure further comprising a first portion and a second portion along an extension direction of the fin structure; etching a portion of the first portion of the first fin layer on both sides of the first opening, and etching a portion of the first fin layer between adjacent second fin layers and A first groove is formed between the second fin layer and the bottom area; a sacrificial layer is formed in the first groove; an isolation structure is formed in the first opening between the first parts, and the top surface of the isolation structure is higher than the top surface of the fin structure; a plurality of first dummy gate structures are formed across the first part of the fin structure and the isolation structure; the first dummy gate structure and the second fin layer and the sacrificial layer covered by the first dummy gate structure are removed to form a first gate opening; a first gate structure is formed in the first gate opening, the first gate structure surrounds each of the first fin layers, and the top surface of the first gate structure is flush with the top surface of the isolation structure.
[0007] Optionally, the material of the first fin layer is different from the material of the second fin layer; the material of the first fin layer includes silicon or silicon germanium; the material of the second fin layer includes silicon or silicon germanium.
[0008] Optionally, the material of the sacrificial layer is the same as that of the second fin layer; the material of the sacrificial layer includes silicon or silicon germanium.
[0009] Optionally, the material of the isolation structure includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon boron carbon nitride.
[0010] Optionally, the process of etching part of the first fin layer in the first portion on both sides of the first opening includes an isotropic wet etching process; process parameters of the wet etching process include: the wet etching solution includes a TMAH solution or an ammonia solution.
[0011] Optionally, a first mask layer is also formed on the fin structure, and the step of forming a sacrificial layer in the first groove includes: forming a sacrificial material layer in the first groove, and the sacrificial material layer also fills the first opening; using the first mask layer as a mask, etching and removing the sacrificial material layer in the first opening, and forming a sacrificial layer in the first groove.
[0012] Optionally, before etching the first portion of the first fin layer on both sides of the first opening, the method further includes: forming a second mask layer on the substrate, wherein the second mask layer exposes the sidewalls of the first portion of the fin structure on both sides of the first opening.
[0013] Optionally, the material of the second mask layer includes: amorphous carbon, bottom anti-reflection material or photoresist material.
[0014] Optionally, after forming the first dummy gate structure, the method further includes: forming source and drain openings in the fin structure on both sides of the first dummy gate structure, wherein the source and drain openings expose the substrate surface; and forming source and drain doping layers in the source and drain openings.
[0015] Optionally, after forming the source / drain openings and before forming the source / drain doping layers, the method further includes: removing a portion of the second fin layer exposed by the sidewalls of the source / drain openings, and forming a second groove on the first fin layer.
[0016] Optionally, before forming the source-drain doped layer, the method further includes: forming an inner sidewall in the second groove, wherein the sidewall of the inner sidewall is flush with the sidewall of the first fin layer.
[0017] Optionally, the material of the inner sidewall includes a low-k dielectric material, an ultra-low-k dielectric material, silicon nitride or silicon oxynitride.
[0018] Optionally, after forming the source / drain doping layer, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer exposes a top surface of the first dummy gate structure.
[0019] Optionally, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall surface of the fin structure.
[0020] Accordingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region; a fin structure located on the substrate in the first region and the second region, the fin structure comprising a bottom region and a top region located on the bottom region, the top region comprising a first fin layer stacked along a normal direction of the substrate surface, a first gap being provided between adjacent first fin layers, the fin structure further comprising a first part and a second part along an extension direction of the fin structure, the distance between adjacent first parts of the fin structures being greater than the distance between the second parts; an isolation structure located between first parts of adjacent fin structures in the first region and the second region, and a second gap being provided between the isolation structure and the first part of the fin structure; a first gate structure spanning the first part of the fin structure, located on the surface of the first fin layer and surrounding the first fin layer, the first gate structure filling the first gap and the second gap, and the top surface of the first gate structure being flush with the top surface of the isolation structure.
[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0022] Before forming the isolation structure, part of the first fin layer on both sides of the first opening is etched away to form a first groove, and then a sacrificial layer is formed in the first groove. The sacrificial layer creates a certain distance between the first fin layer and the isolation structure. In the process of forming the first gate structure, the process window for removing the second fin layer and the sacrificial layer is increased, which reduces the process difficulty. In addition, the formed first gate structure can surround the first fin layer on all sides, thereby enhancing the control ability of the first gate structure over the channel, which is beneficial to improving the performance of the semiconductor structure finally formed.
[0023] In the semiconductor structure provided by the present invention, the isolation structure is located in the first opening between the first region and the second region, and electrical isolation of the first gate structure of the first region and the second region can still be achieved in a highly integrated semiconductor structure; and there is a second gap between the first fin layer and the isolation structure, and the first gate structure can surround the first fin layer on all four sides, thereby enhancing the control ability of the first gate structure over the channel, which is beneficial to improving the performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figures 1 to 5 is a structural schematic diagram of a semiconductor structure forming process in one embodiment;
[0025] Figures 6 to 26 It is a structural schematic diagram corresponding to each step of the semiconductor structure formation process in one embodiment of the present invention. DETAILED DESCRIPTION
[0026] As can be seen from the background, the performance of current forksheet devices still needs to be improved. This will now be analyzed and explained in conjunction with specific embodiments.
[0027] Figures 1 to 5 1 is a schematic structural diagram of a semiconductor structure forming process in one embodiment.
[0028] refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a first area 101 and a second area 102; forming a plurality of fin structures 103 on the first area 101 and the second area 102 respectively, wherein the fin structure 103 includes a bottom area 104 and a first fin layer 105 and a second fin layer 106 stacked in sequence along the normal direction of the surface of the substrate 100 on the bottom area 104, and a first opening 107 is provided between the first area 101 and the second area 102; forming an isolation layer 108 on the substrate 100, wherein the isolation layer 108 covers part of the sidewall surface of the fin structure 103.
[0029] refer to Figure 2 An isolation structure 109 is formed in the first opening 107 , and the isolation structure 109 is flush with the top surface of the fin structure 103 .
[0030] refer to Figure 3 , forming a dummy gate structure 110 spanning the fin structure 103 and the isolation structure 109 .
[0031] refer to Figure 4 , the dummy gate structure 110 and the second fin layer 106 covered by the dummy gate structure 110 are removed to form a gate opening 111 exposing the surface of the first fin layer 105 .
[0032] refer to Figure 5 A gate structure 112 is formed in the gate opening 111 , and a top surface of the gate structure 112 is flush with a top surface of the isolation structure 109 .
[0033] In the process of forming a semiconductor structure using the above method, a first opening 107 is provided between the fin structures 103 of the first region 101 and the second region 102. As the spacing between adjacent device regions becomes smaller and smaller, an isolation structure 109 is formed in the first opening 107 to achieve isolation of the gate structure 112 on the first region 101 and the second region 102, and the side walls of the isolation structure 109 are in contact with the side walls of the fin structures 103 on both sides. On the one hand, in the process of forming the gate structure 112, the space for removing the second fin layer 106 and forming the gate structure 112 in the gate opening 111 is small, and the process window is small, resulting in high process difficulty. On the other hand, the gate structure 112 finally formed only surrounds the fin structure 103 on three sides, and no gate structure is formed surrounding the fin structure 103, which weakens the control ability of the gate structure 112 over the fin structure 103, resulting in an increased risk of leakage, which is not conducive to the performance of the semiconductor structure.
[0034] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure. Before forming the isolation structure, part of the first fin layer of the first part on both sides of the first opening is first etched to form a first groove between adjacent second fin layers, and then a sacrificial layer is formed in the first groove, thereby expanding the distance between the first parts of the fin structure, so that there is a certain space between the remaining first fin layer of the first part and the isolation structure, which has a larger process space when the first gate structure is subsequently formed, reducing the process difficulty; and before forming the first gate structure, the second fin layer and the sacrificial layer are removed, and the formed gate opening completely exposes the top, bottom and sidewall surfaces of the first fin layer, so that the formed first gate structure completely surrounds the first fin layer, thereby enhancing the control ability of the first gate structure over the fin structure and improving the performance of the semiconductor structure.
[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0036] Figures 6 to 26 It is a structural schematic diagram corresponding to each step of the semiconductor structure formation process in one embodiment of the present invention.
[0037] refer to Figure 6 and Figure 7 , Figure 6 is a top view of the semiconductor structure. Figure 7 yes Figure 6 A schematic cross-sectional structural diagram along the AA direction shows a substrate 200 , which includes a first region I and a second region II.
[0038] The substrate 200 provides a process platform for subsequently forming a semiconductor structure, and the first region I and the second region II are used for subsequently forming a MOS device.
[0039] In this embodiment, the first area I and the second area II are arranged along the first direction X.
[0040] The substrate 200 is made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate 200 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In this embodiment, the substrate 200 is a silicon substrate.
[0041] Continue to refer Figure 6 and Figure 7 , a fin structure 210 is formed on the first area I and the second area II, respectively, and a first opening 220 is provided between the fin structures 210 in adjacent first area I and second area II. The fin structure 210 includes a bottom area 211 and a top area located on the bottom area 211. The top area includes a first fin layer 212 and a second fin layer 213 alternately stacked along the normal direction of the surface of the substrate 200. The fin structure 210 also includes a first portion and a second portion along the extension direction of the fin structure 210.
[0042] In this embodiment, the fin structures 210 are arranged along the first direction X and parallel to the second direction Y, and the second direction Y is perpendicular to the first direction X. In this embodiment, a first mask layer 214 is further formed on the fin structures 210 .
[0043] In this embodiment, the first opening 220 provides space for the subsequent formation of an isolation structure. Specifically, an isolation structure is formed in the first opening 220 between the first parts of the fin structure 210, and no isolation structure is subsequently formed in the first opening 220 between the second parts of the fin structure 210. The isolation structure is formed between the first parts of the fin structures 210 in the adjacent first region I and second region II, which is beneficial to improving the integration of the semiconductor structure.
[0044] In this embodiment, the step of forming a fin structure 210 on the first region I and the second region II includes: alternately forming a first fin material layer (not shown) and a second fin material layer (not shown) on the substrate 200 in the first region I and the second region II, the first fin material layer being used for the subsequent formation of a first fin layer, and the second fin material layer being used for the subsequent formation of a second fin layer; forming a first mask layer 214 on the topmost second fin material layer, the first mask layer 214 defining the position and size of the fin structure to be formed; using the first mask layer 214 as a mask, etching the second fin material layer, the first fin material layer and a partial thickness of the substrate 200 to form the fin structure 210 in the first region I and the second region II, respectively.
[0045] In this embodiment, the bottom region 211 of the fin structure 210 is a patterned portion of the substrate 200 .
[0046] The material of the first fin layer 212 is different from the material of the second fin layer 213. The first fin layer 212 and the second fin layer 213 have an etching selectivity to avoid etching damage to the second fin layer 213 when the first fin layer 212 is subsequently etched, or etching damage to the first fin layer 212 when the second fin layer 213 is etched.
[0047] Specifically, the material of the first fin layer 212 is silicon or silicon germanium; the material of the second fin layer 213 is silicon or silicon germanium. In this embodiment, the material of the first fin layer 212 is silicon, and the material of the second fin layer 213 is silicon germanium.
[0048] The material of the first mask layer 214 includes silicon nitride, silicon oxynitride, silicon carbonitride, etc. In this embodiment, the material of the first mask layer 214 is silicon nitride.
[0049] Continue to refer Figure 6 and Figure 7 , an isolation layer 230 is formed on the substrate 200 , wherein the isolation layer 230 covers a portion of the sidewall surface of the fin structure 210 , and a top surface of the isolation layer 230 is lower than a top surface of the fin structure 210 .
[0050] In this embodiment, the isolation layer 230 covers the sidewall surface of the bottom region 211 of the fin structure 210 .
[0051] In this embodiment, the isolation layer 230 is made of silicon oxide.
[0052] In this embodiment, the method for forming the isolation layer 230 includes: forming an initial isolation film (not shown) on the substrate 200 , wherein the initial isolation film covers the sidewalls of the fin structure 210 ; and etching back the initial isolation film to form the isolation layer 230 .
[0053] In this embodiment, the process for forming the initial isolation film is a fluid chemical vapor deposition process. The use of the fluid chemical vapor deposition process to form the initial isolation film ensures better filling performance of the initial isolation film.
[0054] refer to Figure 8 and Figure 9 , Figure 8 is a top view of the semiconductor structure. Figure 9 and Figure 7 A second mask layer 240 is formed on the substrate 200 in the same cross-sectional direction, and the second mask layer 240 exposes the sidewalls of the first portion of the fin structure 210 on both sides of the first opening 220 .
[0055] In this embodiment, the second mask layer 240 covers the sidewall of the fin structure 210 facing away from the first opening 220 , and also covers the sidewall surface of the second portion of the fin structure 210 on both sides of the first opening 220 .
[0056] In this embodiment, the area exposed by the second mask layer 240 is the area where an isolation structure needs to be formed subsequently.
[0057] In this embodiment, the material of the second mask layer 240 is amorphous carbon; in other embodiments, the material of the second mask layer 240 may further include a bottom anti-reflection material or a photoresist material.
[0058] refer to Figure 10 and Figure 11 , Figure 10 It is a top view of the semiconductor structure in which the first mask layer 214, the second mask layer 240 and the topmost second fin layer 213 are omitted. After the second mask layer 240 is formed, the first fin layer 212 of the first part of the fin structure 210 on both sides of the first opening 220 is etched using the second mask layer 240 as a mask, and a first groove 250 is formed between adjacent second fin layers 213 and between the second fin layer 213 and the bottom area 211.
[0059] In this embodiment, an isotropic wet etching process is used to etch the first fin layer 212 , and the etching direction of the wet etching process is parallel to the first direction X.
[0060] In this embodiment, the process parameters of the wet etching include: the wet etching solution includes a TMAH solution or an ammonia solution.
[0061] The depth of the first groove 250 in the first direction X ranges from 1 to 6 nm. If the depth of the first groove 250 is greater than 6 nm, the width of the fin structure 210 in the second direction Y will be too small, resulting in increased resistance and reduced on-current of the semiconductor device, which is detrimental to the electrical performance of the semiconductor structure. If the depth of the first groove 250 is less than 1 nm, the gap between the subsequently formed isolation structure and the fin structure will be too small. When the first gate structure is subsequently formed, the gate material cannot fill the gap between the isolation structure and the fin structure. The first gate structure cannot completely include the first fin layer, resulting in the first gate structure's ability to control the channel being weakened.
[0062] refer to Figure 12 , Figure 12 and Figure 11 After the first groove 250 is formed, a sacrificial layer 251 is formed in the first groove 250 , and the sidewall of the sacrificial layer 251 is flush with the sidewall of the second fin layer 213 .
[0063] In this embodiment, the step of forming a sacrificial layer 251 in the first groove 250 includes: forming a sacrificial material layer (not shown) in the first groove 250, and the sacrificial material layer also fills the first opening 220; using the first mask layer 214 as a mask, etching and removing the sacrificial material layer in the first opening 220 to form a sacrificial layer 251 in the first groove 250.
[0064] In this embodiment, due to the presence of the second mask layer 240 , the sacrificial material layer completely fills the portion of the first opening 220 exposed by the second mask layer 240 .
[0065] The material of the sacrificial layer 251 is the same as that of the second fin layer 213 , which facilitates the removal of the sacrificial layer 251 when the second fin layer 213 is subsequently removed, thereby simplifying the process flow.
[0066] In this embodiment, the material of the sacrificial layer 251 is silicon germanium; in other embodiments, the material of the sacrificial layer 251 may also be silicon.
[0067] In this embodiment, the first mask layer 214 and the sacrificial layer 251 have an etching selectivity ratio. When removing the sacrificial layer 251 in the first opening 220, the first mask layer 214 and the second fin layer 213 and the sacrificial layer 251 covered by the first mask layer 214 can be prevented from suffering etching damage.
[0068] refer to Figure 13 and Figure 14 , Figure 13 FIG. 2 is a top view of the semiconductor structure omitting the isolation layer 230 , the second fin layer 213 , and the sacrificial layer 251 . Figure 14 and Figure 12 An isolation structure 260 is formed in the first opening 220 between the first portions of the fin structures 210 , and a top surface of the isolation structure 260 is higher than a top surface of the fin structure 210 .
[0069] In this embodiment, specifically, the isolation structure 260 is formed in the first opening 220 exposed by the second mask layer 240 .
[0070] In this embodiment, the isolation structure 260 is used to isolate the first gate structure subsequently formed on the first region I and the second region II.
[0071] In this embodiment, the isolation structure 260 is formed by a chemical vapor deposition process; in other embodiments, the isolation structure 260 may also be formed by an atomic layer deposition process.
[0072] In this embodiment, the material of the isolation structure 260 is silicon oxide; in other embodiments, the material of the isolation structure 260 may also be one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon boron carbon nitride.
[0073] After forming the isolation structure 260 , the first mask layer 214 and the second mask layer 240 are removed.
[0074] A dry etching process or a wet etching process is used to remove the first mask layer 214. In this embodiment, the dry etching process is used to remove the first mask layer 214.
[0075] The second mask layer 240 is removed by using a dry etching process or a wet etching process. In this embodiment, the second mask layer 240 is removed by using a dry etching process.
[0076] refer to Figures 15 to 17 , Figure 15 is a top view of the semiconductor structure omitting the isolation layer 230, the second fin layer 213 and the sacrificial layer 251. Figure 16 and Figure 14 The cross-sectional direction is consistent. Figure 17 yes Figure 15 A schematic diagram of the cross-sectional structure along the BB direction shows several first pseudo gate structures 270 formed across the first portion of the fin structure 210 and the isolation structure 260, and the first pseudo gate structures 270 cover the first portion of the fin structure 210 and part of the top surface and side wall surface of the isolation structure 260.
[0077] In this embodiment, the method further includes forming a second dummy gate structure 280 across the second portion of the fin structure 210 , wherein the second dummy gate structure 280 covers a portion of the top and sidewall surfaces of the second portion of the fin structure 210 .
[0078] In this embodiment, the method for forming the first dummy gate structure 270 includes: forming a first dummy gate dielectric layer (not labeled) on the isolation layer 230; forming a first dummy gate layer (not labeled) on the first dummy gate dielectric layer; forming a first dummy gate protection layer (not labeled) on the first dummy gate layer; and forming a first sidewall (not labeled) on the sidewalls of the first dummy gate layer, the first dummy gate dielectric layer and the first dummy gate protection layer.
[0079] In this embodiment, the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer may also be silicon oxynitride.
[0080] In this embodiment, the material of the first dummy gate layer is polysilicon.
[0081] In this embodiment, the method for forming the second dummy gate structure 280 includes: forming a second dummy gate dielectric layer (not labeled) on the isolation layer 230; forming a second dummy gate layer (not labeled) on the second dummy gate dielectric layer; forming a second dummy gate protection layer (not labeled) on the second dummy gate layer; and forming a second sidewall (not labeled) on the sidewalls of the second dummy gate layer, the second dummy gate dielectric layer and the second dummy gate protection layer.
[0082] In this embodiment, the material of the second dummy gate dielectric layer is the same as that of the first dummy gate dielectric layer, and the material of the second dummy gate layer is also the same as that of the first dummy gate layer.
[0083] In this embodiment, the first dummy gate structure 270 and the second dummy gate structure 280 are formed simultaneously. The first dummy gate structure 270 and the second dummy gate structure 280 are formed simultaneously through a global process, which can effectively improve production efficiency.
[0084] refer to Figure 18 , Figure 18 and Figure 17 The cross-sectional direction is consistent with that of the first dummy gate structure 270 , and source / drain openings 290 are formed in the fin structure 210 on both sides of the first dummy gate structure 270 , and the source / drain openings 290 expose the surface of the substrate 200 .
[0085] The source / drain openings 290 provide space for subsequent formation of source / drain doping layers.
[0086] In this embodiment, the method for forming the source-drain opening 290 includes: using the first dummy gate structure 270 as a mask, etching the fin structure 210 until the top surface of the substrate 200 is exposed, and forming source-drain openings 290 in the fin structure 210 on both sides of the first dummy gate structure 270.
[0087] In this embodiment, the method further includes: etching the fin structure 210 using the second dummy gate structure 280 as a mask to form source and drain openings in the fin structure 210 on both sides of the second dummy gate structure 280 .
[0088] In this embodiment, the fin structure 210 is etched using an anisotropic dry etching process. The anisotropic dry etching process is conducive to forming source and drain openings 290 with better morphology, avoiding etching damage to the fin structure 210 at the bottom of the first dummy gate structure 270 and the second dummy gate structure 280, thereby improving the performance of the formed semiconductor structure.
[0089] After the source / drain openings 290 are formed, portions of the second fin layer 213 exposed by the sidewalls of the source / drain openings 290 are removed, and a second groove 300 is formed on the first fin layer 212 .
[0090] In this embodiment, the process for removing a portion of the second fin layer 213 is a wet etching process. The wet etching solution has a good selectivity for silicon and silicon germanium, ensuring that the silicon germanium is removed while the silicon morphology is not affected. The wet etching solution used in this embodiment is: 20% to 90% by volume of hydrogen chloride gas.
[0091] refer to Figure 19 , Figure 19 and Figure 17 An inner sidewall 310 is formed in the second groove 300 , and a sidewall of the inner sidewall 310 is flush with a sidewall of the first fin layer 212 .
[0092] In this embodiment, the method for forming the inner sidewall 310 includes: forming an inner sidewall material layer (not shown) on the second groove 300, the surface of the substrate 200, and the surfaces of the first dummy gate structure 270 and the second dummy gate structure 280; etching the inner sidewall material layer until the surface of the substrate 200, the sidewall surface of the first fin layer 212, and the sidewall and top surface of the first dummy gate structure 270 and the second dummy gate structure 280 are exposed, thereby forming an inner sidewall 310 in the second groove 300.
[0093] In this embodiment, the inner sidewall 310 provides support for the first fin layer 212 when the second fin layer 213 and the sacrificial layer 251 are subsequently removed. On the other hand, it can isolate the subsequently formed source and drain doped layers and the first gate structure.
[0094] In this embodiment, the material of the inner sidewall 310 is silicon nitride; in other embodiments, the material of the inner sidewall 310 can also be silicon oxynitride, a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), including one or more of SiOH, SiOCH, SiOC, and SiOCN.
[0095] refer to Figure 20 , Figure 20 and Figure 19 A source-drain doping layer 291 is formed in the source-drain opening 290 in the same cross-sectional direction.
[0096] In this embodiment, the source-drain doped layer 291 is formed by an epitaxial growth process.
[0097] The source-drain doping layer 291 contains source-drain doping ions. In this embodiment, the ions are doped using an in-situ doping process.
[0098] In this embodiment, the source-drain doped layer 291 includes a first source-drain doped layer located in the fin structure 210 of the first region I, and a second source-drain doped layer located in the fin structure 210 of the second region II; the first source-drain doped layer has first source-drain doping ions, and the second source-drain doped layer has second source-drain doping ions; the first source-drain doping ions and the second source-drain doping ions have different conductivity types.
[0099] The first source and drain doping ions are P-type ions, and the second source and drain doping ions are N-type ions; or the first source and drain doping ions are N-type ions, and the second source and drain doping ions are P-type ions.
[0100] When the first region I is used to form a P-type device, the material of the first source and drain doping layer includes: silicon, germanium or silicon germanium; the first source and drain doping ions are P-type ions, including boron ions, BF 2- ions or indium ions; the second region II is used for N-type devices, and the material of the second source and drain doping layer includes: silicon, gallium arsenide or indium gallium arsenide; the second source and drain doping ions are N-type ions, including phosphorus ions or arsenic ions.
[0101] refer to Figure 21 , Figure 21 and Figure 20 The cross-sectional direction is consistent with that of the substrate 200 . After forming the source-drain doping layer 291 , a dielectric layer 320 is formed on the substrate 200 . The dielectric layer 320 exposes the top surface of the first dummy gate structure 270 .
[0102] In this embodiment, the dielectric layer 320 also exposes the top surface of the second dummy gate structure 280 .
[0103] In this embodiment, the dielectric layer 320 covers the sidewalls and top surface of the source / drain doped layer 291 , the sidewalls and top surface of the fin structure 210 , and the sidewall surfaces of the first dummy gate structure 270 and the second dummy gate structure 280 .
[0104] In this embodiment, the material of the dielectric layer 320 is silicon oxide; in other embodiments, the material of the dielectric layer 320 may also be silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride.
[0105] In this embodiment, the method for forming the dielectric layer 320 includes: forming an initial dielectric layer film (not shown) on the substrate 200, the initial dielectric layer film covering the surface of the substrate 200, the surface of the source-drain doped layer 291, the surface of the fin structure 210, the surface of the first dummy gate structure 270 and the surface of the second dummy gate structure 280; etching the initial dielectric layer film until the top surfaces of the first dummy gate structure 270 and the second dummy gate structure 280 are exposed, thereby forming a dielectric layer 320 on the substrate 200.
[0106] The process for forming the initial dielectric layer film is a deposition process, such as a plasma chemical vapor deposition process or a fluid chemical vapor deposition process.
[0107] The process of etching the initial dielectric layer film includes: a chemical mechanical polishing process.
[0108] refer to Figure 22 , Figure 22 and Figure 21 The cross-sectional direction is consistent. After the dielectric layer 320 is formed, the first dummy gate structure 270 is removed; the second fin layer 213 and the sacrificial layer 251 covered by the first dummy gate structure 270 are removed, and a first gate opening 330 is formed in the dielectric layer 320.
[0109] In this embodiment, the first gate opening 330 exposes the surface of the first fin layer 212 and the sidewall surfaces and top surface of the isolation structure 260 .
[0110] The first gate opening 330 provides space for subsequently forming a first gate structure.
[0111] In this embodiment, the method for forming the first gate opening 330 includes: removing the first dummy gate structure 270 to form a first initial gate opening (not shown) in the dielectric layer 320 ; and removing the second fin layer 213 and the sacrificial layer 251 exposed by the first initial gate opening to form the first gate opening 330 .
[0112] The second fin layer 213 and the sacrificial layer 251 are removed by dry etching or wet etching. In this embodiment, the second fin layer 213 and the sacrificial layer 251 are removed by dry etching. The dry etching process has a good etching selectivity for silicon and silicon germanium, thereby reducing etching damage to the first fin layer 212 and improving the morphology of the first fin layer 212.
[0113] In this embodiment, the process further includes: removing the second dummy gate structure 280 , and forming a second gate opening (not shown) in the dielectric layer 320 .
[0114] refer to Figures 23 to 26 , Figure 23 is a top view of the semiconductor structure with the dielectric layer 320 omitted. Figure 24 yes Figure 23 Schematic diagram of the cross-sectional structure along the C1-C1 direction, Figure 25 yes Figure 23 Schematic diagram of the cross-sectional structure along the C2-C2 direction, Figure 26 yes Figure 23Schematic diagram of the structure along the bb direction, a first gate structure 340 is formed in the first gate opening 330, the first gate structure 340 spans the first part of the fin structure 210, the first gate structure 340 surrounds each first fin layer 212, and the top surface of the first gate structure 340 is flush with the top surface of the isolation structure 260.
[0115] In this embodiment, the first gate structure 340 includes a first sub-gate structure located in the first region I and a second sub-gate structure located in the second region II. The isolation structure 260 isolates the first sub-gate structure from the second sub-gate structure.
[0116] In this embodiment, before forming the first gate structure 340, part of the first fin layer 212 in the first part of the fin structure 210 on both sides of the first opening 220 is etched away, thereby expanding the distance between the first parts of adjacent fin structures 210, so that there is a certain space between the first fin layer 212 and the isolation structure 260, so that the formed first gate structure 340 can surround the first fin layer 212 on all sides, thereby increasing the control capability of the channel.
[0117] In this embodiment, the first gate structure 340 includes a first gate dielectric layer (not shown) and a first gate layer (not labeled) located on the surface of the first gate dielectric layer.
[0118] In this embodiment, the material of the first gate dielectric layer is a high-k dielectric material (dielectric constant greater than 3.9); the high-k dielectric material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.
[0119] The material of the first gate layer is metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.
[0120] In this embodiment, the second gate structure 350 is further formed in the second gate opening. The second gate structure 350 spans the second portion of the fin structure 210 in the first region I and the second portion of the fin structure 210 in the second region II along the first direction X.
[0121] In this embodiment, the second gate structure 350 includes a second gate dielectric layer (not shown) and a second gate layer (not labeled) located on the surface of the second gate dielectric layer.
[0122] In this embodiment, the material of the second gate dielectric layer is the same as that of the first gate dielectric layer; and the material of the second gate layer is the same as that of the first gate layer.
[0123] Correspondingly, an embodiment of the present invention further provides a semiconductor structure.
[0124] refer to Figures 23 to 26 The semiconductor structure includes: a substrate 200, wherein the substrate 200 includes a first region 101 and a second region 102; a fin structure 210 located on the substrate 200 between the first region 101 and the second region 102; the fin structure 210 includes a bottom region 211 and a top region located on the bottom region 211; the top region includes a first fin layer 212 stacked along a normal direction of the surface of the substrate 200; a first gap (not shown) is formed between adjacent first fin layers 212; the fin structure further includes a first portion and a second portion along an extension direction of the fin structure; adjacent fin structures 212 are spaced apart from each other. The distance d1 between the first parts of the fin structure 210 is greater than the distance d2 between the second parts; the isolation structure 260 is located between the first parts of the adjacent fin structures 210 in the first region 101 and the second region 102, and there is a second spacing (not marked) between the isolation structure 260 and the first part of the fin structure 210; the first gate structure 340 spans the first part of the fin structure 210, is located on the surface of the first fin layer 212 and surrounds the first fin layer 212, and the top surface of the first gate structure 340 is flush with the top surface of the isolation structure 260.
[0125] In this embodiment, since there is a second gap between the first fin layer 212 and the isolation structure 260 , the first gate structure 340 can surround the first fin layer 212 on all sides, thereby enhancing the control capability of the channel and improving the performance of the semiconductor structure.
[0126] In this embodiment, the material of the isolation structure 260 is silicon oxide; in other embodiments, the material of the isolation structure 260 may also be one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, or silicon boron carbon nitride.
[0127] In this embodiment, the first gate structure 340 includes a first sub-gate structure located in the first region I and a second sub-gate structure located in the second region II. The isolation structure 260 is used to achieve isolation between the first sub-gate structure and the second sub-gate structure.
[0128] In this embodiment, the second gate structure 350 is further included. The second gate structure 350 spans the second portion of the fin structure 210 along the first direction X and is continuous in the first direction X.
[0129] In this embodiment, the fin structure 210 further includes a source-drain doped layer 291 located in the fin structure 210 on both sides of the first gate structure 340 and the second gate structure 350 .
[0130] In this embodiment, the source-drain doped layer 291 includes a first source-drain doped layer located in the first region I and a second source-drain doped layer located in the second region II, the first source-drain doped layer contains first source-drain doping ions, and the second source-drain doped layer contains second source-drain doping ions; the first source-drain doping ions and the second source-drain doping ions have different conductivity types; the first source-drain doping ions include N-type ions or P-type ions; the second source-drain doping ions include N-type ions or P-type ions.
[0131] In this embodiment, the present invention further includes: a dielectric layer 320 located on the substrate 200 , wherein the dielectric layer 320 covers the sidewalls of the first gate structure 340 and the second gate structure 350 .
[0132] In this embodiment, the present invention further includes: an isolation layer 230 located on the substrate 200 , wherein the isolation layer 230 covers a portion of the sidewall surface of the fin structure 210 , and a top surface of the isolation layer 230 is lower than a top surface of the fin structure 210 .
[0133] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; forming a fin structure on the first region and the second region respectively, with a first opening between adjacent first regions and second regions, the fin structure comprising a bottom region and a top region located on the bottom region, the top region comprising a first fin layer and a second fin layer alternately stacked along a normal direction of a substrate surface, and the fin structure further comprising a first portion and a second portion along an extension direction of the fin structure; Etching a portion of the first fin layer of the first portion on both sides of the first opening to form a first groove between adjacent second fin layers and between the second fin layer and the bottom area; forming a sacrificial layer in the first groove; forming an isolation structure in the first opening between the first portions, wherein a top surface of the isolation structure is higher than a top surface of the fin structure; forming a plurality of first dummy gate structures spanning the first portion of the fin structure and the isolation structure; removing the first dummy gate structure and the second fin layer and the sacrificial layer covered by the first dummy gate structure to form a first gate opening; A first gate structure is formed in the first gate opening, the first gate structure surrounds each of the first fin layers, and a top surface of the first gate structure is flush with a top surface of the isolation structure.
2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first fin layer is different from the material of the second fin layer; the material of the first fin layer includes silicon or silicon germanium; the material of the second fin layer includes silicon or silicon germanium.
3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial layer is the same as that of the second fin layer; the material of the sacrificial layer includes silicon or silicon germanium.
4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the isolation structure includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon boron carbon nitride.
5. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching part of the first fin layer of the first portion on both sides of the first opening includes an isotropic wet etching process; process parameters of the wet etching process include: the wet etching solution includes a TMAH solution or an ammonia solution.
6. The method for forming a semiconductor structure according to claim 1, wherein: A first mask layer is also formed on the fin structure, and the step of forming a sacrificial layer in the first groove includes: forming a sacrificial material layer in the first groove, and the sacrificial material layer also fills the first opening; using the first mask layer as a mask, etching and removing the sacrificial material layer in the first opening, and forming a sacrificial layer in the first groove.
7. The method for forming a semiconductor structure according to claim 1, wherein: Before etching the first portion of the first fin layer on both sides of the first opening, the method further includes: forming a second mask layer on the substrate, wherein the second mask layer exposes the sidewalls of the first portion of the fin structure on both sides of the first opening.
8. The method for forming a semiconductor structure according to claim 7, wherein: The material of the second mask layer includes amorphous carbon, bottom anti-reflection material or photoresist material.
9. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first dummy gate structure, the method further includes: forming source-drain openings in the fin structure on both sides of the first dummy gate structure, wherein the source-drain openings expose the substrate surface; and forming source-drain doping layers in the source-drain openings.
10. The method for forming a semiconductor structure according to claim 9, wherein: After forming the source / drain openings and before forming the source / drain doping layers, the method further includes: removing a portion of the second fin layer exposed by the sidewalls of the source / drain openings, and forming a second groove on the first fin layer.
11. The method for forming a semiconductor structure according to claim 10, wherein: Before forming the source-drain doped layer, the method further includes: forming an inner sidewall in the second groove, wherein the sidewall of the inner sidewall is flush with the sidewall of the first fin layer.
12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the inner sidewall includes low-k dielectric material, ultra-low-k dielectric material, silicon nitride or silicon nitride oxide.
13. The method for forming a semiconductor structure according to claim 9, wherein: After forming the source-drain doping layer, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer exposes the top surface of the first dummy gate structure.
14. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: An isolation layer is formed on the substrate, wherein the isolation layer covers a portion of the sidewall surface of the fin structure.
15. A semiconductor structure, characterized in that: include: a substrate comprising a first region and a second region; A fin structure located on the substrate in the first and second regions, the fin structure comprising a bottom region and a top region located on the bottom region, the top region comprising first fin layers stacked along a normal direction of a substrate surface, a first interval between adjacent first fin layers, the fin structure further comprising a first portion and a second portion along an extension direction of the fin structure, a distance between adjacent first portions of the fin structure being greater than a distance between adjacent second portions; An isolation structure is located between first portions of the adjacent fin structures in the first region and the second region, and a second interval is formed between the isolation structure and the first portion of the fin structure; The first gate structure spans across the first portion of the fin structure, is located on the surface of the first fin layer and surrounds the first fin layer, and the top surface of the first gate structure is flush with the top surface of the isolation structure.