Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor structures and methods of manufacturing the same. A semiconductor structure includes a first stack of active channel layers disposed above a semiconductor substrate and a second stack of active channel layers, wherein the second stack includes dummy channel layers and the first stack is devoid of any dummy channel layers; a gate structure joined with the first and second stacks; and first and second S / D features, the first S / D feature disposed adjacent to the first stack and the second S / D feature disposed adjacent to the second stack, wherein the second S / D feature overlaps the dummy channel layers.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor structures and methods of fabricating the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This process of downscaling has generally provided benefits by increasing production efficiency and reducing associated costs. This downscaling has also increased the complexity of IC processing and manufacturing, necessitating similar developments in IC processing and manufacturing to achieve these advances.

[0003] As integrated circuit (IC) technology progresses to smaller technology nodes, three-dimensional multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed on more than one side of a channel region. A nanosheet field effect transistor (NS FET; alternatively referred to as a gate all-around FET or GAA FET) is an example of a multi-gate device. A NS FET generally includes a gate structure that may extend partially or completely around a channel region to provide access to the channel region on two or more sides. NS FETs having different configurations may be suitable for different circuit functions due to their different performance characteristics. While existing NS FETs and methods for forming NS FETs are generally adequate for their intended purposes, they are not satisfactory in all respects. Summary of the Invention

[0004] According to one aspect of the present disclosure, a semiconductor structure is provided, including: a first stack of effective channel layers, arranged on a semiconductor substrate; a second stack of effective channel layers, arranged on the semiconductor substrate; a dummy channel layer, arranged in the second stack, wherein the first stack does not have any dummy channel layer; a gate structure, joined to the first stack and the second stack; and a first source / drain S / D feature and a second S / D feature, the first S / D feature being arranged adjacent to the first stack, and the second S / D feature being arranged adjacent to the second stack, wherein the second S / D feature overlaps the dummy channel layer.

[0005] According to another aspect of the present disclosure, a semiconductor structure is provided, comprising: a first fin structure comprising a first stack of effective channel layers and protruding from a substrate; a second fin structure comprising a second stack of effective channel layers disposed above at least one dummy channel layer and protruding from the substrate; a gate structure bonded to the first stack and the second stack; a first source / drain (S / D) feature disposed in the first fin structure and adjacent to the first stack, wherein the first S / D feature comprises a first doped epitaxial layer disposed above an undoped epitaxial layer; and a second S / D feature disposed in the second fin structure and adjacent to the second stack, wherein the second S / D feature comprises a second doped epitaxial layer disposed above the undoped epitaxial layer, and wherein the undoped epitaxial layer overlaps the at least one dummy channel layer.

[0006] According to another aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: providing a semiconductor substrate having a first region and a second region; forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin comprises a first stack of effective channel layers and the second fin comprises a second stack of effective channel layers disposed above at least one dummy channel layer, and wherein the effective channel layer and the at least one dummy channel layer have different compositions; forming a dummy gate stack above the first fin and the second fin; forming a first source / drain S / D feature in the first fin and a second S / D feature in the second fin, wherein the second S / D feature overlaps with the at least one dummy channel layer; and replacing the dummy gate stack with a metal gate stack, wherein the metal gate stack is formed adjacent to the first S / D feature and the second S / D feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood by the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A and Figure 1B A flowchart illustrating an example method for fabricating a semiconductor device according to various embodiments of the present disclosure is shown.

[0009] Figure 1C 、 Figure 1D and Figure 1E Each shows a flow chart of an example method for fabricating a portion of a semiconductor device according to various embodiments of the present disclosure.

[0010] Figure 2is a three-dimensional perspective view of a portion of an example semiconductor device according to various embodiments of the present disclosure.

[0011] Figure 3 、 Figure 4 、 Figure 5 and Figure 6A According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 2 The cross-sectional view of the semiconductor device is taken along line LL'.

[0012] Figure 6B and Figure 13A According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stage of the method shown Figure 2 A planar top view of a semiconductor device is shown.

[0013] Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A and Figure 12A According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 6B The cross-sectional view of the semiconductor device is taken along line AA′.

[0014] Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B and Figure 12B According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 6B The cross-sectional view of the semiconductor device is taken along line BB'.

[0015] Figure 7C 、 Figure 8C 、 Figure 9C 、 Figure 10C 、 Figure 11C and Figure 12C According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 6B The cross-sectional view of the semiconductor device is taken along line CC'.

[0016] Figure 14A 、 Figure 16A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 22A 、 Figure 24A 、 Figure 26A 、 Figure 27A 、 Figure 28A 、 Figure 30A 、 Figure 32A 、 Figure 34A 、 Figure 35A 、 Figure 49A 、 Figure 51A and Figure 53A According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A The cross-sectional view of the semiconductor device is taken along line AA′.

[0017] Figure 14B 、 Figure 16B 、 Figure 18B 、 Figure 19B 、 Figure 20B 、 Figure 22B 、 Figure 24B 、 Figure 26B 、 Figure 27B 、 Figure 28B 、 Figure 30B 、 Figure 32B 、 Figure 34B 、 Figure 35B 、 Figure 49B 、 Figure 51B and Figure 53B According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A The cross-sectional view of the semiconductor device is taken along line BB'.

[0018] Figure 14C 、 Figure 16C 、 Figure 18C 、 Figure 19C 、 Figure 20C 、 Figure 22C 、 Figure 24C 、 Figure 26C 、 Figure 27C 、 Figure 28C 、 Figure 30C 、 Figure 32C 、 Figure 34C 、 Figure 35C 、 Figure 49C 、 Figure 51C and Figure 53C According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A The cross-sectional view of the semiconductor device is taken along line CC'.

[0019] Figure 13B 、 Figure 37A 、 Figure 39A 、 Figure 41A 、 Figure 43A 、 Figure 45A 、 Figure 46A and Figure 47A According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A The cross-sectional view of the semiconductor device is taken along line DD′.

[0020] Figure 13C 、 Figure 37B 、 Figure 39B 、 Figure 41B 、 Figure 43B 、 Figure 45B 、 Figure 46B and Figure 47B According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A The cross-sectional view of the semiconductor device is taken along line EE'.

[0021] Figure 13D 、 Figure 37C 、 Figure 39C 、 Figure 41C 、 Figure 43C 、 Figure 45C 、 Figure 46C and Figure 47CAccording to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A The cross-sectional view of the semiconductor device is taken along line FF'.

[0022] Figure 15A 、 Figure 17A 、 Figure 21A 、 Figure 23A 、 Figure 25A 、 Figure 29A 、 Figure 31A 、 Figure 33A 、 Figure 36A 、 Figure 38A 、 Figure 40A 、 Figure 42A 、 Figure 44A 、 Figure 48A 、 Figure 50A 、 Figure 52A and Figure 54A According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A FIG. 1 is a cross-sectional view of the semiconductor device taken along line GG′.

[0023] Figure 15B 、 Figure 17B 、 Figure 21B 、 Figure 23B 、 Figure 25B 、 Figure 29B 、 Figure 31B 、 Figure 33B 、 Figure 36B 、 Figure 38B 、 Figure 40B 、 Figure 42B 、 Figure 44B 、 Figure 48B 、 Figure 50B 、 Figure 52B and Figure 54B According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A The cross-sectional view of the semiconductor device is taken along line HH'.

[0024] Figure 15C 、 Figure 17C 、 Figure 21C 、 Figure 23C、 Figure 25C 、 Figure 29C 、 Figure 31C 、 Figure 33C 、 Figure 36C 、 Figure 38C 、 Figure 40C 、 Figure 42C 、 Figure 44C 、 Figure 48C 、 Figure 50C 、 Figure 52C and Figure 54C According to various embodiments of the present disclosure Figure 1A 、 Figure 1B 、 Figure 1C 、 Figure 1D and / or Figure 1E During the intermediate stages of the method shown along Figure 13A FIG. 1 is a cross-sectional view of the semiconductor device taken along line II′. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description of the present disclosure, a feature formed on, connected to, and / or coupled to another feature may include an embodiment in which additional features are inserted between these features so that these features may not be in direct contact. In addition, spatially related terms such as, for example, "lower," "upper," "horizontally," "vertically," "above," "above," "below," "under," "upward," "downward," "top," "bottom," and the like, as well as derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.), may be used herein to describe the relationship between a feature and another feature in the present disclosure. These spatially related terms are intended to encompass the different orientations of devices comprising features.

[0026] In addition, when "about," "approximately," or the like is used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range including the number, such as within a + / - 10% range of the number or other value understood by one skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0027] The present disclosure relates generally to semiconductor devices and, more particularly, to field effect transistors (FETs) in memory and / or standard logic cells of integrated circuit (IC) structures, such as three-dimensional multi-gate nanostructure (NS) FETs (alternatively referred to as gate-all-around FETs or GAA FETs). Typically, NS FETs are configured with multiple vertically stacked sheets (e.g., nanosheets), wires (e.g., nanowires), or rods (e.g., nanorods) as channel regions that interface with a metal gate stack, thereby allowing for better gate control, lower leakage current, and improved scaling capabilities for various IC applications. The present disclosure includes multiple embodiments. Different embodiments may have different advantages, and no embodiment necessarily requires a specific advantage.

[0028] Now commonly refer to Figure 1A and Figure 1B , a flow chart of a method 100 of forming a semiconductor structure 200 (hereinafter referred to as structure 200 ) is shown according to various aspects of the present disclosure. Figure 1C-1E Flowcharts are shown for methods 300, 400, and 500, respectively, for forming a portion of structure 200 according to various aspects of the present disclosure. Methods 100, 300, 400, and 500 are merely examples and are not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional operations may be provided before, during, and after methods 100, 300, 400, and 500, and some of the operations described may be replaced, eliminated, or moved for additional embodiments of the methods. Figure 2-54C Methods 100, 300, 400, and 500 are described, Figure 2-54C 1 and 2 are various cross-sectional views and planar top views of structure 200 at intermediate steps of method 100. For example, Figure 2 is a three-dimensional perspective view of a portion of structure 200; Figure 3 、 Figure 4 、 Figure 5 and Figure 6A It is along Figure 2 A cross-sectional view of the structure 200 taken along line LL' is shown; and Figure 6B and Figure 13A is a top plan view of the structure 200. In addition, Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A and Figure 12A It is along Figure 6B A cross-sectional view of the structure 200 taken along line AA′ is shown; Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B and Figure 12B It is along Figure 6BA cross-sectional view of the structure 200 taken along line BB′ is shown; Figure 7C 、 Figure 8C 、 Figure 9C 、 Figure 10C 、 Figure 11C and Figure 12C It is along Figure 6B A cross-sectional view of the structure 200 taken along line CC′ is shown; Figure 14A 、 Figure 16A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 22A 、 Figure 24A 、 Figure 26A 、 Figure 27A 、 Figure 28A 、 Figure 30A 、 Figure 32A 、 Figure 34A 、 Figure 35A 、 Figure 49A 、 Figure 51A and Figure 53A It is along Figure 13A A cross-sectional view of the structure 200 taken along line AA′ is shown; Figure 14B 、 Figure 16B 、 Figure 18B 、 Figure 19B 、 Figure 20B 、 Figure 22B 、 Figure 24B 、 Figure 26B 、 Figure 27B 、 Figure 28B 、 Figure 30B 、 Figure 32B 、 Figure 34B 、 Figure 35B 、 Figure 49B 、 Figure 51B and Figure 53B It is along Figure 13A A cross-sectional view of the structure 200 taken along line BB′ is shown; Figure 14C 、 Figure 16C 、 Figure 18C 、 Figure 19C 、 Figure 20C 、 Figure 22C 、 Figure 24C 、 Figure 26C 、 Figure 27C 、 Figure 28C 、 Figure 30C 、 Figure 32C 、 Figure 34C 、 Figure 35C 、 Figure 49C 、 Figure 51C and Figure 53C It is along Figure 13A A cross-sectional view of the structure 200 taken along line CC' is shown; Figure 13B 、 Figure 37A 、 Figure 39A 、 Figure 41A 、 Figure 43A 、 Figure 45A 、 Figure 46A and Figure 47A It is along Figure 13A A cross-sectional view of the structure 200 taken along line DD′ is shown; Figure 13C 、 Figure 37B 、 Figure 39B 、 Figure 41B 、 Figure 43B 、 Figure 45B 、 Figure 46B and Figure 47B It is along Figure 13A A cross-sectional view of the structure 200 taken along line EE′ is shown; Figure 13D 、 Figure 37C 、 Figure 39C 、 Figure 41C 、 Figure 43C 、 Figure 45C 、 Figure 46C and Figure 47C It is along Figure 13A A cross-sectional view of the structure 200 taken along line FF′ is shown; Figure 15A 、 Figure 17A 、 Figure 21A 、 Figure 23A 、 Figure 25A 、 Figure 29A 、 Figure 31A 、 Figure 33A 、 Figure 36A 、 Figure 38A 、 Figure 40A 、 Figure 42A 、 Figure 44A 、 Figure 48A 、 Figure 50A 、 Figure 52A and Figure 54A It is along Figure 13A A cross-sectional view of the structure 200 taken along line GG′ is shown; Figure 15B 、 Figure 17B 、 Figure 21B 、 Figure 23B 、 Figure 25B 、 Figure 29B 、 Figure 31B 、 Figure 33B 、 Figure 36B 、 Figure 38B 、 Figure 40B 、 Figure 42B 、 Figure 44B 、 Figure 48B 、 Figure 50B 、 Figure 52B and Figure 54B It is along Figure 13A A cross-sectional view of structure 200 taken along line HH' is shown; and Figure 15C 、 Figure 17C 、 Figure 21C 、 Figure 23C 、 Figure 25C 、 Figure 29C 、 Figure 31C 、 Figure 33C 、 Figure 36C 、 Figure 38C 、 Figure 40C 、 Figure 42C 、 Figure 44C 、 Figure 48C 、 Figure 50C 、 Figure 52C and Figure 54C It is along Figure 13A The cross-sectional view of the structure 200 is taken along line II′.

[0029] The structure 200 may be an intermediate device fabricated during processing of an IC or a portion thereof, which may include static random access memory (SRAM) and / or other logic circuits, passive components (e.g., resistors, capacitors, and inductors), and active components (e.g., NS FETs, FinFETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and / or other transistors. In the present embodiment, the structure 200 includes one or more NS FETs. The present disclosure is not limited to any particular number of devices or device regions, nor to any particular device configuration. Additional features may be added to the structure 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the structure 200.

[0030] In operation 102, reference Figure 2-Figure 3 , method 100 provides a substrate 202 and forms a non-channel layer 205 and a channel layer 206 on the substrate 202. In this embodiment, the non-channel layer 205 and the channel layer 206 constitute the bottom of a multi-layer structure (ML), thereby forming a fin active area (or fin). As described herein, method 100 forms a bottommost pair of non-channel layers 205 and channel layers 206 at operation 102.

[0031] Substrate 202 may include elemental (single element) semiconductors such as silicon (Si), germanium (Ge), and / or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. Substrate 202 may be a single layer of material having a uniform composition. Alternatively, substrate 202 may include multiple layers of material having similar or different compositions suitable for IC device fabrication. In this embodiment, substrate 202 (and the ML subsequently formed thereon) includes two regions 202a and 202b. Although depicted as being adjacent to each other, regions 202a and 202b are not necessarily physically arranged in this manner and may be separated by (one or more) other regions.

[0032] In the present embodiment, the non-channel layers 205 of the ML are sacrificial layers that are configured to be removed in subsequent processing steps, thereby providing openings between the channel layers 206 for forming portions of the metal gate stack therein. Each channel layer 206 can include a semiconductor material, such as Si, Ge, SiC, SiGe, GeSn, SiGeSn, other suitable semiconductor materials, or combinations thereof, while the composition of each non-channel layer 205 is different from the composition of the channel layer 206. In one such example, as in the present embodiment, the channel layer 206 can include elemental Si and the non-channel layer 205 can include SiGe. In another example, the channel layer 206 can include elemental Si and the non-channel layer 205 can include elemental Ge. In the present embodiment, the channel layer 206 is free or substantially free of any dopant species and is therefore alternatively referred to as an effective channel layer.

[0033] In the present embodiment, forming the non-channel layer 205 and the channel layer 206 includes performing a series of epitaxial processes. The epitaxial process can be implemented by chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure (LP-CVD) and / or plasma enhanced CVD (PE-CVD)), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or combinations thereof. The epitaxial process can use a gas and / or liquid precursor containing a suitable material (e.g., Ge for the non-channel layer 205) that interacts with the composition of the underlying substrate (e.g., substrate 202). In some examples, the non-channel layer 205 and the channel layer 206 can be formed as nanosheets, nanowires, or nanorods.

[0034] In operation 104, reference Figure 4-Figure 5, the method 100 performs an implantation process (eg, an ion implantation process) 602 selectively on the region 202b relative to the region 202a. Figure 4 , method 100 first forms a patterned masking element 207 over region 202a to expose region 202b. The patterned masking element 207 has an etch selectivity relative to the channel layer 206 and can be formed by a series of photolithography and etching processes. The patterned masking element 207 can be a three-layer structure, which includes a photoresist layer, an intermediate layer (including metal, polymer and / or other suitable materials), and a bottom anti-reflective (BARC) layer. Forming the patterned masking element 207 can include exposing the photoresist layer, developing the photoresist layer, and etching the remaining portion of the masking element using the patterned photoresist layer as an etching mask.

[0035] Then, refer to Figure 5 , method 100 performs an implantation process 602 on the region 202b exposed by the patterned masking element 207. The implantation process 602 is configured to form an anti-perforation (APT) layer (alternatively referred to as a dummy channel layer) 206a above the non-channel layer 205 in the region 202b. In other words, the implantation process 602 implants dopant species into the portion of the channel layer 206 in the region 202b, while the portion of the channel layer 206 in the region 202a remains undoped or substantially undoped.

[0036] In some embodiments, the laser is heated at a temperature of about 600° C. to about 1100° C. with a beam energy of about 2 keV to about 100 keV and a beam energy of about 1×10 13 ions / cm 2 to about 1×10 15 ions / cm 2 The implantation process 602 is performed with an ion dose of 1×10 18 ions / cm 32 or higher. In some examples, the thickness of the APT layer 206a can be about 10 nm to about 30 nm and can be detected using techniques such as energy dispersive X-ray spectroscopy (EDS, EDX, EDX, or XEDS). Depending on the conductivity type of the device to be fabricated above the regions 202a and 202b, the implantation process 602 can implant different dopant types. For example, to form an n-type device (e.g., an n-type NS FET), a p-type dopant, such as boron (B) and / or boron difluoride (BF2), is implanted into the APT layer 206a. Conversely, to form a p-type device (e.g., a p-type NS FET), an n-type dopant, such as phosphorus (P) or arsenic (As), is implanted into the APT layer 206a. After performing the implantation process 602, the patterned masking element 207 is removed from the structure 200 by a suitable method such as plasma ashing and / or resist stripping.

[0037] Although structure 200, as described herein, includes only one APT layer 206a formed in region 202b, it should be noted that the present embodiment is not limited to this configuration. For example, after forming APT layer 206a as described above, method 100 may repeat operations 102 and 104 by forming one or more additional pairs of non-channel layers 205 and channel layers 206 above APT layer 206a, forming a patterned masking element (similar to patterned masking element 207) thereon, and performing an implantation process (similar to implantation process 602) to form another APT layer (similar to APT layer 206a) in region 202b before proceeding to operation 106. In this regard, the number M of APT layers formed above substrate 202 as part of the ML may be at least one in region 202b (and none in region 202a), or 1≤M in region 202b, where M is a natural number and is further defined below. Regardless of the total number of APT layers present in structure 200 , the present embodiment replaces at least the bottommost channel layer 206 with an APT layer 206 a in region 202 b .

[0038] In operation 106, reference Figure 6A-6B, method 100 completes forming the ML above the APT layer 206a. The ML includes alternating non-channel layers 205 and channel layers 206 (including the APT layer 206a in region 202b) stacked vertically above the substrate 202. In this embodiment, method 100 forms at least another pair of alternating non-channel layers 205 and channel layers 206 above the APT layer 206a at operation 106. In other words, the total number N of pairs of non-channel layers 205 and channel layers 206 (including the APT layer 206a) in the ML is at least M+1, or (M+1)≤N. Stated another way, 1≤M≤(N-1). In some embodiments, as described herein, the ML includes more channel layers 206 than APT layers 206a. In some embodiments, the ML includes more APT layers 206a than channel layers 206. In some embodiments, N does not exceed 6; however, this embodiment is not limited to this configuration, as long as at least another pair is formed above the APT layer 206a. For example, as described herein, the ML includes one APT layer 206 a and a total of three pairs of alternating non-channel layers 205 and channel layers 206 / APT layers 206 a, or M = 1 and N = 3. In this embodiment, forming the remainder of the ML includes alternating growth of the non-channel layers 205 and the channel layers 206 in a series of epitaxial processes, as discussed in detail above in operation 102.

[0039] In this embodiment, the method 100 further forms a hard mask layer 205a on the ML at operation 106, and forms a hard mask layer 209 on the hard mask layer 205a. The hard mask layer 205a is a sacrificial layer configured to assist in forming isolation features between subsequently formed fins. In some embodiments, the hard mask layer 205a can be formed to a thickness T1 that is greater than the thickness of the non-channel layer 205 and the channel layer 206. The hard mask layer 205a can include any suitable material, such as a semiconductor material, as long as its composition is different from the composition of the isolation features and the channel layer 206 disposed thereunder to allow for selective removal by an etching process. In some embodiments, the hard mask layer 205a has a composition similar to or the same as that of the non-channel layer 205 and includes, for example, SiGe. For embodiments in which the hard mask layer 205a has the same composition as the non-channel layer 205, the hard mask layer 205a is also grown by a similar epitaxial process as described above.

[0040] On the other hand, the hard mask layer 209 is configured to protect the underlying hard mask layer 205a and the ML during subsequent manufacturing processes and can include any suitable dielectric material, such as silicon oxide (SiO and / or SiO2), silicon nitride (SiN), silicon carbide (SiC), oxynitride (SiN), oxycarbide (SiOC), carbonitride (SiCN), aluminum oxide (Al2O3), other suitable materials, or combinations thereof. The hard mask layer 209 can be formed by any suitable method, such as atomic layer deposition (ALD), CVD, other suitable methods, or combinations thereof.

[0041] In operation 108, reference Figure 6B and Figures 7A-7C , method 100 uses a series of photolithography and etching processes (similar to the processes discussed above with respect to forming patterned masking element 207) to form fins 204a-204c from the ML. In the present embodiment, fins 204a and 204b protrude from region 202a, while fin 204c protrudes from region 202b. For example, the photolithography process may include forming a masking element over the ML, exposing the masking element, and developing the exposed masking element to form a patterned masking element (not shown). The patterned masking element is then used as an etch mask to etch the hard mask layer 209, followed by etching the hard mask layer 205a and the ML to form fins 204a-204c protruding from the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), other suitable processes, or combinations thereof. Subsequently, the patterned masking element is removed from the ML using any suitable process, such as ashing and / or resist stripping.

[0042] In operation 110, reference Figures 8A-8CMethod 100 forms an isolation structure 208 in the trench separating the fins 204a-204c. The isolation structure 208 may include silicon oxide (SiO and / or SiO2), tetraethyl orthosilicate (TEOS), doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), a low-k dielectric material (with a dielectric constant less than that of silicon oxide, approximately 3.9), other suitable materials, or combinations thereof. The isolation structure 208 may include a shallow trench isolation (STI) feature. In one embodiment, the isolation structure 208 is formed by filling the trench separating the fins 204a-204c with the above-described dielectric material using any suitable method, such as CVD, flowable CVD (FCVD), spin-on glass (SOG), other suitable methods, or combinations thereof. The dielectric material may then be planarized by a chemical mechanical planarization / polishing (CMP) process and selectively etched back to form isolation structure 208. Isolation structure 208 may include a single-layer structure or a multi-layer structure. In some embodiments, the CMP process also removes hard mask layer 209 from structure 200. In some embodiments, after isolation structure 208 is formed, hard mask layer 209 is removed separately by an etching process.

[0043] In operation 112, reference Figures 9A-9C , method 100 forms a cladding layer 210 over the fins 204a-204c and the isolation structure 208. In the present embodiment, the cladding layer 210 and the non-channel layer 205 are sacrificial layers configured to be replaced with a metal gate stack in the channel region of each fin 204a-204c. In this regard, the cladding layer 210 has a composition substantially the same as that of the non-channel layer 205 so that they can be removed by a common etching process. In the present embodiment, the cladding layer 210 includes SiGe. In some embodiments, the cladding layer 210 is epitaxially deposited by a suitable method discussed above with respect to forming the ML. In some embodiments, as Figures 9A-9C As shown, the cladding layer 210 is conformally deposited (rather than epitaxially grown) as an amorphous layer on the surface of the structure 200, so that the cladding layer 210 is also formed on the isolation structure 208. In some examples, the cladding layer 210 can be formed to a thickness of about 5 nm to about 10 nm. Subsequently, the method 100 performs a directional (or anisotropic) etching process to selectively remove portions of the cladding layer 210, thereby exposing portions of the isolation structure 208 and the top surface of the hard mask layer 205a. The etching process can include a dry etching process, a wet etching process, an RIE process, or a combination thereof. The etching process can implement an etchant that selectively removes horizontal portions of the cladding layer 210 without removing or substantially removing vertical portions of the cladding isolation structure 208 or 210.

[0044] In operation 114, reference Figures 10A-10C , method 100 forms a dielectric feature 211 over structure 200, thereby completely filling the trenches between adjacent fins 204a-204c. Dielectric feature 211 is configured to isolate adjacent fins 204a-204c and provide a substrate on which gate isolation features may be subsequently formed. Dielectric feature 211 may include a single layer structure or a multi-layer structure. As described herein, dielectric feature 211 is separated from each sidewall of fins 204a-204c by a portion of cladding layer 210.

[0045] In this embodiment, dielectric feature 211 includes two layers, with dielectric layer 213 disposed over dielectric layer 212. Dielectric layers 212 and 213 can each include silicon oxide (SiO and / or SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (Al2O3), tetraethyl orthosilicate (TEOS), doped silicon oxide (e.g., borophosphosilicate glass (BPSG), FSG, phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), a high-k dielectric material (with a k value greater than that of silicon oxide, approximately 3.9), other suitable materials, or combinations thereof. The high-k dielectric material can include oxygen, lanthanum, aluminum, titanium, zirconium, tantalum, other suitable materials, or combinations thereof. For example, the high-k dielectric material can include hafnium oxide (HfO2), lanthanum oxide (La2O3), other high-k oxide materials, or combinations thereof. In the present embodiment, the composition of dielectric layer 212 is different from the composition of dielectric layer 213. In some embodiments, the dielectric constant of dielectric layer 213 is greater than the dielectric constant of dielectric layer 212. In one example, dielectric layer 212 may include SiN and dielectric layer 213 may include HfO2. In another example, dielectric layer 212 may include silicon oxide and dielectric layer 213 may include SiN. In some embodiments, dielectric features 211 have a composition similar to or the same as that of isolation structure 208. Of course, the present embodiment is not limited to these compositions. The various layers of dielectric features 211 may be deposited by any suitable method (e.g., CVD, FCVD, SOG, other suitable methods, or combinations thereof) and subsequently planarized by one or more CMP processes to expose the top surface of hard mask layer 205a.

[0046] In operation 116, reference Figures 11A-11C, method 100 forms a dielectric helmet 214 over dielectric feature 211. In some embodiments, dielectric cap 214 provides one or more gate isolation features that are configured to separate (or cut) a metal gate stack subsequently formed over fins 204a-204c. In this embodiment, to enhance etch selectivity, dielectric cap 214 is configured with a composition different from that of dielectric layers 212 and 213 and may include silicon oxide, SiN, SiC, SiON, SiOC, SiCN, Al2O3, a high-k dielectric material, other suitable materials, or combinations thereof. In some embodiments, dielectric cap 214 includes a dielectric material having a higher dielectric constant than dielectric layers 212 and 213. For example, dielectric cap 214 may include a high-k dielectric material, such as HfO2, dielectric layer 212 may include SiN, and dielectric layer 213 may include silicon oxide.

[0047] In some embodiments, method 100 forms dielectric cap 214 by first recessing dielectric feature 211 to form a trench (not shown), depositing a dielectric material in the trench by a suitable method such as CVD and / or ALD, and planarizing the dielectric material by a CMP process to form dielectric cap 214. In some embodiments, dielectric cap 214 is formed to a thickness T2 that is no greater than a thickness T1 of hard mask layer 205a. In some examples, T2 is at least approximately half of T1.

[0048] Now refer to Figures 12A-13D , the method 100 forms a dummy gate stack 220 over the channel region of the fins 204a-204c at operation 118. In this embodiment, referring to Figures 12A-12C , method 100 first removes hard mask layer 205a to form trench 215, thereby exposing the topmost channel layer 206 of the ML. In this embodiment, method 100 selectively removes hard mask layer 205a without removing or substantially removing dielectric cap 214 or the topmost channel layer 206 of the ML.

[0049] Then, refer to Figures 13A-13D , method 100 forms a dummy gate stack 220 over the channel region of the fins 204a-204c, thereby filling the trench 215. In this embodiment, one or more dummy gate stacks 220 are formed over the dielectric cap 214. Each dummy gate stack 220 may include a dummy gate electrode (not separately shown) disposed over an optional dummy gate dielectric layer. In some embodiments, at least a portion of each dummy gate stack 220 will be replaced by a metal gate stack, which may be separated (or cut) by the dielectric cap 214.

[0050] The dummy gate stack 220 can be formed by a series of deposition and patterning processes. For example, the dummy gate stack 220 can be formed by depositing a polysilicon (poly-Si) layer on the fins 204a-204c separated by the dielectric cap 214, and then patterning the polysilicon layer through a series of photolithography and etching processes (e.g., an anisotropic dry etching process). In some embodiments, before forming the dummy gate stack 220, an interface layer 221 is formed on the fins 204a-204c. The interface layer 221 may include silicon oxide and may be formed by any suitable method, such as thermal oxidation, chemical oxidation, other suitable methods, or combinations thereof. In the illustrated embodiment, hard mask layers 223 and 225 are formed on the dummy gate stack 220 to accommodate the patterning process and protect the dummy gate stack 220 during subsequent manufacturing processes. The hard mask layers 223 and 225 may include any suitable dielectric material, including silicon oxide, SiN, SiC, SiON, SiOC, SiCN, Al2O3, high-k dielectric materials (e.g., hafnium oxide (HfO2), lanthanum oxide (La2O3), etc.), other suitable materials, or combinations thereof, and may be formed by any suitable method (e.g., CVD and / or ALD).

[0051] refer to Figure 13A , the method 100 then forms a top gate spacer 222a on the sidewalls of the dummy gate stack 220 at operation 118. The top gate spacer 222a can be a single-layer structure or a multi-layer structure and can include silicon oxide, SiN, SiC, SiON, SiOC, SiCN, air, a low-k dielectric material, a high-k dielectric material (e.g., hafnium oxide (HfO2), lanthanum oxide (La2O3), etc.), other suitable materials, or combinations thereof. Each spacer layer of the top gate spacer 222a can be formed by first depositing a dielectric layer over the dummy gate stack 220 via a suitable deposition method (e.g., CVD and / or ALD), and then removing portions of the dielectric layer in an anisotropic (or directional) etching process (e.g., a dry etching process), leaving the top gate spacer 222a on the sidewalls of the dummy gate stack 220.

[0052] At operation 120, the method 100 forms epitaxial S / D features in portions of the fins 204a-204c adjacent to the dummy gate stack 220. In this embodiment, forming the epitaxial S / D features generally includes: forming S / D recesses in the S / D regions of the fins 204a-204c (i.e., ML), forming internal gate spacers on sidewalls of the non-channel layer 205 exposed in the S / D recesses, and forming the epitaxial S / D features in the S / D recesses. In this embodiment, operation 120 is performed by, respectively, Figure 1C 、 Figure 1D and Figure 1E It should be noted that the methods 300, 400 and 500 are independent of each other and can be substituted for each other, so they are equally applicable to the embodiments disclosed herein. For the sake of clarity, the methods 300, 400 and 500 are discussed separately below. For example, according to Figures 14A-17C Method 300 is discussed; according to Figures 18A-25C Method 400 is discussed; and according to Figures 26A-33A Method 500 is discussed.

[0053] refer to Figure 1D and Figures 14A-15C At operation 302 , method 300 performs an etching process 604 to remove a portion of the S / D region from each of the fins 204 a, 204 b, and 204 c to form S / D recesses 230 a, 230 b, and 230 c, respectively. In this embodiment, etching process 604 selectively removes portions of the fins 204 a-204 c and the cladding layer 210 without removing or substantially removing the dummy gate stack 220, the dielectric feature 211, the dielectric cap 214, and the isolation structure 208. In some embodiments, etching process 604 is a dry etching process using a suitable etchant capable of removing Si (i.e., the channel layer 206) and SiGe (i.e., the non-channel layer 205) of the ML, which includes the APT layer 206 a as part of the fin 204 c. In some non-limiting examples, the dry etching agent can be a chlorine-containing etchant, including Cl 2 , SiCl 4 , BCl 3 , other chlorine-containing gases, or combinations thereof. A cleaning process may then be performed to clean the S / D recesses 230 a - 230 c using a hydrofluoric acid (HF) solution or other suitable solution.

[0054] refer to Figures 15A-15C The depth of each S / D recess 230a, 230b, and 230c, measured from the bottom surface of each S / D recess to the top of each fin (defined as D1, D2, and D3, respectively), is controlled by adjusting the duration of the etching process 604. In this embodiment, the depths D1, D2, and D3 are substantially the same because the etching process 604 is commonly applied to both regions 202a and 202b. Furthermore, the depths D1-D3 are controlled such that each of the S / D recesses 230a-230c extends below the bottommost sheet of ML (i.e., the bottommost non-channel layer 205). In some examples, the ratio of this extension, defined by the depth D1′, to the depth D1 (or either of D2 and D3) can be about 0.1 to about 0.4. Figure 15A and Figure 15B The embodiments shown are essentially the same and each Figure 15C The illustration is different because the S / D recess 230c exposes a portion of the APT layer 206a.

[0055] Still refer to Figures 15A-15C In operation 304, method 300 forms an internal gate spacer 222b on the sidewalls of the non-channel layer 205 exposed in the S / D recesses 230a-230c. The internal gate spacer 222b can be a single-layer structure or a multi-layer structure and can include silicon oxide, SiN, SiCN, SiOC, SiON, SiOCN, a low-k dielectric material, air, a high-k dielectric material (e.g., hafnium oxide (HfO2), lanthanum oxide (La2O3)), other suitable dielectric materials, or combinations thereof. In some embodiments, the internal gate spacer 222b has a composition different from that of the top gate spacer 222a. Forming the internal gate spacer 222b includes performing a series of etching and deposition processes. For example, forming the internal gate spacer 222b can begin by selectively removing a portion of the non-channel layer 205 without removing or substantially removing a portion of the channel layer 206 to form a trench (not shown). The non-channel layer 205 can be etched by a dry etching process. Subsequently, one or more dielectric layers are formed in the trenches, followed by one or more etching processes to remove (i.e., etch back) excess dielectric layer(s) deposited on the surface of the channel layer 206 exposed in the S / D recesses, thereby forming a dielectric layer 206 as shown in FIG. Figures 15A-15C The internal gate spacer 222b is shown. The one or more dielectric layers may be deposited by any suitable method, such as ALD, CVD, physical vapor deposition (PVD), other suitable methods, or combinations thereof.

[0056] Then, refer to Figures 16A-17C At operation 306, method 300 forms epitaxial S / D features 242a, 242b, and 242c in S / D recesses 230a, 230b, and 230c, respectively, in an epitaxial process 606. Each of epitaxial S / D features 242a-242c may be suitable for forming a p-type device (i.e., comprising p-type epitaxial material) or, alternatively, an n-type FET device (i.e., comprising n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon germanium (epi-SiGe), each doped with a p-type dopant, such as boron, boron fluoride (BF2), other p-type dopants, or combinations thereof. The n-type epitaxial material may include one or more epitaxial layers of silicon (epi-Si) or silicon carbon (epi-SiC), each doped with an n-type dopant, such as asparagine, phosphorus, other n-type dopants, or combinations thereof. In this embodiment, the conductivity type of the dopant in epitaxial S / D feature 242 c is different from the conductivity type of the dopant included in APT layer 206 a. For example, if APT layer 206 a includes a p-type dopant, epitaxial S / D feature 242 c includes an n-type dopant to provide an n-type device. Conversely, if APT layer 206 a includes an n-type dopant, epitaxial S / D feature 242 c includes a p-type dopant to provide a p-type device.

[0057] In this embodiment, performing the epitaxial process 606 includes growing epitaxial semiconductor material in each S / D recess 230 a-230 c and over the internal gate spacer 222 b in a process similar to that discussed above with respect to forming the ML. In some embodiments, the epitaxial semiconductor material is in-situ doped by adding the dopant species discussed above to the source material during the epitaxial process 606. In some embodiments, the epitaxial semiconductor material is doped by an ion implantation process after the deposition process is performed. In some embodiments, an annealing process is performed to activate the dopant species in the epitaxial S / D features 242 a-242 c.

[0058] Since the S / D recesses 230a-230c are formed to substantially the same depth, the epitaxial S / D features 242a-242c are also formed to substantially the same size. Figure 17C As shown, the APT layer 206a is present in the fin 204c, and the effective overlap area between the epitaxial S / D feature 242c and the channel region of the fin 204c is determined by the depth D3. eff Limited, depth D3 eff Less than Figure 15C The depth D3 of the S / D recess 230c is shown. In other words, the epitaxial S / D feature 242c overlaps a smaller amount of the channel layer 206 than each of the epitaxial S / D features 242a and 242b. In terms of device function, although the epitaxial S / D feature 242c extends to contact the bottom surface of the S / D recess 230c, the APT layer 206a forms a dummy (or inactive) NS FET with the epitaxial S / D feature 242c. In this regard, the reduction in the overlap area reduces the parasitic gate-drain capacitance (C gd ), thereby improving the processing speed of the NS FET when applied in an alternating current (AC) setting (e.g., by reducing RC delay). On the other hand, in the absence of the APT layer 206a, the effective overlap area between the epitaxial S / D features 242a and 242b and their corresponding channel regions is respectively determined by D1 eff and D2 eff Limited, D1 eff and D2 eff Equal to depths D1 and D2, and both greater than D3 eff In other words, in each NS FET provided by epitaxial S / D features 242a and 242b, an additional channel layer 206 participates in conducting the on-state current, making them more suitable for high current (HC) or high performance computing (HPC) applications than the NS FET provided by epitaxial S / D feature 242c. If fin 204c includes more than one APT layer 206a, then C gd Will be further reduced.

[0059] Thus, the present disclosure contemplates a semiconductor device (i.e., structure 200) comprising at least two different NS FETs having different overlap areas between their respective epitaxial S / D features and channel layers, thereby enabling reduced C gd and increased current conduction. Figures 14A-17C In the illustrated embodiment, this advantage is achieved by providing an APT layer 206a at the bottom of the ML in region 202b, thereby effectively "turning off" the bottom channel layer while keeping the epitaxial S / D features 242a-242c substantially the same size.

[0060] Now refer to Figure 1D and Figures 18A-18C , the method 400 performs an etching process 608 at operation 402 to selectively remove the portion of the fin 204c in the region 202b to form the S / D recess 230c. Figure 18A and Figure 18B , method 400 implements patterned masking element 232 over region 202a to protect fins 204a and 204b from being etched. Patterned masking element 232 can be similar to patterned masking element 207 discussed in detail above. Etching process 608 is similar to etching process 604 in that it is configured to selectively remove ML and cladding layer 210 without removing or substantially removing surrounding dielectric components. In this embodiment, S / D recess 230c is defined by depth D6, as shown in FIG. Figure 21C After forming the S / D recess 230 c , the method 400 removes the patterned masking element 232 by any suitable method, such as plasma ashing and / or resist stripping.

[0061] refer to Figures 19A-19C , the method 400 performs an etching process 610 at operation 404 to selectively remove portions of the fins 204a and 204b in the region 202a to form S / D recesses 230a and 230b. Figure 19C , method 400 implements patterned masking element 234 (which may be similar to patterned masking element 207) over region 202b to protect S / D recess 230c from further etching. Etching process 610 is similar to etching process 608 in that it is configured to selectively remove ML and cladding layer 210 without removing or substantially removing surrounding dielectric components. In this embodiment, S / D recess 230a is formed by such a depth (e.g., Figure 21A The depth of the S / D recess 230b is defined by D4 as shown in FIG. Figure 21BThe depth D5 shown is substantially the same, both of which are greater than the depth D6 of the S / D recess 230c. After forming the S / D recesses 230a and 230b, refer to Figures 20A-20C The method 400 removes the patterned masking element 234 by any suitable method, such as plasma ashing and / or resist stripping.

[0062] In this embodiment, etching process 610 is performed using etching parameters that are different from the etching parameters of etching process 608 to ensure that depths D4 and D5 are greater than depth D6. In some embodiments, when all other parameters remain constant, the duration of etching process 610 is greater than the duration of etching process 608. In some embodiments, when all other parameters remain constant, the voltage bias applied during etching process 610 is greater than the voltage bias applied during etching process 608. Although not specifically discussed, other etching parameters may also be adjusted to ensure that S / D recess 230c is shallower than S / D recesses 230a and 230b.

[0063] In this embodiment, reference Figures 20A-21C The difference D between the depths D5 (or D4) and D6 is measured between the bottom surface of the S / D recess 230b (or S / D recess 203a) and the bottom surface of the S / D recess 230c. diff In some embodiments, the depth D diff The ratio of the depth D5 (or D4) is about 0.1 to about 0.4, and the depth D diff The ratio of the depth D6 is about 0.1 to about 0.5. In some examples, the depth D diff It may be from about 10 nm to about 30 nm.

[0064] refer to Figures 21A-21C , the method 400 forms the internal gate spacers 222 b in the S / D recesses 230 a - 230 c at operation 406 in a series of processes similar to that discussed above with respect to operation 304 .

[0065] Then, refer to Figures 22A-23C, method 400 forms a buffer layer 240 at operation 408 to partially fill the S / D recesses 230 a-230 c during a deposition process 612. In this embodiment, the buffer layer 240 comprises elemental Si and is free of any dopant species. In this respect, the deposition process 612 is similar to the epitaxial process performed to form the ML, wherein the deposition process 612 comprises epitaxially forming an undoped semiconductor layer in the S / D recesses 230 a-230 c, i.e., free of any dopant species. In this embodiment, the deposition process 612 is controlled such that the buffer layer 240 is formed to a thickness D7 no greater than a depth D6, i.e., the buffer layer 240 does not completely fill any of the S / D recesses 230 a-230 c. For embodiments where the number M of APT layers 206 a is less than the number (NM) of undoped channel layers (alternatively referred to as active channel layers) 206 formed thereon, as described herein, the thickness D7 is less than approximately half the depth D6. Alternatively, for embodiments where the number M of APT layers 206a is greater than the number (NM) of undoped channel layers 206 formed thereon, the thickness D7 is greater than about half the depth D6. In some embodiments, the depth D7 is no greater than the depth D6. diff In some examples, depth D7 may be from about 5 nm to about 30 nm.

[0066] Note that the present embodiment does not limit the composition of the buffer layer 240 to epitaxially grown elemental Si, and the buffer layer 240 may be implemented to include semiconductor materials and / or dielectric materials that are epitaxially grown differently (e.g., SiN, SiCN, SiO2, oxygen- and carbon-containing silicon nitride (SiOCN), etc.), as long as it does not contain any dopant species, i.e., any n-type and p-type dopant species. For embodiments in which the buffer layer 240 includes a dielectric material, the deposition process 612 may be performed using CVD, ALD, other suitable processes, or combinations thereof.

[0067] refer to Figures 24A-25CAt operation 410, method 400 forms semiconductor layers 244a, 244b, and 244c over buffer layer 240 in an epitaxial process 614, thereby producing epitaxial S / D features 245a, 245b, and 245c, respectively. In this embodiment, epitaxial process 614 is similar to epitaxial process 606 discussed above with respect to operation 306, wherein epitaxial process 614 includes forming semiconductor layers 244a-244c to include one or more dopant species, respectively, over buffer layer 240 in S / D recesses 230a-230c. For example, each of doped semiconductor layers 244a-244c may be suitable for forming a p-type device (i.e., including p-type epitaxial material) or, alternatively, an n-type FET device (i.e., including n-type epitaxial material), both of which are discussed in detail with respect to epitaxial S / D features 242a-242c. Similar to the above discussion, the conductivity type of the dopant in semiconductor layer 244c is different from the conductivity type of the dopant included in APT layer 206a. For example, if APT layer 206a includes a p-type dopant, semiconductor layer 244c includes an n-type dopant to provide an n-type device. Conversely, if APT layer 206a includes an n-type dopant, semiconductor layer 244c includes a p-type dopant to provide a p-type device.

[0068] and Figures 24A-25C Compared with the embodiment shown, Figures 17A-17C The epitaxial S / D features 242a-242c are shown without any undoped buffer layer. In this regard, the effective overlap area in the epitaxial S / D features 245a, 245b and 245c is determined by the depth D4, D5 and D6, respectively. eff 、D5 eff and D6 eff Define, where depth D6 eff Less than depth D4 eff and D5 eff As described in this article, depth D4 eff 、D5 eff and D6 eff The thickness of the semiconductor layers 244a, 244b and 244c are also defined. In this embodiment, the semiconductor layer 244c does not, or at least substantially does not, overlap with the APT layer 206a. Instead, Figure 17C Each epitaxial S / D feature 242c is shown overlapping the APT layer 206a, but is separated by a depth D3. eff The defined effective overlap area is less than the total depth D3 of the epitaxial S / D features 242 c .

[0069] Now refer to Figure 1E and Figures 26A-26C , the method 500 performs an etching process 616 at operation 502 to selectively remove portions of the fins 204b and 204c to form S / D recesses 230b and 230c, respectively. Figure 26A , method 500 implements patterned masking element 236 on a portion of region 202a to protect fin 204a from being etched. Patterned masking element 236 can be similar to patterned masking element 207 discussed in detail above. Etching process 616 is similar to etching process 604 in that it is configured to selectively remove ML and cladding layer 210 without removing or substantially removing surrounding dielectric components. In this embodiment, S / D recess 230b is formed by such a depth (e.g., Figure 29B The depth of the S / D recess 230c is defined by D9 as shown. Figure 29C After forming the S / D recesses 230b and 230c, the method 100 removes the patterned masking element 236 by any suitable method, such as plasma ashing and / or resist stripping.

[0070] refer to Figures 27A-27C , the method 500 performs an etching process 618 at operation 504 to selectively remove the portion of the fin 204a in the region 202a to form the S / D recess 230a. Figure 27B and Figure 27C , method 100 implements patterned masking element 238 (which may be similar to patterned masking element 207) over a portion of region 202a and region 202b to protect S / D recesses 230b and 230c from further etching. Etching process 618 is similar to etching process 608 in that it is configured to selectively remove ML and cladding layer 210 without removing or substantially removing surrounding dielectric components. In this embodiment, S / D recess 230a is defined by depth D8, as shown in FIG. Figure 29A As shown, the depth D8 is greater than the depths D9 and D10. After forming the S / D concave portion 230a, refer to Figures 28A-28C The method 500 removes the patterned masking element 238 by any suitable method, such as plasma ashing and / or resist stripping.

[0071] Similar to the discussion of method 400 above, etching process 618 is performed using etching parameters that differ from the etching parameters of etching process 616 to ensure that the depth of the resulting S / D recess 230a is greater than the depth of S / D recesses 230b and 230c. In some embodiments, the duration of etching process 618 is greater than the duration of etching process 616, with all other parameters remaining constant. In some embodiments, the voltage bias applied during etching process 618 is greater than the voltage bias applied during etching process 616, with all other parameters remaining constant. Although not specifically discussed, other etching parameters may also be adjusted to ensure that S / D recess 230a is deeper than S / D recesses 230b and 230c.

[0072] In this embodiment, reference Figures 28A-29C The depth difference D′ of the S / D recesses 230a and 230b (or 230c) is measured between the bottom surface of the S / D recess 230a and the bottom surface of the S / D recess 230b (or 230c). diff In some embodiments, the depth D' diff The ratio of the depth D8 is about 0.1 to about 0.4, and the depth D' diff The ratio of the depth D9 is about 0.1 to about 0.5. In some examples, the depth D' diff It may be from about 10 nm to about 30 nm.

[0073] refer to Figures 29A-29C The method 500 forms internal gate spacers 222 b in the S / D recesses 230 a - 230 c at operation 506 in a series of processes similar to that discussed above with respect to operation 304 .

[0074] Then, refer to Figures 30A-31C , method 500 forms a buffer layer 240 at operation 508 to partially fill the S / D recesses 230a-230c during the deposition process 620. Details of the buffer layer 240 and its formation method have been discussed above with respect to operation 408. In the present embodiment, the deposition process 620 is controlled such that the buffer layer 240 does not completely fill the S / D recesses 230a-230c, i.e., the thickness D11 is less than the depths D8, D9, and D10. For embodiments where the number M of APT layers 206a is less than the number (NM) of undoped channel layers 206 formed thereon, as described herein, the thickness D11 is less than approximately half of the depth D10. Alternatively, for embodiments where the number M of APT layers 206a is greater than the number (NM) of undoped channel layers 206 formed thereon, the thickness D11 is greater than approximately half of the depth D10. In some embodiments, the depth D11 is no greater than the depth D' diff In some examples, depth D11 may be from about 5 nm to about 30 nm.

[0075] refer to Figures 32A-33C At operation 510, method 500 forms doped semiconductor layers 246a, 246b, and 246c on buffer layer 240 in an epitaxial process 622, thereby producing epitaxial S / D features 247a, 247b, and 247c, respectively. The details of doped semiconductor layers 246a-246c and their formation methods are similar to the details of doped semiconductor layers 244a-244c and have been discussed above with respect to operation 410.

[0076] and Figures 33A-33C Compared with the embodiment shown, Figures 17A-17CThe epitaxial S / D features 242a-242c are shown without any undoped buffer layer. In this regard, the effective overlap area in the epitaxial S / D features 247b and 247c is determined by the depth D9, D1, D2, D3, and D4, respectively. eff and D10 eff The effective overlap area in the epitaxial S / D feature 247a is defined by the depth D8. eff Limited, depth D8 eff Greater than depth D9 eff and D10 eff As mentioned in this article, the depth D8 eff 、D9 eff and D10 eff The thicknesses of the semiconductor layers 246a, 246b, and 246c are also defined, respectively. Figure 25C In the embodiment shown, the semiconductor layer 246c does not overlap, or at least does not substantially overlap, the APT layer 206a. Figure 33A and Figure 33B Although the epitaxial S / D features 247a and 247b interface with the same amount of channel layer 206, their effective overlapping areas are different due to the different depths of the S / D recesses and the presence of the undoped buffer layer 240, which together result in a depth D8 of eff and D9 eff The difference between.

[0077] After forming the epitaxial S / D features (242a-242c, 245a-245c, or 247a-247c) in the fins 204a-204c, the method 100 continues as follows. Figure 1B The operation shown is 122. For simplicity, use Figures 16A-17C The illustrated embodiment discusses the subsequent operations of method 100, namely operations 122 to 136, as examples. Of course, these operations are equally applicable to Figures 24A-25C and Figures 32A-33C The embodiment shown.

[0078] Now refer to Figure 1B and Figures 34A-34C , the method 100 removes the portion of the dielectric cap 214 exposed in the S / D regions of the fins 204a-204c at operation 122. In this embodiment, the method 100 performs a selective etching process (e.g., a dry etching process) to remove the portion of the dielectric cap 214 without removing or substantially removing the epitaxial S / D features 242a-242c.

[0079] Afterwards, refer to Figures 35A-36C , the method 100 removes the dummy gate stack 220 (and the interface layer 221 ) from the structure 200 at operation 124 . Figures 35A-35CMethod 100 first forms an etch stop layer (ESL) 250 over structure 200 to protect underlying components, such as epitaxial S / D features 242a-242c, during subsequent fabrication processes. ESL 250 may include any suitable dielectric material, such as SiN, SiCN, SiON, Al2O3, other suitable materials, or combinations thereof, and may be formed by CVD, ALD, PVD, other suitable methods, or combinations thereof. In this embodiment, ESL 250 provides etch selectivity relative to surrounding dielectric components to prevent unintended damage.

[0080] Subsequently, method 100 forms an interlayer dielectric (ILD) layer 252 on top of ESL 250 to fill the space between adjacent dummy gate stacks 220. ILD layer 252 may include silicon oxide, a low-k dielectric material, TEOS, doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof, and may be formed by any suitable method, such as CVD, FCVD, SOG, other suitable methods, or combinations thereof. Method 100 then performs one or more CMP processes to expose the top surface of dummy gate stack 220.

[0081] refer to Figures 36A-36C , method 100 then removes the dummy gate stack 220 from the structure 200 in an etching process to form the gate trench 256. In this embodiment, method 100 selectively removes the dummy gate stack 220 (including the interface layer 221) without removing or substantially removing the channel layer 206 and surrounding dielectric components. The etching process can include any suitable process, such as a dry etching process, a wet etching process, RIE, or a combination thereof.

[0082] In some embodiments, although not described herein, method 100 optionally patterns the dielectric cap 214 remaining in the channel region of the fins 204a-204c to form gate isolation features for separating a subsequently formed metal gate stack. The patterning process may include forming a patterned masking element over structure 200 to expose a portion of the dummy gate stack 220, removing the exposed portion of the dummy gate stack 220 to expose a portion of the underlying dielectric cap 214, and removing the exposed portion of the dielectric cap 214. After removing the patterned masking element, the remaining portion of the dielectric cap 214 becomes a gate isolation feature for a subsequently formed metal gate stack. In an alternative embodiment, as will be discussed in detail below, the dielectric cap 214 is removed in its entirety in a subsequent operation, and the gate isolation features are formed separately after the metal gate stack is formed.

[0083] In operation 126, reference Figures 37A-38C, method 100 removes the non-channel layer 205 from the ML to form openings 258 between the channel layers 206 during a sheet formation or sheet release process. In this embodiment, the sheet formation process further removes the remaining cladding layer 210, which has a similar or identical composition to the non-channel layer 205, to form trenches 259 along the sidewalls of the fins 204a-204c. The sheet formation process is configured to selectively remove the non-channel layer 205 and the cladding layer 210 without removing or substantially removing the channel layer 206 or any other surrounding components of the structure 200. In other words, the openings 258 are interleaved with the channel layer 206. In some embodiments, the sheet formation process is implemented in a series of etching and trimming processes. In one example, a wet etching process can be performed to selectively remove the non-channel layer 205, the wet etching process using an oxidant (or oxide) (e.g., ozone (O3; dissolved in water), nitric acid (HNO3), hydrogen peroxide (H2O2), other suitable oxidants) and a fluorine-based etchant (e.g., hydrofluoric acid (HF), ammonium fluoride (NH4F)), other suitable etchants, or a combination thereof.

[0084] In operation 128, reference Figures 39A-40C , method 100 forms a metal gate stack 260 in gate trench 256, opening 258, and trench 259 such that metal gate stack 260 contacts sidewalls of fins 204a-204c and wraps around (or intersects) each channel layer 206. As described herein, metal gate stack 260 is bonded to fins 204a, 204b, and 204c to form NS field effect transistors 200a, 200b, and 220c, respectively.

[0085] In the present embodiment, the metal gate stack 260 includes an interface layer 262, a gate dielectric layer 264 above the interface layer 262, and a metal gate electrode 266 above the gate dielectric layer 264. The composition of the interface layer 262 can be similar to the composition of the interface layer 221. In the present embodiment, the gate dielectric layer 264 includes a high-k dielectric material such as HfO2, La2O3, other suitable materials, or combinations thereof, and the metal gate electrode 266 includes at least one work function metal layer (not shown separately) and a bulk conductive layer (not shown separately) disposed thereon. The work function metal layer can be a p-type or n-type work function metal layer. Example work function metals include TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function metals, or combinations thereof. The bulk conductive layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), other suitable materials, or combinations thereof. The metal gate stack 260 may also include other material layers (not shown), such as a capping layer, a barrier layer, other suitable layers, or combinations thereof. The various layers of the metal gate stack 260 may be formed by various methods, including chemical oxidation, thermal oxidation, ALD, CVD, PVD, electroplating, other suitable methods, or combinations thereof. After forming the bulk conductive layer, one or more CMP processes are performed to remove excess material formed on the top surface of the ILD layer 252, thereby planarizing the structure 200.

[0086] In operation 130, reference Figures 41A-42C , method 100 recesses the metal gate stack 260 in an etching process to form a trench 270. In the present embodiment, the etching process selectively removes a top portion of the metal gate stack 260, including at least some portions of the gate dielectric layer 264 and the metal gate electrode 266, without removing or substantially removing the dielectric cap 214 and other nearby dielectric components. The etching process can be performed by any suitable method using one or more etchants configured to etch components of the metal gate stack 260, including a dry etching process, a wet etching process, RIE, other suitable methods, or combinations thereof. In the present embodiment, the etching process is controlled to recess the metal gate stack 260 so that the top surface of the recessed metal gate stack 260 is lower than the top surface of the dielectric cap 214. In other words, the dielectric cap 214 protrudes from the top surface of the recessed metal gate stack 260.

[0087] At operation 132, the common reference Figures 43A-48C , the method 100 forms gate isolation features 274, which are configured to separate the metal gate stacks 260. Figures 43A-44C, method 100 forms a metal layer 272 over the recessed metal gate stack 260 and the dielectric cap 214. In some embodiments, the metal layer 272 comprises titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), nickel (Ni), W, Ru, Al, Co, other suitable metals, or combinations thereof. The metal layer 272 can be deposited using CVD or metal organic chemical vapor deposition (MOCVD). In one embodiment, the metal layer 272 comprises fluorine-free W and can be deposited using MOCVD. In some embodiments, the metal layer 272 is formed using a bottom-up approach. Subsequently, the method 100 removes the dielectric cap 214 from the structure 200 in a selective etching process (e.g., a dry etching process or a wet etching process) that is configured not to remove or substantially remove the dielectric features 211 or the metal layer 272.

[0088] refer to Figures 45A-45C , method 100 forms a gate isolation feature 274 over at least some portions of the dielectric feature 211. The gate isolation feature 274 may include any suitable material, such as SiN, SiCN, SiON, Al2O3, other suitable materials, or combinations thereof, and may be formed by a series of deposition and patterning processes. For example, forming the gate isolation feature 274 may include depositing a sacrificial layer (not shown) over the metal layer 272, patterning the sacrificial layer to form an opening configured for the gate isolation feature 274, depositing a dielectric layer over the patterned sacrificial layer to fill the opening, planarizing the dielectric layer to form the gate isolation feature 274, and selectively removing the sacrificial layer relative to the gate isolation feature 274. The sacrificial layer may include any suitable material, such as a photoresist layer, a BARC layer, a silicon layer, or other suitable material, as long as its composition is different from the composition of the gate isolation feature 274 to ensure sufficient etching selectivity therebetween.

[0089] Then, refer to Figures 46A-46C, method 100 deposits another metal layer 276 above metal layer 272 and between adjacent gate isolation features 274. In some embodiments, metal layer 276 includes Ti, TiN, Ta, Ni, W, Ru, Al, Co, other suitable metals, or combinations thereof. In some embodiments, metal layers 272 and 276 have the same composition. In some embodiments, metal layer 276 has a multilayer structure. Metal layer 276 can be formed in a manner similar to metal layer 272. In some embodiments, metal layer 276 includes fluorine-free W and can be deposited using MOCVD. In some embodiments, metal layer 272 serves as a seed layer for forming metal layer 276 in a bottom-up approach. In this embodiment, metal layer 276 is configured to electrically connect the portion of metal gate stack 260 between two gate isolation features 274. Therefore, metal layer 276 is formed to be less than the thickness of gate isolation feature 274 so that gate isolation feature 274 protrudes from metal layer 276.

[0090] Now refer to Figures 47A-48C , method 100 forms a dielectric layer 278 over metal layer 276 adjacent to gate isolation feature 274. In some embodiments, dielectric layer 278 comprises SiN, SiCN, SiOC, SiON, SiOCN, other suitable materials, or combinations thereof. Dielectric layer 278 can be deposited by any suitable method, such as ALD, CVD, PVD, other suitable methods, or combinations thereof. Subsequently, method 100 removes portions of dielectric layer 278 formed over gate isolation feature 274 in one or more CMP processes, thereby planarizing the top surface of structure 200.

[0091] refer to Figures 49A-50CAt operation 134, method 100 forms an S / D contact 280 over one or more epitaxial S / D features 242a-242c. In some embodiments, the S / D contact 280 includes Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, other suitable metals, or combinations thereof. In some embodiments, forming the S / D contact 280 includes patterning the ILD layer 252 and the ESL 250 to form contact openings (not shown), forming a metal silicide layer in the contact openings over the epitaxial S / D features 242a-242c, depositing a metal layer in the contact openings and over the metal silicide layer, and performing a CMP process on the metal layer to form the S / D contact 280. Depositing the metal layer can be performed by any suitable method, such as CVD, PVD, electroplating, other methods, or combinations thereof. The metal silicide layer may be formed by depositing a metal layer over the epitaxial S / D features 242 a - 242 c, processing the metal layer to react with the epitaxial S / D features 242 a - 242 c to form the metal silicide layer, and performing an etching process to remove an unreacted top portion of the metal layer and expose the underlying metal silicide layer. In some embodiments, a barrier layer may be formed over the metal silicide layer before forming the S / D contacts 280, wherein the barrier layer may include Ti, TiN, Ta, TaN, WN, other suitable materials, or combinations thereof.

[0092] Figures 51A-52C and Figures 53A-54C Depicted are embodiments of NS FETs 200a-200c that may be substituted for the NS FETs discussed in detail above. Figures 49A-50C For example, Figures 51A-52C The embodiment depicts NS FETs 200a, 200b, and 200c including epitaxial S / D features 245a, 245b, and 245c, respectively, wherein each epitaxial S / D feature 245a, 245b, and 245c comprises a doped epitaxial layer overlying an undoped buffer layer 240, and wherein the effective overlap area of ​​epitaxial S / D feature 245c is less than the effective overlap area of ​​each of epitaxial S / D features 245a and 245b. In this regard, the C of NS FET 200c is gd is less than the C of each of the NS FETs 200a and 200b gd , and NS FETs 200a and 200b are configured to provide greater current conduction than NS FET 200c. In addition, Figures 53A-54CThe embodiment depicts NS FETs 200a, 200b, and 200c including epitaxial S / D features 247a, 247b, and 247c, respectively, wherein each epitaxial S / D feature 247a, 247b, and 247c includes a doped epitaxial layer positioned above an undoped buffer layer 240, and wherein the effective overlap area of ​​each of the epitaxial S / D features 247b and 247c is less than the effective overlap area of ​​the epitaxial S / D feature 247a. In this regard, the C of the NS FETs 200b and 200c is gd Both are less than the C of NSFET 200a gd , and NS FET 200a is configured to provide greater current conduction than NS FETs 200b and 200c. Note that for Figure 54A and Figure 54B The illustrated embodiments of NS-FETs 200 a and 200 b , while not including the APT layer 206 a in either device, adjust the effective overlap area by adjusting the depth of their respective S / D recesses and the presence of the undoped buffer layer 240 .

[0093] Thereafter, method 100 operation 136 performs an additive manufacturing process on structure 200, such as forming a multi-layer interconnect (MLI) structure (not shown) thereon. The MLI may include various interconnect features, such as vias and conductive lines, disposed in dielectric layers (e.g., ESL and ILD layers). In some embodiments, vias are vertical interconnect features configured to interconnect device-level contacts, such as S / D contacts 280 or gate contacts (not shown), with conductive lines, or to interconnect different conductive lines, which are horizontal interconnect features. The ESL and ILD layers of the MLI may have compositions substantially the same as those discussed above with respect to ESL 250 and ILD layer 252, respectively. The vias and conductive lines may each comprise any suitable conductive material, such as Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, metal silicide, other suitable conductive materials, or combinations thereof, and may be formed through a series of patterning and deposition processes. In addition, each via and conductive line may further comprise a barrier layer comprising TiN and / or TaN.

[0094] While not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits to semiconductor devices and their formation. For example, the present disclosure provides different (i.e., hybrid) NS FETs, each configured with a channel layer stack bonded to a metal gate stack, and each NS FET formed over a different region of the same substrate. In this embodiment, the NS FETs differ in the configuration of their respective epitaxial S / D features. In some embodiments, one of the NS FETs includes one or more doped anti-puncture (APT) layers in its channel layer stack such that the overlap area (defined by vertical extension or depth) between the stack and the epitaxial S / D features is reduced compared to another NS FET without any APT layer in the channel layer stack. In some embodiments, the overlap area in one or more NS FETs is adjusted by controlling the depth of the S / D recess and / or by forming an undoped buffer layer below the doped epitaxial layer, with or without any APT layer. In other words, NS FETs with different overlap areas between their respective epitaxial S / D features and channel regions are formed on the same substrate, which in turn provides devices with relatively less overlap area (parasitic capacitance (C gd ) is reduced) and the benefits of devices with relatively more overlapped area (higher current conduction). Embodiments of the disclosed method can be easily integrated into existing processes and technologies for manufacturing NS FETs, FinFETs and / or other suitable devices.

[0095] In one aspect, the present embodiment provides a semiconductor structure comprising: a first stack of effective channel layers and a second stack of effective channel layers disposed above a semiconductor substrate, wherein the second stack includes a dummy channel layer and the first stack does not have any dummy channel layer; a gate structure bonded to the first stack and the second stack; and a first S / D feature and a second S / D feature, the first S / D feature being disposed adjacent to the first stack and the second S / D feature being disposed adjacent to the second stack, wherein the second S / D feature overlaps the dummy channel layer.

[0096] On the other hand, the present embodiment provides a semiconductor structure comprising: a first fin structure comprising a first stack of effective channel layers; and a second fin structure comprising a second stack of effective channel layers, the second stack being disposed above at least one dummy channel layer, the first fin structure and the second fin structure protruding from a substrate; a gate structure bonded to the first stack and the second stack; a first S / D feature disposed in the first fin structure and adjacent to the first stack, wherein the first S / D feature comprises a first doped epitaxial layer located above an undoped epitaxial layer; and a second S / D feature disposed in the second fin structure and adjacent to the second stack, wherein the second S / D feature comprises a second doped epitaxial layer located above the undoped epitaxial layer, and wherein the undoped epitaxial layer overlaps with at least one dummy channel layer.

[0097] On the other hand, the present embodiment provides a method of forming a semiconductor structure, wherein the method includes: providing a semiconductor substrate having a first region and a second region; forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin includes a first stack of effective channel layers and the second fin includes a second stack of effective channel layers disposed above at least one dummy channel layer, and wherein the effective channel layer and the at least one dummy channel layer have different compositions; forming a dummy gate stack above the first fin and the second fin; forming a first S / D feature in the first fin and a second S / D feature in the second fin, wherein the second S / D feature overlaps with the at least one dummy channel layer; and replacing the dummy gate stack with a metal gate stack, wherein the metal gate stack is formed adjacent to the first S / D feature and the second S / D feature.

[0098] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0099] Example 1. A semiconductor structure comprising: a first stack of effective channel layers disposed on a semiconductor substrate; a second stack of effective channel layers disposed on the semiconductor substrate; a dummy channel layer disposed within the second stack, wherein the first stack does not have any dummy channel layer; a gate structure bonded to the first stack and the second stack; and a first source / drain S / D feature and a second S / D feature, the first S / D feature being disposed adjacent to the first stack and the second S / D feature being disposed adjacent to the second stack, wherein the second S / D feature overlaps the dummy channel layer.

[0100] Example 2. A semiconductor structure according to Example 1, wherein the first stack includes a first number of effective channel layers, the second stack includes a second number of effective channel layers, and the second stack includes a third number of the dummy channel layers, and wherein the sum of the second number and the third number is equal to the first number.

[0101] Example 3. The semiconductor structure of Example 2, wherein the third number ranges from 1 to the first number minus 1.

[0102] Example 4. The semiconductor structure of Example 1, wherein the dummy channel layer comprises a first dopant species and the second S / D characteristic comprises a second dopant species having a conductivity type different from a conductivity type of the first dopant species.

[0103] Example 5. The semiconductor structure of Example 1, wherein the dummy channel layer comprises a semiconductor material doped with a p-type dopant or an n-type dopant, and wherein each effective channel layer in the first stack and the second stack does not contain any dopant.

[0104] Example 6. The semiconductor structure of Example 1, wherein the first S / D feature and the second S / D feature each comprise a doped semiconductor layer and have the same depth.

[0105] Example 7. The semiconductor structure of Example 6, wherein the doped semiconductor layer of the second S / D feature overlaps the dummy channel layer.

[0106] Example 8. A semiconductor structure according to Example 1, wherein the first S / D feature includes a first doped semiconductor layer disposed above an undoped semiconductor layer, and the second S / D feature includes a second doped semiconductor layer disposed above the undoped semiconductor layer, and wherein the first doped semiconductor layer extends below the second doped semiconductor layer.

[0107] Example 9. The semiconductor structure of Example 8, wherein the undoped semiconductor layer in the second S / D feature overlaps the dummy channel layer.

[0108] Example 10. A semiconductor structure comprising: a first fin structure comprising a first stack of effective channel layers and protruding from a substrate; a second fin structure comprising a second stack of effective channel layers disposed above at least one dummy channel layer and protruding from the substrate; a gate structure bonded to the first stack and the second stack; a first source / drain S / D feature disposed in the first fin structure and adjacent to the first stack, wherein the first S / D feature comprises a first doped epitaxial layer disposed above an undoped epitaxial layer; and a second S / D feature disposed in the second fin structure and adjacent to the second stack, wherein the second S / D feature comprises a second doped epitaxial layer disposed above the undoped epitaxial layer, and wherein the undoped epitaxial layer overlaps the at least one dummy channel layer.

[0109] Example 11. The semiconductor structure of Example 10, wherein the at least one dummy channel layer comprises a first dopant and the second S / D feature comprises a second dopant, and wherein a conductivity type of the first dopant is different from a conductivity type of the second dopant.

[0110] Example 12. The semiconductor structure of Example 10, wherein a total number of at least one dummy channel layer and active channel layers in the second stack is the same as a total number of active channel layers in the first stack.

[0111] Example 13. The semiconductor structure of Example 10 further includes: a third fin structure comprising a third stack of effective channel layers and protruding from the substrate, wherein the first stack and the third stack include the same number of effective channel layers; and a third S / D feature disposed in the third fin structure and adjacent to the third stack, wherein the third S / D feature comprises a third doped epitaxial layer located above the undoped epitaxial layer, and wherein the first S / D feature extends below the third S / D feature.

[0112] Example 14. The semiconductor structure of Example 13, wherein a first number of effective channel layers in the first stack that overlap the first S / D feature is greater than a second number of effective channel layers in the third stack that overlap the third S / D feature.

[0113] Example 15. The semiconductor structure of Example 13, wherein the offset between bottom surfaces of the first and third S / D features is greater than a thickness of the undoped epitaxial layer.

[0114] Example 16. A method for manufacturing a semiconductor structure, comprising: providing a semiconductor substrate having a first region and a second region; forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin includes a first stack of effective channel layers and the second fin includes a second stack of effective channel layers disposed above at least one dummy channel layer, and wherein the effective channel layer and the at least one dummy channel layer have different compositions; forming a dummy gate stack above the first fin and the second fin; forming a first source / drain S / D feature in the first fin and a second S / D feature in the second fin, wherein the second S / D feature overlaps with the at least one dummy channel layer; and replacing the dummy gate stack with a metal gate stack, wherein the metal gate stack is formed adjacent to the first S / D feature and the second S / D feature.

[0115] Example 17. The method of Example 16, wherein forming the first fin and the second fin includes: forming a sacrificial layer over the semiconductor substrate; forming a bottommost effective channel layer over the sacrificial layer; selectively performing an implantation process on a portion of the bottommost effective channel layer disposed in the second region relative to a portion of the bottommost effective channel layer disposed in the first region; thereafter, alternately forming the sacrificial layer and the effective channel layer over the bottommost effective channel layer to form a stack; and patterning the stack to form the first fin and the second fin.

[0116] Example 18. The method of Example 16, wherein a total number of active channel layers and at least one dummy channel layer in the second stack is the same as a total number of active channel layers in the first stack.

[0117] Example 19. A method according to Example 16, wherein forming the first S / D feature and the second S / D feature includes: forming a first S / D recess in the first fin and forming a second S / D recess in the second fin; epitaxially growing a first semiconductor layer in the first S / D recess and the second S / D recess, wherein the first semiconductor layer does not contain any dopant species, and wherein the first semiconductor layer overlaps with the at least one dummy channel layer; and epitaxially growing a second semiconductor layer above the first semiconductor layer, wherein the second semiconductor layer includes a dopant species.

[0118] Example 20. A method according to Example 16, wherein the effective channel layer does not contain any dopant type, the at least one dummy channel layer includes a first dopant type, and the second S / D feature includes a second dopant type, and wherein the first dopant type and the second dopant type have different conductivity types.

Claims

1. A semiconductor structure comprising: a first stack of active channel layers disposed on a semiconductor substrate; a second stack of active channel layers disposed above the semiconductor substrate; a dummy channel layer disposed in the second stack, wherein the first stack does not have any dummy channel layer; a gate structure bonded to the first stack and the second stack; and A first source / drain and a second source / drain, the first source / drain being disposed adjacent to the first stack and the second source / drain being disposed adjacent to the second stack, wherein the second source / drain overlaps the dummy channel layer.

2. The semiconductor structure according to claim 1, wherein The first stack includes a first number of active channel layers, the second stack includes a second number of active channel layers, and the second stack includes a third number of the dummy channel layers, and wherein a sum of the second number and the third number is equal to the first number.

3. The semiconductor structure according to claim 2, wherein: The third number ranges from 1 to the first number minus 1.

4. The semiconductor structure according to claim 1, wherein The dummy channel layer includes a first dopant species, and the second source / drain includes a second dopant species having a conductivity type different from a conductivity type of the first dopant species.

5. The semiconductor structure according to claim 1, wherein The dummy channel layer includes a semiconductor material doped with a p-type dopant or an n-type dopant, and wherein each of the active channel layers in the first stack and the second stack does not contain any dopant. The semiconductor structure according to claim 1 , wherein: The first source / drain and the second source / drain each include a doped semiconductor layer and have the same depth.

7. The semiconductor structure according to claim 6, wherein: The doped semiconductor layer of the second source / drain overlaps the dummy channel layer.

8. The semiconductor structure according to claim 1, wherein The first source / drain includes a first doped semiconductor layer disposed on an undoped semiconductor layer, and the second source / drain includes a second doped semiconductor layer disposed on the undoped semiconductor layer, wherein the first doped semiconductor layer extends lower than the second doped semiconductor layer.

9. The semiconductor structure according to claim 8, wherein The undoped semiconductor layer in the second source / drain overlaps the dummy channel layer.

10. A semiconductor structure comprising: a first fin structure including a first stack of active channel layers and protruding from the substrate; a second fin structure comprising a second stack of active channel layers disposed over the at least one dummy channel layer and protruding from the substrate; a gate structure bonded to the first stack and the second stack; a first source / drain disposed in the first fin structure and adjacent to the first stack, wherein the first source / drain comprises a first doped epitaxial layer located above the undoped epitaxial layer; and A second source / drain is disposed in the second fin structure and adjacent to the second stack, wherein the second source / drain comprises a second doped epitaxial layer located above the undoped epitaxial layer, and wherein the undoped epitaxial layer overlaps the at least one dummy channel layer.

11. The semiconductor structure according to claim 10, wherein The at least one dummy channel layer includes a first dopant, and the second source / drain includes a second dopant, and wherein a conductivity type of the first dopant is different from a conductivity type of the second dopant.

12. The semiconductor structure according to claim 10, wherein A total number of at least one dummy channel layer and active channel layers in the second stack is the same as a total number of active channel layers in the first stack.

13. The semiconductor structure of claim 10, further comprising: a third fin structure including a third stack of active channel layers and protruding from the substrate, wherein the first stack and the third stack include the same number of active channel layers; and A third source / drain is disposed in the third fin structure and adjacent to the third stack, wherein the third source / drain comprises a third doped epitaxial layer above the undoped epitaxial layer, and wherein the first source / drain extends below the third source / drain.

14. The semiconductor structure according to claim 13, wherein: A first number of effective channel layers in the first stack overlapping the first source / drain is greater than a second number of effective channel layers in the third stack overlapping the third source / drain.

15. The semiconductor structure according to claim 13, wherein An offset between bottom surfaces of the first source / drain and the third source / drain is greater than a thickness of the undoped epitaxial layer.

16. A method of manufacturing a semiconductor structure, comprising: providing a semiconductor substrate having a first region and a second region; forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin includes a first stack of active channel layers and the second fin includes a second stack of active channel layers disposed over at least one dummy channel layer, and wherein the active channel layer and the at least one dummy channel layer have different compositions; forming a dummy gate stack on the first fin and the second fin; forming a first source / drain in the first fin and forming a second source / drain in the second fin, wherein the second source / drain overlaps the at least one dummy channel layer; and The dummy gate stack is replaced with a metal gate stack, wherein the metal gate stack is formed adjacent to the first source / drain and the second source / drain.

17. The method according to claim 16, wherein Forming the first fin and the second fin includes: forming a sacrificial layer on the semiconductor substrate; forming a bottommost effective channel layer on the sacrificial layer; performing an implantation process selectively on a portion of the bottommost effective channel layer disposed in the second region relative to a portion of the bottommost effective channel layer disposed in the first region; Thereafter, alternately forming the sacrificial layer and the active channel layer on the bottommost active channel layer to form a stack; and The stack is patterned to form the first fin and the second fin.

18. The method according to claim 16, wherein A total number of active channel layers and at least one dummy channel layer in the second stack is the same as a total number of active channel layers in the first stack.

19. The method according to claim 16, wherein Forming the first source / drain and the second source / drain includes: forming a first source / drain recess in the first fin and forming a second source / drain recess in the second fin; epitaxially growing a first semiconductor layer in the first source / drain recess and the second source / drain recess, wherein the first semiconductor layer does not contain any dopant species, and wherein the first semiconductor layer overlaps the at least one dummy channel layer; and A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer includes a dopant species.

20. The method according to claim 16, wherein The active channel layer does not contain any dopant species, the at least one dummy channel layer includes a first dopant species, and the second source / drain includes a second dopant species, and wherein the first dopant species and the second dopant species have different conductivity types.

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