Electronic packaging and manufacturing method thereof

Abstract

The present invention relates to an electronic package and a method for manufacturing the same, comprising forming a conductor with a relatively large width on an electrode pad of an electronic component so that a circuit layer contacts the conductor. Therefore, when the relative positions of the electronic component and the circuit layer shift, the circuit layer still contacts the conductor and is electrically connected to the electronic component.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, in particular to an electronic package and a manufacturing method thereof. Background Art

[0002] With the advancement of semiconductor technology, different packaging product types have been developed for semiconductor products. In pursuit of thinner and lighter semiconductor packages, a chip scale package (CSP) has been developed. This chip scale package is characterized by having a size that is equal to or slightly larger than the chip size.

[0003] Figures 1A to 1D It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package 1 .

[0004] like Figure 1A As shown, a first carrier 10a having a first adhesive layer 100a is provided, and at least one semiconductor element 11 is arranged on the first adhesive layer 100a, and a covering layer 12 is formed by molding to cover the semiconductor element 11, wherein the semiconductor element 11 has an active surface 11a and an inactive surface 11b opposite to each other, and a plurality of electrode pads 110 are provided on the active surface 11a, and the semiconductor element 11 is bonded to the first adhesive layer 100a with its active surface 11a.

[0005] like Figure 1B As shown, a portion of the cladding layer 12 is removed by grinding to expose the inactive surface 11b of the semiconductor device 11 on the second surface 12b of the cladding layer 12. Next, a second carrier 10b having a second adhesive layer 100b is placed on the second surface 12b of the cladding layer 12, and the first carrier 10a and the first adhesive layer 100a are removed to expose the first surface 12a of the cladding layer 12.

[0006] like Figure 1C As shown, a redistribution layer (RDL) 13 is formed on the first surface 12a of the cladding layer 12 and the active surface 11a of the semiconductor element 11, and the pad portion 130 of the RDL 13 is electrically connected to the electrode pad 110 of the semiconductor element 11.

[0007] like Figure 1DAs shown, the second adhesive layer 100b and the second carrier 10b are removed, and then a singulation process is performed to form an under bump metallurgy (UBM) 15 on the circuit redistribution layer 13 for connecting multiple conductive elements 17 such as solder balls, wherein the UBM 15 includes an adhesion layer combined with the circuit redistribution layer 13, a wetting layer combined with the adhesion layer, and a protective layer combined with the wetting layer. The material of the adhesion layer is titanium (Ti), chromium (Cr) or titanium tungsten (TiW), the material of the wetting layer is nickel (Ni) or copper (Cu), and the material of the protective layer is a low-resistance metal such as gold, copper, etc.

[0008] However, in the conventional method of manufacturing the semiconductor package 1, when the circuit redistribution layer 13 is manufactured, the relative position between the circuit redistribution layer 13 and the semiconductor element 11 is often misaligned due to precision problems. Figure 1A During the manufacturing process, the coating layer 12 may squeeze the semiconductor element 11 and cause the semiconductor element 11 to shift, or Figure 1C During the manufacturing process, the patterned photoresist used in the production of the RDL 13 may be exposed and developed at an offset, resulting in the pad portion 130 of the RDL 13 being unable to contact the electrode pad 110 of the semiconductor device 11. Figure 1C 'As shown, it causes poor wiring problems.

[0009] Therefore, how to overcome the defects of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the Invention

[0010] To solve the above problems in the prior art, the present invention provides an electronic package and a manufacturing method thereof, which can ensure that the circuit layer is electrically connected to the electronic component when the relative positions of the electronic component and the circuit layer are offset.

[0011] The electronic package of the present invention includes: a covering layer; an electronic component embedded in the covering layer and having a plurality of electrode pads; at least one conductor, which is arranged on at least one of the electrode pads and electrically connected to the electrode pad, and the conductor is a metal structure; and a circuit layer formed on the covering layer and in contact with the conductor.

[0012] The present invention also provides a method for manufacturing an electronic package, comprising: providing at least one electronic component having multiple electrode pads; covering the electronic component with a covering layer, and forming at least one conductor on at least one of the electrode pads so that the conductor is electrically connected to the electrode pad, wherein the conductor is a metal structure; and forming a circuit layer on the covering layer so that the circuit layer contacts the conductor.

[0013] In the aforementioned electronic package and its manufacturing method, the electronic component has a passivation layer having an opening area exposing the electrode pad. For example, the distance between the outermost edge of the conductor layout area and the edge of the opening area is greater than or equal to 10 microns.

[0014] In the aforementioned electronic package and its manufacturing method, the layout area of ​​the conductor is larger than the layout area of ​​the electrode pad.

[0015] In the aforementioned electronic package and its manufacturing method, the conductor includes a plurality of metal layers.

[0016] In the aforementioned electronic package and its manufacturing method, the layout area of ​​the circuit layer is larger than the layout area of ​​the conductor.

[0017] In the aforementioned electronic package and its manufacturing method, the manufacturing process of the conductor includes: first forming the conductor on the electrode pad, and then covering the electronic component and the conductor with the coating layer so that the conductor is buried in the coating layer.

[0018] In the aforementioned electronic package and method of manufacturing the same, the process for manufacturing the conductor includes: first forming a dielectric layer on the cladding layer, then forming an opening in the dielectric layer to expose the electrode pad, and then forming the conductor in the opening so that the conductor contacts the electrode pad and is embedded in the dielectric layer. For example, the width of the opening is greater than the width of the electrode pad.

[0019] In the aforementioned electronic package and its manufacturing method, the circuit layer and the conductor are formed integrally.

[0020] The aforementioned electronic package and its manufacturing method further include forming a plurality of conductive elements electrically connected to the circuit layer on the circuit layer.

[0021] The aforementioned electronic package and its manufacturing method further include forming a circuit structure on the cladding layer and the circuit layer, and the circuit structure is electrically connected to the circuit layer.

[0022] As can be seen from the above, the electronic package and its manufacturing method of the present invention are mainly based on the design of the conductor. When the relative positions of the electronic component and the circuit layer are offset, the circuit layer will still contact the conductor and be electrically connected to the electronic component. Therefore, compared with the prior art, the present invention can avoid the problem of poor wiring of the electronic package due to displacement of the electronic component, thereby avoiding the problem of failure or waste of the end product. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1A to 1D It is a cross-sectional schematic diagram of a conventional method for manufacturing a semiconductor package.

[0024] Figure 1C 'for Figure 1C A partial top view plan diagram of .

[0025] Figures 2A to 2G FIG. 1 is a cross-sectional view of a first embodiment of a method for manufacturing an electronic package according to the present invention.

[0026] Figure 2E 'for Figure 2E A partial enlarged view of .

[0027] Figure 2F 'for Figure 2F A partial top view plan diagram of .

[0028] Figure 2G 'for Figure 2G A cross-sectional schematic diagram of another embodiment of the present invention.

[0029] Figures 3A to 3C FIG. 1 is a cross-sectional view of a second embodiment of a method for manufacturing an electronic package according to the present invention.

[0030] Figures 4A to 4B It is a cross-sectional schematic diagram of a third embodiment of the method for manufacturing an electronic package of the present invention.

[0031] Figure 4A 'for Figure 4A A partial top view plan diagram of .

[0032] Figure 4C for Figure 4B A partial top plan view of one embodiment of the present invention is provided.

[0033] Description of Reference Numerals

[0034] 1:Semiconductor package

[0035] 10a: first carrier

[0036] 10b: Second bearing member

[0037] 100a: first adhesive layer

[0038] 100b: second adhesive layer

[0039] 11: Semiconductor components

[0040] 11a, 21a: Action surface

[0041] 11b, 21b: non-active surface

[0042] 110,210:Electrode pads

[0043] 12,22: coating

[0044] 12a, 22a: first surface

[0045] 12b, 22b: Second surface

[0046] 13,261: Redistribution layer

[0047] 130: cushion

[0048] 15: Metal structure under the bump

[0049] 17,27: Conductive elements

[0050] 2,2',3,4: Electronic packaging

[0051] 20: Loading plate

[0052] 200: Release layer

[0053] 21: Electronic components

[0054] 211: passivation layer

[0055] 212: Opening area

[0056] 23: Circuit layer

[0057] 23a: Conductive traces

[0058] 230: Electrical connection pad

[0059] 24: Dielectric layer

[0060] 240,440: Opening

[0061] 25,35,45: Conductors

[0062] 251: first metal layer

[0063] 252: Second metal layer

[0064] 253: The third metal layer

[0065] 26: Line structure

[0066] 260:Insulation layer

[0067] 28: Insulation protective layer

[0068] 280: Opening

[0069] D, R, W: width

[0070] L1, L2, L3: Length

[0071] S: cutting path

[0072] t: distance. DETAILED DESCRIPTION

[0073] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0074] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0075] Figures 2A to 2G FIG. 1 is a cross-sectional view of a first embodiment of a method for manufacturing an electronic package 2 according to the present invention.

[0076] like Figure 2A As shown, at least one electronic component 21 is placed on a carrier board 20 .

[0077] In this embodiment, the electronic component 21 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, or an inductor. For example, the electronic component 21 is a semiconductor chip having an active surface 21 a and an inactive surface 21 b opposite to each other. The active surface 21 a has a plurality of electrode pads 210 disposed on the carrier board 20.

[0078] In addition, a passivation layer 211, such as silicon nitride (SiN), may be formed on the active surface 21a, and the passivation layer 211 may have a plurality of openings 212 exposing the electrode pads 210. Figure 2E For example, the passivation layer 211 covers a portion of the surface of the electrode pad 210. However, in other embodiments, the surface of the passivation layer 211 may be flush with the surface of the electrode pad 210. It should be understood that there are many types of materials and configurations for the passivation layer, and they are not limited to the above.

[0079] In addition, the carrier plate 20 is, for example, a plate made of semiconductor material (such as silicon or glass), on which a release layer 200 (or adhesive layer) may be formed as required, so that the active surface 21 a of the electronic component 21 can be combined with the release layer 200 .

[0080] like Figure 2BAs shown, a coating layer 22 is formed on the carrier board 20 , so that the coating layer 22 covers the electronic component 21 .

[0081] In this embodiment, the coating layer 22 has a first surface 22a and a second surface 22b opposite to each other, and the first surface 22a is bonded to the release layer 200. For example, the coating layer 22 is an insulating material, such as an epoxy resin encapsulant, and can be formed on the carrier board 20 by lamination or molding.

[0082] In other embodiments (not shown), a flattening process may be performed to level the second surface 22b of the cladding layer 22 with the inactive surface 21b of the electronic component 21. For example, the flattening process may remove a portion of the material of the electronic component 21 and a portion of the material of the cladding layer 22 by grinding.

[0083] like Figure 2C As shown, the carrier plate 20 and the release layer 200 are removed to expose the active surface 21 a of the electronic component 21 and the first surface 22 a of the cladding layer 22 . The first surface 22 a of the cladding layer 22 is flush with the active surface 21 a of the electronic component 21 .

[0084] like Figure 2D As shown, a dielectric layer 24 is formed on the first surface 22 a of the cladding layer 22 and the active surface 21 a (or passivation layer 211 ) of the electronic element 21 , and a plurality of openings 240 corresponding to the electrode pads 210 are formed on the dielectric layer 24 .

[0085] In this embodiment, the width of the opening 240 can be uniform or non-uniform (eg, tapered or other appropriate shapes).

[0086] like Figure 2E As shown, a conductor 25 is formed in each of the openings 240 so that the conductors 25 are electrically connected to the electrode pad 210 .

[0087] In this embodiment, the conductor 25 is a metal structure, which may include at least one metal layer, such as titanium (Ti), chromium (Cr), titanium tungsten (TiW), nickel (Ni), copper (Cu), gold or a combination thereof. For example, the conductor 25 may be an under bump metallurgy (UBM) structure, such as Figure 2EAs shown, it includes a first metal layer 251 coupled to the electrode pad 210, a second metal layer 252 coupled to the first metal layer 251, and a third metal layer 253 coupled to the second metal layer 252. The first metal layer 251 is made of titanium (Ti), chromium (Cr), or titanium tungsten (TiW), the second metal layer 252 is made of nickel (Ni) or copper (Cu), and the third metal layer 253 is made of gold (Au) or copper. It should be understood that there are many embodiments of the UBM, such as a single metal layer, and the UBM is not limited to the above.

[0088] In addition, the layout area (such as width R) of the conductor 25 is larger than the layout area (such as width D) of the electrode pad 210. For example, the distance t between the outermost edge of the layout area of ​​the conductor 25 and the opening edge of the opening area 212 of the passivation layer 211 is greater than or equal to 10 micrometers (um) (i.e., t≧10um), such as Figure 2E 'As shown, the best is 12um.

[0089] like Figure 2F As shown, a redistribution layer (RDL) process is performed on the dielectric layer 24 to form a circuit layer 23 on the dielectric layer 24 .

[0090] In this embodiment, the circuit layer 23 is made of electroplated copper and includes a plurality of conductive traces 23a and an electrical connection pad 230 disposed at one end of the conductive traces 23a. Figure 2F ', so that the electrical connection pad 230 contacts the conductor 25 and is electrically connected to the electrode pad 210.

[0091] In addition, the layout area of ​​the circuit layer 23 (such as the length L of the conductive trace 23a including the two ends thereof, such as Figure 2F The sum of the lengths L1, L2, and L3 of the three line segments shown (ie, L=L1+L2+L3) is greater than the layout area (eg, width R) of the conductor 25.

[0092] like Figure 2G As shown, an insulating protection layer 28 is formed on the dielectric layer 24 and the circuit layer 23 , and the insulating protection layer 28 is formed with a plurality of openings 280 exposing a portion of the circuit layer 23 so as to plant a plurality of conductive elements 27 such as solder balls on the circuit layer 23 .

[0093] In this embodiment, the Figure 2F The cutting path S shown is used for performing a singulation process to obtain the electronic package 2 , which can be connected to an electronic device (not shown) such as a circuit board via the conductive elements 27 in a subsequent process.

[0094] In addition, in another embodiment, if Figure 2G The electronic package 2 shown can form a circuit structure 26 on the dielectric layer 24 and the circuit layer 23 as required, and the circuit structure 26 is electrically connected to the circuit layer 23. For example, the circuit structure 26 includes at least one insulating layer 260 and a redistribution layer (RDL) 261 disposed on the insulating layer 260. The insulating protective layer 28 can be disposed on the outermost insulating layer 260, and the conductive elements 27 can be formed on the outermost RDL 261 to electrically connect the conductive elements 27 to the RDL 261. The RDL 261 can be formed of copper, and the insulating layer 260 can be formed of a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or other dielectric materials.

[0095] Therefore, the manufacturing method of the present invention mainly forms a conductor 25 with a larger width R on the electrode pad 210 of the electronic component 21 first, and then forms the circuit layer 23. When the relative positions of the electronic component 21 and the circuit layer 23 shift, the electrical connection pad 230 of the circuit layer 23 will still contact the conductor 25 and be electrically connected to the electronic component 21. Therefore, compared with the prior art, the present invention can avoid the problem of poor wiring of the electronic package 2, 2' due to the displacement of the electronic component 21, that is, the circuit layer 23 and the electrode pad 210 will not have poor conductivity, thereby avoiding the problem of failure or waste of the terminal product.

[0096] In addition, by controlling the layout area (or width R) of the conductor 25 , such as setting the distance t to be greater than or equal to 10 μm (optimally t=12 μm), the problem of poor connection caused by the shift of the electronic component 21 can be avoided.

[0097] Figures 3A to 3C 2 is a cross-sectional view of a second embodiment of the method for manufacturing an electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the process sequence of manufacturing the conductor 25. The other processes are substantially the same, so the similarities will not be repeated below.

[0098] like Figure 3A As shown, a conductor 35 is formed on the electrode pad 210 of the electronic component 21. Then, the electronic component 21 is placed on the release layer 200 of the carrier board 20 with the conductor 35 on its active surface 21b, so that the conductor 35 is partially (or completely) embedded in the release layer 200.

[0099] like Figure 3B As shown, continue Figures 2B to 2CThe process shown forms the encapsulation layer 22 to encapsulate the electronic component 21 and the conductor 35, and then removes the carrier plate 20 and the release layer 200 to expose the first surface 22a of the encapsulation layer 22 and the conductor 35, so that the conductor 35 partially (or completely) protrudes from the first surface 22a of the encapsulation layer 22.

[0100] like Figure 3C As shown, continue Figures 2D to 2G The process shown forms the dielectric layer 24 and the circuit layer 23 on the first surface 22a of the cladding layer 22, and forms an insulating protection layer 28 and a plurality of conductive elements 27 on the dielectric layer 24 and the circuit layer 23, and performs a singulation process to obtain the electronic package 3.

[0101] Therefore, the manufacturing method of the present invention mainly forms a conductor 35 on the electrode pad 210 that is wider than the electrode pad 210, so that when the relative positions of the electronic component 21 and the circuit layer 23 are offset, the circuit layer 23 will still contact the conductor 35 and be electrically connected to the electronic component 21. Therefore, compared with the prior art, the manufacturing method of the present invention can avoid the problem of poor wiring of the electronic package due to the displacement of the electronic component 21, that is, the circuit layer 23 and the electrode pad 210 will not have poor conductivity, thereby avoiding the problem of failure or waste of the terminal product.

[0102] In addition, by controlling the layout area of ​​the conductor 35 , the problem of poor connection caused by the deviation of the electronic component 21 can also be avoided.

[0103] Figures 4A to 4B 1 is a cross-sectional view of a third embodiment of the method for manufacturing an electronic package 4 of the present invention. The difference between this embodiment and the first embodiment lies in the process of forming the dielectric layer opening. The other processes are substantially the same, so the similarities will not be described in detail below.

[0104] like Figure 4A As shown in Figure 2D In the manufacturing process, a plurality of openings 440 corresponding to the electrode pads 210 are formed in the dielectric layer 24 .

[0105] In this embodiment, the width W of the opening 440 is greater than the width D of the electrode pad 210. Figure 4A ', so that the electrode pad 210 and the surrounding active surface 21a are exposed in the opening 440.

[0106] like Figure 4B As shown, continue Figures 2F to 2GIn the process shown, a circuit layer 23 is formed on the dielectric layer 24, and a conductor 45 is formed in the opening 440, so that the circuit layer 23 and the conductor 45 are integrally formed. Next, an insulating protective layer 28 and a plurality of conductive elements 27 are formed on the cladding layer 22 and the circuit layer 23, and a singulation process is performed to obtain the electronic package 4.

[0107] In this embodiment, since the circuit layer 23 and the conductor 45 are integrally formed, manufacturing time can be saved, thereby reducing manufacturing costs.

[0108] Therefore, the manufacturing method of the present invention mainly forms a wider opening 440 through the dielectric layer 24, that is, increases the width W of the opening 440 (or the layout area of ​​the conductor 45), so that when the relative position of the opening 440 and the electrode pad 210 deviates, Figure 4C As shown, the opening 440 will still expose part of the surface of the electrode pad 210, so that the conductor 45 will still contact the electrode pad 210, and thus the circuit layer 23 can be electrically connected to the electronic component 21. Therefore, compared with the prior art, the manufacturing method of the present invention can avoid the problem of poor wiring of the electronic package due to the exposure and development deviation of the patterned photoresist used in the production of the circuit layer 23, thereby avoiding the problem of failure or waste of the terminal product.

[0109] In addition, by increasing the layout area of ​​the conductor 45 , the problem of poor connection caused by the deviation of the electronic component 21 can also be avoided.

[0110] The present invention further provides an electronic package 2 , 2 ′, 3 , 4 , comprising: a coating layer 22 , an electronic component 21 , at least one conductor 25 , 35 , 45 , and a circuit layer 23 .

[0111] The coating layer 22 has a first surface 22 a and a second surface 22 b opposite to each other.

[0112] The electronic component 21 is embedded in the covering layer 22 , with the first surface 22 a of the covering layer 22 exposed, and has a plurality of electrode pads 210 .

[0113] The conductors 25 , 35 , and 45 are disposed on at least one of the electrode pads 210 and electrically connected to the electrode pad 210 , wherein the conductors 25 , 35 , and 45 are metal structures.

[0114] The circuit layer 23 is disposed on the first surface 22 a of the cladding layer 22 to contact the conductors 25 , 35 , and 45 .

[0115] In one embodiment, the electronic component 21 has a passivation layer 211 having a plurality of openings 212 exposing the electrode pads 210. For example, a distance t between the outermost edge of the arrangement area of ​​the conductors 25, 35 and the edge of the opening 212 is greater than or equal to 10 microns.

[0116] In one embodiment, the layout area (eg, width R) of the conductors 25 , 35 , and 45 is larger than the layout area (eg, width D) of the electrode pad 210 .

[0117] In one embodiment, the conductors 25 , 35 include first, second, and third metal layers 251 , 252 , 253 .

[0118] In one embodiment, the layout area (eg, length L) of the circuit layer 23 is larger than the layout areas (eg, width R) of the conductors 25 , 35 , and 45 .

[0119] In one embodiment, the conductor 35 is embedded in the cladding layer 22 .

[0120] In one embodiment, the electronic package 2, 2', 4 further includes a dielectric layer 24 formed on the first surface 22a of the cover layer 22, so that the conductors 25, 45 are embedded in the dielectric layer 24. For example, the dielectric layer 24 has at least one opening 440, whose width W is greater than the width D of the electrode pad 210.

[0121] In one embodiment, the circuit layer 23 and the conductor 45 are integrally formed.

[0122] In one embodiment, the electronic packages 2 , 2 ′, 3 , 4 further include a plurality of conductive elements 27 disposed on the circuit layer 23 and electrically connected to the circuit layer 23 .

[0123] In one embodiment, the electronic package 2 ′ further includes a circuit structure 26 disposed on the first surface 22 a of the cladding layer 22 and the circuit layer 23 , and the circuit structure 26 is electrically connected to the circuit layer 23 .

[0124] In summary, in the electronic package and its manufacturing method of the present invention, the design of the conductor allows the circuit layer to still contact the conductor and electrically connect to the electronic component even when the position of the electronic component is shifted. Therefore, the present invention can avoid the problem of poor wiring in the electronic package due to displacement of the electronic component, thereby avoiding the problem of failure or waste of the end product.

[0125] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any skilled artisan may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. An electronic package, characterized in that: include: cladding; an electronic component embedded in the coating layer and having a plurality of electrode pads; At least one conductor, which is disposed on at least one of the electrode pads and electrically connected to the electrode pad, and the conductor is a metal structure and is embedded in the coating layer; as well as a circuit layer formed on the cladding layer and contacting the conductor; The layout area of ​​the conductor is larger than the layout area of ​​the electrode pad. The conductor has a surface contacting the electrode pad, and the width of the surface is larger than the width of the electrode pad.

2. The electronic package according to claim 1, wherein The electronic component is provided with a passivation layer, and the passivation layer is provided with an opening area exposing the electrode pad.

3. The electronic package according to claim 2, wherein: The distance between the outermost edge of the arrangement area of ​​the conductor and the edge of the opening area is greater than or equal to 10 micrometers.

4. The electronic package according to claim 1, wherein: The conductor includes a plurality of metal layers.

5. The electronic package according to claim 1, wherein: The layout area of ​​the circuit layer is larger than the layout area of ​​the conductor.

6. The electronic package according to claim 1, wherein: The electronic package also includes a dielectric layer formed on the covering layer so that the conductor is buried in the dielectric layer.

7. The electronic package according to claim 6, wherein: The dielectric layer has an opening, and the width of the opening is greater than the width of the electrode pad.

8. The electronic package according to claim 1, wherein: The circuit layer and the conductor are formed as one piece.

9. The electronic package according to claim 1, wherein: The electronic package also includes a plurality of conductive elements disposed on the circuit layer and electrically connected to the circuit layer.

10. The electronic package according to claim 1, wherein The electronic package also includes a circuit structure arranged on the covering layer and the circuit layer, and the circuit structure is electrically connected to the circuit layer.

11. A method for manufacturing an electronic package, characterized in that: include: Providing at least one electronic component having a plurality of electrode pads; forming at least one conductor on at least one of the electrode pads, and then simultaneously covering the electronic component and the conductor with a coating layer so that the conductor is electrically connected to the electrode pad, wherein the conductor is a metal structure; and forming a circuit layer on the cladding layer so that the circuit layer contacts the conductor; The layout area of ​​the conductor is larger than the layout area of ​​the electrode pad. The conductor has a surface contacting the electrode pad, and the width of the surface is larger than the width of the electrode pad.

12. The method for manufacturing an electronic package according to claim 11, wherein: The electronic component is provided with a passivation layer, and the passivation layer is provided with an opening area exposing the electrode pad.

13. The method for manufacturing an electronic package according to claim 12, wherein: The distance between the outermost edge of the arrangement area of ​​the conductor and the edge of the opening area is greater than or equal to 10 micrometers.

14. The method for manufacturing an electronic package according to claim 11, wherein: The conductor includes a plurality of metal layers.

15. The method for manufacturing an electronic package according to claim 11, wherein: The layout area of ​​the circuit layer is larger than the layout area of ​​the conductor.

16. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing process of the conductor includes: first forming a dielectric layer on the cladding layer, then forming an opening on the dielectric layer to expose the electrode pad, and then forming the conductor in the opening to make the conductor contact the electrode pad.

17. The method for manufacturing an electronic package according to claim 16, wherein: The width of the opening is greater than the width of the electrode pad.

18. The method for manufacturing an electronic package according to claim 11, wherein: The circuit layer and the conductor are formed as one piece.

19. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further comprises forming a plurality of conductive elements electrically connected to the circuit layer on the circuit layer.

20. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method further includes forming a circuit structure on the cladding layer and the circuit layer, and electrically connecting the circuit structure to the circuit layer.

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