Test structure, test method, apparatus and semiconductor structure for through-hole interface failure

Abstract

The application provides a test structure, a test method, a device and a semiconductor structure for testing a via interface failure, the test structure comprising: a semiconductor structure layer, which is a single crystal silicon structure layer and / or a polycrystalline silicon structure layer; and a plurality of metal parts, including a first metal part and a second metal part, wherein the first metal part is electrically connected to the semiconductor structure layer through a first metal conductive column, and the second metal part is electrically connected to the semiconductor structure layer through a second metal conductive column. The test structure solves the problem that it is difficult to evaluate the reliability of a polycrystalline silicon-via interface or a single crystal silicon-via interface in the prior art.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a test structure, test method, apparatus, and semiconductor structure for via interface failure. Background Technology

[0002] In semiconductor structures, metal components are typically electrically connected to semiconductor layers via conductive metal pillars. These pillars form a metal-semiconductor interface, such as a tungsten-polycrystalline silicon (TPS) or tungsten-monocrystalline silicon (TMS) interface. The degradation and resistance changes at the metal-semiconductor interface under current are extremely weak and often ignored. Failure of the metal-semiconductor interface indicates a material anomaly, making reliability assessment difficult.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a test structure, test method, apparatus, and semiconductor structure for via interface failure, in order to solve the problem that it is difficult to evaluate the reliability of polysilicon-via interface or monocrystalline silicon-via interface in the prior art.

[0005] According to one aspect of the present invention, a test structure for via interface failure is provided. The test structure includes: a semiconductor structure layer, which is a monocrystalline silicon structure layer and / or a polycrystalline silicon structure layer; and a plurality of metal portions, including a first metal portion and a second metal portion, wherein the first metal portion is electrically connected to the semiconductor structure layer through a first metal conductive post, and the second metal portion is electrically connected to the semiconductor structure layer through a second metal conductive post.

[0006] Optionally, the plurality of metal portions further include a third metal portion, which is electrically connected to the semiconductor structure layer via a third metal conductive post, and the third metal conductive post is located between the first metal conductive post and the second metal conductive post.

[0007] Optionally, the semiconductor structure layer includes a first semiconductor layer and at least two second semiconductor layers spaced apart from each other. The first semiconductor layer and the second semiconductor layers are different semiconductor structure layers. The test structure also includes at least two insulating isolation structures spaced apart from each other. All the insulating isolation structures are embedded in the first semiconductor layer. The number of insulating isolation structures is the same as the number of second semiconductor layers. The second semiconductor layer includes a first overlapping portion and a second overlapping portion. The first overlapping portion is located on the first semiconductor layer and electrically connected to the first semiconductor layer. The second overlapping portion is located on the corresponding insulating isolation structure. The first metal portion is electrically connected to the first semiconductor layer through a first metal conductive post. The second metal portion is electrically connected to the first semiconductor layer through a second metal conductive post. At least one insulating isolation structure is provided between the first metal conductive post and the second metal conductive post. The plurality of metal portions also include at least one fourth metal portion. Any two second semiconductor layers are electrically connected through one fourth metal portion. The fourth metal portion is electrically connected to the corresponding two second semiconductor layers through a fourth metal conductive post.

[0008] Optionally, the fourth metal portion is electrically connected to the second overlapping portion in the corresponding second semiconductor layer through the fourth metal conductive post, and the fourth metal conductive post is partially embedded in the second overlapping portion.

[0009] Optionally, the third metal part is electrically connected to the first overlapping part through the third metal conductive post, and the third metal conductive post is partially embedded in the first overlapping part.

[0010] Optionally, the number of the third metal portions is the same as the number of the second semiconductor layers and corresponds one-to-one, and each of the third metal portions is electrically connected to the corresponding first overlapping portion through the corresponding third metal conductive post.

[0011] Optionally, the number of the second semiconductor layers and the number of the insulating isolation structures are both two, and the distance between the first overlapping portion of any one second semiconductor layer and the other second semiconductor layer is greater than the distance between the second overlapping portion of the same second semiconductor layer and the other second semiconductor layer.

[0012] Optionally, the at least two insulating isolation structures are located between the first metal conductive pillar and the second metal conductive pillar.

[0013] Optionally, the first semiconductor layer is a monocrystalline silicon structure layer, and the second semiconductor layer is a polycrystalline silicon structure layer.

[0014] Optionally, the length of each of the polycrystalline silicon structural layers in a predetermined direction is greater than or equal to a first predetermined length, wherein the predetermined direction is the arrangement direction of the shallow trench isolation.

[0015] Optionally, the semiconductor structure layer may have one and be a single-crystal silicon structure layer; or, the semiconductor structure layer may have one and be a polycrystalline silicon structure layer.

[0016] According to another aspect of the present invention, a test method for via interface failure is also provided, the method comprising: a first measurement step, measuring the resistance between all adjacent metal parts to obtain a plurality of first resistances; a degradation test step, applying current stress between the first metal parts and the second metal parts for a predetermined time; a second measurement step, measuring the resistance between all adjacent metal parts to obtain a plurality of second resistances, wherein the second resistances correspond one-to-one with the first resistances; and a determination step, determining whether a failed metal-semiconductor interface exists based on the first resistances and the second resistances.

[0017] Optionally, determining whether a failed metal-semiconductor interface exists based on the first resistor and the second resistor includes: if the ratio of the second resistor to the corresponding first resistor is greater than a predetermined value, determining that the metal-semiconductor interface between two adjacent metal portions corresponding to the first resistor is failed, wherein the predetermined value corresponds one-to-one with the first resistor; and if the ratios of all the second resistors to the corresponding first resistors are less than or equal to the corresponding predetermined values, determining that no failed metal-semiconductor interface exists.

[0018] Optionally, after the determination step, the method further includes: if it is determined that there is no failed metal-semiconductor interface, repeating the degradation test step, the second measurement step, and the determination step until it is determined that there is a failed metal-semiconductor interface and / or the sum of the multiple predetermined times is greater than the predetermined test time.

[0019] According to another aspect of the present invention, a testing apparatus for via interface failure is also provided. The apparatus includes: a degradation testing unit for applying current stress between a first metal portion and a second metal portion for a predetermined time; a measuring unit for measuring the resistance between all adjacent metal portions before the degradation testing unit applies current stress between the first metal portion and the second metal portion for the predetermined time to obtain a plurality of first resistances, and for measuring the resistance between all adjacent metal portions after the degradation testing unit applies current stress between the first metal portion and the second metal portion for the predetermined time to obtain a plurality of second resistances, wherein the second resistances correspond one-to-one with the first resistances; and a determining unit for determining whether a failed metal-semiconductor interface exists based on the first resistances and the second resistances.

[0020] According to another aspect of the present invention, a semiconductor structure is also provided, including a device region and a non-device region, wherein the non-device region has the aforementioned test structure for via interface failure, and the device region has a semiconductor device having a metal-semiconductor interface.

[0021] In this embodiment of the invention, the test structure for the failure of the via interface includes a semiconductor structure layer and a plurality of metal parts. The semiconductor structure layer is a monocrystalline silicon structure layer and / or a polycrystalline silicon structure layer. The plurality of metal parts include a first metal part and a second metal part. The first metal part is electrically connected to the semiconductor structure layer through a first metal conductive post, and the second metal part is electrically connected to the semiconductor structure layer through a second metal conductive post. In this test structure, when the semiconductor structure layer is a monocrystalline silicon structure layer, the interface between the first metal conductive pillar and the semiconductor structure layer is a monocrystalline silicon-via interface, and the interface between the second metal conductive pillar and the semiconductor structure layer is also a monocrystalline silicon-via interface. Current stress is applied between the first metal part and the second metal part, causing the monocrystalline silicon-via interface to degrade to failure. The reliability of the monocrystalline silicon-via interface can then be evaluated based on the change in resistance. Similarly, when the semiconductor structure layer is a polycrystalline silicon structure layer, the interface between the first metal conductive pillar and the semiconductor structure layer is also a polycrystalline silicon-via interface, and the interface between the second metal conductive pillar and the semiconductor structure layer is also a polycrystalline silicon-via interface. Current stress is applied between the first metal part and the second metal part, causing the polycrystalline silicon-via interface to degrade to failure. The reliability of the polycrystalline silicon-via interface can then be evaluated based on the change in resistance. The semiconductor structure layer includes a monocrystalline silicon structure layer and a polycrystalline silicon structure layer. One metal part is electrically connected to the monocrystalline silicon structure layer through a via, forming a monocrystalline silicon-via interface. Another metal part is electrically connected to the polycrystalline silicon structure layer through a via, forming a polycrystalline silicon-via interface. Current stress is applied between the first metal part and the second metal part, causing the monocrystalline silicon-via interface and the polycrystalline silicon-via interface to degrade to failure. The reliability of the monocrystalline silicon-via interface and the polycrystalline silicon-via interface can be evaluated based on the change in resistance. This solves the problem in the prior art that it is difficult to evaluate the reliability of the polycrystalline silicon-via interface or the monocrystalline silicon-via interface. Furthermore, the reliability of the corresponding interface in the semiconductor device can be evaluated based on the reliability of the polycrystalline silicon-via interface or the monocrystalline silicon-via interface. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 A schematic diagram of a test structure for through-hole interface failure according to an embodiment of this application is shown;

[0024] Figure 2 A schematic diagram of a test structure for through-hole interface failure according to another embodiment of this application is shown;

[0025] Figure 3 A schematic diagram of a test structure for through-hole interface failure according to another embodiment of this application is shown;

[0026] Figure 4 A flowchart is shown showing a test method for a test structure of through-hole interface failure according to an embodiment of this application;

[0027] Figure 5 A schematic diagram of a test apparatus for a test structure for through-hole interface failure according to an embodiment of this application is shown.

[0028] The above figures include the following reference numerals:

[0029] 10. Monocrystalline silicon structure layer; 20. Polycrystalline silicon structure layer; 30. Insulating isolation structure; 40. First metal part; 401. First metal conductive pillar; 50. Second metal part; 501. Second metal conductive pillar; 60. Third metal part; 601. Third metal conductive pillar; 70. Fourth metal part; 701. Fourth metal conductive pillar; 80. Dielectric layer. Detailed Implementation

[0030] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] It should be understood that when an element (such as a layer, film, region, or structural layer) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0034] As mentioned in the background section, it is difficult to assess the reliability of polysilicon-via interfaces or monocrystalline silicon-via interfaces in the prior art. In order to solve the above problems, a typical embodiment of this application provides a test structure, test method, apparatus and semiconductor structure for via interface failure.

[0035] According to embodiments of this application, a test structure for through-hole interface failure is provided, such as... Figure 1 As shown, the test structure includes:

[0036] The semiconductor structure layer is a monocrystalline silicon structure layer 10 and / or a polycrystalline silicon structure layer 20.

[0037] Multiple metal portions, including a first metal portion 40 and a second metal portion 50, wherein the first metal portion 40 is electrically connected to the semiconductor structure layer via a first metal conductive post 401, and the second metal portion 50 is electrically connected to the semiconductor structure layer via a second metal conductive post 501.

[0038] The test structure for the failure of the via interface mentioned above includes a semiconductor structure layer and multiple metal parts. The semiconductor structure layer is a monocrystalline silicon structure layer and / or a polycrystalline silicon structure layer. The multiple metal parts include a first metal part and a second metal part. The first metal part is electrically connected to the semiconductor structure layer through a first metal conductive post, and the second metal part is electrically connected to the semiconductor structure layer through a second metal conductive post. In this test structure, when the semiconductor structure layer is a monocrystalline silicon structure layer, the interface between the first metal conductive pillar and the semiconductor structure layer is a monocrystalline silicon-via interface, and the interface between the second metal conductive pillar and the semiconductor structure layer is also a monocrystalline silicon-via interface. Applying current stress between the first and second metal parts causes the monocrystalline silicon-via interface to degrade to failure. The reliability of the monocrystalline silicon-via interface can then be evaluated based on the change in resistance. Similarly, when the semiconductor structure layer is a polycrystalline silicon structure layer, the interface between the first metal conductive pillar and the semiconductor structure layer is a polycrystalline silicon-via interface, and the interface between the second metal conductive pillar and the semiconductor structure layer is also a polycrystalline silicon-via interface. Applying current stress between the first and second metal parts causes the polycrystalline silicon-via interface to degrade to failure. The reliability of the polycrystalline silicon-via interface can then be evaluated based on the change in resistance. The reliability of silicon-through-hole (TBH) interfaces is assessed in a semiconductor structure layer comprising a monocrystalline silicon (MSS) layer and a polycrystalline silicon (PCS) layer. One metal portion is electrically connected to the MSS layer via a via, forming a MSS-TBH interface. Another metal portion is electrically connected to the PCS layer via a via, forming a PCS-TBH interface. Current stress is applied between the first and second metal portions, causing both the MSS-TBH and PCS-TBH interfaces to degrade to failure. The reliability of the MSS-TBH and PCS-TBH interfaces can be evaluated based on changes in resistance. This solves the problem of difficulty in evaluating the reliability of either the PCS-TBH or MSS-TBH interfaces in existing technologies. Furthermore, the reliability of corresponding interfaces in semiconductor devices can be evaluated based on the reliability of either the PCS-TBH or MSS-TBH interfaces.

[0039] In one embodiment of this application, the plurality of metal portions further includes a third metal portion. The third metal portion is electrically connected to the semiconductor structure layer via a third metal conductive post, and the third metal conductive post is located between the first metal conductive post and the second metal conductive post. Specifically, the first metal portion is electrically connected to the semiconductor structure layer via the first metal conductive post, and the second metal portion is electrically connected to the semiconductor structure layer via the second metal conductive post, forming two metal-semiconductor interfaces. These two metal-semiconductor interfaces can be two monocrystalline silicon-via interfaces or two polycrystalline silicon-via interfaces, or they can be one monocrystalline silicon-via interface and one polycrystalline silicon-via interface. The third metal portion is electrically connected to the semiconductor structure layer via the third metal conductive post, and the third metal conductive post is located between the first metal conductive post and the second metal conductive post. This allows for the detection of resistance changes between the first and third metal portions to assess the reliability of one metal-semiconductor interface, and the detection of resistance changes between the second and third metal portions to assess the reliability of the other metal-semiconductor interface, thus determining the failure location. It should be noted that the aforementioned metal-semiconductor interface for which reliability can be assessed is the metal-semiconductor interface through which current stress would pass when applied between the first metal part and the second metal part.

[0040] In one embodiment of this application, a portion of the first metal conductive pillar is embedded in the semiconductor structure layer, a portion of the second metal conductive pillar is embedded in the semiconductor structure layer, and a portion of the third metal conductive pillar is embedded in the semiconductor structure layer. Specifically, the above structure ensures good contact between the first metal conductive pillar and the semiconductor structure layer, good contact between the second metal conductive pillar and the semiconductor structure layer, and good contact between the third metal conductive pillar and the semiconductor structure layer, thus avoiding interference with reliability assessment.

[0041] In one embodiment of this application, such as Figure 1As shown, the aforementioned semiconductor structure layer includes a first semiconductor layer and at least two second semiconductor layers spaced apart from each other. The first semiconductor layer and the second semiconductor layers are different semiconductor structure layers. The test structure also includes at least two spaced-apart insulating isolation structures. All of the aforementioned insulating isolation structures 30 are embedded in the first semiconductor layer. The number of the aforementioned insulating isolation structures 30 is the same as the number of the aforementioned second semiconductor layers. The aforementioned second semiconductor layer includes a first overlapping portion and a second overlapping portion. The first overlapping portion is located on the aforementioned first semiconductor layer and is electrically connected to the aforementioned first semiconductor layer. The second overlapping portion is located on the corresponding insulating isolation structure. In the isolation structure, the first metal portion 40 is electrically connected to the first semiconductor layer via the first metal conductive post 401, and the second metal portion 50 is electrically connected to the first semiconductor layer via the second metal conductive post 501. At least one insulating isolation structure 30 is provided between the first metal conductive post 401 and the second metal conductive post 501. The plurality of metal portions also include at least one fourth metal portion 70. Any two second semiconductor layers are electrically connected via one fourth metal portion 70, and the fourth metal portion 70 is electrically connected to the corresponding two second semiconductor layers via the fourth metal conductive post 701. Specifically, as... Figure 1 As shown, the arrows indicate the direction of the current. The above test structure can apply current stress between the first metal part 40 and the second metal part 50, so that the current flows sequentially through the first metal part 40, the first metal conductive pillar 401, the first semiconductor layer, the first overlap, the fourth metal conductive pillar 701 on the left, the fourth metal part, the fourth metal conductive pillar 701 on the right, the second overlap, the first semiconductor layer, the second metal conductive pillar 501, and the second metal part 50. In the case where the second semiconductor layer is a polycrystalline silicon structure layer 20, the first overlap and the second overlap are polycrystalline silicon gates. This causes the current stress to pass through the monocrystalline silicon structure layer-via interface in both positive and negative directions, and the current to pass through the polycrystalline silicon gate-via interface in both positive and negative directions, resulting in possible reliability degradation. By monitoring the change in resistance between adjacent metal parts, the reliability of the monocrystalline silicon structure layer-via interface or the polycrystalline silicon gate-via interface under different current directions can be determined.

[0042] It should be noted that, as Figure 1 As shown, the above test structure also includes a dielectric layer 80. The first metal conductive pillar 401 and the second metal conductive pillar 501 respectively penetrate the dielectric layer 80 and are electrically connected to the first semiconductor layer. The third metal conductive pillar 601 and the fourth metal conductive pillar 701 respectively penetrate the dielectric layer 80 and are electrically connected to the corresponding second semiconductor layer.

[0043] In one embodiment of this application, such as Figure 1As shown, the fourth metal portion 70 is electrically connected to the corresponding second overlap portion in the second semiconductor layer via the fourth metal conductive post 701, and the fourth metal conductive post 701 is partially embedded in the second overlap portion. Specifically, the above structure ensures good contact between the fourth metal conductive post and the second semiconductor layer, avoiding interference with reliability assessment.

[0044] In one embodiment of this application, such as Figure 1 As shown, the third metal portion 60 is electrically connected to the first overlapping portion via the third metal conductive post 601, and the third metal conductive post 601 is partially embedded in the first overlapping portion. Specifically, the above structure ensures good contact between the third metal conductive post and the second semiconductor layer, avoiding interference with reliability assessment.

[0045] In one embodiment of this application, such as Figure 1 As shown, the number of the third metal portions 60 is the same as the number of the second semiconductor layers and corresponds one-to-one. Each third metal portion 60 is electrically connected to the corresponding first overlap portion through a corresponding third metal conductive post 601. Specifically, the fourth metal portion is electrically connected to the second overlap portion of the second semiconductor layer through a fourth metal conductive post to form a metal-semiconductor interface, and the third metal portion is electrically connected to the first overlap portion of the second semiconductor layer through a third metal conductive post. This allows for the detection of resistance changes between the fourth and third metal portions to assess the reliability of the metal-semiconductor interface and determine the failure location. Therefore, by ensuring that the number of third metal portions is the same as the number of the second semiconductor layers and corresponds one-to-one, the reliability of the metal-semiconductor interface can be detected one-to-one.

[0046] In one embodiment of this application, such as Figure 1 As shown, both the number of second semiconductor layers and the number of insulating isolation structures 30 are two. The distance between the first overlap portion of any one second semiconductor layer and the other second semiconductor layer is greater than the distance between the second overlap portion of the same second semiconductor layer and the other second semiconductor layer. Specifically, the first overlap portion of any one second semiconductor layer is arranged in a direction away from the other second semiconductor layer to ensure that the third metal conductive post is located between the first metal conductive post and the fourth metal conductive post, or between the second metal conductive post and the fourth metal conductive post.

[0047] In one embodiment of this application, the at least two insulating isolation structures are both located between the first metal conductive pillar and the second metal conductive pillar. Specifically, the above structure can prevent the first semiconductor layer from directly connecting the first metal conductive pillar and the second metal conductive pillar, ensuring that current flows through the metal-semiconductor interface, thereby achieving reliable detection of the metal-semiconductor interface.

[0048] In one embodiment of this application, such as Figure 1 As shown, the first semiconductor layer is a monocrystalline silicon structure layer 10, and the second semiconductor layer is a polycrystalline silicon structure layer 20. Specifically, in one case, the first semiconductor layer is a monocrystalline silicon structure layer 10, and the second semiconductor layer is a polycrystalline silicon structure layer 20; in another case, the first semiconductor layer is a polycrystalline silicon structure layer 20, and the second semiconductor layer is a monocrystalline silicon structure layer 10.

[0049] In one embodiment of this application, the length of each of the aforementioned polysilicon structural layers in a predetermined direction is greater than or equal to a first predetermined length, where the predetermined direction is the arrangement direction of the aforementioned insulating isolation structure. Specifically, the length of the aforementioned polysilicon structural layers in the predetermined direction is set within the aforementioned range to reduce the interference of the polysilicon structural layers on resistance changes and improve the accuracy of reliability testing. The aforementioned first predetermined length can be set according to actual conditions, for example, 100 μm.

[0050] In one embodiment of this application, the length of each of the aforementioned metal portions in the predetermined direction is less than or equal to a second predetermined length. Specifically, the length of the aforementioned metal portions in the predetermined direction is set within the aforementioned range to reduce the interference of the metal portions on resistance changes and improve the accuracy of reliability testing. The aforementioned second predetermined length can be set according to actual conditions, for example, 50 μm.

[0051] In one embodiment of this application, the test structure includes a first pad, a second pad, a third pad, and a fourth pad. The first pad is electrically connected to the first metal portion, the second pad is electrically connected to the second metal portion, the third pad is electrically connected to the third metal portion in a corresponding order, and the fourth pad is electrically connected to the fourth metal portion in a corresponding order. Specifically, current stress is applied by energizing the first and second pads, and resistance can also be detected by energizing the pads, which facilitates testing.

[0052] In one embodiment of this application, such as Figure 2 As shown, the aforementioned semiconductor structure layer includes one and is a single-crystal silicon structure layer 10. Specifically, when the semiconductor structure layer is a single-crystal silicon structure layer, the interface between the first metal conductive pillar and the semiconductor structure layer is a single-crystal silicon-via interface, and the interface between the second metal conductive pillar and the semiconductor structure layer is also a single-crystal silicon-via interface. Current stress is applied between the first metal part and the second metal part, causing the single-crystal silicon-via interface to degrade to failure. The reliability of the single-crystal silicon-via interface can then be evaluated based on the change in resistance.

[0053] In one embodiment of this application, such as Figure 3As shown, the aforementioned semiconductor structure layer includes one polysilicon structure layer 20. Specifically, when the semiconductor structure layer is a polysilicon structure layer, the interface between the first metal conductive pillar and the semiconductor structure layer is a polysilicon-via interface, and the interface between the second metal conductive pillar and the semiconductor structure layer is also a polysilicon-via interface. Applying current stress between the first metal portion and the second metal portion causes the polysilicon-via interface to degrade to failure. The reliability of the polysilicon-via interface can then be assessed based on the change in resistance.

[0054] According to an embodiment of this application, a test method for through-hole interface failure is provided.

[0055] Figure 4 This is a flowchart of a test method for a test structure of through-hole interface failure according to an embodiment of this application. Figure 4 As shown, the method includes the following steps:

[0056] Step S101, the first measurement step, measures the resistance between all adjacent metal parts to obtain multiple first resistors;

[0057] Step S102, degradation test step, applying current stress between the first metal part and the second metal part for a predetermined time;

[0058] Step S103, the second measurement step, measures the resistance between all adjacent metal parts to obtain multiple second resistors, each of which corresponds to the first resistor.

[0059] Step S104, Determine the existence of a failed metal-semiconductor interface based on the first resistor and the second resistor.

[0060] In the aforementioned test method for via interface failure, firstly, the resistance between all adjacent pairs of metal parts is measured to obtain multiple first resistances; then, a current stress is applied between the first and second metal parts for a predetermined time; subsequently, the resistance between all adjacent pairs of metal parts is measured to obtain multiple second resistances, each corresponding to one of the first resistances; finally, the presence of a failed metal-semiconductor interface is determined based on the first and second resistances. This test method detects the resistance between adjacent pairs of metal parts before and after applying current stress, obtaining first and second resistances respectively, and determines the change in resistance based on the first and second resistances, thereby determining the presence of a failed metal-semiconductor interface, evaluating the reliability of the metal-semiconductor interface, and solving the problem in the prior art of difficulty in evaluating the reliability of polycrystalline silicon-via interfaces or monocrystalline silicon-via interfaces.

[0061] In one embodiment of this application, determining whether a failed metal-semiconductor interface exists based on the first resistor and the second resistor includes: if the ratio of the second resistor to the corresponding first resistor is greater than a predetermined value, determining that the metal-semiconductor interface between two adjacent metal portions corresponding to the first resistor is failed, where the predetermined value corresponds one-to-one with the first resistor; if the ratios of all the second resistors to the corresponding first resistors are less than or equal to the predetermined value, determining that no failed metal-semiconductor interface exists. Specifically, metal-semiconductor interface degradation and failure can lead to a significant change in resistance. Therefore, if the ratio of the second resistor to the corresponding first resistor is greater than the predetermined value, it can be determined that the metal-semiconductor interface between two adjacent metal portions corresponding to the first resistor is failed; otherwise, no failure is found. The predetermined value can be selected according to actual conditions, for example, 150%.

[0062] In one embodiment of this application, after the determination step, the method further includes: if it is determined that there is no failed metal-semiconductor interface, repeating the degradation test step, the second measurement step, and the determination step until a failed metal-semiconductor interface is determined and / or the sum of multiple predetermined times is greater than a predetermined test time. Specifically, the method cyclically tests multiple times until a failed metal-semiconductor interface appears, or until no failed metal-semiconductor interface appears after the predetermined test time, thereby accurately evaluating the reliability of the metal-semiconductor interface based on the test time at the time of failure. The predetermined test time can be set according to actual requirements.

[0063] This application also provides a testing apparatus for via interface failure. It should be noted that the via interface failure testing apparatus of this application can be used to execute the via interface failure testing method provided in this application. The via interface failure testing apparatus provided in this application will be described below.

[0064] Figure 5 This is a schematic diagram of a test apparatus for through-hole interface failure according to an embodiment of this application. Figure 5 As shown, the device includes:

[0065] The degradation test unit 100 is used to apply current stress between the first metal part and the second metal part for a predetermined time;

[0066] The measuring unit 200 is used to measure the resistance between all two adjacent metal parts before the degradation test unit applies current stress between the first metal part and the second metal part for a predetermined time, to obtain a plurality of first resistances, and is also used to measure the resistance between all two adjacent metal parts after the degradation test unit applies current stress between the first metal part and the second metal part for a predetermined time, to obtain a plurality of second resistances, wherein the second resistances correspond one-to-one with the first resistances.

[0067] The determining unit 300 is used to determine whether a failed metal-semiconductor interface exists based on the first resistor and the second resistor.

[0068] In the aforementioned via interface failure testing apparatus, a degradation testing unit applies current stress between the first metal portion and the second metal portion for a predetermined time. A measuring unit measures the resistance between all adjacent metal portions before the degradation testing unit applies current stress between the first and second metal portions for the predetermined time, obtaining multiple first resistances. It also measures the resistance between all adjacent metal portions after the degradation testing unit applies current stress between the first and second metal portions for the predetermined time, obtaining multiple second resistances, each corresponding to a first resistance. A determining unit determines whether a failed metal-semiconductor interface exists based on the first and second resistances. This testing apparatus detects the resistance between adjacent metal portions before and after applying current stress, obtaining first and second resistances respectively. It then determines the change in resistance based on the first and second resistances, thereby determining whether a failed metal-semiconductor interface exists and evaluating the reliability of the metal-semiconductor interface. This solves the problem in the prior art of difficulty in evaluating the reliability of polycrystalline silicon-via interfaces or monocrystalline silicon-via interfaces.

[0069] In one embodiment of this application, the determining unit includes a first determining module and a second determining module. The first determining module is used to determine that the metal-semiconductor interface between two adjacent metal portions corresponding to the first resistor is failed when the ratio of the second resistor to the corresponding first resistor is greater than a predetermined value. The predetermined value corresponds one-to-one with the first resistor. The second determining module is used to determine that no failed metal-semiconductor interface exists when all ratios of the second resistor to the corresponding first resistor are less than or equal to the predetermined value. Specifically, metal-semiconductor interface degradation and failure can cause a significant change in resistance. Therefore, if the ratio of the second resistor to the corresponding first resistor is greater than the predetermined value, it can be determined that the metal-semiconductor interface between two adjacent metal portions corresponding to the first resistor is failed; otherwise, no failure is detected. The predetermined value can be selected according to actual conditions, for example, 150%.

[0070] In one embodiment of this application, the apparatus further includes a repeating unit. This repeating unit is used, after the determining step, to repeat the degradation test step, the second measurement step, and the determining step if it is determined that no failed metal-semiconductor interface exists, until a failed metal-semiconductor interface is determined to exist and / or the sum of multiple predetermined times is greater than a predetermined test time. Specifically, the method repeatedly tests until a failed metal-semiconductor interface appears, or until no failed metal-semiconductor interface appears after the predetermined test time, thereby accurately assessing the reliability of the metal-semiconductor interface based on the test time at the time of failure. The predetermined test time can be set according to actual requirements.

[0071] This application also provides a semiconductor structure, including a device region and a non-device region, wherein the non-device region has a test structure for via interface failure, and the device region has a semiconductor device, wherein the semiconductor device has a metal-semiconductor interface.

[0072] In the aforementioned semiconductor structure, the aforementioned test method for via interface failure is used to test the metal-semiconductor interface through the via interface failure test structure, thereby evaluating the reliability of the metal-semiconductor interface and solving the problem in the prior art that it is difficult to evaluate the reliability of polycrystalline silicon-via interface or monocrystalline silicon-via interface.

[0073] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0074] 1) The test structure for via interface failure in this application includes a semiconductor structure layer and multiple metal portions. The semiconductor structure layer is a monocrystalline silicon structure layer and / or a polycrystalline silicon structure layer. The multiple metal portions include a first metal portion and a second metal portion. The first metal portion is electrically connected to the semiconductor structure layer through a first metal conductive post, and the second metal portion is electrically connected to the semiconductor structure layer through a second metal conductive post. In this test structure, when the semiconductor structure layer is a monocrystalline silicon structure layer, the interface between the first metal conductive post and the semiconductor structure layer is a monocrystalline silicon-via interface, and the interface between the second metal conductive post and the semiconductor structure layer is also a monocrystalline silicon-via interface. Current stress is applied between the first metal portion and the second metal portion, causing the monocrystalline silicon-via interface to degrade to failure. The reliability of the monocrystalline silicon-via interface can then be evaluated based on the change in resistance. When the semiconductor structure layer is a polycrystalline silicon structure layer, the interface between the first metal conductive post and the semiconductor structure layer is a polycrystalline silicon-via interface, and the interface between the second metal conductive post and the semiconductor structure layer is also a polycrystalline silicon-via interface. Current stress is applied between the first metal portion and the second metal portion, causing the polycrystalline silicon-via interface to degrade to failure. When the via interface degrades to failure, the reliability of the polysilicon-via interface can be assessed based on the change in resistance. The semiconductor structure layer includes a monocrystalline silicon structure layer and a polycrystalline silicon structure layer. One metal part is electrically connected to the monocrystalline silicon structure layer through a via, forming a monocrystalline silicon-via interface. Another metal part is electrically connected to the polycrystalline silicon structure layer through a via, forming a polycrystalline silicon-via interface. Current stress is applied between the first metal part and the second metal part, causing the monocrystalline silicon-via interface and the polycrystalline silicon-via interface to degrade to failure. The reliability of the monocrystalline silicon-via interface and the polycrystalline silicon-via interface can then be assessed based on the change in resistance, solving the problem in the prior art that it is difficult to assess the reliability of polycrystalline silicon-via interfaces or monocrystalline silicon-via interfaces.

[0075] 2) In the test method for via interface failure of this application, firstly, the resistance between all adjacent pairs of metal parts is measured to obtain multiple first resistances; then, current stress is applied between the first metal parts and the second metal parts for a predetermined time; subsequently, the resistance between all adjacent pairs of metal parts is measured to obtain multiple second resistances, each corresponding to one of the first resistances; finally, the presence of a failed metal-semiconductor interface is determined based on the first and second resistances. This test method detects the resistance between adjacent pairs of metal parts before and after applying current stress to obtain first and second resistances, and determines the change in resistance based on the first and second resistances, thereby determining whether a failed metal-semiconductor interface exists and evaluating the reliability of the metal-semiconductor interface. This solves the problem in the prior art that it is difficult to evaluate the reliability of polysilicon-via interfaces or monocrystalline silicon-via interfaces.

[0076] 3) In the via interface failure testing apparatus of this application, the degradation testing unit applies current stress between the first metal part and the second metal part for a predetermined time; the measuring unit is used to measure the resistance between all adjacent metal parts before the degradation testing unit applies current stress between the first metal part and the second metal part for the predetermined time, obtaining multiple first resistances, and is also used to measure the resistance between all adjacent metal parts after the degradation testing unit applies current stress between the first metal part and the second metal part for the predetermined time, obtaining multiple second resistances, the second resistances corresponding one-to-one with the first resistances; the determining unit determines whether a failed metal-semiconductor interface exists based on the first resistances and the second resistances. This testing apparatus detects the resistance between adjacent metal parts before and after applying current stress, obtaining first resistances and second resistances, and determines the change in resistance based on the first resistances and the second resistances, thereby determining whether a failed metal-semiconductor interface exists, evaluating the reliability of the metal-semiconductor interface, and solving the problem in the prior art that it is difficult to evaluate the reliability of polysilicon-via interfaces or monocrystalline silicon-via interfaces.

[0077] 4) In the semiconductor structure of this application, the above-mentioned test method for via interface failure is used to test the metal-semiconductor interface through the test structure for via interface failure, and to evaluate the reliability of the via interface, which solves the problem that it is difficult to evaluate the reliability of polycrystalline silicon-via interface or monocrystalline silicon-via interface in the prior art.

[0078] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A test structure for through-hole interface failure, characterized in that, The test structure includes: The semiconductor structure layer is a monocrystalline silicon structure layer and / or a polycrystalline silicon structure layer; Multiple metal portions, including a first metal portion and a second metal portion, wherein the first metal portion is electrically connected to the semiconductor structure layer via a first metal conductive post, and the second metal portion is electrically connected to the semiconductor structure layer via a second metal conductive post; The plurality of metal portions further include a third metal portion, which is electrically connected to the semiconductor structure layer via a third metal conductive post, and the third metal conductive post is located between the first metal conductive post and the second metal conductive post; The semiconductor structure layer includes a first semiconductor layer and at least two second semiconductor layers spaced apart from each other. The first semiconductor layer and the second semiconductor layers are different semiconductor structure layers. The test structure also includes at least two insulating isolation structures spaced apart from each other. All the insulating isolation structures are embedded in the first semiconductor layer. The number of insulating isolation structures is the same as the number of second semiconductor layers. The second semiconductor layer includes a first overlap portion and a second overlap portion. The first overlap portion is located on the first semiconductor layer and electrically connected to the first semiconductor layer. The second overlap portion is located on the corresponding insulating isolation structure. The first metal portion is electrically connected to the first semiconductor layer through a first metal conductive post. The second metal portion is electrically connected to the first semiconductor layer through a second metal conductive post. At least one insulating isolation structure is provided between the first metal conductive post and the second metal conductive post. The plurality of metal portions also include at least one fourth metal portion. Any two second semiconductor layers are electrically connected through one fourth metal portion. The fourth metal portion is electrically connected to the corresponding two second semiconductor layers through a fourth metal conductive post.

2. The test structure according to claim 1, characterized in that, The fourth metal part is electrically connected to the second overlapping part in the corresponding second semiconductor layer through the fourth metal conductive post, and the fourth metal conductive post is partially embedded in the second overlapping part.

3. The test structure according to claim 1, characterized in that, The third metal part is electrically connected to the first overlapping part through the third metal conductive post, and the third metal conductive post is partially embedded in the first overlapping part.

4. The test structure according to claim 3, characterized in that, The number of the third metal portions is the same as the number of the second semiconductor layers and corresponds one-to-one. Each of the third metal portions is electrically connected to the corresponding first overlapping portion through the corresponding third metal conductive post.

5. The test structure according to claim 1, characterized in that, The number of the second semiconductor layer and the number of the insulating isolation structure are both two, and the distance between the first overlapping portion of any second semiconductor layer and the other second semiconductor layer is greater than the distance between the second overlapping portion of the same second semiconductor layer and the other second semiconductor layer.

6. The test structure according to claim 5, characterized in that, The at least two insulating isolation structures are located between the first metal conductive pillar and the second metal conductive pillar.

7. The test structure according to claim 1, characterized in that, The first semiconductor layer is a monocrystalline silicon structure layer, and the second semiconductor layer is a polycrystalline silicon structure layer.

8. The test structure according to claim 1, characterized in that, The length of each of the polycrystalline silicon structural layers in a predetermined direction is greater than or equal to a first predetermined length, and the predetermined direction is the arrangement direction of the insulating isolation structure.

9. The test structure according to claim 1, characterized in that, The semiconductor structure layer has one and is a single-crystal silicon structure layer; or, the semiconductor structure layer has one and is a polycrystalline silicon structure layer.

10. A test method for through-hole interface failure, characterized in that, The test method for through-hole interface failure is applied to the test structure for through-hole interface failure according to any one of claims 1 to 9, and the method includes: The first measurement step involves measuring the resistance between all adjacent metal parts to obtain multiple first resistances. The degradation test procedure involves applying current stress between the first metal part and the second metal part for a predetermined time. The second measurement step involves measuring the resistance between all adjacent metal parts to obtain multiple second resistors, each of which corresponds one-to-one with the first resistor. The determination step involves identifying whether a failed metal-semiconductor interface exists based on the first resistor and the second resistor.

11. The method according to claim 10, characterized in that, Determining the presence of a failed metal-semiconductor interface based on the first resistor and the second resistor includes: If the ratio of the second resistor to the corresponding first resistor is greater than a predetermined value, it is determined that the metal-semiconductor interface between the two adjacent metal parts corresponding to the first resistor is faulty, and the predetermined value corresponds one-to-one with the first resistor. If the ratio of all the second resistors to the corresponding first resistors is less than or equal to the corresponding predetermined value, it is determined that there is no failed metal-semiconductor interface.

12. The method according to claim 11, characterized in that, After determining the steps, the method further includes: If it is determined that there is no failed metal-semiconductor interface, the degradation test step, the second measurement step, and the determination step are repeated until a failed metal-semiconductor interface is determined and / or the sum of the predetermined times is greater than the predetermined test time.

13. A testing device for through-hole interface failure, characterized in that, The via interface failure testing apparatus is applied to the via interface failure testing structure according to any one of claims 1 to 9, the apparatus comprising: A degradation test unit is used to apply current stress between a first metal part and a second metal part for a predetermined time. The measuring unit is configured to measure the resistance between all adjacent metal parts before the degradation test unit applies current stress between the first metal part and the second metal part for a predetermined time, thereby obtaining a plurality of first resistances; and is also configured to measure the resistance between all adjacent metal parts after the degradation test unit applies current stress between the first metal part and the second metal part for a predetermined time, thereby obtaining a plurality of second resistances, wherein the second resistances correspond one-to-one with the first resistances. A determining unit is used to determine whether a failed metal-semiconductor interface exists based on the first resistor and the second resistor.

14. A semiconductor structure, characterized in that, It includes a device region and a non-device region, wherein the non-device region has a test structure for via interface failure as described in any one of claims 1 to 9, and the device region has a semiconductor device, wherein the semiconductor device has a metal-semiconductor interface.

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