A fast recovery diode, chip and its fabrication method

Abstract

This disclosure provides a fast recovery diode, a chip, and a method for fabricating the same, comprising: a P+ type anode region, a base region, and an N+ type cathode region. The portion of the base region near the N+ cathode region further comprises: at least one buried layer region, wherein the at least one buried layer region comprises a first portion having a first doping type and a second portion having a second doping type, the first portion and the second portion forming a PN junction.

Description

Technical Field

[0001] This relates to the field of semiconductor devices, and in particular to a fast recovery diode, a chip, and a method for manufacturing the same. Background Technology

[0002] In power device application circuits, such as those for IGBT power devices, most loads are inductive, thus requiring an anti-parallel diode. This ensures that after the main device is turned off, the anti-parallel diode provides a freewheeling path for the inductive load.

[0003] With the development of IGBT technology, anti-parallel diodes are required to operate at currents of up to hundreds of amperes, with a reverse recovery time of only a few microseconds, i.e., fast recovery capability. Furthermore, to avoid damage to diodes and power devices due to current resonance and electromagnetic compatibility issues, diodes are required to avoid current "step" phenomena at the end of the reverse recovery period, i.e., possess soft recovery characteristics.

[0004] However, in the prior art, fast soft recovery capability may conflict with other diode performance characteristics. For example, to achieve fast soft recovery, low on-state loss performance such as low forward voltage drop and low leakage current may be sacrificed.

[0005] Therefore, this disclosure provides a fast recovery diode, a chip, and a method for manufacturing the same, to solve the above-mentioned problems. Summary of the Invention

[0006] According to one aspect of this disclosure, a fast recovery diode is provided, comprising: a P+ type anode region, a base region, and an N+ type cathode region, wherein the base region near the N+ cathode region further comprises: at least one buried layer region, the at least one buried layer region comprising a first portion and a second portion, the first portion having a different doping type than the second portion, and the first portion and the second portion forming a PN junction.

[0007] According to some embodiments, the base region is N-type doped.

[0008] According to some embodiments, the first portion is closer to the P+ type anode region than the second portion, and the second portion is closer to the N+ type cathode region than the first portion.

[0009] According to some embodiments, the doping concentration of the first portion is not greater than the doping concentration of the second portion.

[0010] According to some embodiments, the first portion is P+ type doped and the second portion is N+ type doped.

[0011] According to some embodiments, the thickness of the at least one buried layer region is less than that of the base region.

[0012] According to some embodiments, any one of the at least one buried layer regions has a rectangular, circular, or hexagonal shape on the horizontal plane.

[0013] According to some embodiments, the at least one buried layer area is centrally symmetrically distributed.

[0014] According to another aspect of this disclosure, a fast recovery diode chip is provided, including a chip active region, said chip active region including the fast recovery diode as described above.

[0015] According to another aspect of this disclosure, a method for fabricating a fast recovery diode is provided, comprising the following steps: doping a substrate to form an N+ type cathode region; forming an N- type base region on the N+ type cathode region; forming a buried layer region in the N- type base region near the N+ type cathode region, the buried layer region including a PN junction; and forming a P+ type anode region on the N- type base region.

[0016] This disclosure improves the switching softness of a fast recovery diode without compromising its low on-state loss performance by adding a buried region structure to the diode.

[0017] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a diode.

[0020] Figure 2 This is a schematic diagram of a diode based on an FCE.

[0021] Figure 3 This is a schematic diagram of a diode based on CIBH.

[0022] Figure 4 This is a schematic diagram of another type of diode based on CIBH;

[0023] Figure 5 This is a schematic diagram of the structure of a fast recovery diode according to an exemplary embodiment of the present disclosure;

[0024] Figure 6This is a top view schematic diagram of the buried structure of a fast recovery diode according to an exemplary embodiment of the present disclosure;

[0025] Figure 7 This is a schematic flowchart of a method for manufacturing a fast recovery diode according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0026] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0027] Spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” “above,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below,” “below,” or “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary terms “below” and “below” can cover both orientations above and below. Terms such as “before” or “in front” and “after” or “follow” can similarly be used, for example, to indicate the order in which light passes through the elements. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein shall be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or there can be one or more intermediate layers.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used in this specification designate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items, and the phrase “at least one of A and B” means only A, only B, or both A and B.

[0029] It will be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," it may be directly on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or directly adjacent to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "directly adjacent to another component or layer," no intermediate components or layers exist. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

[0030] Embodiments of this disclosure are described herein with reference to illustrative illustrations (and intermediate structures) of idealized embodiments. Therefore, variations in the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations due to manufacturing processes. Thus, the regions illustrated are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of this disclosure.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0032] Figure 1This is a schematic diagram of the structure of a diode 100. (Example) Figure 1 As shown, the PIN diode 100 has a P+ type anode region 101, an N+ type cathode region 103, and an N- type base region 102. The anode region 101, base region 102, and cathode region 103 constitute the PIN diode 100. When the PIN diode 100 is turned on transiently, the cathode of the anode region 101 and the anode of the cathode region 103 inject holes and electrons into the P+N- junction and N-N+ junction at both ends, respectively. Then, electrons and holes diffuse towards the N-base region while recombining. Due to the rapid increase of the anode current during the turn-on transient, but the diffusion rate of electrons and holes is limited, the carrier concentration in the low-doped N-base region is very low during the transient state, resulting in a high resistance. Therefore, in the initial stage of conduction, the forward voltage drop of the diode gradually increases with the current. As time accumulates, excess carriers in the N-base region continuously accumulate, and the concentration gradually increases, forming conductivity modulation. The forward voltage drop of the diode gradually returns to its normal value. When a PIN diode 100 is forward-biased, the N-base region contains a large number of excess carriers due to conductivity modulation. When a reverse bias is suddenly applied, these excess carriers need to be removed, forming a reverse recovery current. There are two mechanisms for eliminating excess electrons and holes in the base region: one is the sweeping current, formed by the electric field sweeping out the expanded space charge region. This sweeping current mainly exists in the early stages of reverse recovery. The other is the tailing current. In the later stages of reverse recovery, the device has already been subjected to a reverse bias, and at this time, the carriers are mainly eliminated by recombination of the remaining carriers. The length of the recombination lifetime determines the tailing time of the reverse recovery current.

[0033] Therefore, as Figure 1 The PIN diode 100 shown, while possessing advantages such as low forward voltage drop and low leakage current, exhibits high reverse recovery charge and a long switching time. To balance diode performance—for example, to strike a trade-off between the forward conduction, reverse cutoff, and reverse recovery characteristics of a high-voltage diode, achieving at least two of the advantages of low on-state loss, high breakdown voltage, and fast soft recovery characteristics simultaneously, or even further to simultaneously improve the device's resistance to dynamic avalanche degradation to adapt to harsh application conditions—continuous improvements to the structure of high-voltage diodes are necessary.

[0034] According to one embodiment, in order to improve the reverse recovery characteristics of the device and enhance its resistance to dynamic avalanche, its structure is improved by attaching... Figure 2 Structure: Field charge extraction (FCE) diode. Figure 2 This is a schematic diagram of a diode 200 based on FCE.

[0035] like Figure 2As shown, diode 200 has an anode region 201, a base region 202, and a cathode region 203. A shallow, high-concentration P+ region is embedded near the N+ cathode region 203, and an N- region is inserted between the N- base region 202 and the cathode region 203, effectively creating a parasitic PNP transistor on the cathode side of the diode. During reverse recovery, this PNP transistor conducts, and holes are injected into the base region from the P+N junction in the cathode region, establishing a plasma layer at the N+N- junction. This maintains the tail current at the end of the reverse recovery phase, resulting in soft recovery characteristics for the device.

[0036] Although Figure 2 The structure of diode 200 shown achieves soft-recovery characteristics, but this method increases the forward voltage drop, leading to increased conduction losses.

[0037] To further address the above issues, please refer to the appendix. Figure 3 The structures of diodes 300 and 400 described in section 4 are: back-side hole-injected controlled (CIBH) diodes. Figure 3 This is a schematic diagram of a CIBH-based diode 300. Figure 4 This is a schematic diagram of another type of diode 400 based on CIBH. (See diagram below.) Figure 3 As shown, it has an anode region 301, a base region 302, and a cathode region 303, relative to Figure 1 The diode 100 shown has at least one P-type buried layer region 304 (e.g., four P-type regions) embedded near the N+ cathode region, as shown. Figure 4 As shown, it has an anode region 401, a base region 402, and a cathode region 403, relative to Figure 1 The diode shown has an N-type region added near the N+ cathode region, and at least one P-type buried layer region 404 (e.g., four P-type regions) embedded in the N-type region. Figure 3 and Figure 4 The structure shown avoids, for example Figure 2 The diode exhibits the disadvantage of increased forward voltage drop. Furthermore, during reverse recovery, avalanche breakdown occurs in the P-region, generating carriers to sustain the tail current. However, with increasing P-type buried layer width and injection dose, its breakdown voltage decreases, and leakage current increases.

[0038] Therefore, for power devices (such as IGBTs and MOSFETs), the fast recovery diodes (FRDs) may experience current oscillations during reverse recovery, which can lead to damage to the IGBTs and diodes.

[0039] To avoid current oscillations, it is urgent to improve the switching softness of fast recovery.

[0040] Therefore, a fast recovery diode structure with soft recovery characteristics is proposed. Figure 5 This is a schematic diagram of the fast recovery diode 500 according to an exemplary embodiment of the present disclosure. Figure 6 This is a top view schematic diagram of the buried structure of a fast recovery diode according to an exemplary embodiment of the present disclosure, as shown below. Figure 5 As shown, a fast recovery diode 500 includes: a P+ type anode region 501, a base region 502, and an N+ type cathode region 503. The portion of the base region 502 near the N+ cathode region 503 further includes: at least one buried layer region 504. The at least one buried layer region 504 includes a first portion 5041 and a second portion 5042, wherein the first portion 5041 and the second portion 5042 have different doping types, and the first portion 5041 and the second portion 5042 form a PN junction.

[0041] Therefore, it can be seen that by adding a buried layer structure to the fast recovery diode, the switching softness of the diode can be improved without increasing the low on-state loss performance.

[0042] According to some embodiments of this disclosure, the base region is N-type doped. In other embodiments, the base region may also be selected as an intrinsic region.

[0043] According to some embodiments of this disclosure, the first portion is closer to the P+ type anode region than the second portion, and the second portion is closer to the N+ type cathode region than the first portion. According to some embodiments of this disclosure, the first portion is P+ type doped, and the second portion is N+ type doped.

[0044] like Figure 5 As shown, in the PN junction of the buried layer region 504, the P+ layer is closer to the P+ anode region, and the N+ layer is closer to the N+ cathode region. Furthermore, the first part of the P+ layer and the second part of the N+ layer, as a whole, are closer to the N+ cathode region. The high electric field buried layer structure formed by N+P+ allows the charge carriers flowing through this region to undergo a multiplication effect, thereby improving the switching softness of the diode 500 and avoiding current oscillation.

[0045] According to some embodiments of this disclosure, the doping concentration of the first portion is not greater than the doping concentration of the second portion. For example, the doping concentration of N+ is ≥ 5 × 10⁻⁶. 17 cm -3 By selecting the doping concentration, a high electric field can be achieved in the buried layer region, thereby realizing the carrier multiplication effect, improving fast-turn-off softness, and avoiding current oscillation.

[0046] According to some embodiments of this disclosure, the thickness of the at least one buried layer region 504 is less than that of the base region 502.

[0047] Since the N+ and P+ layers in the buried region are relatively thin, the presence of the buried region will not affect the diode's withstand voltage.

[0048] According to some embodiments of this disclosure, such as Figure 6 As shown, any one of the at least one buried layer areas has a rectangular, circular, or hexagonal shape on the horizontal plane.

[0049] Continue to refer to Figure 6 In other implementations, the embedded layer can also be in the shape of concentric rectangles or concentric circles. Because the embedded layer shape can be selected from a variety of shapes, this increases the flexibility in the manufacturing process and reduces the difficulty of production.

[0050] Continue to refer to Figure 6 According to some embodiments of this disclosure, the at least one buried layer region is centrally symmetrically distributed. The at least one buried layer region may include multiple buried layer regions, which are substantially centrally symmetrically distributed to ensure uniform carrier distribution and thus consistent diode performance.

[0051] Therefore, by incorporating an N+P+ junction buried layer structure, at least one of the following advantages can be achieved: The high electric field of the N+P+ buried layer structure allows for a multiplication effect of charge carriers flowing through this region, thereby improving the switching softness of the diode and preventing current oscillations. Since this buried layer structure is located near the cathode side of the N- region and does not directly contact the cathode electrode, it does not reduce the forward voltage drop of the diode. Furthermore, the high N+P+ doping concentration results in a low buried layer ratio, and the N+ and P+ layers are relatively thin, thus not affecting the device's breakdown voltage.

[0052] According to some embodiments of this disclosure, a fast recovery diode chip is also provided, comprising: a chip active region, wherein the chip active region includes the aforementioned fast recovery diode.

[0053] For example, the active area of ​​the chip can be connected to areas such as the chip terminal protection area, but this disclosure does not limit this.

[0054] For example, the thickness of the fast recovery diode chip provided in this disclosure can be 60μm to 750μm, and the withstand voltage range can be 600V to 6500V.

[0055] According to some embodiments of this disclosure, a method for manufacturing a fast recovery diode is also provided.

[0056] The substrate material for fabricating this fast recovery diode can be any type of semiconductor-on-insulator substrate. In some embodiments, the semiconductor-on-insulator substrate can be a silicon-on-insulator (SOI) substrate.

[0057] In some embodiments, the substrate can be made of any suitable material (e.g., silicon or germanium). For example, it can be a conventional semiconductor such as Si or a wide-bandgap semiconductor such as SiC or GaN.

[0058] The following is combined Figure 7 This disclosure introduces a method for manufacturing a fast recovery diode according to embodiments. Figure 7 This is a schematic flowchart of a fast recovery diode manufacturing method 700 according to an exemplary embodiment of the present disclosure.

[0059] According to some embodiments of this disclosure, a method 700 for manufacturing a fast recovery diode includes the following steps:

[0060] S701 provides the substrate;

[0061] S702, doping the substrate to form an N+ type cathode region;

[0062] S703, an N-type base region is formed on the N+ type cathode region;

[0063] S704, a buried region is formed in the portion of the N-type base region near the N+ type cathode region, the buried region including a PN junction;

[0064] S705, a P+ type anode region is formed on the N-type base region.

[0065] Therefore, it can be seen that by adding a buried layer structure to the fast recovery diode, the switching softness of the diode can be improved without increasing the low on-state loss performance.

[0066] For example, the doping method in the fabrication of a fast recovery diode can employ thermal diffusion or ion implantation techniques, and this disclosure does not limit it to either.

[0067] According to some embodiments of this disclosure, the buried layer region is a PN junction formed by N+P+.

[0068] According to some embodiments of this disclosure, the method further includes: forming an ohmic contact between the N+ type cathode region and the P+ type anode region to connect an external electrical signal.

[0069] According to some embodiments of this disclosure, the base region is N-type doped. In other embodiments, the base region may also be selected as an intrinsic region.

[0070] According to some embodiments of this disclosure, the first portion is closer to the P+ type anode region than the second portion, and the second portion is closer to the N+ type cathode region than the first portion. According to some embodiments of this disclosure, the first portion is P+ type doped, and the second portion is N+ type doped.

[0071] like Figure 5 As shown, in the PN junction of the buried layer region 504, the P+ layer is closer to the P+ anode region, and the N+ layer is closer to the N+ cathode region. Furthermore, the first part of the P+ layer and the second part of the N+ layer, as a whole, are closer to the N+ cathode region. The high electric field buried layer structure formed by N+P+ allows the charge carriers flowing through this region to undergo a multiplication effect, thereby improving the switching softness of the diode 500 and avoiding current oscillation.

[0072] According to some embodiments of this disclosure, the doping concentration of the first portion is not greater than the doping concentration of the second portion. For example, N+ ≥ P+ ≥ 5 × 10⁻⁶. 17 cm -3 By selecting the doping concentration, a high electric field can be achieved in the buried layer region, thereby realizing the carrier multiplication effect, improving fast-turn-off softness, and avoiding current oscillation.

[0073] According to some embodiments of this disclosure, the thickness of the at least one buried layer region 504 is less than that of the base region 502.

[0074] Because the N+ and P+ layers in the buried region are relatively thin, they do not affect the diode's withstand voltage.

[0075] According to some embodiments of this disclosure, such as Figure 6 As shown, any one of the at least one buried layer areas has a rectangular, circular, or hexagonal shape on the horizontal plane.

[0076] Continue to refer to Figure 6 In other implementations, the embedded layer can also be in the shape of concentric rectangles or concentric circles. Because the embedded layer shape can be selected from a variety of shapes, this increases the flexibility in the manufacturing process and reduces the difficulty of production.

[0077] Continue to refer to Figure 6 According to some embodiments of this disclosure, the at least one buried layer region is centrally symmetrically distributed. The at least one buried layer may include multiple buried layers, which are substantially centrally symmetrically distributed to ensure uniform carrier distribution and thus consistent diode performance.

[0078] Therefore, by incorporating an N+P+ junction buried layer structure, at least one of the following advantages can be achieved: The high electric field of the N+P+ buried layer structure allows for a multiplication effect of charge carriers flowing through this region, thereby improving the switching softness of the diode and preventing current oscillations. Since this buried layer structure is located near the cathode side of the N- region and does not directly contact the cathode electrode, it does not reduce the forward voltage drop of the diode; furthermore, the high N+P+ doping concentration results in a small buried layer ratio and thin N+ and P+ layers, which does not affect the device's breakdown voltage.

[0079] Although this disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and suggestive, not restrictive; this disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and implement variations of the disclosed embodiments in practice with respect to the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "a plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be beneficial.

Claims

1. A fast recovery diode, comprising: P+ type anode region, base region, and N+ type cathode region The base region near the N+ cathode region further includes at least one buried layer region, which is spaced apart from the N+ cathode region. The at least one buried layer region includes a first part and a second part, both of which are located in the base region, and the first part is located on the side surface of the second part facing away from the N+ cathode region, wherein the second part is spaced apart from the N+ cathode region; The doping type of the first part is different from that of the second part, and the first part and the second part constitute a PN junction; At least one buried layer region includes multiple buried layer regions, which are centrally symmetrically distributed among each other; each buried layer region constitutes an independent PN junction.

2. The diode according to claim 1, characterized in that, The base region is N-type doped.

3. The diode according to claim 1 or 2, characterized in that, The first portion is closer to the P+ type anode region than the second portion, and the second portion is closer to the N+ type cathode region than the first portion.

4. The diode according to claim 3, characterized in that, The doping concentration of the first part is not greater than the doping concentration of the second part.

5. The diode according to claim 3, characterized in that, The first part is P+ type doped, and the second part is N+ type doped.

6. The diode according to claim 1 or 2, characterized in that, The thickness of at least one buried layer region is less than that of the base region.

7. The diode according to claim 6, characterized in that, The shape of any one of the at least one buried layer areas on the horizontal plane is rectangular, circular, or hexagonal.

8. The diode according to claim 6, characterized in that, The buried layer area is centrally symmetrically distributed.

9. A fast recovery diode chip, comprising: The active region of the chip includes the fast recovery diode as described in any one of claims 1-7.

10. A method for manufacturing a fast recovery diode, comprising the following steps: The substrate is doped to form an N+ type cathode region; An N-type base region is formed on the N+ type cathode region; At least one buried layer region is formed in the portion of the N-type base region near the N+ type cathode region, and the buried layer region is spaced apart from the N+ cathode region; the buried layer region includes a PN junction; the at least one buried layer region includes a plurality of buried layer regions, which are centrally symmetrically distributed; each buried layer region constitutes an independent PN junction; the at least one buried layer region includes a first portion and a second portion, both of which are located in the base region, and the first portion is located on the surface of the second portion facing away from the N+ cathode region, wherein... The second part is spaced apart from the N+ cathode region; A P+ type anode region is formed on the N-type base region.

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