A power tube width switching circuit and method for buck converter

Abstract

The present invention discloses a power tube width switching circuit and method for a step-down converter. The circuit includes an analog-to-digital converter, an isolation circuit, a clock signal generating circuit, and a power tube driving circuit. The isolation circuit isolates signal jitter; the analog-to-digital converter receives a load current passing through the isolation circuit and generates a digital signal corresponding to the load current; the clock signal generating circuit generates a clock signal to drive the analog-to-digital converter; and the power tube driving circuit selectively turns on the corresponding power switch tube according to the digital signal output by the analog-to-digital converter. The advantages of the present invention are: the switch tube width is adaptively selected according to the load current size, which can reduce the power consumption of the switch tube during operation, does not require the introduction of a current sampling circuit, and there is no delay from the current sampling circuit to the final control effect, thereby eliminating the influence of the current sampling circuit on circuit stability.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuit design, and more particularly to a power tube width switching circuit and method applied to a buck converter. Background Art

[0002] Most electronic devices today, such as laptops, smartphones, and media players, have a single built-in battery. The battery's output voltage varies when fully charged and when nearly depleted, and different modules within an electronic device require different voltages. The power management unit (PMU) provides a stable and reliable voltage for each module within the device.

[0003] A buck converter is a type of constant current source characterized by high efficiency and compact size. There are many modulation methods for buck converters, such as pulse width modulation (PWM) and pulse frequency modulation (PFM). Pulse width modulation is an analog control method. It achieves control by varying the on-time of the output transistor or transistors of a switching regulator power supply, and is currently the most widely used method. PWM has high energy efficiency when the converter is heavily loaded, but lower efficiency at light loads, a drawback of PWM. Derivation shows that the power consumption of the converter's power transistors when on accounts for a significant portion of the system power. To overcome this drawback of PWM's low efficiency at light loads, some have proposed methods that adjust the size of the power transistors by sensing the load current.

[0004] Traditionally, load current is detected using a current sampling circuit, as exemplified by the high-precision input current sampling method for a buck-boost converter disclosed in Chinese patent application CN202010602333.7. However, the introduction of a current sampling circuit presents several challenges, including inherent power consumption and the potential delay between the current sampling circuit and the final control action, which can lead to system instability. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that the existing technology for switching the power tube width of a buck converter requires the introduction of a current sampling circuit. However, the current sampling circuit itself has power consumption, resulting in high system power consumption. In addition, the delay from the current sampling circuit to the final control effect may have the hidden danger of causing system instability.

[0006] The present invention solves the above-mentioned technical problems through the following technical means: a power tube width switching circuit applied to a buck converter, comprising an analog-to-digital converter, an isolation circuit, a clock signal generating circuit and a power tube driving circuit, wherein the isolation circuit and the clock signal generating circuit are connected to the analog-to-digital converter, and the analog-to-digital converter is connected to the power tube driving circuit; the isolation circuit isolates signal jitter; the analog-to-digital converter receives the load current passing through the isolation circuit and generates a digital signal corresponding to the load current; the clock signal generating circuit generates a clock signal to drive the analog-to-digital converter; and the power tube driving circuit selects to turn on the corresponding power switch tube according to the digital signal output by the analog-to-digital converter.

[0007] The power tube drive circuit of the present invention selectively turns on the corresponding power switch tube according to the digital signal output by the analog-to-digital converter, and the digital signal output by the analog-to-digital converter is converted from the load current. Therefore, the corresponding power switch tube can be adaptively selected and turned on according to the load current. Different power switch tube turning-on modes correspond to different switch tube widths, thereby achieving adaptive selection of the switch tube width according to the load current. This can reduce the power consumption of the switch tube during operation, eliminate the need for introducing a current sampling circuit, and eliminate the delay from the current sampling circuit to the final control effect, thereby eliminating the influence of the current sampling circuit on circuit stability.

[0008] Furthermore, the buck converter includes a pulse width modulation circuit and an error amplifier, both of which are operational amplifiers. The error amplifier is connected to the isolation circuit and the pulse width modulation circuit, and the pulse width modulation circuit is connected to the clock signal generating circuit and the power tube driving circuit.

[0009] Furthermore, the analog-to-digital converter is an N-bit successive approximation register type analog-to-digital converter.

[0010] Furthermore, the output of the voltage output circuit of the buck converter is a feedback signal V after the resistor divider FB Connected to the inverting terminal of the error amplifier, and the non-inverting terminal of the error amplifier is connected to the reference voltage V REF1 ; Error amplifier output V EA Connect the in-phase terminal of the pulse width modulation circuit and the input terminal of the isolation circuit, input the sawtooth wave signal to the inverting terminal of the pulse width modulation circuit; the output V PWM Connect one input end of the power tube drive circuit and the input end of the clock signal generating circuit, and the output V ADC The output CLK of the clock signal generating circuit is connected to one input terminal of the analog-to-digital converter, and the other input terminal of the analog-to-digital converter also receives the reference voltage V REF2 , the N outputs B1, B2…B of the analog-to-digital converter N-1 、B NConnect the other N input terminals of the power tube drive circuit to the output V PWM Together they serve as the logic control signal for the power tube drive circuit.

[0011] Furthermore, the output V of the power tube driving circuit G0 、V G1 、V G2 …V GN-1 、V GN Connect the gates of N+1 power switch tubes respectively, where the output of the pulse width modulation circuit V PWM Control the power tube drive circuit output V G0 , V G0 With power switch tube M P0 The gate connection of the analog-to-digital converter controls the N outputs of the power tube drive circuit to output V G1 、V G2 …V GN-1 、V GN , V G1 、V G2 …V GN-1 、V GN Respectively with the power switch tube M P1 ,M P2 …M PN-1 ,M PN Gate connection.

[0012] Furthermore, when V EA Less than 1 / 2 N V REF2 The output of the analog-to-digital converter is B1B2…B N-1 B N =00…00,V G1 =V G2 =…V GN-1 =V GN =1, power switch tube M P1 ,M P2 …M PN-1 ,M PN In the off state, the power switch tube M P0 The opening is by V PWM Regulation; when V EA More than 1 / 2 N V REF2 , when less than 2 / 2 N V REF2 When the output of the analog-to-digital converter is B1B2…B N-1 B N =00…01,V G1 =V G2 =…V GN-1 =1 power switch tube MP1 ,M P2 …M PN-1 In the off state, the power switch tube M P0 and M PN The opening is by V PWM Regulation; when V EA Greater than 2 / 2 N V REF2 , less than 3 / 2 N V REF2 When the output of the analog-to-digital converter is B1B2…B N-1 B N =00…10,V G1 =V G2 =…V GN-2 =1, power switch tube M P1 ,M P2 …M PN-2 In the off state, the power switch tube M P0 、M PN-1 and M PN The opening is by V PWM Regulation; Similarly, when V EA Greater than V REF2 When the analog-to-digital converter outputs B1B2…B N-1 B N =11…11, power switch tube M P0 ,M P1 ,M P2 …M PN-1 ,M PN The opening is all by V PWM Regulation.

[0013] Furthermore, the clock signal generating circuit includes a D flip-flop DFF1, an inverting gate INV3 and an AND gate AND1, which samples the output V PWM The rising edge of the signal V PULSE , signal V PULSE They are respectively input to the CLK terminal of the D flip-flop DFF1 and one input terminal of the AND gate AND1, the Q terminal of the D flip-flop DFF1 is connected to the input terminal of the NOT gate INV3, the output terminal of the NOT gate INV3 and the D terminal of the D flip-flop DFF1 are both connected to the other input terminal of the AND gate AND1, and the AND gate AND1 outputs the clock signal CLK.

[0014] Furthermore, the power tube driving circuit includes N first buffers, N second buffers, N NOT gates and N OR gates, and the outputs B1B2...B N-1 B NThe first buffers are connected in cascade, and the input of the first buffer is connected to the output of the pulse width modulation circuit V PWM The output of each OR gate is connected to the input of a second buffer, and the output of the last first buffer outputs V G0 , all second buffers output V G1 、V G2 …V GN-1 、V GN .

[0015] Furthermore, the isolation circuit is a source follower with NMOS as input tube, and the output V EA It is transmitted to the input of the analog-to-digital converter, but the voltage change at the input of the analog-to-digital converter is not transmitted to the output of the error amplifier, and the voltage is transmitted in one direction.

[0016] The present invention further provides a method for a power tube width switching circuit applied to a buck converter, the method comprising:

[0017] The isolation circuit isolates signal jitter; the analog-to-digital converter receives the load current passing through the isolation circuit and generates a digital signal corresponding to the load current; the clock signal generation circuit generates a clock signal to drive the analog-to-digital converter; the power tube drive circuit selects to turn on the corresponding power switch tube according to the digital signal output by the analog-to-digital converter. Different power switch tube turning-on modes correspond to different switch tube widths, thereby realizing adaptive selection of the switch tube width according to the load current size.

[0018] The advantages of the present invention are:

[0019] (1) The power tube driving circuit of the present invention selects to turn on the corresponding power switch tube according to the digital signal output by the analog-to-digital converter, and the digital signal output by the analog-to-digital converter is converted from the load current. Therefore, the corresponding power switch tube can be adaptively selected to turn on according to the load current. Different power switch tube turning-on modes correspond to different switch tube widths, thereby realizing adaptive selection of the switch tube width according to the load current size, which can reduce the power consumption of the switch tube during operation, does not require the introduction of a current sampling circuit, and does not have a delay from the current sampling circuit to the final control effect, thereby eliminating the influence of the current sampling circuit on the circuit stability.

[0020] (2) The present invention has a simple structure, and the required signals all come from the signals of the buck converter system itself, so signal multiplexing does not require the introduction of new modules to cause unnecessary power consumption.

[0021] (3) Conventional buck converters must operate in discontinuous conduction mode to maintain high efficiency at light loads, but this is only applicable at fixed loads. The present invention enables the buck converter to maintain high efficiency over a wide load range.

[0022] (4) The present invention uses an isolation circuit to isolate the output V EA Isolation from the ADC avoids some problems caused by charge redistribution during sampling.

[0023] (5) The present invention uses analog-to-digital conversion technology to detect the load current size and select the sum of the widths of different power switch tubes. This achieves the purpose of switching the width of the power switch tube without increasing the cost by making the size of the power switch tube too large. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a principle block diagram of a power tube width switching circuit applied to a buck converter disclosed in an embodiment of the present invention;

[0025] Figure 2 A detailed circuit schematic diagram of a power tube width switching circuit applied to a buck converter disclosed in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a clock signal generating circuit in a power tube width switching circuit for a buck converter disclosed in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of a power tube driving circuit in a power tube width switching circuit for a buck converter disclosed in an embodiment of the present invention;

[0028] Figure 5 This is a working principle diagram of an isolation circuit in a power tube width switching circuit applied to a buck converter disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0030] like Figure 1As shown, a power transistor width switching circuit for a buck converter includes an isolation circuit 1, a clock signal generating circuit 2, an analog-to-digital converter 3, and a power transistor driver circuit 4. The isolation circuit 1 and the clock signal generating circuit 2 are connected to the analog-to-digital converter 3, which is in turn connected to the power transistor driver circuit 4. The isolation circuit 1 isolates signal jitter; the analog-to-digital converter 3 receives the load current passing through the isolation circuit 1 and generates a digital signal corresponding to the load current; the clock signal generating circuit 2 generates a clock signal to drive the analog-to-digital converter 3; and the power transistor driver circuit 4 selectively activates the corresponding power switch transistor based on the digital signal output by the analog-to-digital converter 3. Different power switch activation modes correspond to different switch transistor widths, thereby enabling adaptive selection of the switch transistor width based on the load current. The analog-to-digital converter 3 is an N-bit successive approximation register type analog-to-digital converter 3.

[0031] like Figure 2 As shown, the buck converter includes a pulse width modulation circuit 5 and an error amplifier 6, both of which are operational amplifiers. The error amplifier 6 is connected to the isolation circuit 1 and the pulse width modulation circuit 5, and the pulse width modulation circuit 5 is connected to the clock signal generating circuit 2 and the power tube driving circuit 4.

[0032] Continue reading Figure 2 The output of the buck converter's voltage output circuit is divided by resistors to generate the feedback signal V FB The inverting terminal of the error amplifier 6 is connected to the reference voltage V REF1 ; Error amplifier 6 output V EA Connect the in-phase terminal of the pulse width modulation circuit 5 and the input terminal of the isolation circuit 1, input the sawtooth wave signal to the inverting terminal of the pulse width modulation circuit 5, and the output V EA Compared with the sawtooth wave signal; the pulse width modulation circuit 5 is essentially a comparator, which represents the result of the comparison between the two signals with a binary number. The sawtooth wave signal is input to the inverting input terminal of the pulse width modulation circuit 5, and the sawtooth wave signal is compared with V EA The result of the comparison is the output V of the pulse width modulation circuit 5. PWM . Figure 2 Other components and connection relationships are not important improvements of the present invention and are not described in detail. Figure 2 .

[0033] The output V of the pulse width modulation circuit 5 PWM Connect one input end of the power tube driving circuit 4 and the input end of the clock signal generating circuit 2, and the output V ADCThe output CLK of clock signal generating circuit 2 is connected to an input terminal of analog-to-digital converter 3. The output CLK of clock signal generating circuit 2 serves as the clock signal required for the operation of analog-to-digital converter 3. Analog-to-digital converter 3 is a dynamic circuit and requires a clock for normal operation. A separate, dedicated clock generator increases complexity, power consumption, and cost. Internal generation reduces complexity and power consumption. An internal clock has a high frequency. A lower clock frequency can further increase efficiency. In short, speed is sacrificed for improved efficiency.

[0034] Isolation circuit 1 output V ADC The purpose of connecting to one input terminal of the analog-to-digital converter 3 is to eliminate the charge redistribution caused by the analog-to-digital converter 3 during sampling. The other input terminal of the analog-to-digital converter 3 also receives the reference voltage V REF2 , the N outputs B1, B2…B of the analog-to-digital converter 3 N-1 、B N The other N input terminals of the power tube driving circuit 4 are connected to the output V PWM Together they serve as the logic control signal of the power tube driving circuit 4.

[0035] The output V of the power tube driving circuit 4 G0 、V G1 、V G2 …V GN-1 、V GN The gates of N+1 power switch tubes are connected respectively, wherein the output V PWM Control the power tube drive circuit 4 to output V G0 , V G0 With power switch tube M P0 The gate of the analog-to-digital converter 3 is connected, and the N outputs of the power tube drive circuit 4 respectively control the output V G1 、V G2 …V GN-1 、V GN , V G1 、V G2 …V GN-1 、V GN Respectively with the power switch tube M P1 ,M P2 …M PN-1 ,M PN Gate connection.

[0036] Changes in load current will cause the error comparator output V EA According to the principle of successive approximation register analog-to-digital converter (SAR ADC), when V EA Less than 1 / 2 N V REF2The output of analog-to-digital converter 3 is B1B2…B N-1 B N =00…00,V G1 =V G2 =…V GN-1 =V GN =1, power switch tube M P1 ,M P2 …M PN-1 ,M PN In the off state, the power switch tube M P0 The opening is by V PWM Regulation; when V EA More than 1 / 2 N V REF2 , when less than 2 / 2 N V REF2 When the output of analog-to-digital converter 3 is B1B2…B N-1 B N =00…01,V G1 =V G2 =…V GN-1 =1 power switch tube M P1 ,M P2 …M PN-1 In the off state, the power switch tube M P0 and M PN The opening is by V PWM Regulation; when V EA Greater than 2 / 2 N V REF2 , less than 3 / 2 N V REF2 When the output of analog-to-digital converter 3 is B1B2…B N-1 B N =00…10,V G1 =V G2 =…V GN-2 =1, power switch tube M P1 ,M P2 …M PN-2 In the off state, the power switch tube M P0 、M PN-1 and M PN The opening is by V PWM Regulation; Similarly, when V EA Greater than V REF2 When the analog-to-digital converter 3 outputs B1B2…B N-1 B N =11…11, power switch tube M P0 ,M P1 ,M P2 …M PN-1 ,M PN The opening is all by VPWM As mentioned above, the width of the power switch tube can be changed into 2 according to the load current. N Switch tubes with different total widths.

[0037] The following is a detailed introduction to the structure and principle of each circuit module:

[0038] like Figure 3 As shown, the clock signal generating circuit 2 includes a D flip-flop DFF1, an inverting gate INV3 and an AND gate AND1, which samples the output V of the pulse width modulation circuit 5. PWM The rising edge of the signal V PULSE , signal V PULSE The CLK terminal of the D flip-flop DFF1 and one input terminal of the AND gate AND1 are respectively inputted. The Q terminal of the D flip-flop DFF1 is connected to the input terminal of the NOT gate INV3. The output terminal of the NOT gate INV3 and the D terminal of the D flip-flop DFF1 are both connected to the other input terminal of the AND gate AND1. The AND gate AND1 outputs the clock signal CLK. By sampling V PWM The rising edge of V PULSE , then V PULSE A gating circuit (D flip-flop) reduces the frequency, maintaining the same pulse width while generating the clock signal CLK. Each multiplexing of a gating circuit reduces the clock frequency by half. This circuit sacrifices width switching speed but further reduces power consumption, which is crucial for high-efficiency applications.

[0039] like Figure 4 As shown, the power tube driving circuit 4 includes N first buffers, N second buffers, N NOT gates and N OR gates, and the outputs B1B2...B N-1 B N The first buffers are connected in series, and the input end of the first buffer is connected to the output V of the pulse width modulation circuit 5. PWM The output of each OR gate is connected to the input of a second buffer, and the output of the last first buffer outputs V G0 , all second buffers output V G1 、V G2 …V GN-1 、V GN .like Figure 4This is a schematic diagram of a 2-bit successive approximation register type analog-to-digital converter 3 (N is 2). In the figure, BUF1 and BUF2 are the first buffers, BUF3 and BUF4 are the second buffers, OR1 and OR2 are OR gates, INV1 and INV2 are NOT gates, and the two outputs B1 and B2 are connected to the input of the power tube drive circuit 4 and the output V of the pulse width modulation circuit 5. PWM Together they serve as the logic control signal of the power tube drive circuit 4. The output V G0 、V G1 、V G2 The gates of the three power switch tubes are connected respectively. The driving circuit of the present invention has the advantage of multiplexing the existing signals in the system, avoiding the increase of power consumption by introducing other modules.

[0040] In the power tube driving circuit 4 of the present invention, V G0 Control the minimum power tube to solve the startup problem. The change of load current will cause the output V EA According to the principle of successive approximation register analog-to-digital converter (SAR ADC), taking N=2 as an example, the power switch tube M P0 All by V PWM Regulation, when V EA Less than 1 / 4V REF2 When the output of the 2-bit successive approximation register analog-to-digital converter (SAR ADC) is B1B2 = 00, V G1 =V G2 =1, power switch tube M P1 ,M P2 In the off state; when V EA Greater than 1 / 4V REF2 , less than 1 / 2V REF2 When the output of the 2-bit successive approximation register analog-to-digital converter (SAR ADC) is B1B2=01, V G2 =1, power switch tube M P2 In the off state, the power switch tube M P1 The opening is by V PWM Regulation; when V EA Greater than 1 / 2V REF2 , when less than 3 / 4V REF2 When the output of the 2-bit successive approximation register analog-to-digital converter (SAR ADC) is B1B2=10, V G1 =1, power switch tube M P1 In the off state, the power switch tube M P2 The opening is by V PWM Regulation; when V EA Greater than V REF2When the output of the 2-bit successive approximation register analog-to-digital converter (SAR ADC) is B1B2=11, the power switch tube M P1 and M P2 The opening is all by V PWM As mentioned above, the width of the power switch tube can be changed into four different widths according to the size of the load current.

[0041] According to the basic principle of the buck converter, the relationship between the output voltage and the input voltage can be expressed as:

[0042] V OUT =V IN D (1)

[0043] In formula (1), V OUT Indicates the output voltage, V IN Denotes the input voltage, and D denotes the low-level duty cycle of the pulse width modulation signal. According to the above, the relationship between the duty cycle D and the load current when the buck converter operates in DCM mode can be expressed as:

[0044]

[0045] In formula (2), L represents the inductance, I OUT Indicates the load current, and T indicates the size of one clock cycle. When the load current changes, the duty cycle changes accordingly, causing the output voltage to change, V EA Also changes accordingly.

[0046] Under a certain load, the width of the power switch tube with the lowest power consumption is:

[0047]

[0048] In formula (3), W P Indicates the width of the power switch tube, V IN Indicates the input power supply voltage, C OX Indicates the gate capacitance per unit area of ​​the switch tube, I P Indicates the current flowing through the power switch tube, μ indicates the hole mobility, V tp represents the threshold voltage of the power switch tube, f represents the switching frequency, and η represents the fan-out coefficient of the buffer.

[0049] Therefore, the width of the power switch tube is W P The current I flowing through the power switch tube PThat is, the load current is relevant, so the width of the power switch tube can be adjusted according to the load current. The present invention utilizes analog-to-digital conversion technology to overcome the disadvantage of requiring a current sampling circuit. This allows the power tube to be adaptively adjusted in size under different load conditions.

[0050] like Figure 5 As shown, the isolation circuit 1 is a source follower with NMOS as input tube, and the output V EA The voltage is transmitted to the input of the analog-to-digital converter 3, but the voltage change at the input of the analog-to-digital converter 3 is not transmitted to the output of the error amplifier 6. The voltage is transmitted in one direction. It is generally believed that the input of the analog-to-digital converter 3 can be directly connected to the output of the error amplifier 6. However, in reality, the sampling operation in the analog-to-digital converter 3 will affect the output voltage V EA The value of V EA The value of will directly determine the duty cycle of the PWM signal after comparing it with the sawtooth wave, which in turn will determine the output voltage V OUT Therefore, V EA The change of the value will affect the output voltage, and eventually cause the output accuracy to decrease. Through the above analysis, it can be seen that on the one hand, it is hoped that the input signal of the analog-to-digital converter 3 is V EA On the other hand, we do not want the ADC 3 sampling operation to affect V EA If there is a circuit that inserts V EA and the ADC 3 input, so that V EA The value of can be transmitted to the input of analog-to-digital converter 3, while the voltage change of the input of analog-to-digital converter 3 will not be transmitted to V EA The isolation circuit 1 introduced in the present invention eliminates the charge redistribution caused by the analog-to-digital converter 3 during sampling.

[0051] The simplest way to implement isolation circuit 1 is to use a source follower with an NMOS input transistor. The characteristic of a source follower is that the voltage from the input end to the output end is unidirectional, thus achieving unidirectional voltage transmission. Another advantage of using a source follower is that it can reduce the input voltage of the analog-to-digital converter 3 by half the gate-source voltage V GS Keep V EA -V GS Always within the input range of the analog-to-digital converter 3. EA The voltage range is 300mV~1.5V, and the input range of analog-to-digital converter 3 is 0~1.2V. EA By reducing 300mV, the detection range of the analog-to-digital converter 3 can completely include V EA, avoid missing detection. Make full use of the detection range of analog-to-digital converter 3 to avoid resource waste.

[0052] Through the above technical solution, the power tube driving circuit 4 of the present invention selects to turn on the corresponding power switch tube according to the digital signal output by the analog-to-digital converter 3, and the digital signal output by the analog-to-digital converter 3 is converted from the load current. Therefore, the corresponding power switch tube can be adaptively selected to turn on according to the load current. Different power switch tube turning-on modes correspond to different switch tube widths, thereby realizing adaptive selection of the switch tube width according to the load current size, which can reduce the power consumption of the switch tube during operation, does not require the introduction of a current sampling circuit, and there is no delay from the current sampling circuit to the final control effect, thereby eliminating the influence of the current sampling circuit on circuit stability.

[0053] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A power tube width switching circuit for a buck converter, characterized in that: It includes an analog-to-digital converter, an isolation circuit, a clock signal generating circuit and a power tube driving circuit. The isolation circuit and the clock signal generating circuit are connected to the analog-to-digital converter, and the analog-to-digital converter is connected to the power tube driving circuit. The isolation circuit isolates signal jitter. The analog-to-digital converter receives the load current passing through the isolation circuit and generates a digital signal corresponding to the load current. The clock signal generating circuit generates a clock signal to drive the analog-to-digital converter. The power tube driving circuit selects to turn on the corresponding power switch tube according to the digital signal output by the analog-to-digital converter. Different power switch tube turning-on modes correspond to different switch tube widths, thereby realizing adaptive selection of the switch tube width according to the load current size. The buck converter includes a pulse width modulation circuit and an error amplifier. The pulse width modulation circuit and the error amplifier are both operational amplifiers. The error amplifier is connected to the isolation circuit and the pulse width modulation circuit. The pulse width modulation circuit is connected to the clock signal generating circuit and the power tube driving circuit.

2. The power tube width switching circuit for a buck converter according to claim 1, wherein: The analog-to-digital converter is an N-bit successive approximation register type analog-to-digital converter.

3. The power tube width switching circuit for a buck converter according to claim 2, wherein: The output of the buck converter's voltage output circuit is the feedback signal V after the resistor divider FB Connected to the inverting terminal of the error amplifier, and the non-inverting terminal of the error amplifier is connected to the reference voltage V REF1 ; Error amplifier output V EA Connect the non-inverting terminal of the pulse width modulation circuit and the input terminal of the isolation circuit, and input the sawtooth wave signal to the inverting terminal of the pulse width modulation circuit; The output of the pulse width modulation circuit V PWM Connect one input end of the power tube drive circuit and the input end of the clock signal generating circuit, and the output V ADC The output CLK of the clock signal generating circuit is connected to one input terminal of the analog-to-digital converter, and the other input terminal of the analog-to-digital converter also receives the reference voltage V REF2 , the N outputs B1, B2…B of the analog-to-digital converter N-1 、B N Connect the other N input terminals of the power tube drive circuit to the output V PWM Together they serve as the logic control signal for the power tube drive circuit.

4. The power tube width switching circuit for a buck converter according to claim 3, wherein: The output V of the power tube drive circuit G0 、V G1 、V G2 …V GN-1 、V GN Connect the gates of N+1 power switch tubes respectively, where the output of the pulse width modulation circuit V PWM Control the power tube drive circuit output V G0 , V G0 With power switch tube M P0 The gate connection of the analog-to-digital converter controls the N outputs of the power tube drive circuit to output V G1 、V G2 …V GN-1 、V GN , V G1 、V G2 …V GN-1 、V GN Respectively with the power switch tube M P1 ,M P2 …M PN-1 ,M PN Gate connection.

5. The power tube width switching circuit for a buck converter according to claim 4, characterized in that: When V EA Less than 1 / 2 N V REF2 The output of the analog-to-digital converter is B1B2…B N-1 B N =00…00,V G1 =V G2 =…V GN-1 =V GN =1, power switch tube M P1 ,M P2 …M PN-1 ,M PN In the off state, the power switch tube M P0 The opening is by V PWM Regulation; when V EA More than 1 / 2 N V REF2 , when less than 2 / 2 N V REF2 When the output of the analog-to-digital converter is B1B2…B N-1 B N =00…01,V G1 =V G2 =…V GN-1 =1 power switch tube M P1 ,M P2 …M PN-1 In the off state, the power switch tube M P0 and M PN The opening is by V PWM Regulation; when V EA Greater than 2 / 2 N V REF2 , less than 3 / 2 N V REF2 When the output of the analog-to-digital converter is B1B2…B N-1 B N =00…10,V G1 =V G2 =…V GN-2 =1, power switch tube M P1 ,M P2 …M PN-2 In the off state, the power switch tube M P0 、M PN-1 and M PN The opening is by V PWM Regulation; Similarly, when V EA Greater than V REF2 When the analog-to-digital converter outputs B1B2…B N-1 B N =11…11, power switch tube M P0 ,M P1 ,M P2 …M PN-1 ,M PN The opening is all by V PWM Regulation.

6. The power tube width switching circuit for a buck converter according to claim 1, wherein: The clock signal generating circuit includes a D flip-flop DFF1, an inverting gate INV3 and an AND gate AND1, and samples the output V of the pulse width modulation circuit. PWM The rising edge of the signal V PULSE , signal V PULSE They are respectively input to the CLK terminal of the D flip-flop DFF1 and one input terminal of the AND gate AND1, the Q terminal of the D flip-flop DFF1 is connected to the input terminal of the NOT gate INV3, the output terminal of the NOT gate INV3 and the D terminal of the D flip-flop DFF1 are both connected to the other input terminal of the AND gate AND1, and the AND gate AND1 outputs the clock signal CLK.

7. The power tube width switching circuit for a buck converter according to claim 1, wherein: The power tube driving circuit includes N first buffers, N second buffers, N NOT gates and N OR gates, and the outputs B1B2...B N-1 B N The output of each NOT gate is connected to an input of an OR gate, and the other input of each OR gate is connected to the output of a first buffer. Therefore, the first buffers are cascaded in sequence, and the input of the first buffer is connected to the output of the pulse width modulation circuit V PWM The output of each OR gate is connected to the input of a second buffer, and the output of the last first buffer outputs V G0 , all second buffers output V G1 、V G2 …V GN-1 、V GN .

8. The power tube width switching circuit for a buck converter according to claim 1, wherein: The isolation circuit is a source follower with NMOS as input tube, and the output of the error amplifier V EA It is transmitted to the input of the analog-to-digital converter, but the voltage change at the input of the analog-to-digital converter is not transmitted to the output of the error amplifier, and the voltage is transmitted in one direction.

9. The method for switching a power transistor width of a buck converter according to any one of claims 1 to 8, wherein: The method comprises: The isolation circuit isolates signal jitter; the analog-to-digital converter receives the load current passing through the isolation circuit and generates a digital signal corresponding to the load current; the clock signal generation circuit generates a clock signal to drive the analog-to-digital converter; the power tube drive circuit selects to turn on the corresponding power switch tube according to the digital signal output by the analog-to-digital converter. Different power switch tube turning-on modes correspond to different switch tube widths, thereby realizing adaptive selection of the switch tube width according to the load current size.

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