Anti-inversion interface circuit for a floating N-well

Abstract

The application provides a floating N-well anti-inversion interface circuit, which comprises a power supply module, a gate tracking module, a floating N-well module, a floating N-well stabilizing module, an output driving stage module and a transistor. When a chip enters a low-power consumption state, the floating N-well module delivers a first high potential to the gate tracking module, and the gate tracking module outputs a second high potential to the control end of the transistor after receiving the first high potential, so as to disconnect the electrical connection between the power supply module and the output driving stage module. Anti-inversion is realized, and the chip is prevented from being mistakenly awakened. The cooperation of the gate tracking module, the floating N-well module, the floating N-well stabilizing module and the transistor realizes anti-inversion, and the anti-inversion of the voltage or current of the chip is more stable and reliable. The floating N-well module stabilizes the potential of the floating N-well module, so that the floating N-well module provides a stable first high potential, and the anti-inversion stability is further improved, thereby solving the problems in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a floating N-well anti-backflow interface circuit. Background Technology

[0002] When the chip is in a low-power saving mode, such as when the chip enters sleep mode, the voltage of the IO terminal of the general-purpose input / output (GPIO) power supply is 0. If there is still a powered IO interface connected to the GPIO peripheral interface, due to the potential difference between the periphery and the inside of the GPIO, the voltage or current of the peripheral IO interface will flow back from the GPIO to the chip power supply, thus waking up the chip falsely.

[0003] Chinese patent CN 203243306 U discloses a reverse-current protection circuit for a chip multiplexed signal interface, including a diode D1, a transistor T1, resistors R1 and R2. The cathode of diode D1 is connected to the system hardware interface, and the anode of diode D1 is connected to the emitter E of transistor T1. The base B of transistor T1 is connected to the chip output pin, and the collector C of transistor T1 is grounded. Resistors R1 and R2 are connected in parallel and are both connected to the anode of diode D1. Resistor R2 is also connected to the chip output pin. This invention uses a Schottky diode D1 between the hardware interface and transistor T1 to prevent reverse current from flowing into the UART circuit, ensuring that 5V or 9V power cannot enter the circuit. However, this invention only uses a single Schottky diode for reverse current protection, making the protection unstable.

[0004] Therefore, it is necessary to provide a floating N-well anti-backflow interface circuit to solve the problems existing in the prior art. Summary of the Invention

[0005] The purpose of this invention is to provide a floating N-well anti-backflow interface circuit to solve the problems of backflow and anti-backflow instability of the chip.

[0006] To achieve the above objectives, the floating N-well anti-backflow interface circuit of the present invention includes a power supply module, a gate tracking module, a floating well module, a floating well stabilization module, an output driver stage module, and a transistor. The power supply module is connected to the gate tracking module, the floating well module, and the floating well stabilization module. The gate tracking module is connected to the control terminal of the transistor and the floating well module. The source of the transistor is connected to the power supply module, and the drain of the transistor is connected to the output driver stage module. The floating well module is connected to the floating well stabilization module, and the floating well module is used to stabilize the potential of the floating well module.

[0007] When the chip enters a low-power state, the floating trap module sends a first high potential to the gate tracking module. After receiving the first high potential, the gate tracking module outputs a second high potential to the control terminal of the transistor to disconnect the power supply module from the output driver stage module.

[0008] The beneficial effects of the floating N-well anti-backflow interface circuit of the present invention are as follows: The floating N-well anti-backflow interface circuit includes a power supply module, a gate tracking module, a floating well module, a floating well stabilization module, an output driver stage module, and a transistor. When the chip enters a low-power state, the floating well module sends a first high potential to the gate tracking module. After receiving the first high potential, the gate tracking module outputs a second high potential to the control terminal of the transistor to disconnect the electrical connection between the power supply module and the output driver stage module, thereby preventing current backflow to the output power supply module, achieving anti-backflow, and preventing the chip from being falsely woken up. The anti-backflow is achieved through the cooperation of the gate tracking module, the floating well module, the floating well stabilization module, and the transistor, making the voltage or current anti-backflow of the chip more stable and reliable. The floating well module stabilizes the potential of the floating well module, further improving the anti-backflow stability.

[0009] Optionally, the power supply module includes a battery, an I / O power supply, and an external power supply. The battery is connected to the I / O power supply, which is connected to the gate tracking module, the source of the transistor, the floating trap module, and the floating trap stabilization module. The external power supply is connected to the drain of the transistor via a reverse-flow terminal.

[0010] Optionally, the floating trap module includes a first PMOS transistor and a floating N-well. The gate of the first PMOS transistor is connected to the IO power supply. The substrate and source of the first PMOS transistor are shorted and connected to the floating N-well. The source of the first PMOS transistor is connected to the reverse-current terminal.

[0011] Optionally, the gate tracking module includes a second PMOS transistor, the gate of which is connected to the IO power supply, the source of which is connected to the source of the first PMOS transistor, the drain of which is connected to the control terminal of the transistor, and the substrates of the second PMOS transistor and the transistor are both connected to the floating N-well.

[0012] Optionally, when the chip enters a low-power state, the output voltage of the IO power supply is 0, the gate voltage of the first PMOS transistor is 0, the source and drain of the first PMOS transistor are turned on, the external power supply generates the first high potential and transmits the first high potential to the drain and substrate of the first PMOS transistor through the reverse-flow terminal, so that the potential of the floating N-well is the first high potential, and the potential from the first high potential to the substrate potential of the second PMOS transistor is the first high potential;

[0013] The gate voltage of the second PMOS transistor is 0, and its source and drain are turned on. The drain of the second PMOS transistor outputs a second high potential to the control terminal of the transistor, causing the source and drain of the transistor to disconnect, thereby disconnecting the electrical connection between the power supply module and the output driver stage module. The beneficial effect is that when the chip enters a low-power state, the first PMOS transistor turns on, transmitting a first high potential to the substrate of the second PMOS transistor. The second PMOS transistor then turns on, outputting a second high potential to the gate of the transistor, thus disconnecting the source and drain of the transistor and disconnecting the electrical connection between the power supply module and the output driver stage module. This achieves the reverse current protection function. By turning on the first PMOS transistor and raising the source voltage of the second PMOS transistor, and by turning on the second PMOS transistor and raising the gate voltage of the transistor, the stability of the reverse current protection is enhanced, avoiding accidental triggering of the reverse current protection mechanism.

[0014] Optionally, the floating trap stabilization module includes a first NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The gate of the first NMOS transistor is connected to the IO power supply and the gate of the third PMOS transistor. The drain of the first NMOS transistor is connected to the source of the third PMOS transistor and the source of the first PMOS transistor. The source of the first NMOS transistor is connected to the drain of the third PMOS transistor and the gate of the fourth PMOS transistor.

[0015] The drain of the fourth PMOS transistor is connected to the IO power supply, and the source of the fourth PMOS transistor is shorted to the substrate and connected to the source of the first PMOS transistor.

[0016] Optionally, when the chip is in normal operating condition, after the gate of the first NMOS transistor receives the output voltage of the IO power supply, the drain potential of the first NMOS transistor is a first low potential, and the source and drain of the first NMOS transistor are turned on to deliver the first low potential to the gate of the fourth PMOS transistor, so that the source and drain of the fourth PMOS transistor are turned on, and the output voltage of the IO power supply is transmitted to the floating N-well through the fourth PMOS transistor.

[0017] After the gate of the second PMOS transistor receives the output voltage of the IO power supply, the source and drain of the second PMOS transistor are disconnected, and the drain of the second PMOS transistor outputs a second low potential to the control terminal of the transistor, causing the source and drain of the transistor to conduct, thereby enabling the output driver stage module to work normally. Its beneficial effect is that when the chip is in normal working condition, the first NMOS transistor is turned on, and the source and drain of the first NMOS transistor conduct, thereby delivering the first low potential to the gate of the fourth PMOS transistor, causing the fourth PMOS transistor to turn on. The source and drain of the second PMOS transistor are disconnected, and it outputs a second low potential to the control terminal of the transistor, thereby turning on the transistor, and the chip's output driver stage module works normally. Therefore, the floating trap stabilization module not only plays a role in stabilizing and preventing backflow when the chip enters a low-power state, but also plays a role in stabilizing the chip's working state when the chip is working normally.

[0018] Optionally, the floating N-well backflow prevention interface circuit further includes an electrostatic discharge (ESD) protection module. This module comprises a battery ESD unit, an I / O power supply ESD unit, and a floating N-well ESD unit. The battery ESD unit is connected to the battery, the I / O power supply ESD unit is connected to the I / O power supply, and the floating N-well ESD unit is connected to the floating N-well. The advantage is that the ESD protection module protects against ESD, thereby reducing or even preventing damage to the chip from static electricity and improving chip lifespan.

[0019] Optionally, the output driver stage module includes a switch, a plurality of first inverters and a plurality of second inverters, the plurality of first inverters being connected in series, wherein the output terminal of one of the first inverters is connected to the first terminal of the switch, the second terminal of the switch is connected to the control terminal of the transistor and the drain of the second PMOS transistor, and the plurality of second inverters being connected in series.

[0020] Optionally, the floating N-well anti-backflow interface circuit further includes a second NMOS transistor and a third NMOS transistor, wherein the drain of the first NMOS transistor is connected to the output terminal of one of the second inverters and the gate of the third NMOS transistor, and the source of the second NMOS transistor is shorted to the substrate and grounded;

[0021] The drain of the third NMOS transistor is connected to the drain of the transistor, and the source of the third NMOS transistor is shorted to the substrate and grounded.

[0022] Optionally, the floating N-well anti-backflow interface circuit further includes a second NMOS transistor and a third NMOS transistor, wherein the drain of the first NMOS transistor is connected to the output terminal of one of the second inverters and the gate of the third NMOS transistor, and the source of the second NMOS transistor is shorted to the substrate and grounded;

[0023] The drain of the third NMOS transistor is connected to the drain of the transistor, and the source of the third NMOS transistor is shorted to the substrate and grounded. Its beneficial effect is that when the chip is in a low-power state, the gate of the fifth PMOS transistor receives a low level and is thus turned on. The drain of the fifth PMOS transistor outputs a high level to the gate of the second NMOS transistor, causing the second NMOS transistor to turn on. This allows current to flow from the source of the second NMOS transistor to ground, thereby preventing current from flowing back into the output drive module. Therefore, the anti-backflow logic module can further prevent backflow, thereby further strengthening the anti-backflow effect and improving the fault tolerance rate of the anti-backflow mechanism.

[0024] Optionally, the gate of the fifth PMOS transistor is connected to the gate of the fourth NMOS transistor and the first terminal of the switch, the source of the fifth PMOS transistor is connected to the drain of the first PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor and the gate of the second NMOS transistor, the substrate of the fifth PMOS transistor is connected to the floating N-well, and the source of the fourth NMOS transistor is grounded.

[0025] When the chip enters a low-power state, the fifth and fourth PMOS transistors generate switching control signals to control the switch to open, preventing the output current of the first inverter from flowing to the control terminal of the output driver stage transistor. The beneficial effect is that when the chip enters a low-power state, the fifth and fourth PMOS transistors generate switching control signals to control the switch to open, avoiding the transmission of the high level pulled up by the second PMOS transistor to the preceding circuit, and preventing current from flowing back from the first inverter to the I / O power supply, further achieving backflow prevention. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the floating N-well anti-backflow interface circuit of the present invention;

[0027] Figure 2 This is a circuit diagram of the floating N-well anti-backflow interface circuit according to an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0029] To address the problems existing in the prior art, embodiments of the present invention provide a floating N-well anti-backflow interface circuit. Figure 1 This is a schematic diagram of the floating N-well anti-backflow interface circuit of the present invention.

[0030] Reference Figure 1 The floating N-well anti-backflow interface circuit of the present invention includes a power supply module 1, a gate tracking module 2, a floating well module 3, a floating well stabilization module 4, an output driver stage module 5, and a transistor 6. The power supply module 1 is connected to the gate tracking module 2, the floating well module 3, and the floating well stabilization module 4. The gate tracking module 2 is connected to the control terminal of the floating well module 3 and the transistor 6. The source of the transistor 6 is connected to the power supply module 1, the drain of the transistor 6 is connected to the output driver stage module 5, the substrate of the transistor 6 is connected to the floating well module 3, and the floating well module 3 is connected to the floating well stabilization module 4. The floating well module 3 is used to stabilize the potential of the floating well module 3.

[0031] When the chip enters a low-power state, the floating trap module 3 provides a first high potential to the gate tracking module 2. After receiving the first high potential, the gate tracking module 2 outputs a second high potential to the control terminal of the transistor 6 to disconnect the power supply module 1 from the output driver stage module 5.

[0032] The advantages of the floating N-well anti-backflow interface circuit of the present invention are as follows: The floating N-well anti-backflow interface circuit includes a power supply module 1, a gate tracking module 2, a floating trap module 3, a floating trap stabilization module 4, an output driver stage module 5, and a transistor 6. When the chip enters a low-power state, the floating trap module 3 sends a first high potential to the gate tracking module 2. After receiving the first high potential, the gate tracking module 2 outputs a second high potential to the control terminal of the transistor 6 to disconnect the electrical connection between the power supply module 1 and the output driver stage module 5, thereby preventing current backflow to the output power supply module, achieving anti-backflow, and preventing the chip from being falsely woken up. The anti-backflow is achieved through the cooperation of the gate tracking module 2, the floating trap module 3, the floating trap stabilization module 4, and the transistor 6, making the voltage or current anti-backflow of the chip more stable and reliable. The anti-backflow stability is further improved by stabilizing the potential of the floating trap module 3.

[0033] In some embodiments, the transistor 6 is a PMOS transistor, and the control terminal of the transistor 6 refers to the gate of the PMOS transistor.

[0034] In some embodiments, the floating N-well anti-backflow interface circuit of the present invention can not only be used for anti-backflow of GPIO, but also be compatible with segment code LCD screen interfaces, that is, it can be used for anti-backflow of segment code LCD screen interfaces, and has high compatibility.

[0035] Figure 2 This is a circuit diagram of the floating N-well anti-backflow interface circuit according to an embodiment of the present invention.

[0036] As an optional embodiment of the present invention, refer to Figure 2 The power supply module 1 includes a battery 11, an I / O power supply 12, and an external power supply 13. The battery 11 is connected to the I / O power supply 12. The I / O power supply 12 is connected to the gate tracking module 2, the source of the transistor 6, the floating trap module 3, and the floating trap stabilization module 4. The external power supply 13 is connected to the drain of the transistor 6 through the backflow terminal PAD.

[0037] As an optional embodiment of the present invention, refer to Figure 2 The floating trap module 3 includes a first PMOS transistor 31 and a floating N-well 32. The gate of the first PMOS transistor 31 is connected to the IO power supply 12. The substrate and source of the first PMOS transistor 31 are shorted and connected to the floating N-well 32. The source of the first PMOS transistor 31 is connected to the reverse-current terminal PAD.

[0038] As an optional embodiment of the present invention, refer to Figure 2The gate tracking module 2 includes a second PMOS transistor 21. The gate of the second PMOS transistor 21 is connected to the IO power supply 12, the source of the second PMOS transistor 21 is connected to the drain of the first PMOS transistor 31, and the drain of the second PMOS transistor 21 is connected to the control terminal of the transistor 6. The substrates of the second PMOS transistor 21 and the transistor 6 are both connected to the floating N-well 32. (Refer to...) Figure 2 In the figure, FN on the substrate of the second PMOS transistor 21 and the substrate of the transistor 6 both indicate that the substrate is connected to the floating N-well 32.

[0039] As an optional embodiment of the present invention, when the chip enters a low-power state, the output voltage of the IO power supply 12 is 0, the gate voltage of the first PMOS transistor 31 is 0, the source and drain of the first PMOS transistor 31 are turned on, the external power supply 13 generates the first high potential and transmits the first high potential to the source of the first PMOS transistor 31 through the reverse-flow terminal PAD, the source and drain of the first PMOS transistor 31 are turned on, and the source of the first PMOS transistor 31 transmits the first high potential to the drain of the first PMOS transistor 31 so that the floating N-well potential of the third PMOS transistor 42 and the fourth PMOS transistor 43 is also the first high potential;

[0040] The gate voltage of the second PMOS transistor 21 is 0, and the source and drain of the second PMOS transistor 21 are turned on. The drain of the second PMOS transistor 21 outputs a second high potential to the control terminal of the transistor 6, thereby disconnecting the source and drain of the transistor 6 and breaking the electrical connection between the power supply module 1 and the output driver stage module 5. Its advantage is that when the chip enters a low-power state, the first PMOS transistor 31 turns on, transmitting the first high potential to the substrate of the second PMOS transistor 21. The second PMOS transistor 21 then turns on, outputting the second high potential to the gate of the transistor 6, thereby disconnecting the source and drain of the transistor 6. This achieves layered control, enhances the stability of the backflow prevention, and avoids accidental triggering of the backflow prevention mechanism.

[0041] As an optional embodiment of the present invention, refer to Figure 2 The floating trap stabilization module 4 includes a first NMOS transistor 41, a third PMOS transistor 42, and a fourth PMOS transistor 43. The gate of the first NMOS transistor 41 is connected to the IO power supply 12 and the gate of the third PMOS transistor 42. The drain of the first NMOS transistor 41 is connected to the source of the third PMOS transistor 42 and the source of the first PMOS transistor 41. The source of the first NMOS transistor 41 is connected to the drain of the third PMOS transistor 42 and the gate of the fourth PMOS transistor 43. The substrate of the first NMOS transistor 41 is grounded.

[0042] The source of the fourth PMOS transistor 43 is connected to the IO power supply 12, and the source of the fourth PMOS transistor 43 is shorted to the substrate and connected to the drain of the first PMOS transistor 31.

[0043] Reference Figure 2 The substrate of the third PMOS transistor 42 is connected to FN, i.e., connected to the floating N-well 32. The source and substrate of the fourth PMOS transistor 43 are both connected to FN, i.e. connected to the floating N-well 32.

[0044] As an optional embodiment of the present invention, when the chip is in normal working state, after the gate of the first NMOS transistor 41 receives the output voltage of the IO power supply 12, the potential of the drain of the first NMOS transistor is a first low potential. The source and drain of the first NMOS transistor 41 are turned on to deliver the first low potential to the gate of the fourth PMOS transistor 43, so that the source and drain of the fourth PMOS transistor 43 are turned on, and the output voltage of the IO power supply 12 is transmitted to the floating N-well 32 through the fourth PMOS transistor 43.

[0045] After the gate of the second PMOS transistor 21 receives the output voltage of the IO power supply 12, the source and drain of the second PMOS transistor 21 are disconnected, and the drain of the second PMOS transistor 21 outputs a second low potential to the control terminal of the transistor 6, making the source and drain of the transistor 6 conduct, so that the output driver stage module 5 can work normally. Its advantage is that when the chip is in normal working condition, the first NMOS transistor 41 is turned on, causing the fourth PMOS transistor 43 to turn on, the source and drain of the second PMOS transistor 21 are disconnected and output a second low potential to the control terminal of the transistor 6, thereby turning on the transistor 6 and enabling the chip's output driver stage module 5 to work normally; therefore, the floating trap stabilization module 4 not only plays a role in stabilizing and preventing backflow when the chip enters a low-power state, but also plays a role in stabilizing the chip's working state when the chip is working normally.

[0046] As an optional embodiment of the present invention, refer to Figure 2 The floating N-well anti-backflow interface circuit further includes an electrostatic discharge (ESD) protection module 7. The ESD protection module 7 includes a battery ESD protection unit 71, an I / O power supply ESD protection unit 72, and a floating N-well ESD protection unit 73. The battery ESD protection unit 71 is connected to the battery 11, the I / O power supply ESD protection unit 72 is connected to the I / O power supply 12, and the floating N-well ESD protection unit 73 is connected to the floating N-well 32. Its advantage is that the ESD protection module 7 is used for ESD protection, thereby reducing or even avoiding the damage of static electricity to the chip and improving the chip's lifespan.

[0047] As an optional embodiment of the present invention, refer to Figure 2The output drive stage module 5 includes a switch 51, a plurality of first inverters 53 and a plurality of second inverters 54. The plurality of first inverters 53 are connected in series, the output terminal of one of the first inverters 53 is connected to the first terminal of the switch 51, the second terminal of the switch 51 is connected to the control terminal of the transistor 6 and the drain of the second PMOS transistor 21, and the plurality of second inverters 54 are connected in series.

[0048] As an optional embodiment of the present invention, refer to Figure 2 The floating N-well anti-backflow interface circuit also includes a second NMOS transistor 9 and a third NMOS transistor 91. The drain of the first NMOS transistor 41 is connected to the second terminal of the second switch 52 and the gate of the third NMOS transistor 91. The source of the second NMOS transistor 9 is shorted to the substrate and grounded.

[0049] The drain of the third NMOS transistor 91 is connected to the drain of the transistor 6, and the source of the third NMOS transistor 91 is shorted to the substrate and grounded.

[0050] As an optional embodiment of the present invention, refer to Figure 2 The floating N-well anti-backflow interface circuit also includes an anti-backflow logic module 8, which includes a fifth PMOS transistor 81 and a fourth NMOS transistor 82.

[0051] The gate of the fifth PMOS transistor 81 is connected to the gate of the fourth NMOS transistor 82 and the switch 51. The source of the fifth PMOS transistor 81 is connected to the drain of the first PMOS transistor 31. The source of the fifth PMOS transistor 81 receives the potential signal of the reverse-current terminal PAD. The substrate of the fifth PMOS transistor is connected to FN, that is, the substrate of the fifth PMOS transistor 81 is connected to the floating N-well 32. The drain of the fifth PMOS transistor 81 is connected to the drain of the fourth NMOS transistor 82 and the gate of the second NMOS transistor 9. The source of the fourth NMOS transistor 82 is grounded.

[0052] When the chip enters a low-power state, the fifth PMOS transistor 81 and the fourth PMOS transistor 82 generate a switch control signal to control the switch 51 to open, so as to prevent the second PMOS transistor 21 from turning on and pulling the potential on the right side of the switch 51 high when the gate tracking module 2 is working, thus avoiding the transmission of the high level pulled by the second PMOS transistor 21 to the previous circuit and preventing the current at the first inverter 52 from flowing back to the IO power supply.

[0053] The gate of the fifth PMOS transistor 81 receives a low level and is thus turned on. The drain of the fifth PMOS transistor 81 outputs a high level to the gate of the second NMOS transistor 9, causing the second NMOS transistor 9 to turn on. This allows current to flow from the source of the second NMOS transistor 9 to ground, cutting off the path from the reverse-current terminal PAD of the third NMOS transistor 91 to ground. Therefore, the anti-reverse-current logic module 8 can further prevent reverse-current, thereby further strengthening the anti-reverse-current effect and improving the fault tolerance rate of the anti-reverse-current.

[0054] Therefore, the backflow prevention logic module 8 can further prevent backflow, thereby strengthening the backflow prevention effect and improving the backflow prevention fault tolerance rate.

[0055] In some specific embodiments, the working process of the floating N-well anti-backflow interface circuit of the present invention is as follows:

[0056] (1) When the chip is in normal working state, the IO power supply 12 outputs voltage VDDIO, and the external power supply 13 is floating; the reverse-flow terminal PAD passively receives the high level transmitted by transistor 6 or the low level transmitted by the third NMOS transistor 91; at this time, the drain potential of the first NMOS transistor 41 is the low potential of PAD, the switch 51 is closed, and the third NMOS transistor 91 is turned on; the first PMOS transistor 31, the second PMOS transistor 21, the third PMOS transistor 42 and the second NMOS transistor 9 are all in the off state; the gate of the first NMOS transistor 41 turns on after receiving VDDIO, and the source and drain of the first NMOS transistor 41 are connected, thereby transmitting the low level to the fourth PMOS transistor 43, thereby turning on the fourth PMOS transistor 43, and the source and drain of the fourth PMOS transistor 43 are connected, thereby making the voltage VDDIO input to the floating N-well 32 through the fourth PMOS transistor 43, thereby making the voltage of the floating N-well 32 VDDIO;

[0057] Since the second PMOS transistor 21 is in the off state, the drain of the second PMOS transistor 21 outputs a low level to the control terminal of the transistor 6, thereby turning on the transistor 6. The source and drain of the transistor 6 are connected, realizing the circuit connection between the IO power supply 12 and the output driver module 5. At this time, the chip works normally.

[0058] (2) When the chip enters the low power state, the output voltage VDDIO of the IO power supply 12 is 0, the first PMOS transistor 31, the second PMOS transistor 21 and the third PMOS transistor 42 are all turned on, the first NMOS transistor 41 is in the off state, the external power supply 13 generates the first high potential and transmits the first high potential to the source of the first PMOS transistor 31, the first high potential is the PAD high potential; at this time, the potentials of the drain of the first PMOS transistor 31, the first NMOS transistor 41, the drain of the third PMOS transistor, the drain of the transistor 6 and the floating N-well 32 are all PAD high potentials;

[0059] The drain of the first PMOS transistor 31 outputs a high potential PAD to the source of the second PMOS transistor 21, thereby pulling up the source potential of the second PMOS transistor 21. After the second PMOS transistor 21 is turned on, the drain of the second PMOS transistor 21 outputs a high potential to the gate of the transistor 6, which makes the transistor 6 in the off state. The source and drain of the transistor 6 are disconnected, thereby disconnecting the electrical connection between the power supply module 1 and the output drive stage module 5, and realizing the backflow prevention.

[0060] Meanwhile, the fifth PMOS transistor 81 and the fourth PMOS transistor 82 generate switch control signals to control the switch 51 to open, so as to prevent the first inverter 52 from outputting current to the control terminal of the transistor 6, and also to prevent the current output from the drain of the second PMOS transistor 21 from flowing back to the output driver module 5, thus further realizing the backflow prevention.

[0061] Meanwhile, since the output drive stage module 5 has a low potential, the gate of the fifth PMOS transistor 81 receives the low potential and turns on. The source and drain of the fifth PMOS transistor 81 are turned on, thereby transmitting the high potential of PAD to the gate of the second NMOS transistor 9, thereby turning on the second NMOS transistor 9 and outputting the current of the second inverter 53 to ground, avoiding current backflow and further realizing backflow prevention.

[0062] Meanwhile, since the second NMOS transistor 9 is turned on and transmits the current of the second inverter 53 to ground, the gate level of the third NMOS transistor 91 is low, which makes the third NMOS transistor 91 in the off state, disconnecting the circuit connection between the external power supply 13 and the output driver module 5, preventing the current output by the external power supply 13 from leaking to GND through the third NMOS transistor 91, thereby further realizing the backflow prevention.

[0063] In summary, for the floating N-well anti-backflow interface circuit of the present invention, after the chip enters the low-power state, it can not only disconnect the connection between the power supply circuit 1 and the output driving stage module 5 by controlling the transistor 6 to enter the cut-off state, achieving primary anti-backflow; but also disconnect the connection between the first inverter 52 and the control terminal of the transistor 6 by controlling the switch 51 to be disconnected, thus achieving secondary anti-backflow; and can also send the current of the second inverter 53 to the ground by controlling the second NMOS transistor 9 to be turned on, thus achieving tertiary anti-backflow; and can also avoid the current output by the external power supply 13 from leaking to the GND through the third NMOS transistor 91 by controlling the third NMOS transistor 91 to be turned off, thus achieving quaternary anti-backflow; therefore, the floating N-well anti-backflow interface circuit of the present invention can perform multi-level anti-backflow after the chip enters the low-power state, greatly enhancing the anti-backflow stability and greatly reducing the possibility of chip false wake-up.

[0064] In some embodiments, the floating N-well 32 of the present invention can more widely prevent the occurrence of backflow and has an anti-fooling function;

[0065] In the prior art, when the voltage VDDIO of the IO power supply 12 is any value (0V / 0.7V / 1.8V / 3V...), as long as the PAD voltage is higher than the VDDIO + Vth voltage, the GPIO will have a backflow phenomenon; the cooperation of the floating well module 3 and the floating well stabilization module 4 of the present invention can effectively avoid the above-mentioned backflow phenomenon. When VDDIO < PAD - Vth, the gate tracking module starts, where Vth is the threshold voltage of the second PMOS transistor 21. When the floating N-well anti-backflow interface circuit of the present invention is working, as long as the PAD voltage is any voltage less than the battery 11 voltage VBAT, anti-backflow operation can be performed to achieve anti-backflow and has an anti-fooling function;

[0066] Compared with the existing anti-backflow circuit, while simply adding a circuit, the present invention greatly improves the anti-backflow performance and stability and increases the anti-backflow fault tolerance rate of the circuit.

[0067] In order to verify the effect of the floating N-well anti-backflow interface circuit of the present invention, the inventor also conducted the following experiment:

[0068] (1) Make the chip enter the low-power state. At this time, the voltage VDDIO of the IO power supply 12 of the GPIO is 0, and the first high potential PAD of the GPIO is any level less than the battery 11 voltage VBAT; after testing, the transistor 6 is in the cut-off state, the anti-backflow function of the GPIO is enabled, and the chip is not falsely awakened;

[0069] (2) Make the battery 11 voltage VBAT of the chip 0V. At this time, the IO power supply 12 voltage VDDIO of GPIO is also 0. The first high potential PAD of GPIO is any level less than the battery 11 voltage VBAT. After testing, transistor 6 is in the off state, the reverse current protection function of GPIO is enabled, and the chip is not woken up by mistake.

[0070] Therefore, the anti-backflow interface circuit of the present invention can still achieve its anti-backflow function when the battery is depleted.

[0071] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A floating N-well anti-backflow interface circuit, characterized in that, The floating N well anti-flood interface circuit comprises a power supply module, a gate tracking module, a floating well module, a floating well stabilizing module, an output driving stage module and a transistor, the power supply module is connected with the gate tracking module, the floating well module and the floating well stabilizing module, the gate tracking module is connected with the control end of the transistor and the floating well module, the source of the transistor is connected with the power supply module, the drain of the transistor is connected with the output driving stage module, and the floating well module is connected with the floating well stabilizing module; the power supply module comprises a battery, an IO power supply and an external power supply, the battery is connected with the IO power supply, the IO power supply is connected with the gate tracking module, the source of the transistor, the floating well module and the floating well stabilizing module, and the external power supply is connected with the drain of the transistor through a reverse flow end; the floating well module comprises a first PMOS tube and a floating N well, the gate of the first PMOS tube is connected with the IO power supply, the substrate and the drain of the first PMOS tube are short-circuited and connected with the floating N well, and the source of the first PMOS tube is connected with the reverse flow end; the gate tracking module comprises a second PMOS tube, the gate of the second PMOS tube is connected with the IO power supply, the source of the second PMOS tube is connected with the source of the first PMOS tube, the drain of the second PMOS tube is connected with the control end of the transistor, and the substrate of the second PMOS tube and the substrate of the transistor are connected with the floating N well; the floating well stabilizing module comprises a fourth PMOS tube, the drain of the fourth PMOS tube is connected with the IO power supply, the source and the substrate of the fourth PMOS tube are short-circuited and connected with the source of the first PMOS tube; the output driving stage module comprises a switch, a plurality of first inverters and a plurality of second inverters, a plurality of the first inverters are connected in series, the output end of one of the first inverters is connected with the first end of the switch, the second end of the switch is connected with the control end of the transistor and the drain of the second PMOS tube, and a plurality of the second inverters are connected in series; the floating N well anti-flood interface circuit further comprises a second NMOS tube, the source and the substrate of the second NMOS tube are short-circuited and grounded; the floating N well anti-flood interface circuit further comprises an anti-flood logic module, the anti-flood logic module comprises a fifth PMOS tube and a fourth NMOS tube, the gate of the fifth PMOS tube is connected with the gate of the fourth NMOS tube and the first end of the switch, the source of the fifth PMOS tube is connected with the drain of the first PMOS tube, the drain of the fifth PMOS tube is connected with the drain of the fourth NMOS tube and the gate of the second NMOS tube, the substrate of the fifth PMOS tube is connected with the floating N well, and the source of the fourth NMOS tube is grounded; when the chip enters a low-power consumption state, the fifth PMOS tube and the fourth PMOS tube generate a switch control signal to control the switch to be turned off, so as to prevent the first inverter from outputting current to the control end of the output driving stage transistor.

2. The levitation N-well anti-inrush interface circuit of claim 1, wherein, When the chip enters the low power consumption state, the output voltage of the IO power supply is 0, the gate voltage of the first PMOS tube is 0, the source and drain of the first PMOS tube are turned on, the external power supply generates a first high potential and transmits the first high potential to the drain and substrate of the first PMOS tube through the backflow end, so that the potential of the floating N well is the first high potential, and the potential of the first high potential to the substrate of the second PMOS tube is the first high potential; The gate voltage of the second PMOS tube is 0, the source and drain of the second PMOS tube are turned on, the drain of the second PMOS tube outputs a second high potential to the control end of the transistor, so that the source and drain of the transistor are disconnected, thereby disconnecting the electrical connection between the power supply module and the output drive stage module.

3. The levitation N-well anti-inrush interface circuit of claim 1, wherein, The floating well stabilizing module comprises a first NMOS tube and a third PMOS tube, the gate of the first NMOS tube is connected to the IO power supply and the gate of the third PMOS tube, the drain of the first NMOS tube is connected to the source of the third PMOS tube and the source of the first PMOS tube, and the source of the first NMOS tube is connected to the drain of the third PMOS tube and the gate of the fourth PMOS tube.

4. The levitation N-well anti-inrush interface circuit of claim 3, wherein, When the chip is in a normal working state, after the gate of the first NMOS tube receives the output voltage of the IO power supply, the drain potential of the first NMOS tube is a first low potential, the source and drain of the first NMOS tube are turned on to transmit the first low potential to the gate of the fourth PMOS tube, so that the source and drain of the fourth PMOS tube are turned on, and the output voltage of the IO power supply is transmitted to the floating N well through the fourth PMOS tube; After the gate of the second PMOS tube receives the output voltage of the IO power supply, the source and drain of the second PMOS tube are disconnected, the drain of the second PMOS tube outputs a second low potential to the control end of the transistor, the source and drain of the transistor are turned on, and the output drive stage module works normally.

5. The levitation N-well anti-inrush interface circuit of claim 4, wherein, It also comprises an electrostatic discharge protection module, the electrostatic discharge protection module comprises a battery electrostatic discharge unit, an IO power supply electrostatic discharge unit and a floating well electrostatic discharge unit, the battery electrostatic discharge unit is connected to the battery, the IO power supply electrostatic discharge unit is connected to the IO power supply, and the floating well electrostatic discharge unit is connected to the floating N well.

6. The levitation N-well anti-inrush interface circuit of claim 5, wherein, It also comprises a third NMOS tube, the drain of the first NMOS tube is connected to the output end of one of the second inverters and the gate of the third NMOS tube; The drain of the third NMOS tube is connected to the drain of the transistor, and the source and substrate of the third NMOS tube are short-circuited and grounded.

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