Distributed weight updates for backpropagation of neural networks

Abstract

By updating the weights of the neural network in parallel, the speed of training the neural network is improved. In at least one embodiment, after backpropagation, the gradients are distributed to multiple processors, each of which computes a portion of the updated weights of the neural network.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 675,069, filed November 5, 2019, entitled “Distributed Weight Update for Backpropagation of a Neural Network,” the entire contents of which are incorporated herein by reference and used for all purposes. Technical Field

[0003] At least one embodiment relates to processing resources for performing and facilitating the training of neural networks. For example, at least one embodiment relates to a processor or computing system for training neural networks according to the various new techniques described herein. Background Technology

[0004] Neural networks are a crucial component of many computer-based solutions. In at least one embodiment, training a neural network is an intensive iterative process, which in some examples may consume significant amounts of memory, time, or computational resources. Therefore, reducing the amount of memory, time, or computational resources used to train a neural network is an important issue. Attached Figure Description

[0005] Various techniques will be described with reference to the accompanying drawings, in which:

[0006] Figure 1 An example of a machine learning process according to one embodiment is shown, wherein weight updates are performed redundantly and in parallel;

[0007] Figure 2 An example of a machine learning process according to one embodiment is shown, wherein weight updates are distributed across a set of workers and performed in parallel;

[0008] Figure 3 An example of a machine learning process according to one embodiment is shown, wherein weight updates are performed in a distributed and parallel manner;

[0009] Figure 4 An example of a machine learning process according to one embodiment is shown, wherein weight updates are performed in a distributed and redundant parallel manner;

[0010] Figure 5 An example of a machine learning process according to one embodiment is shown, wherein weight updates are distributed and performed in parallel across a set of workers based on available processing bandwidth;

[0011] Figure 6An example of a process according to one embodiment is shown, which, as a result of execution by a computer system, trains a machine learning model whose weight updates are performed in parallel;

[0012] Figure 7 An example of a process according to one embodiment is shown, which, as a result of execution by a computer system, trains a machine learning model, wherein weight updates are assigned to individual workers based on available processing power.

[0013] Figure 8 An example of a process according to one embodiment is shown, which, as a result of execution by a computer system, trains a machine learning model, wherein weight updates are incrementally distributed to individual workers.

[0014] Figure 9A The inference and / or training logic according to at least one embodiment is illustrated;

[0015] Figure 9B The inference and / or training logic according to at least one embodiment is illustrated;

[0016] Figure 10 The training and deployment of a neural network according to at least one embodiment are illustrated;

[0017] Figure 11 An example data center system according to at least one embodiment is shown;

[0018] Figure 12A An example of an autonomous vehicle according to at least one embodiment is shown;

[0019] Figure 12B The illustration shows an embodiment according to at least one of the embodiments. Figure 12A Examples of camera positions and field of view for autonomous vehicles;

[0020] Figure 12C This is an illustration based on at least one embodiment. Figure 12A A block diagram of an example system architecture for an autonomous vehicle;

[0021] Figure 12D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 12A A diagram of a system for communication between autonomous vehicles;

[0022] Figure 13 This is a block diagram illustrating a computer system according to at least one embodiment;

[0023] Figure 14 This is a block diagram illustrating a computer system according to at least one embodiment;

[0024] Figure 15A computer system according to at least one embodiment is shown;

[0025] Figure 16 A computer system according to at least one embodiment is shown;

[0026] Figure 17A A computer system according to at least one embodiment is shown;

[0027] Figure 17B A computer system according to at least one embodiment is shown;

[0028] Figure 17C A computer system according to at least one embodiment is shown;

[0029] Figure 17D A computer system according to at least one embodiment is shown;

[0030] Figure 17E and Figure 17F A shared programming model according to at least one embodiment is shown;

[0031] Figure 18 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0032] Figure 19A and Figure 19B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0033] Figure 20A and Figure 20B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0034] Figure 21 A computer system according to at least one embodiment is shown;

[0035] Figure 22A A parallel processor according to at least one embodiment is shown;

[0036] Figure 22B A partitioning unit according to at least one embodiment is shown;

[0037] Figure 22C A processing cluster according to at least one embodiment is shown;

[0038] Figure 22D A graphics multiprocessor according to at least one embodiment is shown;

[0039] Figure 23 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0040] Figure 24 A graphics processor according to at least one embodiment is shown;

[0041] Figure 25 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0042] Figure 26 A deep learning application processor according to at least one embodiment is shown;

[0043] Figure 27 A block diagram of an example neuromorphic processor is shown according to at least one embodiment;

[0044] Figure 28 At least a portion of a graphics processor according to one or more embodiments is shown;

[0045] Figure 29 At least a portion of a graphics processor according to one or more embodiments is shown;

[0046] Figure 30 At least a portion of a graphics processor according to one or more embodiments is shown;

[0047] Figure 31 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0048] Figure 32 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0049] Figure 33A and Figure 33B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0050] Figure 34 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0051] Figure 35 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0052] Figure 36 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown; and

[0053] Figure 37 A streaming multiprocessor according to at least one embodiment is shown. Detailed Implementation

[0054] This document describes a system and method for improving the training of machine learning models by allowing parallel updates of node weights. In at least one embodiment, multiple workers perform forward and backward propagation to generate gradient sets in parallel. In at least one embodiment, a worker can be a thread, process, processor, processor core, or parallel processing circuit that executes instructions in parallel with other workers. In at least one embodiment, gradients are distributed among workers, and each worker is assigned a subset of weights to which gradients are applied. In at least one embodiment, each worker applies gradients to its assigned subset of weights in parallel with other workers. In at least one embodiment, after applying gradients, updated weights are distributed among workers such that each worker has the complete updated weight set. In at least one embodiment, by updating weights in parallel with multiple workers, the speed at which the network can be trained is improved. In at least one embodiment, the backpropagation process is repeated iteratively until training is complete.

[0055] In at least one embodiment, training a deep learning model using the backpropagation algorithm is an iterative process, with each iteration comprising three phases: forward propagation pass, backpropagation pass, and weight update. In at least one embodiment, training is distributed in parallel among multiple workers, such that the work for forward and backpropagation passes is partitioned among the workers. In at least one embodiment, weight updates are performed at least partially by the workers in parallel. In at least one embodiment, some or all of the weight updates may be performed redundantly by multiple workers. In at least one embodiment, the weight update portion of training the deep learning model is accelerated by a factor approximately equal to the number of workers. In at least one embodiment, a worker may be a thread, process, processor, processor core, or processor with a multiprocessor graphics processing unit (“GPU”).

[0056] In at least one embodiment, in a synchronous data-parallel distributed deep learning (“DL”) training implementation, each of the multiple workers has access to a local copy of the weights of the machine learning model. In at least one embodiment, each worker computes the weight gradients during backpropagation and performs an all-reduced reduction across all workers, thereby providing each worker with a copy of its own sum of weight gradients across workers. In at least one embodiment, workers then use this to redundantly update their own copies of weights, ensuring that workers maintain identical updated copies of weights into the next iteration.

[0057] In at least one embodiment, a reduce-scatter operation is replaced with a reduce-scatter operation before updating the weights, and an all-gather operation is invoked after updating the weights. In at least one embodiment, the reduce-scatter operation results in each worker computing a unique 1 / k slice of the weight gradient across workers (where k is the number of workers). In at least one embodiment, each of the k workers then updates only those weights corresponding to the slices for which the worker has the cross-worker sum. In at least one embodiment, this reduces the weight update time by a factor of k (the number of workers). In at least one embodiment, the updated weights are then all-gathered among the workers, such that each worker receives an updated copy of the new weights.

[0058] In at least one embodiment, the net memory traffic remains constant because full reduction is implemented as a combination of reduce-distribution and full collection, moving as many bytes as the algorithm presented in this example. In at least one embodiment, a difference is that instead of a full collection summing the weight gradients, a full collection is applied to the updated weights, thus allowing for a distributed implementation of weight updates.

[0059] In at least one embodiment, the method described herein has the advantage of reducing the total memory footprint per worker. In at least one embodiment, the optimizer algorithm needs to maintain a persistent state across training iterations that go beyond individual weights and weight gradients. In at least one embodiment, this state is typically proportional to the size of the weights and includes tensors, such as higher-precision copies of the weights, or first and second moment estimates of the gradients. In at least one embodiment, using a distributed optimizer algorithm, each of the "k" workers only needs to maintain a 1 / k slice of these tensors corresponding to the weights it is responsible for updating.

[0060] In at least one embodiment, the synchronous data-parallel DL training scheme focuses on optimizing the optimizer code for each worker while maintaining the principle of redundant updates for all workers. In at least one embodiment, the model-parallel distributed training scheme benefits from fewer optimizer steps per worker due to the fact that each worker only has a small fraction of the model's weights. In at least one embodiment, this is accompanied by a significant increase in the complexity of other parts of the execution flow.

[0061] In at least one embodiment, as DL training scales to more GPUs (typically across nodes), the cost of weight updates becomes a compelling long pole in performance for many models. In at least one embodiment, this is addressed by improving the performance of the weight update kernel on a per-worker basis. However, in at least one embodiment, this is a fixed cost in terms of end-to-end runtime, unlike other computational components that become faster as more workers are added. In at least one embodiment, the method provides an algorithmic change that allows the optimizer's cost to decrease with scale, thereby reducing its cost as a part of the total runtime. In at least one embodiment, such optimization is important for being competitive with several machine learning training models.

[0062] In at least one embodiment, the techniques described herein have the effect of mitigating some of the memory capacity limitations currently observed when training large models on GPUs. In at least one embodiment, significant amounts of memory can be freed up by allocating weights to the FP32 master copy during mixed-precision training, along with some other persistent state required by optimizers like SGD and Adam, potentially allowing for larger models or larger batch sizes of existing models.

[0063] Figure 1 An example of a machine learning process with redundantly and parallelly executed weight updates is illustrated according to one embodiment. In at least one embodiment, the computer system training includes a machine learning model comprising a set of nodes or neurons, each node or neuron having associated weights or coefficients. In at least one embodiment, weights 102 are updated in response to training data during training. In at least one embodiment, the training data includes inputs and outputs, and the training process produces a trained machine learning model that estimates a function suitable for the training data. In at least one embodiment, forward and backward propagation processes are used to generate a set of gradients 104 for weights 102. In at least one embodiment, in forward propagation, input data is provided to the machine learning model to produce output values, and the output values ​​are backpropagated to estimate a set of gradients 104.

[0064] In at least one embodiment, a full reduction process is performed, wherein gradient 104 is assigned to a group of workers. In at least one embodiment, the workers apply gradient 104 to previous weights to produce updated weights 108. In at least one embodiment, each worker redundantly applies gradient 106 to all weights so that each worker processes and generates matching information. In at least one embodiment, the updated weights 108 are then used during the next round of forward and backward propagation.

[0065] In at least one embodiment, the workers are implemented as threads running on a computer system, such as the computer system described below. In at least one embodiment, the workers are implemented as processes on a graphics processing unit, such as the graphics processing unit described below. In at least one embodiment, the workers are implemented as processes on a multiprocessor computer system. In at least one embodiment, the workers run on a single core of a multi-core processor.

[0066] In at least one embodiment, process 100 allows for parallel processing of forward and backward propagation to generate weight gradients. In at least one embodiment, the speed of gradient generation is improved by adding additional workers to the training task. In at least one embodiment, weight updates are performed redundantly by each worker, thus requiring a consistent amount of time regardless of the number of workers applied.

[0067] In at least one embodiment, the number of weights in the machine learning model is based at least in part on the number of nodes and the number of layers. In at least one embodiment, the model has many layers and nodes, and updating the weights consumes a significant amount of processing time.

[0068] In at least one embodiment, Figure 1 A synchronous data-parallel distributed deep learning (“DL”) training implementation is illustrated, wherein each of a plurality of workers has access to a local copy of the weights of the machine learning model. In at least one embodiment, the weight gradient of each worker is computed during backpropagation and a full reduction is performed across all workers, thereby providing each worker with its own copy of the sum of weight gradients across workers. In at least one embodiment, workers are able to use copies of the weight gradients to redundantly update corresponding copies of the weights, ensuring that each worker maintains a matching copy of the updated weights into future iterations.

[0069] Figure 2 An example of a machine learning process 200 according to an embodiment is shown, wherein weight updates are distributed among a set of workers and performed in parallel. In at least one embodiment, the machine learning model comprising a set of nodes has an associated set of weights 202. In at least one embodiment, the set of weights is a set of numerical coefficients that, when applied to the input of a neural network and propagated through the neural network, approximate a function defined by a set of test data used to train the model. In at least one embodiment, the test data is forward-propagated through the model to produce results, and errors determined at least in part based on the expected results in the test data are back-propagated to produce gradient estimates. In at least one embodiment, the gradient estimates are used to adjust the weights of the model.

[0070] In at least one embodiment, a group of workers operates on each path to generate a set of gradients 204 in parallel. In at least one embodiment, the set of gradients 204 is generated by applying a gradient descent algorithm. In at least one embodiment, the gradient is a slope that can be expressed as the ratio between the generated error and the input parameters of the neural network. In at least one embodiment, the gradient represents the relationship between changes in the input and the generated error. In at least one embodiment, the gradient set 204 includes a set of partial derivatives of the contribution of each input parameter to the change in error.

[0071] In at least one embodiment, a reduce-distribution operation is performed before updating the 206 weights and a call to full-collection is performed after the weights are updated. In at least one embodiment, the reduce-distribution results in each worker computing the sum across workers of a unique 1 / k slice of the weight gradient (where k is the number of workers). In at least one embodiment, various work assignments can be allocated to workers based on available processing power, bandwidth, memory, or other computing resources. In at least one embodiment, each of the multiple workers (k) updates those weights corresponding to the slice it has been assigned. In at least one embodiment, this operation is performed in parallel by the workers, thereby reducing the amount of time required to complete the weight update. In at least one embodiment, the amount of time required to update the weights is reduced by a factor K, where K is the number of workers.

[0072] In at least one embodiment, the workers are implemented as threads running on a computer system, such as the computer system described below. In at least one embodiment, the workers are implemented as processes on a graphics processing unit, such as the graphics processing unit described below. In at least one embodiment, the workers are implemented as processes on a multiprocessor computer system. In at least one embodiment, the workers run on a single core of a multi-core processor.

[0073] In at least one embodiment, after each worker updates its weight portion, the updated portion is distributed among the workers such that each worker has the complete set of updated weights 208. In at least one embodiment, the updated weights are then fully collected across the workers such that each worker obtains a complete updated copy of the new weights of the neural network.

[0074] Figure 3An example of a machine learning process 300 according to an embodiment is shown, wherein weight updates are performed in a distributed and parallel manner. In at least one embodiment, an initial set of weights is distributed among four workers, and a corresponding set of gradients 302 is computed by the workers. In at least one embodiment, the workers may be implemented as individual threads running on a computer system, individual processes on a graphics processing unit, or processes on a multiprocessor computer system. In at least one embodiment, a reduction-distribution operation divides the weight update operation into multiple substantially equal portions, which are assigned to the workers. In at least one embodiment, in an intermediate state 304, a portion of the gradients is distributed among the workers. In at least one embodiment, a first worker is assigned a first portion 308 of the weight update, a second worker is assigned a second portion 310 of the weight update, a third worker is assigned a third portion 312 of the weight update, and a fourth worker is assigned a fourth portion 314 of the weight update. In at least one embodiment, the portions of the weight update are evenly distributed among the workers. In at least one embodiment, the portions of the weight update do not overlap.

[0075] In at least one embodiment, each worker processes its assigned weight update portion by applying gradients to existing weights. In at least one embodiment, each worker distributes the updated weight portion to other workers, such that each worker has a matching copy of the updated weights. In at least one embodiment, each worker updates the weights in a shared memory region accessible to all workers. In at least one embodiment, gradients and updated weights are distributed among workers using inter-process communication. In at least one embodiment, completed portions are collected, such that in end state 306, each worker has a matching copy of the updated weights.

[0076] Figure 4An example of a machine learning process 400 according to an embodiment is shown, wherein weight updates are distributed and redundantly performed in parallel. In at least one embodiment, an initial set of weights is distributed among four workers, and a corresponding set of gradients 402 is computed by the workers. In at least one embodiment, the workers may be implemented as individual threads running on a computer system, individual processes on a graphics processing unit, or processes on a multiprocessor computer system. In at least one embodiment, a reduction-distribution operation divides the weight update operation into multiple substantially equal parts, which are assigned to workers. In at least one embodiment, in an intermediate state 404, a portion of the gradients is distributed among the workers. In at least one embodiment, a first worker is assigned a first portion 408 of the weight update, a second worker is assigned a second portion 410 of the weight update, a third worker is assigned a third portion 312 of the weight update, and a fourth worker is assigned a fourth portion 414 of the weight update. In at least one embodiment, the portions of the weight update are evenly distributed across the set of workers such that each weight is computed by two or more workers. In at least one embodiment, workers are divided into pairs, and the weight update is evenly distributed among the pairs. In at least one embodiment, each worker is assigned a weight update portion that overlaps with at least a portion of the weight update portions of the other two workers.

[0077] In at least one embodiment, each worker processes its assigned weight update portion by applying gradients to existing weights. In at least one embodiment, each worker distributes the updated weight portions to other workers, such that each worker has a matching copy of the updated weights. In at least one embodiment, each worker updates the weights in a shared memory region accessible to all workers. In at least one embodiment, gradients and updated weights are distributed among workers using inter-process communication. In at least one embodiment, completed portions are collected, such that in end state 406, each worker has a matching copy of the updated weights.

[0078] Figure 5An example of a machine learning process 500 according to an embodiment is shown, wherein weight updates are distributed across a group of workers and executed in parallel based on available processing bandwidth. In at least one embodiment, an initial set of weights is allocated among four workers, and a corresponding set of gradients 502 is computed by the workers. In at least one embodiment, the workers may be implemented as individual threads running on a computer system, individual processes on a graphics processing unit, or processes on a multiprocessor computer system. In at least one embodiment, a reduction-distribution operation divides the weight update operation into multiple substantially equal parts, which are assigned to workers. In at least one embodiment, in an intermediate state 504, a portion of the gradients is distributed among the workers. In at least one embodiment, a first worker is assigned a first portion 508 of the weight update, a second worker is assigned a second portion 510 of the weight update, a third worker is assigned a third portion 512 of the weight update, and a fourth worker is assigned a fourth portion 514 of the weight update. In at least one embodiment, the portions of the weight update are distributed among the workers to determine all weights and to compute weights without redundancy. In at least one embodiment, the amount of weight update assigned to each worker is determined based on the characteristics of each worker. In at least one embodiment, weight updates are assigned to workers based on the amount of processing bandwidth available to each worker. In at least one embodiment, work is assigned to workers incrementally, and additional work is assigned by an execution process that coordinates the allocation of weight update work as each worker completes its assigned portion.

[0079] In at least one embodiment, each worker processes its assigned weight update portion by applying gradients to existing weights. In at least one embodiment, each worker distributes the updated weight portion to other workers, such that each worker has a matching copy of the updated weights. In at least one embodiment, each worker updates the weights in a shared memory region accessible to all workers. In at least one embodiment, gradients and updated weights are distributed among workers using inter-process communication. In at least one embodiment, completed portions are collected, such that in end state 506, each worker has a matching copy of the updated weights.

[0080] Figure 6An example of process 600 according to one embodiment is shown, which, as a result of execution by a computer system, trains a machine learning model using weight updates performed in parallel. In at least one embodiment, at block 602, the computer system begins training a machine learning model by forward propagating a set of input values ​​from a training dataset to produce a set of outputs. In at least one embodiment, gradient 604 is generated by backpropagating the difference between the produced outputs and the training data. In at least one embodiment, the gradient describes the relationship between changes in the input values ​​and error terms produced by the machine learning model. In at least one embodiment, the gradient is generated in parallel by multiple workers. In at least one embodiment, the workers may execute on separate threads, processors, processor cores, or processes on the computer system. In at least one embodiment, the gradient is generated in parallel by workers at least partially.

[0081] In at least one embodiment, at block 606, gradients are distributed among a group of workers. In at least one embodiment, gradients are distributed via an inter-process communication mechanism. In at least one embodiment, gradients are distributed among a group of workers using shared memory. In at least one embodiment, gradients are aggregated by an executor, and the reassigned gradients are sent to each of the workers.

[0082] In at least one embodiment, at block 608, the trained computer system analyzes a set of weights associated with the machine learning model and divides the task of updating said weights into a set of weight update portions to be performed by workers. In at least one embodiment, at block 610, each worker computes a portion of the weight update in parallel using gradients. In at least one embodiment, the weight update operations are evenly distributed among workers, and the weight update operations are performed in parallel. In at least one embodiment, the weight update operations may be distributed among workers, as per [the relevant context]. Figure 3-5 As shown and described.

[0083] In at least one embodiment, at block 612, a worker produces the result of a weight update operation, which is distributed to other workers such that each worker has a complete set of matching copies of the updated weights. In at least one embodiment, at block 614, each worker merges a portion of its updated weights with portions of updated weights obtained from other workers to produce a complete set of updated weights. In at least one embodiment, the weights are assembled in a shared memory region accessible to all workers. In at least one embodiment, the shared memory region is a semiconductor memory having accessible regions mapped to an address space accessible to all workers. In at least one embodiment, the shared memory is a file on a storage medium such as a hard disk. In at least one embodiment, the storage medium is a hard disk. In at least one embodiment, the storage medium is a solid-state memory device, such as an SD drive.

[0084] In at least one embodiment, at box 614, process 600 returns to box 602, where the next iteration of the training process is performed.

[0085] Figure 7 An example of process 700 according to one embodiment is shown, which, as a result of execution by a computer system, trains a machine learning model, wherein weight updates are allocated to individual workers based on available processing power. In at least one embodiment, at block 702, the computer system begins training a machine learning model by forward propagating a set of input values ​​from the training dataset to produce a set of outputs. In at least one embodiment, a set of gradients 704 is generated by backpropagating the difference between the produced outputs and the training data. In at least one embodiment, the gradients describe the relationship between changes in the input values ​​and error terms produced by the machine learning model. In at least one embodiment, the gradients are generated in parallel by multiple workers. In at least one embodiment, the workers may execute on separate threads, processors, processor cores, or processes on the computer system. In at least one embodiment, the gradients are generated in parallel by workers at least partially.

[0086] In at least one embodiment, at block 706, gradients are distributed among a group of workers. In at least one embodiment, gradients are distributed via an inter-process communication mechanism. In at least one embodiment, gradients are distributed among a group of workers using shared memory. In at least one embodiment, gradients are aggregated by an execution process that reallocates the gradients to each worker. In at least one embodiment, the execution process is a process that coordinates the entire training of the neural network.

[0087] In at least one embodiment, at block 708, the execution process determines the amount of processing bandwidth available to each worker. In at least one embodiment, the amount of processing bandwidth available to each worker is determined by executing a test task on each worker. In at least one embodiment, the number of available processing providers is determined based on clock speed, processor type, or processing priority associated with each worker.

[0088] In at least one embodiment, at block 710, the trained computer system analyzes the set of weights associated with the machine learning model and divides the task of updating the weights into a set of weight update portions to be performed by workers. In at least one embodiment, the weight update operations are distributed among workers, and the weight update operations are performed in parallel. In at least one embodiment, the weight update operations may be distributed among workers, as per [the relevant context]. Figure 3-5 As shown and described. In at least one embodiment, work is allocated to workers in proportion to the amount of processing bandwidth determined above. In at least one embodiment, at block 712, each worker uses gradient parallel computation to compute a portion of the weight update.

[0089] In at least one embodiment, at block 714, a worker produces the result of a weight update operation, which is distributed to other workers such that each worker has a complete set of matching copies of the updated weights. In at least one embodiment, at block 716, each worker merges a portion of its updated weights with portions of the updated weights obtained from other workers to produce a complete set of updated weights. In at least one embodiment, the weights are assembled in a shared memory region accessible to all workers. In at least one embodiment, the shared memory region is a semiconductor memory having an accessible region mapped to an address space accessible to all workers. In at least one embodiment, the shared memory is a file on a storage medium such as a hard disk. In at least one embodiment, the storage medium is a hard disk. In at least one embodiment, the storage medium is a solid-state memory device, such as an SD drive.

[0090] In at least one embodiment, at box 716, process 700 returns to box 702, where the next iteration of the training process is performed.

[0091] Figure 8An example of process 800 according to one embodiment is shown, which, as a result of execution by a computer system, trains a machine learning model, wherein weight updates are incrementally assigned to individual workers. In at least one embodiment, at block 802, the execution process divides the task of updating the weights of the machine learning model into a set of work units. In at least one embodiment, the number of work units is significantly greater than the number of available workers to perform the task of updating the weights. In at least one embodiment, at block 802, an executor assigns individual work units to each available worker. In at least one embodiment, the executor is a process that controls the actions of multiple workers running on one or more processors. In at least one embodiment, the executor is capable of starting, stopping, and assigning work to one or more workers.

[0092] In at least one embodiment, at decision block 804, workers execute their respective work units until at least one worker completes its work unit and is idle. In at least one embodiment, at block 806, an idle worker is identified, and an additional work unit is assigned to the idle worker. In at least one embodiment, at decision block 808, if there is an additional work unit to assign, execution returns to decision block 804, and the executor waits for the additional worker to become idle. In at least one embodiment, if there is no additional work unit, execution proceeds to block 810. In at least one embodiment, at block 810, the executor waits for all workers to complete their assigned tasks. In at least one embodiment, the process of updating the weights of the machine learning model is completed when all workers have completed their assigned tasks. In at least one embodiment, by assigning work units incrementally, worker utilization can be improved when a set of non-homogeneous workers is used in parallel to perform weight update tasks.

[0093] In at least one embodiment, the worker can be a thread, process, processor, processor core, or parallel processing circuit that executes instructions in parallel with other workers. The worker operates on a computer system to allow simultaneous task execution, as described below and illustrated in Figures 9-37. For example, in at least one embodiment, the worker can be implemented on the core of a graphics processing unit, such as... Figure 22D The GPU shown and described herein. In at least one embodiment, the techniques described herein can be used in computer systems (such as...) Figure 13-17D The techniques described herein are implemented on a computer system shown in the diagram and described in the related description. In at least one embodiment, the techniques described herein are implemented using executable instructions stored on a physical computer-readable storage medium, and the system implements the techniques described herein as a result of the execution of the executable instructions on one or more processors of the computer system.

[0094] Reasoning and training logic

[0095] Figure 9A Inference and / or training logic 915 is shown for performing inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 9A and / or Figure 9B Provide details about reasoning and / or training logic 915.

[0096] In at least one embodiment, inference and / or training logic 915 may include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters configuring neurons or layers of a neural network trained for and / or used for inference in one or more embodiments. In at least one embodiment, training logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 901 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0097] In at least one embodiment, any portion of the code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 901 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 901 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip or off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0098] In at least one embodiment, inference and / or training logic 915 may include, but is not limited to, code and / or data storage 905 to store backpropagation and / or output weights and / or input / output data neural networks corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, code and / or data storage 905 stores weight parameters and / or input / output data for each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, training logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, an arithmetic logic unit (ALU)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of the code and / or data storage 905 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice between the code and / or data storage 905 being internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0099] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially the same storage structure and partially different storage structures. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0100] In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 920, which are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, activation is activated in response to execution instructions or other code, linear algebraic and / or matrix-based mathematical generation performed by ALU 910, and the activation is stored in activation storage 920, wherein weight values ​​stored in code and / or data storage 905 and / or data 901 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, and any or all of these can be stored in code and / or data storage 905 or code and / or data storage 901 or other on-chip or off-chip storage.

[0101] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 910, while in another embodiment, one or more ALUs 910 may be located outside the processor or other hardware logic device or the circuitry using them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 910 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, data storage 901, code and / or data storage 905, and activation storage 920 may be on the same processor or other hardware logic device or circuitry, while in another embodiment, they may be on different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 920 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0102] In at least one embodiment, the active memory 920 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 920 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 920 is internal to or external to the processor may depend on the available on-chip or off-chip storage, the latency requirements for training and / or inference functions, the batch size of the data used in inference and / or training the neural network, or some combination of these factors. For example, it may include DRAM, SRAM, flash memory, or other memory types. In at least one embodiment, Figure 9A The inference and / or training logic 915 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9A The inference and / or training logic 915 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware (such as field programmable gate array (“FPGA”)).

[0103] Figure 9B An inference and / or training logic 915 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 915 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B The inference and / or training logic 915 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9BThe inference and / or training logic 915 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 9B In at least one embodiment shown, each of code and / or data storage 901 and code and / or data storage 905 is associated with dedicated computing resources (e.g., computing hardware 902 and computing hardware 906). In at least one embodiment, each of computing hardware 902 and computing hardware 906 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) only on the information stored in code and / or data storage 901 and code and / or data storage 905, respectively, and the results of the function execution are stored in activation storage 920.

[0104] In at least one embodiment, each of the code and / or data storage 901 and 905 and the corresponding computing hardware 902 and 906 corresponds to a different layer of the neural network, such that activation obtained from one “store / computation pair 901 / 902” of the code and / or data storage 901 and computing hardware 902 provides input as input to the next “store / computation pair 905 / 906” of the code and / or data storage 905 and computing hardware 906, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / computation pair 901 / 902 and 905 / 906 may correspond to more than one layer of the neural network. In at least one embodiment, additional store / computation pairs (not shown) may be included in the inference and / or training logic 915 after or in parallel with the store / computation pairs 901 / 902 and 905 / 906.

[0105] Neural network training and deployment

[0106] Figure 10 Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks.

[0107] In at least one embodiment, training framework 1004 trains an untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0108] In at least one embodiment, supervised learning is used to train an untrained neural network 1006, wherein the training dataset 1002 includes inputs paired with desired outputs for input, or wherein the training dataset 1002 includes inputs with known outputs and the neural network 1006 is a manually hierarchical output. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner, processing inputs from the training dataset 1002 and comparing the resulting outputs with a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through the untrained neural network 1006. In at least one embodiment, a training framework 1004 adjusts the weights controlling the untrained neural network 1006. In at least one embodiment, the training framework 1004 includes tools for monitoring the degree to which the untrained neural network 1006 converges to a model (e.g., a trained neural network 1008) adapted to generate the correct answer (e.g., result 1014) based on known input data (e.g., a new dataset 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to improve the output of the untrained neural network 1006 using a loss function and tuning algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches the desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0109] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1006, wherein the untrained neural network 1006 attempts to train itself using unlabeled data.

[0110] In at least one embodiment, the unsupervised learning training dataset 1002 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training dataset 1002 and can determine how each input relates to the untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph, which is a type of trained neural network 1008 capable of performing operations useful for reducing the dimensionality of the new dataset 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 1012 that deviate from the normal patterns of the new dataset 1012.

[0111] In at least one embodiment, semi-supervised learning can be used, a technique in which the training dataset 1002 includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to a new dataset 1012 without forgetting the knowledge injected into the network during initial training.

[0112] Data Center

[0113] Figure 11 An example data center 1100 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0114] In at least one embodiment, such as Figure 11 As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, packet computing resources 1114, and node computing resources (“nodes CR”) 1116(1)-1116(N), where “N” represents any whole positive integer. In at least one embodiment, nodes CR 1116(1)-1116(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1116(1)-1116(N) may be servers having one or more of the aforementioned computing resources.

[0115] In at least one embodiment, the grouped computing resource 1114 may include individual groups (not shown) of node CRs housed within one or more racks, or a plurality of racks (also not shown) housed within data centers in various geographical locations. The individual groups of node CRs within the grouped computing resource 1114 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0116] In at least one embodiment, resource coordinator 1112 may be configured or otherwise control one or more nodes CR1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may include a Software Design Infrastructure (“SDI”) management entity for data center 1100. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0117] In at least one embodiment, such as Figure 11 As shown, framework layer 1120 includes a job scheduler 1132, a configuration manager 1134, a resource manager 1136, and a distributed file system 1138. In at least one embodiment, framework layer 1120 may include a framework of software 1131 supporting software layer 1130 and / or one or more applications 1142 supporting application layer 1140. In at least one embodiment, software 1131 or application 1142 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 1138 for large-scale data processing (e.g., “big data”). TM(Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1132 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of data center 1100. In at least one embodiment, the configuration manager 1134 may be able to configure different layers, such as software layer 1130 and framework layer 1120 including Spark and a distributed file system 1138 for supporting large-scale data processing. In at least one embodiment, the resource manager 1136 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1138 and job scheduler 1132. In at least one embodiment, cluster or group computing resources may include group computing resources 1114 on data center infrastructure layer 1110. In at least one embodiment, the resource manager 1136 may coordinate with resource coordinator 1112 to manage these mapped or allocated computing resources.

[0118] In at least one embodiment, the software 1132 included in software layer 1130 may include software used by at least a portion of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0119] In at least one embodiment, one or more applications 1142 included in application layer 1140 may include one or more types of applications used by at least a portion of nodes CR1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1138 of framework layer 1120. One or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0120] In at least one embodiment, any of the configuration manager 1134, resource manager 1136, and resource coordinator 1112 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1100 and can prevent underutilization and / or poor performance of the data center.

[0121] In at least one embodiment, data center 1100 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1100, by using weight parameters calculated through one or more training techniques described herein.

[0122] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0123] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 11 The training logic 915 is used for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, the training logic 915 includes two or more processing cores for training portions of the neural network individually in parallel, as described herein.

[0124] Autonomous vehicles

[0125] Figure 12A An example of an autonomous vehicle 1200 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1200 (which may alternatively be referred to herein as "vehicle 1200") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1200 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1200 may be an aircraft, robotic vehicle, or other type of vehicle.

[0126] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their standard “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In one or more embodiments, vehicle 1200 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1200 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0127] In at least one embodiment, vehicle 1200 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1200 may include, but is not limited to, propulsion system 1250, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1250 may be connected to the drivetrain of vehicle 1200, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1200. In at least one embodiment, propulsion system 1250 may be controlled in response to receiving a signal from throttle / accelerator 1252.

[0128] In at least one embodiment, when the propulsion system 1250 is operating (e.g., when the vehicle 1200 is traveling), the steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, the steering system 1254 may receive signals from the steering actuator 1256. The steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 1246 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1248 and / or brake sensors.

[0129] In at least one embodiment, the controller 1236 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 12AA controller 1236 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1200. For example, in at least one embodiment, controller 1236 may send signals to operate vehicle braking via brake actuator 1248, to operate steering system 1254 via one or more steering actuators 1256, and to operate propulsion system 1250 via one or more throttles / accelerators 1252. One or more controllers 1236 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1200. In at least one embodiment, one or more controllers 1236 may include a first controller 1236 for autonomous driving functions, a second controller 1236 for functional safety functions, a third controller 1236 for artificial intelligence functions (e.g., computer vision), a fourth controller 1236 for infotainment functions, a fifth controller 1236 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1236 may handle two or more of the functions described above, and two or more controllers 1236 may handle a single function and / or any combination thereof.

[0130] In at least one embodiment, one or more controllers 1236 provide signals for controlling one or more components and / or systems of vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1258 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more inertial measurement unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), and remote cameras (…). Figure 12A (not shown in the image), medium-range camera ( Figure 12A(Not shown in the diagram) One or more speed sensors 1244 (e.g., for measuring the speed of vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more brake sensors (e.g., as part of brake sensor system 1246) and / or other sensor types are received.

[0131] In at least one embodiment, one or more controllers 1236 may receive input (e.g., represented by input data) from the dashboard 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1234, a voice signaler, a speaker, and / or other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 12A The HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving operation of the vehicle that has been, is being, or will be made (e.g., changing lanes now, exiting exit 34B within two miles, etc.). For example, in at least one embodiment, the HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about the driving operation of the vehicle that has been, is being, or will be made (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0132] In at least one embodiment, vehicle 1200 further includes a network interface 1224 that can communicate over one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, network interface 1224 may be able to communicate via Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”), etc. In at least one embodiment, one or more wireless antennas 1226 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc.).

[0133] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. In conjunction with this... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 12A The operation is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In at least one embodiment, the neural network used by the autonomous vehicle 1200 can be operated using inference performed by one or more neural networks, each neural network being trained by two or more processing kernels to train portions of the neural network separately in parallel, as described herein.

[0134] Figure 12B The illustration shows an embodiment according to at least one of the embodiments. Figure 12A Examples of camera positions and fields of view for an autonomous vehicle 1200. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1200.

[0135] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1200. One or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, may be used to improve photosensitivity.

[0136] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0137] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to cut out stray light and reflections from within the vehicle (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. For side-view cameras, in at least one embodiment, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0138] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1200 can be used for surround view and, with the assistance of one or more controllers 1236 and / or control SoCs, to help identify the forward path and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0139] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering from the periphery (e.g., pedestrians, crosswalkers, or bicycles). Although in Figure 12BOnly one wide-angle camera 1270 is shown; however, in other embodiments, the vehicle 1200 may have any number (including zero) of wide-angle cameras 1270. In at least one embodiment, any number of remote cameras 1298 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 1298 can also be used for object detection and classification, as well as basic object tracking.

[0140] In at least one embodiment, any number of stereo cameras 1268 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1268 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1200, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera samples (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1200 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 may also be used in addition to those described herein.

[0141] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 1200 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1274 (e.g., such as...) Figure 12B The four surround cameras 1274 shown can be positioned on the vehicle 1200. One or more surround cameras 1274 can include, but are not limited to, any number and combination of wide-angle cameras 1270, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, the four fisheye cameras can be located at the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0142] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 1200 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0143] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B This document provides details regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 can be... Figure 12B The system is used to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In at least one embodiment, the neural network used by the autonomous vehicle 1200 can be operated using inference performed by one or more neural networks, each neural network being trained by two or more processing kernels to train portions of the neural network separately in parallel, as described herein.

[0144] Figure 12C The illustration shows an embodiment according to at least one of the embodiments. Figure 12A A block diagram of an example system architecture for an autonomous vehicle 1200. In at least one embodiment, Figure 12C Each of one or more components, one or more features, and one or more systems of vehicle 1200 is shown as connected via bus 1202. In at least one embodiment, bus 1202 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network within vehicle 1200 used to help control various features and functions of vehicle 1200, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1202 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1202 can be read to find steering wheel angle, ground speed, engine rotation speed ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1202 may be an ASIL B compliant CAN bus.

[0145] In at least one embodiment, FlexRay and / or Ethernet may be selected from CAN in addition to CAN. In at least one embodiment, any number of buses 1202 may be used, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1202 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1202 may be used for a collision avoidance function, and a second bus 1202 may be used for actuation control. In at least one embodiment, each bus 1202 may communicate with any component of vehicle 1200, and two or more buses 1202 may communicate with the same component. In at least one embodiment, each of any number of system-on-chip (“SoC”) 1204, each of one or more controllers 1236, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 1200) and may be connected to a common bus, such as a CAN bus.

[0146] In at least one embodiment, vehicle 1200 may include one or more controllers 1236, such as those described herein. Figure 12A The controller 1236 can be used for a variety of functions. In at least one embodiment, the controller 1236 can be coupled to any of the various other components and systems of the vehicle 1200 and can be used to control the vehicle 1200, the artificial intelligence of the vehicle 1200, the infotainment and / or similar functions of the vehicle 1200.

[0147] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. Each of the SoCs 1204 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1206, a graphics processing unit (“one or more GPUs”) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data storage 1216, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1204 may be used to control vehicle 1200 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1204 may be combined with a high-definition (“HD”) map 1222 in a system (e.g., the system of vehicle 1200), the high-definition map 1222 being accessible from one or more servers via a network interface 1224. Figure 12C (Not shown in the image) Get map refresh and / or update.

[0148] In at least one embodiment, one or more CPUs 1206 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1206 can be active at any given time.

[0149] In at least one embodiment, one or more CPUs 1206 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when a core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; clock gating of each core cluster when all cores are clock-gated or power-gated; and / or power gating of each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0150] In at least one embodiment, one or more GPUs 1208 may include integrated GPUs (or "iGPUs" herein). In at least one embodiment, one or more GPUs 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more of the streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0151] In at least one embodiment, one or more GPUs 1208 may be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1208 may be fabricated on a FinFET (“FinFET”). In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0152] In at least one embodiment, one or more GPUs 1208 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as graphics double data rate type five synchronous random access memory (“GDDR5”).

[0153] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1208 to directly access the page tables of one or more CPUs 1206. In at least one embodiment, when one or more GPUs 1208 memory management units (“MMUs”) experience a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, one or more CPUs 1206 may look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for the memory of both one or more CPUs 1206 and one or more GPUs 1208, thereby simplifying the programming of one or more GPUs 1208 and the porting of applications to one or more GPUs 1208.

[0154] In at least one embodiment, one or more GPUs 1208 may include any number of access counters that can track the frequency of memory accesses by one or more GPUs 1208 to other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0155] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a Level 3 (“L3”) cache available for one or more CPUs 1206 and one or more GPUs 1208 (e.g., connected to both CPU 1206 and GPU 1208). In at least one embodiment, one or more caches 1212 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB or more.

[0156] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks from one or more GPUs 1208 (e.g., freeing up more cycles from one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0157] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). One or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphone 1296; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0158] In at least one embodiment, the DLA can perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, the designer can target one or more DLAs or one or more GPUs 1208 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1208 and / or one or more other accelerators 1214.

[0159] In at least one embodiment, one or more accelerators 1214 (e.g., hardware acceleration clusters) may include one or more programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. One or more PVAs may provide a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0160] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0161] In at least one embodiment, DMA enables one or more components of a PVA to access system memory independently of one or more CPUs 1206. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0162] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0163] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0164] In at least one embodiment, one or more accelerators 1214 (e.g., hardware acceleration clusters) may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM containing, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0165] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0166] In at least one embodiment, one or more SoCs 1204 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0167] In at least one embodiment, one or more accelerators 1214 (e.g., a cluster of hardware accelerators) have broad applications for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well-matched to algorithmic domains that require predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that require predictable runtimes with low latency and low power consumption. In at least one embodiment, for autonomous vehicles, such as vehicle 1200, the PVA is designed to run classical computer vision algorithms because they are efficient in object detection and integer mathematical operations.

[0168] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching during operation (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0169] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0170] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positives rather than false positives. For example, in at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1266 related to the vehicle 1200 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1264 or one or more RADAR sensors 1260).

[0171] In at least one embodiment, one or more SoCs 1204 may include one or more data storage devices 1216 (e.g., memory). In at least one embodiment, one or more data storage devices 1216 may be on-chip memory of one or more SoCs 1204, which may store neural networks to be executed on one or more GPUs 1208 and / or DLAs. In at least one embodiment, one or more data storage devices 1216 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 1212 may include L2 or L3 caches.

[0172] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). One or more processors 1210 may include a startup and power management processor, which may be a dedicated processor and subsystem to handle startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1204s and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1204s, and / or power state management of one or more SoCs 1204s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1204s may use the ring oscillator to detect the temperature of one or more CPUs 1206s, one or more GPUs 1208s, and / or one or more accelerators 1214s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1204s into a lower power state and / or place the vehicle 1200 into a driver's safe stopping pattern (e.g., bring the vehicle 1200 to a safe stop).

[0173] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0174] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, peripheral support (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0175] In at least one embodiment, one or more processors 1210 may further include a security cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the security cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In a secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0176] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1204, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0177] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0178] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1208 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0179] In at least one embodiment, one or more SoCs 1204 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs 1204 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0180] In at least one embodiment, one or more SoCs 1204 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. One or more SoCs 1204 may be used to process data from (e.g., via gigabit multimedia serial links and Ethernet connections) cameras, sensors (e.g., one or more LiDAR sensors 1264, one or more RADAR sensors 1260, etc., which may be connected via Ethernet), data from bus 1202 (e.g., vehicle 1200 speed, steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., via Ethernet or CAN bus connections), etc. In at least one embodiment, one or more SoCs 1204 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 1206 from routine data management tasks.

[0181] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data storage devices 1216, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0182] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (such as the C programming language) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0183] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1220) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0184] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: flashing lights indicate icy conditions" and a light can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executed on the CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1208.

[0185] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1200. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0186] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1262, to execute emergency vehicle safety routines, slow down the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0187] In at least one embodiment, vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1204 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1218 may include x86 processors. For example, one or more CPUs 1218 may be used to perform any of the various functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1204, and / or monitoring the status and health of one or more monitoring controllers 1236 and / or on-chip information systems (“information SoCs”) 1230.

[0188] In at least one embodiment, vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, one or more GPUs 1220 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1200 (e.g., sensor data).

[0189] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas 1226 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via the Internet using the cloud (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 1200 and other vehicles. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. The vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles near vehicle 1200 (e.g., vehicles in front, to the side, and / or behind vehicle 1200). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1200.

[0190] In at least one embodiment, network interface 1224 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, network interface 1224 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0191] In at least one embodiment, vehicle 1200 may further include one or more data storage units 1228, which may include, but are not limited to, off-chip (e.g., one or more SoC 1204) storage. In at least one embodiment, one or more data storage units 1228 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0192] In at least one embodiment, the vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0193] In at least one embodiment, vehicle 1200 may further include one or more RADAR sensors 1260. One or more RADAR sensors 1260 can be used by vehicle 1200 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. One or more RADAR sensors 1260 may use CAN and / or bus 1202 (e.g., to transmit data generated by one or more RADAR sensors 1260) for control and access to object tracking data, and in some examples, may access Ethernet to access raw data. In at least one embodiment, a wide variety of RADAR sensor types can be used. For example, but not limited to, one or more of the RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1260 are pulse Doppler RADAR sensors.

[0194] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1260 can help distinguish between stationary and moving objects and can be used by the ADAS system 1238 for emergency braking assistance and forward collision warning. One or more sensors 1260 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the surrounding environment of the vehicle 1200 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles entering or leaving the lane 1200.

[0195] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor blind spots behind and near the vehicle. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1238 for blind spot detection and / or lane change assistance.

[0196] In at least one embodiment, the vehicle 1200 may further include one or more ultrasonic sensors 1262. One or more ultrasonic sensors 1262, which may be positioned at the front, rear, and / or sides of the vehicle 1200, can be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1262 can be used, and different ultrasonic sensors 1262 can be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1262 can operate at the ASIL B functional safety level.

[0197] In at least one embodiment, vehicle 1200 may include one or more LiDAR sensors 1264. The one or more LiDAR sensors 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LiDAR sensors 1264 may be of functional safety level ASIL B. In at least one embodiment, vehicle 1200 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1264 that can use Ethernet (e.g., providing data to a Gigabit Ethernet switch).

[0198] In at least one embodiment, one or more LiDAR sensors 1264 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1264 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors 1264 may be used. In such embodiments, one or more LiDAR sensors 1264 may be implemented as small devices that can be embedded in the front, rear, side, and / or corner locations of a vehicle 1200. In at least one embodiment, one or more LiDAR sensors 1264, in such embodiments, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0199] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to a range from the vehicle 1200 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light in the form of a 3D ranging point cloud and co-registered intensity data.

[0200] In at least one embodiment, the vehicle may further include one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 may be located at the center of the rear axle of the vehicle 1200. In at least one embodiment, one or more IMU sensors 1266 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1266 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1266 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0201] In at least one embodiment, one or more IMU sensors 1266 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1266 may enable vehicle 1200 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 may be combined in a single integrated unit.

[0202] In at least one embodiment, vehicle 1200 may include one or more microphones 1296 placed inside and / or around vehicle 1200. In at least one embodiment, in addition, one or more microphones 1296 may be used for emergency vehicle detection and identification.

[0203] In at least one embodiment, vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide-angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long-range cameras 1298, one or more mid-range cameras 1276, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1200. In at least one embodiment, the type of camera used depends on vehicle 1200. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1200. In at least one embodiment, the number of cameras can vary depending on the embodiment. For example, in at least one embodiment, vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. The cameras may be examples, but are not limited to, supporting Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, previously referenced herein... Figure 12A and Figure 12B Each camera can be described in more detail.

[0204] In at least one embodiment, the vehicle 1200 may further include one or more vibration sensors 1242. The one or more vibration sensors 1242 can measure vibrations of components of the vehicle 1200 (e.g., axles). For example, in at least one embodiment, changes in vibration can indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1242 are used, differences between vibrations can be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a freely rotating axle).

[0205] In at least one embodiment, vehicle 1200 may include ADAS system 1238. ADAS system 1238 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 1238 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0206] In at least one embodiment, the ACC system may use one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to vehicles adjacent to vehicle 1200 and automatically adjusts the speed of vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1200 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0207] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1224 and / or one or more wireless antennas 1226 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, the V2V communication concept provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1200 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1200, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0208] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1260, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0209] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0210] In at least one embodiment, when vehicle 1200 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration components. The LKA system is a variant of the LDW system. If vehicle 1200 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1200.

[0211] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0212] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1200 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the applied vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0213] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1200 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first controller 1236 or the second controller 1236). For example, in at least one embodiment, ADAS system 1238 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 1238 may be provided to a monitoring MCU. In at least one embodiment, if the outputs of the primary computer and the auxiliary computer conflict, the monitoring MCU determines how to reconcile the conflict to ensure safe operation.

[0214] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0215] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from both the host computer and the auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the output of the auxiliary computer can be trusted and when it cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grat or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1204s.

[0216] In at least one embodiment, the ADAS system 1238 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0217] In at least one embodiment, the output of the ADAS system 1238 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0218] In at least one embodiment, vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system 1230 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation systems, rear parking assist, radio data systems, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to the vehicle. For example, the infotainment SoC 1230 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, automobile, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1234, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory) to users of the vehicle, such as information from ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0219] In at least one embodiment, the infotainment SoC 1230 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 may communicate with other devices, systems, and / or components of the vehicle 1200 via a bus 1202 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1230 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1236 (e.g., the main computer and / or backup computer of the vehicle 1200). In at least one embodiment, the infotainment SoC 1230 may cause the vehicle 1200 to enter a driver-to-safe-stop mode, as described herein.

[0220] In at least one embodiment, vehicle 1200 may further include instrument panel 1232 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). Instrument panel 1232 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1232 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1230 and instrument panel 1232. In at least one embodiment, instrument panel 1232 may be included as part of infotainment SoC 1230, or vice versa.

[0221] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be in the system. Figure 12C The operation is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In at least one embodiment, the neural network used by the autonomous vehicle 1200 can be operated using inference performed by one or more neural networks, each neural network being trained by two or more processing kernels to train portions of the neural network separately in parallel, as described herein.

[0222] Figure 12D It is based on at least one embodiment in a cloud-based server and Figure 12AA diagram of a system 1276 for communication between autonomous vehicles 1200. In at least one embodiment, system 1276 may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. One or more servers 1278 may include, but is not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPU 1284), PCIe switches 1282(A)-1282(H) (collectively referred to herein as PCIe switch 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPU 1280). GPU 1284, CPU 1280, and PCIe switch 1282 may be interconnected with high-speed interconnects, such as, but not limited to, NVLink interface 1288 developed by NVIDIA and / or PCIe connection 1286. In at least one embodiment, the GPU 1284 is connected via NVLink and / or NVSwitchSoC, and the GPU 1284 and PCIe switch 1282 are connected via PCIe interconnect. In at least one embodiment, although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1278 may include, but is not limited to, any combination of any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0223] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290, the image showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 1278 may transmit a neural network 1292, an updated neural network 1292, and / or map information 1294, including but not limited to information about traffic and road conditions, to the vehicle via one or more networks 1290. In at least one embodiment, updating the map information 1294 may include, but is not limited to, updating the HD map 1222, for example, information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, the neural network 1292, the updated neural network 1292, and / or map information 1294 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1278 and / or other servers).

[0224] In at least one embodiment, one or more servers 1278 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. The training data may be generated by the vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1290), and / or the machine learning model may be used by one or more servers 1278 to remotely monitor the vehicle.

[0225] In at least one embodiment, one or more servers 1278 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1278 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 may include a deep learning infrastructure in a data center using CPU power.

[0226] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of fast, real-time inference and can use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as image sequences and / or objects located by vehicle 1200 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1200, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1200 is malfunctioning, one or more servers 1278 may signal to vehicle 1200 to instruct the fail-safe computer of vehicle 1200 to take control, notify passengers, and complete a safe stopping operation.

[0227] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 915 is used to execute one or more embodiments. This document incorporates... Figure 9A and / or Figure 9B Provide details about the 915 hardware architecture.

[0228] Computer System

[0229] Figure 13 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof formed with a processor 1300, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, the computer system 1300 may include, but is not limited to, components such as processor 1302, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, the computer system 1300 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Cor TM or Nervan TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1300 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0230] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0231] In at least one embodiment, the computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the system 1300 is a single-processor desktop or server system, but in another embodiment, the system 1300 may be a multiprocessor system. In at least one embodiment, the processor 1302 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1302 may be coupled to a processor bus 1310, which may transmit data signals between the processor 1302 and other components in the computer system 1300.

[0232] In at least one embodiment, processor 1302 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1302. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1306 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0233] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1302. The processor 1302 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packaged instruction set 1309. In at least one embodiment, by including the packaged instruction set 1309 in the instruction set of the general-purpose processor 1302, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 1302 can be used to perform operations used by many multimedia applications. In one or more embodiments, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor's data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0234] In at least one embodiment, execution unit 1308 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. Memory 1320 may store instructions 1319 and / or data 1321 represented by data signals that can be executed by processor 1302.

[0235] In at least one embodiment, the system logic chip may be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may initiate data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1316 may be coupled to memory 1320 via high-bandwidth memory path 1318, and graphics / video card 1312 may be coupled to MCH 1316 via Accelerated Graphics Port (“AGP”) interconnect 1314.

[0236] In at least one embodiment, computer system 1300 may use system I / O 1322, which is a proprietary hub interface bus, to couple MCH 1316 to I / O controller hub (“ICH”) 1330. In at least one embodiment, ICH 1330 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, audio controller 1329, firmware hub (“FlashBIOS”) 1328, wireless transceiver 1326, data storage 1324, a conventional I / O controller 1323 including user input and keyboard interfaces, serial expansion port 1327 (e.g., Universal Serial Bus (USB)), and network controller 1334. Data storage 1324 may include hard disk drives, floppy disk drives, CD-ROM devices, flash memory devices, or other mass storage devices.

[0237] In at least one embodiment, Figure 13 One embodiment is shown that includes interconnected hardware devices or "chips," while in other embodiments, Figure 13 An exemplary system-on-a-chip (SoC) can be illustrated. In at least one embodiment, Figure 13The devices shown can be interconnected with dedicated interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1300 are interconnected using a Fast Compute Link (CXL) interconnect.

[0238] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A 9B provides details regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can be used in the system. Figure 13 In this context, the operation is used to infer or predict based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network usage as described herein. In at least one embodiment, the neural network used by the electronic device 1200 can be operated using inference performed by one or more neural networks, each neural network being trained by two or more processing kernels to train portions of the neural network separately in parallel, as described herein.

[0239] Figure 14 This is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410 according to at least one embodiment. In at least one embodiment, the electronic device 1400 may be, for example, but not limited to, a laptop, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0240] In at least one embodiment, system 1400 may include, but is not limited to, processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1410 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Attachment (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 14 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 14 An exemplary system-on-a-chip (SoC) can be illustrated. In at least one embodiment, Figure 14 The devices shown can be interconnected with dedicated interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, a compute fast link (CXL) interconnect is used for interconnection. Figure 14One or more components.

[0241] In at least one embodiment, Figure 14 It may include a display 1424, a touch screen 1425, a touchpad 1430, a near field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, a fast chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, a BIOS / firmware / flash (“BIOS, FW flash”) 1422, a DSP 1460, a drive (“SSD or HDD”) 1420 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0242] In at least one embodiment, other components may be communicatively coupled to processor 1410 via the components discussed above. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1446, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1464, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1464 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as WLAN unit 1450, Bluetooth unit 1452, and WWAN unit 1456 can be implemented in a next-generation form factor (“NGFF”).

[0243] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A 9B provides details regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be... Figure 14 The system is used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture or neural network usage as described herein. In at least one embodiment, the neural network used by the computer system 1500 can be operated using inference performed by one or more neural networks, each neural network being trained by two or more processing kernels to train portions of the neural network separately in parallel, as described herein.

[0244] Figure 15 A computer system 1500 according to at least one embodiment is shown. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0245] In at least one embodiment, the computer system 1500 includes, but is not limited to, at least one central processing unit (“CPU”) 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Fast Peripheral Component Interconnect (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1500 includes, but is not limited to, main memory 1504 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in main memory 1504, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks for receiving data from other systems of system 1500 and transmitting data to other systems having computer system 1500.

[0246] In at least one embodiment, the computer system 1500 includes, but is not limited to, an input device 1508, a parallel processing system 1512, and a display device 1506 that can be implemented using conventional cathode ray tubes (“CRTs”), liquid crystal displays (“LCDs”), light-emitting diodes (“LEDs”), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1508, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0247] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A9B provides details regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 can be used in the system. Figure 15 In this context, the operation is used to infer or predict based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network usage as described herein. In at least one embodiment, the neural network used by the computer system 1600 can be operated using inference performed by one or more neural networks, each neural network being trained by two or more processing kernels to train portions of the neural network separately in parallel, as described herein.

[0248] Figure 16 A computer system 1600 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1600 includes, but is not limited to, a computer 1610 and a USB stick 1620. In at least one embodiment, the computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1610 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0249] In at least one embodiment, the USB stick 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing core 1630 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1630 includes an application-specific integrated circuit (“ASIC”) optimized to perform any amount and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1630 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1630 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0250] In at least one embodiment, the USB interface 1640 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1640 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1650 may include any amount and type of logic that enables the processing unit 1630 to engage with a device (e.g., computer 1610) via the USB connector 1640.

[0251] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 can be used to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network usage as described herein. In at least one embodiment, as Figure 17A The architecture shown can be used to implement parallel operations to train the neural network as described above.

[0252] Figure 17A An exemplary architecture is illustrated, in which multiple GPUs 1710-1713 are communicatively coupled to multiple multi-core processors 1705-1706 via high-speed links 1740-1743 (e.g., bus / point-to-point interconnect, etc.). In one embodiment, the high-speed links 1740-1743 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0253] Furthermore, in one embodiment, two or more GPUs 1710-1713 are interconnected via high-speed links 1729-1730, which may use the same or different protocols / links as those used for high-speed links 1740-1743. Similarly, two or more multi-core processors 1705-1706 may be connected via high-speed link 1728, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, the same protocol / link (e.g., via a common interconnect structure) may be used. Figure 17A This shows all communication between the various system components.

[0254] In one embodiment, each multi-core processor 1705-1706 is communicatively coupled to processor memories 1701-1702 via memory interconnects 1726-1727, and each GPU 1710-1713 is communicatively coupled to GPU memories 1720-1723 via GPU memory interconnects 1750-1753. Memory interconnects 1726-1727 and 1750-1753 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 1701-1702 and GPU memories 1720-1723 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, some portions of the processor memories 1701-1702 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0255] As described in this article, although the various processors 1705-1706 and GPUs 1710-1713 can be physically coupled to specific memories 1701-1702 and 1720-1723 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across the various physical memories. For example, processor memories 1701-1702 can each contain 64GB of system memory address space, and GPU memories 1720-1723 can each contain 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0256] Figure 17B Additional details are shown regarding the interconnection between a multi-core processor 1707 and a graphics acceleration module 1746 according to an exemplary embodiment. The graphics acceleration module 1746 may include one or more GPU chips integrated on a line card coupled to the processor 1707 via a high-speed link 1740. Alternatively, the graphics acceleration module 1746 may be integrated on the same package or chip as the processor 1707.

[0257] In at least one embodiment, the illustrated processor 1707 includes multiple cores 1760A-1760D, each core having a translation back buffer 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, cores 1760A-1760D may include various other components (not shown) for executing instructions and processing data. Caches 1762A-1762D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 1756 may be included in caches 1762A-1762D and shared by the respective groups of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. Processor 1707 and graphics acceleration module 1746 are connected to system memory 1714, which may include Figure 17A The processor memory 1701-1702 in the memory.

[0258] The consistency bus 1764 maintains consistency for data and instructions stored in the various caches 1762A-1762D, 1756 and system memory 1714 via inter-core communication. For example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1764 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is executed via the consistency bus 1764 to snoop on cache accesses.

[0259] In one embodiment, proxy circuitry 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, thereby allowing graphics acceleration module 1746 to participate in cache coherence protocols as a peer of cores 1760A-1760D. Specifically, interface 1735 provides connectivity to proxy circuitry 1725 via high-speed link 1740 (e.g., PCIe bus, NVLink, etc.), and interface 1737 connects graphics acceleration module 1746 to link 1740.

[0260] In one implementation, the accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 1731, 1732, and N of the graphics acceleration module. The graphics processing engines 1731, 1732, and N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1731, 1732, and N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731-1732, and N, or the graphics processing engines 1731-1732, and N may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0261] In one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1714. The MMU 1739 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1738 stores commands and data for effective access by graphics processing engines 1731-1732,N. In one embodiment, data stored in cache 1738 and graphics memories 1733-1734,M is kept consistent with core caches 1762A-1762D,1756 and system memory 1714. As previously mentioned, this task can be accomplished via proxy circuitry 1725 representing cache 1738 and graphics memory 1733-1734, M (e.g., sending updates related to modifications / accesses to cache lines on processor caches 1762A-1762D, 1756 to cache 1738 and receiving updates from cache 1738).

[0262] A set of registers 1745 stores the context data of the threads executed by graphics processing engines 1731-1732, N, and context management circuitry 1748 manages the thread context. For example, context management circuitry 1748 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1748 can store the current register value to a designated area in memory (e.g., identified by a context pointer). The register value can then be restored when returning to the context. In one embodiment, interrupt management circuitry 1747 receives and processes interrupts received from system devices.

[0263] In one implementation, MMU 1739 translates virtual / effective addresses from graphics processing engine 1731 into real / physical addresses in system memory 1714. One embodiment of accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. Graphics accelerator module 1746 may be dedicated to a single application executing on processor 1707, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of graphics processing engines 1731-1732, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0264] In at least one embodiment, the accelerator integrated circuit 1736 acts as a system bridge for the graphics acceleration module 1746 and provides address translation and system memory caching services. Additionally, the accelerator integrated circuit 1736 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1731-1732.

[0265] Because of the graphics processing engines 1731-1732, N's hardware resources are explicitly mapped to the real address space seen by the host processor 1707, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1736 is to physically separate the graphics processing engines 1731-1732, N, so that they appear as independent units to the system.

[0266] In at least one embodiment, one or more graphics memories 1733-1734, M are coupled to each graphics processing engine 1731-1732, N. The graphics memories 1733-1734, M store instructions and data processed by each graphics processing engine 1731-1732, N. The graphics memories 1733-1734, M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-RAM.

[0267] In one embodiment, to reduce data traffic on link 1740, a biasing technique is used to ensure that the data stored in graphics memories 1733-1734, M is the data most frequently used by graphics processing engines 1731-1732, N, and preferably not used (or at least infrequently used) by cores 1760A-1760D. Similarly, the biasing mechanism attempts to keep the data needed by the cores (and preferably not graphics processing engines 1731-1732, N) in the core caches 1762A-1762D, 1756 and system memory 1714.

[0268] Figure 17C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1736 is integrated within the processor 1707. In this embodiment, graphics processing engines 1731-1732,N communicate directly with the accelerator integrated circuit 1736 via a high-speed link 1740 through interfaces 1737 and 1735 (which can also utilize any form of bus or interface protocol). The accelerator integrated circuit 1736 can perform operations related to... Figure 17B The operations described are the same. However, due to its close proximity to the coherence bus 1764 and caches 1762A-1762D, 1756, it may have higher throughput. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by accelerator integrated circuit 1736 and a programming model controlled by graphics acceleration module 1746.

[0269] In at least one embodiment, graphics processing engines 1731-1732,N are dedicated to a single application or process within a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1731-1732,N, thereby providing virtualization within a VM / partition.

[0270] In at least one embodiment, graphics processing engines 1731-1732, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1731-1732, N to allow each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1731-1732, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1731-1732, N to provide access to each process or application.

[0271] In at least one embodiment, the graphics acceleration module 1746 or the individual graphics processing engines 1731-1732, N uses a process handle to select a process element. In one embodiment, the process element is stored in system memory 1714 and can be addressed using the effective address to physical address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 1731-1732, N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0272] Figure 17D An exemplary accelerator integration slice 1790 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1736. The application is an effective address space 1782 in system memory 1714 that stores process element 1783. In one embodiment, process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on processor 1707. Process element 1783 contains the process state of the corresponding application 1780. A job descriptor (WD) 1784 contained in process element 1783 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1784 is a pointer to a job request queue in the application’s address space 1782.

[0273] The graphics acceleration module 1746 and / or the various graphics processing engines 1731-1732, N, can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1784 to the graphics acceleration module 1746 to begin operations in a virtualized environment.

[0274] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 1746 or an individual graphics processing engine 1731. Since the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0275] In operation, the WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1746. Data from the WD 1784 can be stored in register 1745 and used by the MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page roaming circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. The interrupt management circuitry 1747 can handle interrupt events 1792 received from the graphics acceleration module 1746. When performing graphics operations, the effective address 1793 generated by the graphics processing engines 1731-1732,N is translated into a real address by the MMU 1739.

[0276] In one embodiment, the same set of registers 1745 is copied for each graphics processing engine 1731-1732,N and / or graphics acceleration module 1746, and these registers 1745 can be initialized by a hypervisor or the operating system. Each of these copied registers can be included in the accelerator integration slice 1790. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0277] Table 1 – Registers for Supervisor Initialization

[0278]

[0279]

[0280] Table 2 shows exemplary registers that can be initialized by the operating system.

[0281] Table 2 – Operating System Initialization Registers

[0282] 1 Process and thread identifiers 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) accelerator utilization record pointer 4 Virtual address (VA) memory segment table pointer 5 Access Control 6 Job descriptor

[0283] In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731-1732,N. It contains all the information required for the graphics processing engine 1731-1732,N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0284] Figure 17E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1798, in which a list of process elements 1799 is stored. The hypervisor real address space 1798 can be accessed via a hypervisor 1796, which virtualizes the graphics acceleration module engine for operating system 1795.

[0285] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. Two programming models exist, in which the graphics acceleration module 1746 is shared by multiple processes and partitions: time-slice sharing and graphics-oriented sharing.

[0286] In this model, the hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. For the graphics acceleration module 1746 to support virtualization through the hypervisor 1796, the graphics acceleration module 1746 can comply with the following conditions: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 1746 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 1746 guarantees that application job requests are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1746 provides the ability to preempt job processing. 3) When operating in a directed shared programming model, fairness among the processes of the graphics acceleration module 1746 must be ensured.

[0287] In at least one embodiment, application 1780 needs to make an operating system 1795 system call using the graphics acceleration module 1746 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1746 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1746 type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 1746. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. If the implementation of the accelerator integrated circuit 1736 and the graphics acceleration module 1746 does not support the User Authority Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 1796 may selectively apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 1783. In at least one embodiment, CSRP is one of registers 1745 containing the effective address of a region in the application's address space 1782 for the graphics acceleration module 1746 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0288] Upon receiving a system call, operating system 1795 can verify that application 1780 has been registered and granted permission to use graphics acceleration module 1746. Then, operating system 1795 uses the information shown in Table 3 to invoke hypervisor 1796.

[0289] Table 3 – Operating System to Hypervisor Call Parameters

[0290] 1 Working Descriptor (WD) 2 Access Control Register (AMR) value (may be masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Log Pointer (AURP) 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0291] Upon receiving a hypervisor call, hypervisor 1796 verifies that operating system 1795 has been registered and granted permission to use graphics acceleration module 1746. Then, hypervisor 1796 adds process element 1783 to the linked list of process elements of the corresponding graphics acceleration module 1746 type. The process element may include the information shown in Table 4.

[0292] Table 4 – Process Element Information

[0293] 1 Working Descriptor (WD) 2 Access Control Register (AMR) value (may be masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Log Pointer (AURP) 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table derived from parameters called by the management program 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0294] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1790 registers 1745.

[0295] like Figure 17F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1701-1702 and GPU memories 1720-1723. In this implementation, operations performed on GPUs 1710-1713 utilize the same virtual / effective memory address space to access processor memories 1701-1702, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701, a second portion to second processor memory 1702, a third portion to GPU memory 1720, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1701-1702 and GPU memories 1720-1723, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0296] In one embodiment, the bias / coherence management circuitry 1794A-1794E within one or more MMUs 1739A-1739E ensures cache coherence between the caches of one or more host processors (e.g., 1705) and the GPUs 1710-1713, and implements biasing techniques that indicate the physical memory in which certain types of data should be stored. While in Figure 17F Several instances of the bias / coherence management circuitry 1794A-1794E are shown, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 1705 and / or within the accelerator integrated circuit 1736.

[0297] One embodiment allows GPU-attached memory 1720-1723 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memory 1720-1723 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows host processor 1705 software to set operands and access computation results without the overhead of conventional I / O DMA data copying. Such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memory 1720-1723 without cache coherence overhead can be critical for the execution time of offloaded computations. For example, in cases with high streaming write traffic to memory, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1710-1713. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0298] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure (i.e., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPUs 1710-1713, the bias table can be implemented across one or more stolen memory ranges of GPU-attached memory 1720-1723. Alternatively, the entire bias table can be maintained within the GPU.

[0299] In at least one embodiment, prior to actual access to GPU memory, the bias table entry associated with each access to GPU-attached memory 1720-1723 is accessed, causing the following operations: First, a local request from GPUs 1710-1713 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 1720-1723. A local request from the GPU to find its page in the host bias is forwarded to processor 1705 (e.g., via the high-speed link discussed above). In one embodiment, a request from processor 1705 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests to GPU bias pages can be forwarded to GPUs 1710-1713. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, in limited cases, purely hardware-based mechanisms.

[0300] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that subsequently invokes the GPU's device driver, which then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migrations, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrations from the host processor 1705 bias to the GPU bias, but not for the reverse migration.

[0301] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1705 cannot cache. To access these pages, the processor 1705 may request access from the GPU 1710, which may or may not grant access immediately. Therefore, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial to ensure that the GPU bias pages are those required by the GPU, not those required by the host processor 1705, and vice versa.

[0302] One or more hardware structures 915 are used to implement one or more embodiments. In conjunction with this document... Figure 9A and / or Figure 9B Provide details about one or more of the said hardware structures 915.

[0303] Figure 18Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0304] Figure 18 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that may be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1800 includes peripheral or bus logic including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and a sup.2S / I.sup.2C controller 1840. In at least one embodiment, the integrated circuit 1800 may include a display device 1845 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industrial Processor Interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0305] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in integrated circuit 1800 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In at least one embodiment, as Figure 19A and Figure 19B The architecture shown can be used to implement parallel operations to train the neural network as described above.

[0306] Figure 19A and Figure 19BExemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0307] Figure 19A and Figure 19B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 19A An exemplary graphics processor 1910 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 19B An additional exemplary graphics processor 1940 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 19A The graphics processor 1910 is a low-power graphics processor core. In at least one embodiment, Figure 19B The graphics processor 1940 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1910, 1940 may be... Figure 18 A variant of the 1810 graphics processor.

[0308] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N-1 and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, such that the vertex processor 1905 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1905 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1915A-1915N use the primitive and vertex data generated by the vertex processor 1905 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1915A-1915N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0309] In at least one embodiment, the graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A-1920B, one or more caches 1925A-1925B, and one or more circuit interconnects 1930A-1930B. In at least one embodiment, one or more MMUs 1920A-1920B provide a virtual-to-physical address mapping for the graphics processor 1910, including for the vertex processor 1905 and / or fragment processors 1915A-1915N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B can be synchronized with other MMUs within the system, including with... Figure 18 One or more application processors 1805, graphics processors 1815, and / or video processors 1820 are associated with one or more MMUs, enabling each processor 1805-1820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable the graphics processor 1910 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0310] In at least one embodiment, the graphics processor 1940 includes one or more MMUs 1920A-1920B, caches 1925A-1925B, and... Figure 19A The graphics processor 1910 has circuit interconnects 1930A-1930B. In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N-1 and 1955N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1955A-1955N and a tile unit 1958 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0311] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 may be integrated into an integrated circuit. Figure 19A and / or Figure 19B This is used for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions or architectures, or the neural network use cases described herein. In at least one embodiment, such as Figures 20A-20B The graphics processor logic shown can be used to implement parallel operations to train the neural network as described above.

[0312] Figure 20A and Figure 20B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 20A It shows that it can be included in Figure 18 The graphics core 2000 within the graphics processor 1810, and in at least one embodiment, may be as follows: Figure 19B The Unified Shader Cores 1955A-1955N are shown. Figure 20B A highly parallel general-purpose graphics processing unit 2030 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0313] In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and cache / shared memory 2020, which are common to the execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A-2001N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2000. Slices 2001A-2001N may include supporting logic, including local instruction caches 2004A-2004N, thread schedulers 2006A-2006N, thread dispatchers 2008A-2008N, and a set of registers 2010A-2010N. In at least one embodiment, slices 2001A-2001N may include a set of additional functional units (AFU2012A-2012N), floating-point units (FPU 2014A-2014N), integer arithmetic logic units (ALU 2016A-2016N), address calculation units (ACU 2013A-2013N), double-precision floating-point units (DPFPU 2015A-2015N), and matrix processing units (MPU2017A-2017N).

[0314] In at least one embodiment, the FPU 2014A-2014N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2015A-2015N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2016A-2016N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2017A-2017N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2017A-2017N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2012A-2012N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0315] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is combined with... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in the graphics core 2000 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein. In at least one embodiment, as Figures 20A-20B The graphics processor logic shown can be used to implement parallel operations to train the neural network as described above.

[0316] Figure 20BA general-purpose processing unit (GPGPU) 2030 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 2030 can be directly linked to other instances of the GPGPU 2030 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 for connection to a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 to allocate execution threads associated with those commands to a set of compute clusters 2036A-2036H. In at least one embodiment, compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, cache memory 2038 can be used as a higher-level cache than cache memory within computing clusters 2036A-2036H.

[0317] In at least one embodiment, the GPGPU 2030 includes memories 2044A-2044B, which are coupled to computing clusters 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, memories 2044A-2044B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0318] In at least one embodiment, each of the computing clusters 2036A-2036H includes a set of graphics cores, for example... Figure 20A The graphics core 2000 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2036A-2036H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0319] In at least one embodiment, multiple instances of the GPGPU 2030 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by the computing clusters 2036A-2036H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 2030 communicate via a host interface 2032. In at least one embodiment, the GPGPU 2030 includes an I / O hub 2039 that couples the GPGPU 2030 to a GPU link 2040, enabling direct connection to other instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between the multiple instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 2030 reside in a separate data processing system and communicate via network devices accessible through the host interface 2032. In at least one embodiment, GPU link 2040 may be configured to enable connection to a host processor other than or alternative to host interface 2032.

[0320] In at least one embodiment, the GPGPU 2030 can be configured to train a neural network. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment, when using the GPGPU 2030 for inference, the GPGPU may include fewer compute clusters 2036A-2036H compared to when training a neural network. In at least one embodiment, the memory technology associated with memories 2044A-2044B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of the deployed neural network.

[0321] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9BDetails are provided regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in the GPGPU 2030 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein. In at least one embodiment, as Figure 21 The computing system 2100 shown can be used to implement parallel operations for workers training neural networks as described above.

[0322] Figure 21 A block diagram of a computer system 2100 according to at least one embodiment is shown. In at least one embodiment, the computer system 2100 includes a processing subsystem 2101 having one or more processors 2102 and a system memory 2104 communicating via an interconnect path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset assembly or may be integrated within one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that enables the computer system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 enables a display controller to provide output to one or more display devices 2110A, the display controller being included in one or more processors 2102. In at least one embodiment, one or more display devices 2110A coupled to the I / O hub 2107 may include local, internal, or embedded display devices.

[0323] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to the memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 can be any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 2112 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 2112 form a graphics processing subsystem that can output pixels to one or more display devices 2110A coupled via an I / O hub 2107. In at least one embodiment, the one or more parallel processors 2112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2110B.

[0324] In at least one embodiment, system storage unit 2114 may be connected to I / O hub 2107 to provide a storage mechanism for computer system 2100. In at least one embodiment, I / O switch 2116 may be used to provide an interface mechanism to enable connectivity between I / O hub 2107 and other components, such as network adapter 2118 and / or wireless network adapter 2119 which may be integrated into the platform, and various other devices that can be added via one or more additional devices 2120. In at least one embodiment, network adapter 2118 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2119 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0325] In at least one embodiment, the computer system 2100 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2107. In at least one embodiment, the interconnection can be implemented using any suitable protocol (e.g., PCI-based protocols such as PCI-Express or other bus or point-to-point communication interfaces and / or protocols). Figure 21 The communication paths of various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0326] In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2112 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2112, memory hub 2105, processor 2102, and I / O hub 2107 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 2100 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2100 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0327] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding the inference and / or training logic 915 are provided. In at least one embodiment, the inference and / or training logic 915 can be... Figure 21 The system 2100 is used for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein. In at least one embodiment, such as Figure 22A The parallel processor shown can be used to implement parallel operations to train the neural network as described above.

[0328] processor

[0329] Figure 22A A parallel processor 2200 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2200 is according to an exemplary embodiment. Figure 21 The variant of the parallel processor 2112 shown.

[0330] In at least one embodiment, the parallel processor 2200 includes a parallel processing unit 2202. In at least one embodiment, the parallel processing unit 2202 includes an I / O unit 2204 that enables communication with other devices, including other instances of the parallel processing unit 2202. In at least one embodiment, the I / O unit 2204 can be directly connected to other devices. In at least one embodiment, the I / O unit 2204 is connected to other devices using a hub or switch interface (e.g., a memory hub 2105). In at least one embodiment, the connection between the memory hub 2105 and the I / O unit 2204 forms a communication link 2113. In at least one embodiment, the I / O unit 2204 is connected to a host interface 2206 and a memory crossbar switch 2216, wherein the host interface 2206 receives commands for performing processing operations, and the memory crossbar switch 2216 receives commands for performing memory operations.

[0331] In at least one embodiment, when host interface 2206 receives a command buffer via I / O unit 2204, host interface 2206 can direct work operations to execute those commands to front end 2208. In at least one embodiment, front end 2208 is coupled to scheduler 2210, which is configured to assign commands or other work items to processing cluster array 2212. In at least one embodiment, scheduler 2210 ensures that processing cluster array 2212 is correctly configured and in an active state before assigning tasks to processing cluster array 2212. In at least one embodiment, scheduler 2210 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2212. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2212 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2212 by the scheduler 2210 logic within the microcontroller, which includes the scheduler 2210.

[0332] In at least one embodiment, the processing cluster array 2212 may include up to "N" processing clusters (e.g., clusters 2214A, 2214B to 2214N). In at least one embodiment, each cluster 2214A-2214N of the processing cluster array 2212 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2210 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2214A-2214N of the processing cluster array 2212, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2210, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2212. In at least one embodiment, different clusters 2214A-2214N of the processing cluster array 2212 may be assigned to process different types of programs or to perform different types of computations.

[0333] In at least one embodiment, the processing cluster array 2212 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2212 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0334] In at least one embodiment, the processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2202 may transfer data from system memory via I / O unit 2204 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) and then written back to system memory.

[0335] In at least one embodiment, when the parallel processing unit 2202 is used to perform graphics processing, the scheduler 2210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2214A-2214N of the processing cluster array 2212. In at least one embodiment, portions of the processing cluster array 2212 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2214A-2214N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2214A-2214N for further processing.

[0336] In at least one embodiment, the processing cluster array 2212 may receive processing tasks to be executed via a scheduler 2210, which receives commands defining the processing tasks from a front end 2208. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2210 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2208. In at least one embodiment, the front end 2208 may be configured to ensure that the processing cluster array 2212 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0337] In at least one embodiment, each of one or more instances of the parallel processing unit 2202 may be coupled to the parallel processor memory 2222. In at least one embodiment, the parallel processor memory 2222 may be accessed via a memory crossbar switch 2216, which may receive memory requests from the processing cluster array 2212 and the I / O unit 2204. In at least one embodiment, the memory crossbar switch 2216 may be accessed via a memory interface 2218. In at least one embodiment, the memory interface 2218 may include a plurality of partition units (e.g., partition units 2220A, 2220B to 2220N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2222. In at least one embodiment, the plurality of partition units 2220A-2220N are configured to be equal to the number of memory units, such that the first partition unit 2220A has a corresponding first memory unit 2224A, the second partition unit 2220B has a corresponding memory unit 2224B, and the Nth partition unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partition units 2220A-2220N may not be equal to the number of memory devices.

[0338] In at least one embodiment, memory cells 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2224A-2224N, allowing partitioning cells 2220A-2220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2222. In at least one embodiment, local instances of the parallel processor memory 2222 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0339] In at least one embodiment, any of clusters 2214A-2214N of the processing cluster array 2212 can process data to be written to any memory cell 2224A-2224N within the parallel processor memory 2222. In at least one embodiment, the memory crossbar switch 2216 can be configured to transfer the output of each cluster 2214A-2214N to any partition cell 2220A-2220N or another cluster 2214A-2214N, and clusters 2214A-2214N can perform further processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with the memory interface 2218 via the memory crossbar switch 2216 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2216 has a connection to the memory interface 2218 for communication with the I / O unit 2204, and a connection to a local instance of the parallel processor memory 2222, thereby enabling processing units within different processing clusters 2214A-2214N to communicate with system memory or other memory not local to the parallel processing unit 2202. In at least one embodiment, the memory crossbar switch 2216 may use virtual channels to separate traffic flows between clusters 2214A-2214N and partition units 2220A-2220N.

[0340] In at least one embodiment, multiple instances of the parallel processing unit 2202 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2202 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2202 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2202 or the parallel processor 2200 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0341] Figure 22B This is a block diagram of partitioning unit 2220 according to at least one embodiment. In at least one embodiment, partitioning unit 2220 is... Figure 22AThis is an example of one of the partitioning units 2220A-2220N. In at least one embodiment, the partitioning unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and a ROP 2226 (raster operation unit). The L2 cache 2221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2216 and the ROP 2226. In at least one embodiment, the L2 cache 2221 outputs read misses and urgent write-back requests to the frame buffer interface 2225 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2225. In at least one embodiment, the frame buffer interface 2225 communicates with memory cells in the parallel processor memory (such as...). Figure 22A The memory cells 2224A-2224N (e.g., within the parallel processor memory 2222) interact with one of them.

[0342] In at least one embodiment, ROP 2226 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2226 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2226 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. The compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. The type of compression performed by ROP 2226 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0343] In at least one embodiment, ROP 2226 is included within each processing cluster (e.g., clusters 2214A-2214N of FIG. 22), rather than within partition unit 2220. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2216 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 21 Displayed by one or more display devices 2110, routed by processor 2102 for further processing, or by... Figure 22A One of the processing entities within the parallel processor 2200 is routed for further processing.

[0344] Figure 22CThis is a block diagram of a processing cluster 2214 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an example of one of the processing clusters 2214A-2214N of FIG. 22. In at least one embodiment, the processing cluster 2214 may be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0345] In at least one embodiment, the operation of the processing cluster 2214 can be controlled by a pipeline manager 2232 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2232 receives instructions from the scheduler 2210 of FIG. 22 and manages the execution of these instructions via the graphics multiprocessor 2234 and / or texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2214 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2214 may include one or more instances of the graphics multiprocessor 2234. In at least one embodiment, the graphics multiprocessor 2234 can process data, and the data crossover switch 2240 can be used to distribute the processed data to one of several possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2232 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2240.

[0346] In at least one embodiment, each graphics multiprocessor 2234 within the processing cluster 2214 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0347] In at least one embodiment, instructions sent to the processing cluster 2214 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2234. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2234. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2234, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2234.

[0348] In at least one embodiment, the graphics multiprocessor 2234 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 may forgo the internal cache and use a cache memory (e.g., L1 cache 2248) within the processing cluster 2214. In at least one embodiment, each graphics multiprocessor 2234 may also access an L2 cache within partition units (e.g., partition units 2220A-2220N of FIG. 22), which are shared among all processing clusters 2214 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2202 may be used as global memory. In at least one embodiment, the processing cluster 2214 includes multiple instances of the graphics multiprocessor 2234, which may share common instructions and data that may be stored in the L1 cache 2248.

[0349] In at least one embodiment, each processing cluster 2214 may include a memory management unit (“MMU”) 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2245 may reside within the memory interface 2218 of FIG. 22. In at least one embodiment, MMU 2245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on tiles) and optionally to cache line indices. In at least one embodiment, MMU 2245 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2234 or the L1 cache or processing cluster 2214. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0350] In at least one embodiment, the processing cluster 2214 may be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2234, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2234 outputs a processed task to a data crossbar switch 2240 to provide the processed task to another processing cluster 2214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2216. In at least one embodiment, the preROP 2242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit that may be located together with partitioning units described herein (e.g., partitioning units 2220A-2220N of FIG. 22). In at least one embodiment, the PreROP 2242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0351] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9BDetails are provided regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in graphics processing cluster 2214 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein. In at least one embodiment, as Figure 22D The graphics multiprocessor shown can be used to implement parallel operations to train the neural network as described above.

[0352] Figure 22D A graphics multiprocessor 2234 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2234 is coupled to a pipeline manager 2232 of a processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 has an execution pipeline including, but not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more general-purpose graphics processing unit (GPGPU) cores 2262, and one or more load / store units 2266. The GPGPU cores 2262 and the load / store units 2266 are coupled to a cache memory 2272 and a shared memory 2270 via a memory and cache interconnect 2268.

[0353] In at least one embodiment, instruction cache 2252 receives a stream of instructions to be executed from pipeline manager 2232. In at least one embodiment, instructions are cached in instruction cache 2252 and dispatched to instruction unit 2254 for execution. In one embodiment, instruction unit 2254 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2262. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2256 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2266.

[0354] In at least one embodiment, register file 2258 provides a set of registers for functional units of graphics multiprocessor 2234. In at least one embodiment, register file 2258 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2234 (e.g., GPGPU core 2262, load / store unit 2266). In at least one embodiment, register file 2258 is partitioned among each functional unit, such that a dedicated portion of register file 2258 is allocated to each functional unit. In at least one embodiment, register file 2258 is partitioned among different thread bundles being executed by graphics multiprocessor 2234.

[0355] In at least one embodiment, each of the GPGPU cores 2262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2234. The GPGPU cores 2262 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2234 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0356] In at least one embodiment, the GPGPU core 2262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0357] In at least one embodiment, the memory and cache interconnect 2268 is an interconnect network connecting each functional unit of the graphics multiprocessor 2234 to the register file 2258 and the shared memory 2270. In at least one embodiment, the memory and cache interconnect 2268 is a cross-switch interconnect that allows the load / store unit 2266 to perform load and store operations between the shared memory 2270 and the register file 2258. In at least one embodiment, the register file 2258 can operate at the same frequency as the GPGPU core 2262, resulting in very low latency for data transfer between the GPGPU core 2262 and the register file 2258. In at least one embodiment, the shared memory 2270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2234. In at least one embodiment, the cache memory 2272 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2236. In at least one embodiment, the shared memory 2270 can also be used as a program-managed cache.

[0358] In at least one embodiment, in addition to the automatically cached data stored in cache memory 2272, the thread executing on GPGPU core 2262 can also programmatically store data in shared memory.

[0359] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0360] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A9B and / or 9B provide details regarding the inference and / or training logic 915. In at least one embodiment, the inference and / or training logic 915 may be used in the graphics multiprocessor 2234 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network features and / or architecture, or neural network usage as described herein. In at least one embodiment, as Figure 23 The multi-GPU computing system shown can be used to implement parallel operations to train the neural network as described above.

[0361] Figure 23 A multi-GPU computing system 2300 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2300 may include a processor 2302 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2306A-D via a host interface switch 2304. In at least one embodiment, the host interface switch 2304 is a fast PCI switch device that couples the processor 2302 to a fast PCI bus through which the processor 2302 can communicate with the GPGPUs 2306A-D. The GPGPUs 2306A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2316. In at least one embodiment, the GPU-to-GPU links 2316 are connected to each of the GPGPUs 2306A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2316 enable direct communication between each of the GPGPUs 2306A-D without requiring communication on the host interface bus 2304 to which the processor 2302 is connected. In at least one embodiment, the host interface bus 2304 remains available for system memory access or communication with other instances of the multi-GPU computing system 2300, for example, via one or more network devices, through GPU-to-GPU traffic directed to the P2P GPU link 2316. While in at least one embodiment, the GPGPUs 2306A-D are connected to the processor 2302 via the host interface switch 2304, in at least one embodiment, the processor 2302 includes direct support for the P2P GPU link 2316 and can be directly connected to the GPGPUs 2306A-D.

[0362] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A9B and / or 9B provide details regarding inference and / or training logic 915. In at least one embodiment, inference and / or training logic 915 may be used in a multi-GPU computing system 2300 for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network capabilities and / or architecture, or neural network usage as described herein. In at least one embodiment, as Figure 24 The graphics processor shown can be used to implement parallel operations to train the neural network as described above.

[0363] Figure 24 This is a block diagram of a graphics processor 2400 according to at least one embodiment. In at least one embodiment, the graphics processor 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, the ring interconnect 2402 couples the graphics processor 2400 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2400 is one of many processors integrated within a multi-core processing system.

[0364] In at least one embodiment, the graphics processor 2400 receives multiple batches of commands via a ring interconnect 2402. In at least one embodiment, the incoming commands are interpreted by a command stream converter 2403 in a pipeline front-end 2404. In at least one embodiment, the graphics processor 2400 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 2403 provides commands to the geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, the command stream converter 2403 provides commands to a video front-end 2434 coupled to a media engine 2437. In at least one embodiment, the media engine 2437 includes a video quality engine (VQE) 2430 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2433 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each generate execution threads for thread execution resources provided by at least one graphics core 2480A.

[0365] In at least one embodiment, the graphics processor 2400 includes scalable thread execution resources characterized by modular cores 2480A-2480N (sometimes referred to as core slices), each graphics core having multiple sub-cores 2450A-2450N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2400 may have any number of graphics cores 2480A to 2480N. In at least one embodiment, the graphics processor 2400 includes a graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, the graphics processor 2400 is a low-power processor having a single sub-core (e.g., 2450A). In at least one embodiment, the graphics processor 2400 includes multiple graphics cores 2480A-2480N, each graphics core including a set of first sub-cores 2450A-2450N and a set of second sub-cores 2460A-2460N. In at least one embodiment, each of the first sub-cores 2450A-2450N includes at least a first set of execution units 2452A-2452N and media / texture samplers 2454A-2454N. In at least one embodiment, each of the second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each sub-core 2450A-2450N and 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0366] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, inference and / or training logic 915 may be used in graphics processor 2400 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture, or neural network usage described herein. In at least one embodiment, as Figure 25 The microarchitecture shown can be used to implement parallel operations to train the neural network as described above.

[0367] Figure 25This is a block diagram illustrating the microarchitecture of a processor 2500 that may include logic circuitry for executing instructions according to at least one embodiment. In at least one embodiment, the processor 2500 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2510 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled MMX technology microprocessors. TM Registers. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2510 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0368] In at least one embodiment, processor 2500 includes an ordered front end (“front end”) 2501 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2501 may include several units. In at least one embodiment, instruction prefetcher 2526 fetches instructions from memory and provides the instructions to instruction decoder 2528, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2528 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2528 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2530 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2534 for execution. In at least one embodiment, when the trace cache 2530 encounters complex instructions, the microcode ROM 2532 provides the microinstructions required to complete the operation.

[0369] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2528 may access the microcode ROM 2532 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2528. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2532. In at least one embodiment, the trace cache 2530 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2532 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2532 has completed the micro-operation ordering of the instructions, the machine front end 2501 may resume fetching micro-operations from the trace cache 2530.

[0370] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2503 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. The out-of-order execution engine 2503 includes, but is not limited to, an allocator / register renamer 2540, a memory microinstruction queue 2542, an integer / floating-point microinstruction queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2504, and a simple floating-point scheduler (“simple FP scheduler”) 2506. In at least one embodiment, the fast scheduler 2502, the slow / general-purpose floating-point scheduler 2504, and the simple floating-point scheduler 2506 are also collectively referred to as “microinstruction schedulers 2502, 2504, 2506”. The allocator / register renamer 2540 allocates the machine buffers and resources required for each microinstruction to be executed sequentially. In at least one embodiment, the allocator / register renamer 2540 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2540 also assigns entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2542 for memory operations and integer / floating-point microinstruction queue 2544 for non-memory operations, preceding the memory scheduler 2546 and microinstruction schedulers 2502, 2504, 2506. In at least one embodiment, the microinstruction schedulers 2502, 2504, 2506 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2502 of at least one embodiment can schedule every half master clock cycle, while the slow / general-purpose floating-point scheduler 2504 and the simple floating-point scheduler 2506 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2502, 2504, and 2506 arbitrate the scheduling port to schedule microinstructions for execution.

[0371] In at least one embodiment, execution block b11 includes, but is not limited to, integer register file / tribute network 2508, floating-point register file / tribute network (“FP register file / tribute network”) 2510, address generation units (“AGU”) 2512 and 2514, fast arithmetic logic units (“fast ALU”) 2516 and 2518, slow arithmetic logic unit (“slow ALU”) 2520, floating-point ALU (“FP”) 2522, and floating-point movement unit (“FP movement”) 2524. In at least one embodiment, integer register file / tribute network 2508 and floating-point register file / bypass network 2510 are also referred to herein as “register files 2508, 2510”. In at least one embodiment, AGUs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating-point ALU 2522, and floating-point movement unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524". In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0372] In at least one embodiment, register files 2508 and 2510 may be arranged between microinstruction schedulers 2502, 2504, and 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, the integer register file / tribute network 2508 performs integer operations. In at least one embodiment, the floating-point register file / tribute network 2510 performs floating-point operations. In at least one embodiment, each of the register files 2508 and 2510 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2508 and 2510 can communicate data with each other. In at least one embodiment, the integer register file / tribute network 2508 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2510 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0373] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524 can execute instructions. In at least one embodiment, register files 2508 and 2510 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2500 can be, but is not limited to, any number of execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524, and combinations thereof. In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2522 can be, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2516 and 2518. In at least one embodiment, fast ALUs 2516 and 2518 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2520, because slow ALU 2520 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUs 2512 and 2514. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2522 and the floating-point movement unit 2524 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2522 and the floating-point movement unit 2524 can operate on 128-bit wide packaged data operands that can be combined with SIMD and multimedia instructions.

[0374] In at least one embodiment, microinstruction schedulers 2502, 2504, and 2506 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2500, processor 2500 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0375] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register may be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0376] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into execution block 2511 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2511. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2511 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0377] Figure 26A deep learning application processor 2600 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2600 uses instructions, which, if executed by the deep learning application processor 2600, cause the deep learning application processor 2600 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2600 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2600 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2600 includes, but is not limited to, a processing cluster 2610(1)-2610(12), an inter-chip link (“ICL”) 2620(1)-2620(12), an inter-chip controller (“ICC”) 2630(1)-2630(2), a second-generation high-bandwidth memory (“HBM2”) 2640(1)-2640(4), a memory controller (“Mem Ctrlr”) 2642(1)-2642(4), a high-bandwidth memory physical layer (“HBM PHY”) 2644(1)-2644(4), a management controller central processing unit (“management controller CPU”) 2650, a serial peripheral interface, internal integrated circuits and general purpose input / output blocks (“SPI, I2C, GPIO”) 2660, a peripheral component interconnect fast controller and direct memory access block (“PCIe controller and DMA”) 2670, and a sixteen-channel peripheral component interconnect fast port (“PCI Express”). x 16”)2680.

[0378] In at least one embodiment, processing cluster 2610 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2610 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2600 can include any number and type of processing cluster 2600. In at least one embodiment, the inter-chip link 2620 is bidirectional. In at least one embodiment, the inter-chip link 2620 and the inter-chip controller 2630 enable multiple deep learning application processors 2600 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2600 can include any number (including zero) and type of ICL 2620 and ICC 2630.

[0379] In at least one embodiment, the HBM2 2640 provides a total of 32GB of memory. The HBM2 2640(i) is associated with both the memory controller 2642(i) and the HBM PHY 2644(i). In at least one embodiment, any number of HBM2 2640s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2642 and HBM PHY 2644. In at least one embodiment, any number and type of blocks can replace SPI, I2C, GPIO 3360, PCIe controller 2660, and DMA 2670 and / or PCIe 2680 to implement any number and type of communication standards in any technically feasible manner.

[0380] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details are provided regarding the inference and / or training logic 915. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2600. In at least one embodiment, the deep learning application processor 2600 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2600. In at least one embodiment, the processor 2600 may be used to perform one or more neural network use cases described herein. In at least one embodiment, as... Figure 27 The neuromorphic processor shown can be used to implement parallel operations to train workers of the neural network described above.

[0381] Figure 27This is a block diagram of a neuromorphic processor 2700 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2700 may receive one or more inputs from a source external to the neuromorphic processor 2700. In at least one embodiment, these inputs may be transmitted to one or more neurons 2702 within the neuromorphic processor 2700. In at least one embodiment, the neurons 2702 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, thousands of instances of neurons 2702, but any suitable number of neurons 2702 may be used. In at least one embodiment, each instance of a neuron 2702 may include a neuron input 2704 and a neuron output 2706. In at least one embodiment, a neuron 2702 may generate an output that can be transmitted to the inputs of other instances of the neuron 2702. In at least one embodiment, the neuron input 2704 and the neuron output 2706 may be interconnected via synapses 2708.

[0382] In at least one embodiment, neuron 2702 and synapse 2708 may be interconnected, causing neuromorphic processor 2700 to operate to process or analyze information received by neuromorphic processor 2700. In at least one embodiment, neuron 2702 may send an output pulse (or “trigger” or “peak”) when the input received through neuron input 2704 exceeds a threshold. In at least one embodiment, neuron 2702 may sum or integrate the signal received at neuron input 2704. For example, in at least one embodiment, neuron 2702 may be implemented as a leaky integral-triggered neuron, wherein if the summation (referred to as a “membrane potential”) exceeds a threshold, neuron 2702 may use a transfer function such as a sigmoid or threshold function to generate an output (or “trigger”). In at least one embodiment, the leaky integral-triggered neuron may sum the signal received at neuron input 2704 to a membrane potential and may apply an attenuation factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaking integral-triggered neuron may trigger if multiple input signals are received at neuron input 2704 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2702 may be implemented using circuitry or logic that receives input, integrates the input to the membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2702 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2706 when the result of applying the transfer function to neuron input 2704 exceeds a threshold. In at least one embodiment, once neuron 2702 is triggered, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2702 may resume normal operation after a suitable period of time (or recovery period).

[0383] In at least one embodiment, neurons 2702 can be interconnected via synapses 2708. In at least one embodiment, synapses 2708 can be operated to transmit signals from the output of a first neuron 2702 to the input of a second neuron 2702. In at least one embodiment, neurons 2702 can transmit information on more than one instance of synapses 2708. In at least one embodiment, one or more instances of neuron outputs 2706 can be connected via instances of synapses 2708 to instances of neuron inputs 2704 in the same neuron 2702. In at least one embodiment, an instance of neuron 2702 that produces an output to be transmitted on the instance of synapse 2708 can be referred to as a "presynaptic neuron". In at least one embodiment, an instance of neuron 2702 that receives input transmitted via an instance of synapse 2708 can be referred to as a "postsynaptic neuron". In at least one embodiment, regarding various instances of synapse 2708, since instances of neuron 2702 can receive input from one or more instances of synapse 2708 and can also transmit output through one or more instances of synapse 2708, a single instance of neuron 2702 can be both a "presynaptic neuron" and a "postsynaptic neuron".

[0384] In at least one embodiment, neurons 2702 may be organized into one or more layers. Each instance of neuron 2702 may have a neuron output 2706, which can fan out to one or more neuron inputs 2704 via one or more synapses 2708. In at least one embodiment, the neuron output 2706 of neuron 2702 in the first layer 2710 may be connected to the neuron input 2704 of neuron 2702 in the second layer 2712. In at least one embodiment, layer 2710 may be referred to as a “feedforward layer.” In at least one embodiment, each instance of neuron 2702 in an instance of the first layer 2710 may fan out to each instance of neuron 2702 in the second layer 2712. In at least one embodiment, the first layer 2710 may be referred to as a “fully connected feedforward layer.” In at least one embodiment, each instance of neuron 2702 in an instance of the second layer 2712 fan out to fewer than all instances of neuron 2702 in the third layer 2714. In at least one embodiment, the second layer 2712 may be referred to as a “sparsely connected feedforward layer.” In at least one embodiment, neurons 2702 in the second layer 2712 may fan out to neurons 2702 in multiple other layers, including neurons 2702 fan out to (the same) second layer 2712. In at least one embodiment, the second layer 2712 may be referred to as a “recurrent layer.” The neuromorphic processor 2700 may include, but is not limited to, any suitable combination of recurrent layers and feedforward layers, including, but not limited to, sparsely connected feedforward layers and fully connected feedforward layers.

[0385] In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnects to connect synapses 2708 to neurons 2702. In at least one embodiment, the neuromorphic processor 2700 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2702 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2708 may be connected to neurons 2702 using interconnect structures (such as on-chip networks) or via dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0386] Figure 28A processing system according to at least one embodiment is illustrated. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2802 or processor cores 2807. In at least one embodiment, system 2800 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0387] In at least one embodiment, system 2800 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2800 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2800 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 2800 is a television or set-top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.

[0388] In at least one embodiment, one or more processors 2802 each include one or more processor cores 2807 to process instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2807 is configured to process a particular instruction set 2809. In at least one embodiment, the instruction set 2809 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the processor cores 2807 may each process a different instruction set 2809, which may include instructions that facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 2807 may also include other processing devices, such as digital signal processors (DSPs).

[0389] In at least one embodiment, processor 2802 includes cache memory 2804. In at least one embodiment, processor 2802 may have a single internal cache or more levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2802. In at least one embodiment, processor 2802 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2807 using known cache coherence techniques. In at least one embodiment, processor 2802 further includes a register file 2806, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2806 may include general-purpose registers or other registers.

[0390] In at least one embodiment, one or more processors 2802 are coupled to one or more interface buses 2810 to transmit communication signals, such as address, data, or control signals, between the processors 2802 and other components in the system 2800. In at least one embodiment, the interface bus 2810 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2810 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2802 includes an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, the memory controller 2816 facilitates communication between memory devices and other components of the processing system 2800, while the platform controller hub (PCH) 2830 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0391] In at least one embodiment, memory device 2820 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2820 may be used as system memory of processing system 2800 to store data 2822 and instructions 2821 for use when one or more processors 2802 execute an application or process. In at least one embodiment, memory controller 2816 is also coupled to an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 of processor 2802 to perform graphics and media operations. In at least one embodiment, display device 2811 may be connected to processor 2802. In at least one embodiment, display device 2811 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2811 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0392] In at least one embodiment, the platform controller hub 2830 enables peripheral devices to connect to the storage device 2820 and the processor 2802 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, a touch sensor 2825, and a data storage device 2824 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2824 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2825 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2826 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2828 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2834 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2810. In at least one embodiment, audio controller 2846 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 2800 includes an optional legacy I / O controller 2840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. In at least one embodiment, platform controller hub 2830 may also be connected to one or more Universal Serial Bus (USB) controllers 2842 that connect input devices, such as a keyboard and mouse combination 2843, a camera 2844, or other USB input devices.

[0393] In at least one embodiment, instances of the memory controller 2816 and platform controller hub 2830 may be integrated into a discrete external graphics processor, such as external graphics processor 2812. In at least one embodiment, the platform controller hub 2830 and / or the memory controller 2816 may be external to one or more processors 2802. For example, in at least one embodiment, system 2800 may include an external memory controller 2816 and platform controller hub 2830, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with processor 2802.

[0394] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9BDetails regarding the inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the graphics processor 2800. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in the 3D pipeline 2812. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, in addition to Figure 9A or Figure 9B The logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2800 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0395] Figure 29 This is a block diagram of a processor 2900 having one or more processor cores 2902A-2902N, an integrated memory controller 2914, and an integrated graphics processor 2908 according to at least one embodiment. In at least one embodiment, the processor 2900 may include additional cores, up to and including additional cores 2902N indicated by dashed boxes. In at least one embodiment, each processor core 2902A-2902N includes one or more internal cache units 2904A-2904N. In at least one embodiment, each processor core may also access one or more shared cache units 2906.

[0396] In at least one embodiment, internal cache units 2904A-2904N and shared cache unit 2906 represent cache memory hierarchies within processor 2900. In at least one embodiment, cache memory units 2904A-2904N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2906 and 2904A-2904N.

[0397] In at least one embodiment, the processor 2900 may further include a set of one or more bus controller units 2916 and a system agent core 2910. In at least one embodiment, one or more bus controller units 2916 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2910 provides management functions for various processor components. In at least one embodiment, the system agent core 2910 includes one or more integrated memory controllers 2914 to manage access to various external memory devices (not shown).

[0398] In at least one embodiment, one or more processor cores 2902A-2902N include support for multi-threaded concurrent processing. In at least one embodiment, system agent core 2910 includes components for coordinating and operating cores 2902A-2902N during multi-threaded processing. In at least one embodiment, system agent core 2910 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2902A-2902N and graphics processor 2908.

[0399] In at least one embodiment, processor 2900 further includes a graphics processor 2908 for performing graph processing operations. In at least one embodiment, graphics processor 2908 is coupled to a shared cache unit 2906 and a system proxy core 2910 including one or more integrated memory controllers 2914. In at least one embodiment, system proxy core 2910 further includes a display controller 2911 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2911 may also be a separate module coupled to graphics processor 2908 via at least one interconnect, or it may be integrated within graphics processor 2908.

[0400] In at least one embodiment, ring-based interconnect unit 2912 is used to couple internal components of processor 2900. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, graphics processor 2908 is coupled to ring interconnect 2912 via I / O link 2913.

[0401] In at least one embodiment, I / O link 2913 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2918 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2902A-2902N and graphics processor 2908 uses embedded memory module 2918 as a shared last-level cache.

[0402] In at least one embodiment, processor cores 2902A-2902N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 2902A-2902N executing a common instruction set, while one or more other processor cores 2902A-2902N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2902A-2902N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2900 may be implemented on one or more chips or implemented as a SoC integrated circuit.

[0403] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 9A and / or Figure 9B Details regarding inference and / or training logic 915 are provided. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the graphics processor 2908. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in the 3D pipeline 2812, graphics core 2915A, shared function logic 2916, graphics core 2915B, shared function logic 2920, or... Figure 29 In other logic within the [unclear context]. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use [unclear context]. Figure 9A or Figure 9B The logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2910 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0404] Figure 30This is a block diagram of a graphics processing unit 3000, which may be a discrete graphics processing unit or a graphics processing unit integrated with multiple processing cores. In at least one embodiment, the graphics processing unit 3000 communicates with registers on the graphics processing unit 3000 and commands placed in memory via a memory-mapped I / O interface. In at least one emb...

Claims

1. A processor comprising circuitry to: cause different processing cores to perform updates to weights belonging to different portions of one or more neural networks in parallel; cause at least one of the different processing cores to receive updates to weights belonging to different portions of the one or more neural networks from other ones of the different processing cores; cause at least one of the different processing cores to generate an updated copy of the one or more neural networks based at least in part on the received updates.

2. The processor of claim 1, wherein the different processing cores apply one or more gradients to different sets of nodes of the one or more neural networks.

3. The processor of claim 1, wherein the one or more neural networks are trained at least in part by generating updates to the weights belonging to the one or more neural networks by combining updates to the weights belonging to the one or more neural networks produced in parallel by the different processing cores.

4. The processor of claim 1, wherein the processor is further to divide a weight update operation into a plurality of partial weight update operations and assign each partial weight update operation to the different processing cores.

5. The processor of claim 4, wherein the partial weight update operations are produced by dividing an initial weight and gradient update into a plurality of different portions.

6. The processor of claim 4, wherein each partial weight update is performed using a different thread.

7. The processor of claim 4, wherein the processor is further to collect the partial weight updates to generate the updated copy.

8. A system comprising: one or more processors to execute software to: cause different processing cores to perform updates to weights belonging to different portions of one or more neural networks in parallel; cause at least one of the different processing cores to receive updates to weights belonging to different portions of the one or more neural networks from other ones of the different processing cores; cause at least one of the different processing cores to generate an updated copy of the one or more neural networks based at least in part on the received updates; and one or more memories to store the one or more neural networks.

9. The system of claim 8, wherein the one or more neural networks are trained at least in part by: generating updates to the weights belonging to the one or more neural networks in parallel using the different processors; and combining the updates to the weights belonging to the one or more neural networks to produce a weight gradient update.

10. The system of claim 9, wherein the updates to the weights belonging to the one or more neural networks are produced in parallel using a plurality of worker threads.

11. The system of claim 9, wherein the one or more neural networks are trained at least in part by: forward propagating an input through the one or more neural networks to produce an output; determining an error based at least in part on a difference between the output and a desired value; and ​ ​ The error is backpropagated to determine gradients, the updates to the weights being based at least in part on the gradients.

12. The system of claim 9, wherein the updates to the weights are generated at least by: identifying a plurality of subsets of network nodes of the one or more neural networks; and generating an update to the weights for each subset of the plurality of subsets.

13. The system of claim 12, wherein the plurality of subsets are non-overlapping subsets of the weights of the one or more neural networks.

14. The system of claim 12, wherein: an individual subset of the plurality of subsets includes an amount of node weights; and the amount of node weights is determined based at least in part on an amount of processing power available to a worker assigned to process the individual subset relative to other workers assigned to process other subsets.

15. The system of claim 8, wherein: the system determines a set of gradients for each input of a set of inputs; and the set of gradients is distributed to each of the different processing cores.

16. A method comprising: The one or more neural networks are trained at least in part by: causing different processing cores to perform updates to the weights of different portions of the one or more neural networks in parallel; causing at least one of the different processing cores to receive updates to the weights of different portions of the one or more neural networks from other ones of the different processing cores; causing at least one of the different processing cores to generate an updated copy of the one or more neural networks based at least in part on the received updates.

17. The method of claim 16, wherein: the one or more neural networks are trained at least in part by distributing gradient information to a plurality of workers; the plurality of workers compute the updates to the weights in parallel; and the updates to the weights are aggregated to generate new weight values for the one or more neural networks.

18. The method of claim 17, wherein the one or more neural networks are trained at least in part by: forward propagating an input through the one or more neural networks to generate an output; determining an error based at least in part on the output; and determining gradients at least by backpropagating the error, the updates to the weights being based at least in part on the gradients.

19. The method of claim 18, wherein: the gradients are distributed to each of the plurality of workers; and the plurality of workers compute the updates to the weights.

20. The method of claim 16, wherein each of the plurality of workers executes on a different one of the different processing cores.

21. The method of claim 16, wherein each of the plurality of workers executes in parallel using the different processing cores on a graphics processing unit.

22. The method of claim 17, wherein a number of the updates to the weights matches a number of the different processing cores available to the computer system.

23. The method of claim 17, wherein the updates to the owning weights are partitioned into equal, non-overlapping groups of node weights to produce the different portions.

24. A speech processing system comprising one or more neural networks that take as input a digital representation of sound and identify elements of human speech, wherein, identifying human speech by different processing cores respectively and concurrently updating owning weights of different portions of the one or more neural networks by: performing updates to the owning weights by the different processing cores; receiving, by at least one of the different processing cores, updates to the owning weights of different portions of the one or more neural networks from other ones of the different processing cores; and generating, by at least one of the different processing cores, an updated copy of the one or more neural networks based at least in part on the received updates.

25. The speech processing system of claim 24, wherein the one or more neural networks: concurrently generate updates to the owning weights; and combine the updates to the owning weights into the updated copy.

26. The speech processing system of claim 24, wherein the speech processing system further comprises one or more processors and memory to store executable instructions that, as a result of execution by the different processing cores, cause the speech processing system to at least: obtain data representing audio from a microphone; process the data using the one or more neural networks to identify a spoken word represented in the data; and perform an action based at least in part on the identity of the spoken word.

27. The speech processing system of claim 26, wherein the action is a navigation request to be processed by a navigation system of a vehicle.

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