Low power and robust level shifting pulse latch for dual power supply memories

Abstract

A level-shifted pulse latch for a self-timed memory clock signal for a memory is provided. The level-shifted pulse latch includes a system power domain to memory power domain level shifter that inverts and level shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory power domain latch to generate the self-timed memory clock signal.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Indian Provisional Patent Application No. 201941045726 filed November 11, 2019, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to embedded memories, and more specifically to low-power and robust level-shifted pulse latches for embedded dual power supply memories. BACKGROUND

[0004] Memories such as SRAM are typically self-timed. For example, assertion of a word line for a read or write operation is triggered by a self-timed memory clock signal that is asserted in response to assertion of a system clock signal. But the self-timed memory clock signal has a duty cycle that is independent of the system clock signal. In particular, the self-timed memory clock signal is reset in response to completion of a memory function.

[0005] To generate the self-timed memory clock signal, a pulse latch is conventionally used that asserts the self-timed memory clock signal in response to assertion of the system clock signal and resets the self-timed memory clock signal once the word line can be released. The pulse latch thus pulses the self-timed memory clock signal so as to have a pulse width that meets a required duty cycle. But the system clock signal is generated in a system power domain that is powered by a system supply voltage that is independent of a memory supply voltage used to power the memory. The pulse latch must therefore be a level-shifted pulse latch. Conventional level-shifted pulse latches suffer from excessive power dissipation due to the need for level shifting, particularly in situations where the system supply voltage is higher than the memory supply voltage. SUMMARY

[0006] According to a first aspect of the present disclosure, a level-shifted pulse latch is provided that includes a level-shifted inverter configured to invert and level-shift a system clock signal from a system power domain powered by a system supply voltage into a memory power domain inverted clock signal for a memory power domain powered by a memory supply voltage; a pass transistor configured to conduct to pass the memory power domain inverted clock signal to form a latched input signal on an input signal node in response to assertion of both a memory select signal for selecting a memory in the memory power domain and the system clock signal; and a memory power domain latch configured to latch the latched input signal to provide a self-timed memory clock signal for the memory.

[0007] According to a second aspect of the disclosure, there is provided a method for operating a level shifted pulse latch, the method comprising the following acts: inverting and level shifting a system clock signal from a system power domain powered by a system supply voltage into a memory power domain inverted clock signal for a memory power domain powered by a memory supply voltage; in response to both an assertion of a memory select signal for selecting a memory in the memory power domain and an assertion of the system clock signal from the system power domain, transmitting the memory power domain inverted clock signal to form a latch input signal; and inverting the latch input signal to provide a self-timed memory clock signal for the memory.

[0008] According to a third aspect of the disclosure, there is provided a level shifted pulse latch, the level shifted pulse latch comprising: a system power domain latch configured to latch a memory select signal to form a pass transistor control signal; a clock path circuit configured to generate a pair of internal clock signals to control the system power domain latch to be transparent when a system clock signal is discharged and a reset signal is not asserted, and to control the system power domain latch to be closed when the system clock signal is charged to the system supply voltage; a pass transistor configured to turn on to transmit an inverted version of the system clock signal to form a latch input signal on an input signal node in response to an assertion of the pass transistor control signal, and a memory power domain latch configured to latch the latch input signal to provide a self-timed memory clock signal for a memory.

[0009] These and other advantageous features can be better understood with reference to the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a diagram of a system-on-a-chip according to an aspect of the disclosure, the system-on-a-chip including a level shifted pulse latch for a self-timed memory clock signal for an embedded memory.

[0011] Figure 2A is a circuit diagram of a first portion of a level shifted pulse latch according to an aspect of the disclosure.

[0012] Figure 2B is a circuit diagram of a second portion of a level shifted pulse latch according to an aspect of the disclosure.

[0013] Figure 3 is a flowchart of an example method of operation of a level shifted pulse latch according to an aspect of the disclosure.

[0014] Figure 4 Some example electronic systems each including a level shifted pulse latch for a self-timed memory clock signal according to an aspect of the disclosure are illustrated.

[0015] Embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description along with the accompanying drawings in which like reference numerals refer to like parts throughout the various drawings. For the purpose of clarity, not all of the individual components of the embodiments have been shown in each of the drawings. DETAILED DESCRIPTION

[0016] In Figure 1 A system-on-chip (SoC) 100 is shown in which an example level shift pulsed latch (PL) 105 is included. As used herein, the term "latch" refers to any suitable storage element which can be synchronous (e.g., a register or a flip-flop) or asynchronous (e.g., a set-reset latch). In the SoC 100, a system 110 is powered by a system supply voltage vddcx which is independent of a memory supply voltage vddmx which powers an embedded memory 115. The embedded memory 115 can thus also be denoted as a dual-supply memory since its memory supply voltage vddmx is independent of the system supply voltage vddcx. Due to this independence, the system supply voltage vddcx can be greater than or less than the memory supply voltage vddmx. Since the SoC 100 typically includes multiple embedded memories, the system 110 controls access to a particular embedded memory, such as the embedded memory 115, by asserting a corresponding memory select signal. In the SoC 100, the memory select signal for the embedded memory 115 is a low-active memory select signal cs_n, although it will be understood that a high-active memory select signal can be implemented in alternative embodiments. In this regard, when the binary state of a signal disclosed herein is true, the signal will be considered "asserted" whether the signal is a high-active signal or a low-active signal. Thus, a low-active signal is asserted by discharging and de-asserted by charging to the supply voltage. Conversely, a high-active signal is asserted by charging to the supply voltage and de-asserted by discharging. The system 110 triggers an access (read or write operation) to the embedded memory 115 by asserting the memory select signal cs_n. A read or write operation for the memory access then occurs in response to a rising edge of a system clock signal (clk) from a clock source 120. In alternative embodiments, the memory access can be triggered in response to a falling edge of the system clock signal clk.

[0017] Since the operation of the level shift pulsed latch 105 is independent of whether the memory access is a read or write operation, the following discussion will refer to the memory access operation as a general term to represent both a read operation or a write operation of the embedded memory 115. With both the memory select signal cx n and the system clock signal clk asserted, the level shift pulsed latch 105 asserts the self-timed memory clock signal iclk to trigger the memory access operation in the embedded memory 115. This assertion of the self-timed memory clock signal iclk is a level shift assertion since the system clock signal clk is a system power domain signal powered by the system supply voltage vddcx and the self-timed memory clock signal is a memory power domain signal powered by the memory supply voltage vddmx. As used herein, the terms“system power domain” and“system” are used interchangeably. Similarly, the terms“memory power domain” and“memory” are used interchangeably herein. It will be understood that in an alternative implementation as opposed to being embedded in the SoC 100, the embedded memory 115 can instead be an external memory of the SoC 100.

[0018] Within the embedded memory 115, the assertion of the self-timed memory clock signal iclk causes the assertion of a word line voltage of a word line (not illustrated). But the word line is only asserted for a period timed by the self-timed circuit 125 (e.g., dummy word line and dummy bit line) to complete the memory function. Once the self-timed circuit 125 times a period sufficient to complete the memory access operation, the self-timed circuit 125 asserts a reset signal (e.g., low active reset signal) that resets the level shift pulsed latch 105 of the self-timed memory clock signal iclk. The duty cycle of the self-timed memory clock signal iclk is thus independent of the duty cycle of the system clock signal clk. Because of this independence, the system clock signal clk can be reset before the self-timed memory clock signal iclk is reset. Despite the system clock signal clk being reset, to maintain the self-timed memory clock signal iclk asserted, the level shift pulsed latch 105 latches the asserted self-timed memory clock signal iclk. This latched assertion of the self-timed memory clock signal iclk is only released when the reset signal is asserted.

[0019] The level shift pulsed latch 105 has no control over the system clock signal clk, so it must be robust to various skew values of the system clock signal clk. In addition, level shifting has traditionally caused a large power dissipation for various corner conditions. Referring to the first portion 200 of the level shift pulsed latch 105 shown in Figure 2A Figure 2B ​The improvements to the level shift pulsed latch 105 that reduce power consumption for these corner conditions can be better understood with reference to the second portion 260 of the level shift pulsed latch 105 shown in FIG. 2. The first portion 200 includes a system power domain latch 205 that latches a pass transistor control signal clk_pl_in. To generate the pass transistor control signal clk_pl_in, the first portion 200 includes a NAND gate 215 that inverts the memory select signal cs_n with a low level active scan input signal scan_n asserted for scan mode of operation. The scan mode signal scan_in will thus be high during normal (non-scan) operation such that the NAND gate 215 functions to invert the memory select signal cs_n as a latch input signal 216. An inverter 217 functions as further discussed herein to invert the latch input signal 216 to form an inverted version of the pass transistor control signal clk_pl_in (clk_pl_inb). The system power domain latch 205 functions to invert the clk_pl_inb signal to form the pass transistor control signal clk_pl_in.

[0020] As is known in the art of latches, a latch is considered "transparent" when its output signal changes in response to a change in the latch's input signal. Conversely, a latch is considered "closed" when the latch latches the binary state of the latch's output signal such that the latch's output signal does not change despite any changes in the latch input signal. With reference to the system power domain latch 205, the inverter 217 controls whether the system power domain latch 205 is transparent. In particular, the system power domain latch 205 is transparent only when the inverter 217 has both a power supply and a ground. To control whether the system power domain latch 205 is transparent or closed, the clock path circuit 210 generates a pair of internal clock signals, clk1 and clk2, in response to the system clock signal clk. As will be further explained herein, the internal clock signal clk1 (which is also denoted herein as the first internal clock signal) is asserted to the system power supply voltage vddcx when the system clock signal clk is low (grounded) and the self-timed memory clock signal iclk is low (not as defined herein, a signal is considered "low" when discharged and "high" when charged to the power supply voltage). Conversely, the internal clock signal clk2 (also denoted herein as the second internal clock signal) is low when the first internal clock signal clk1 is high. When the internal clock signal clk1 is high and the internal clock signal clk2 is low, the inverter 217, formed by a series combination of a p-type metal oxide semiconductor (PMOS) inverter transistor P2 and an n-type metal oxide semiconductor (NMOS) inverter transistor M2, is powered. In particular, the source of the transistor M2 is coupled to ground through an NMOS transistor Ml controlled by the internal clock signal clk1. Similarly, the source of the transistor P2 is coupled to the node for the system power supply voltage vddcx through a PMOS transistor PI controlled by the internal clock signal clk2. Thus, when both the system clock signal clk and the self-timed memory clock signal iclk are low, the inverter 217 will be powered and grounded such that the inverter 217 will invert the latch input signal 216 to the clk_pl_inb signal that is latched and inverted in the system power domain latch 205 to form the pass transistor control signal clk_pl_in.

[0021] The system power domain latch 205 is therefore transparent and when both the system clock signal clk and the self-timed memory clock signal iclk are low, the pass latch input signal 216 (which is inverted twice as discussed further herein) is passed to form the pass transistor control clk_pl_inb. Since the pass latch input signal 216 is an inverted version of the memory select signal cx_n, when the memory select signal is asserted and the system power domain latch is transparent, the pass transistor control signal clk_pl_in is asserted. The NOR (or NOT) gate 220 inverts the signal clk_pl_inb with the self-timed memory clock signal iclk. The inverter 217 acts as a first inverter and the NOR gate 220 therefore acts as a second inverter in the system power domain latch 205 to invert the clk_pl_inb signal when the self-timed memory clock signal iclk is reset (discharged to ground) to form the pass transistor control signal clk_pl_in. Therefore, when the memory select signal cx_n is asserted and the system power domain latch 205 is transparent, the pass transistor control signal clk_pl_in is asserted to the system power supply signal vddcx. When the self-timed memory clock signal iclk and / or the system clock signal is asserted, the system power domain latch 205 is closed because the inverter 217 is then cut off from power and ground since both transistors PI and Ml will be cut off. At the same time, the inverter 225 formed by the series combination of PMOS transistor P4 and NMOS transistor M4 then receives power and ground. The source of transistor M4 is coupled to ground through NMOS transistor M3 controlled by the internal clock signal clk2. Similarly, the source of transistor P4 is coupled to the node for the system power supply voltage vddcx through PMOS transistor P3 controlled by the internal clock signal clk1. The inverter 225 will therefore be powered and grounded such that when the internal clock signal clk1 is low and the internal clock signal clk2 is high (the system power domain latch 205 is closed), the system power domain latch 205 latches the pass transistor control signal clk_pl_in. The output of the inverter 225 drives the input of the NOR gate 220. Since the output of the NOR gate 220 drives the input to the inverter 225 (the gates of transistors P4 and M4), the NOR gate 220 and the inverter 225 are cross-coupled and therefore latch the pass transistor control signal clk_pl_in when the system power domain latch 205 is closed.

[0022] As will be further explained herein, the inverted clock signal vssg in the clock path circuit 210 is an inverted and level shifted version of the system clock signal clk. The inverter clock signal vssg is a memory power domain signal, while the system clock signal is a system power domain signal. The clock path circuit 210 includes an inverter 230 that inverts the inverted clock signal vssg to form a vssg complement signal (vssg_n) that is NORed with the self-timed memory clock signal iclk in a NOR gate 235. The output signal of the NOR gate 235 is level shifted from the memory power domain to the system power domain by an MX-to-CX level shifter (LS) 240, where MX represents the memory supply voltage vddmx and CX represents the system supply voltage vddcx. The level shifter 240 is also represented herein as a memory power domain to system power domain level shifter. An inverter 245 inverts the output signal of the MX-to-CX level shifter 240 to drive a NOR gate 250 that also NORs the system clock signal clk. The output of the NOR gate 250 forms an internal clock signal clk1 that is inverted by an inverter 255 to form an internal clock signal clk2. Thus, the internal clock signals clk1 and clk2 are gated by the action of the NOR gate 235 from the self-timed memory clock signal iclk.

[0023] Only when the self-timed memory clock signal iclk is reset low can the internal clock signal clk1 go low and the internal clock signal ck2 go high to render the system power domain latch 205 transparent. This is quite advantageous to prevent DC current loss, which otherwise can exist for the NOR gate 220 for corner conditions when the system supply voltage vddcx is relatively high (e.g., 1.082 V) and the memory supply voltage vddmx is relatively low (e.g., 0.635 V). In this high CX, low MX corner condition, it can be the case that the self-timed memory clock signal iclk is still asserted, but a new asserted value of the memory select signal cs_n occurs. The clk_pl_inb signal would then be grounded, while the self-timed memory clock signal iclk is high. But this high value of the self-timed memory clock signal iclk is effectively zero for the PMOS transistor (not illustrated) within the NOR gate 220. That PMOS transistor then forms part of a DC current path through the NOR gate 220, which would undesirably waste power. But the gating by the NOR gate 235 prevents the system power domain latch 205 from being transparent until the self-timed memory clock signal iclk is reset, to advantageously prevent this DC current loss in the NOR gate 220.

[0024] The operation of the second portion 260 of the level shift pulse latch 105 will now be discussed. Inverter 270 and inverter 275 form a memory power domain latch 280 for latching the self-timed memory clock signal iclk. An NMOS pass transistor M7 controlled by a pass transistor control signal clk_pl_in from the system power domain latch 205 controls whether the inverted clock signal vssg can be passed to the memory power domain latch 280 as a latched input signal iclk_n carried on input signal node 271. When the memory select signal cs_n is asserted low and the system power domain latch 205 is transparent, the pass transistor control signal clk_pl_in is asserted to turn on pass transistor M7 and allow the inverted clock signal vssg to pass through to form the latched input signal iclk_n for the memory power domain latch 280. Inverter 270 in the memory power domain latch 280 inverts the latched input signal iclk_n to form the self-timed memory clock signal iclk.

[0025] The CX-to-MX level shifter 265 inverts and level shifts the system clock signal clk from the system power domain to the memory power domain to form the inverted clock signal vssg. NMOS transistor M8 in the CX-to-MX level shifter 265 has its source tied to ground and its gate controlled by the system clock signal clk. The drain of transistor M8 forms a node for the inverted clock signal vssg. Thus, when the system clock signal clk is asserted, the inverted clock signal vssg is grounded through transistor M8. If the pass transistor M7 is turned on due to assertion of the pass transistor control signal clk_pl_in, then the input signal iclk_n is grounded to cause the self-timed memory clock signal iclk to be asserted. Thus, if the memory is selected by assertion of the memory select signal cx_n, the self-timed memory clock signal iclk will be asserted in response to assertion of the system clock signal clk.

[0026] The reset signal will remain de-asserted by being charged to the memory power supply voltage vddmx before the self-timed memory clock signal iclk is reset, causing NMOS transistor M6 to be on and PMOS transistor P8 to be off. Transistor M6 has its source connected to ground and its drain connected to the source of NMOS transistor M5 in inverter 275. The drain of transistor M5 is connected to input signal node 271. The self-timed memory clock signal iclk drives the gate of transistor M5, such that transistor M5 is on when the self-timed memory clock signal iclk is asserted. Since the reset signal has not yet been asserted low, the discharged latched input signal iclk_n on input signal node 271 is latched in memory power domain latch 280 by the reinforcing action of inverters 270 and 275 to latch the self-timed memory clock signal iclk. The self-timed memory clock signal iclk drives the gates of PMOS transistor P7 and NMOS transistor M5 in inverter 275. Transistor P7 has a drain connected to the drain of transistor M5 and also to input signal node 271. Thus, transistor P7 will be off when the self-timed memory clock signal iclk is asserted. After the memory function is timed by the self-timed circuit 125, the reset signal is asserted to turn off transistor M6 and turn on transistor P8. Transistor P8 has a source connected to the node for the memory power supply voltage vddmx and a drain connected to input signal node 271. Transistor P8 is turned on in response to the assertion of the reset signal low, causing the input signal iclk_n to be charged to the memory power supply voltage vddmx, which in turn causes inverter 270 to discharge the self-timed memory clock signal iclk. The self-timed memory clock signal iclk is thus discharged in response to the assertion of the reset signal, such that transistor P8 acts as a reset circuit. It will be understood that other types of reset circuits can be used in place of transistor P8 to reset the self-timed memory clock signal iclk. Figure 1

[0027] The source of transistor P7 is coupled to the power node for the memory power supply voltage vddmx through a pair of PMOS transistors P5 and P6 coupled in parallel. The sources of transistors P5 and P6 are connected to the power node for the memory power supply voltage vddmx, while the drains of transistors P5 and P6 are connected to the source of transistor P7. The system clock signal clk drives the gate of transistor P6, while a pass transistor control signal clk_pl_in drives the gate of transistor P5. Thus, whenever the system clock signal clk is low or the memory is not selected, transistor P7 is powered such that a low state of the self-timed memory clock signal iclk turns on transistor P7 to reinforce a high state of the input signal iclk_n and latch a low state of the self-timed memory clock signal iclk in the memory power domain latch 280.​

[0028] In the CX to MX level shifter 265, the system clock signal clk drives the gate of PMOS transistor P10, the source of which is connected to a power node for the memory supply voltage vddmx, and the drain of which is connected to the source of PMOS transistor P9. The drain of transistor M8 is connected to the drain of transistor P9. The gate of transistor P9 is connected to the drain of PMOS transistor P12, which in turn has a connection to the drain of NMOS transistor M9. The source of transistor M9 is connected to ground, and its gate is driven by the output of inverter 285, which inverts the system clock signal clk. Thus, when the system clock signal clk is high, transistor M9 will be off. The output of inverter 285 also drives the gate of PMOS transistor P11, the source of which is connected to the power node for the memory supply voltage vddmx, and the drain of which is connected to the source of transistor P12. The drain of transistor M8 is connected to the gate of transistor P12. Thus, when the system clock signal clk is high, both transistors P11 and P12 will be on to charge the gate of transistor P9, ensuring that transistor P9 is off. When the system clock signal clk goes low, transistor M9 turns on and transistors P11 and P12 turn off. Transistor P9 then turns on by discharging through the drain of transistor M9. Thus, both transistors P9 and P10 turn on through the low state of the system clock signal clk to charge the inverted clock signal vssg to the memory supply voltage vddmx.

[0029] The level shifting by the CX-to-MX level shifter 265 is quite advantageous in resolving corner conditions such as high CX, low MX at the power supply voltage levels discussed earlier. For example, assume that the system clock signal is simply inverted to form the system power domain inverted clock signal vssg. If the low state (binary zero) of the system clock signal clk is simply inverted without level shifting to form the system power domain inverted clock signal vssg when the reset signal is asserted and when the pass transistor control signal clk_pl_in is high, then the source of the pass transistor M7 will be relatively high compared to its drain, causing the pass transistor M7 to turn on to pass the system power domain inverted clock signal vssg to the input signal node 271. The system power supply voltage vddcx will then pass from the input signal node 271 through transistor P7 and transistor P6 to discharge to the power supply node for the memory power supply voltage vddmx, resulting in significant power dissipation. But the CX-to-MX level shifter 265 prevents this power discharge because in this corner case, both the drain and source of the pass transistor M7 will be charged to the memory power supply voltage vddmx. Then, there can be no discharge from the system power domain to the memory power domain via the pass transistor M7. A similar CX-to-MX power discharge can occur at power up through the pass transistor M7, which is prevented by the CX-to-MX level shifter 265. Thus, the level shifting pulse latch 105 saves significant power and has no limitation on input clock turn around. In addition, the CX-to-MX level shifter 265 will advantageously increase the hold time of data output buffers (not illustrated) at the corners of low CX and high MX.

[0030] The operation of the level shifting pulse latch will now be discussed with reference to the flowchart of Figure 3 The method includes a first act of inverting and level shifting a system clock signal from a system power domain supplied by a system power supply voltage into a memory power domain inverted clock signal for a memory power domain supplied by a memory power supply voltage. The generation of the inverted clock signal vssg by the CX-to-MX level shifter 265 is one example of act 300. The method also includes an act 305 of passing the memory power domain inverted clock signal to form a latched input signal in response to both an assertion of a memory select signal for selecting a memory in the memory power domain and an assertion of the system clock signal from the system power domain. An example of act 305 is the control of the pass transistor M7 by the system power domain latch 205 to control whether the inverted clock signal vssg is passed to drive the input signal node 271 of the memory power domain latch 280. Finally, the method includes an act 310 of inverting the latched input signal to provide a self-timed memory clock signal for the memory. The action of the inverter 270 is an example of act 310.

[0031] The level shifting pulse latches as disclosed herein can be advantageously incorporated into any suitable electronic system. For example, as shown in FIG. 4, a cellular telephone 400, a laptop computer 405, and a tablet PC 410 can each include a memory clocked by a self-timed memory clock signal generated from a level shifting pulse latch according to the present disclosure. Other exemplary electronic systems (e.g., music players, video players, communication devices, and personal computers) can also be configured with level shifting pulse latches constructed according to the present disclosure. Figure 4

[0032] It will be understood that many modifications, substitutions and changes can be made to the methods of using materials, equipment, configurations, and devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to the scope of the particular embodiments exemplified and described herein, as they are only some examples of the present disclosure, but should be fully commensurate with the scope of the appended claims and functional equivalents thereof.​

Claims

1. A level-shift pulse latch, comprising: a level-shift inverter configured to invert and level-shift a system clock signal from a system power domain into a memory power domain inverted clock signal for a memory power domain, the system power domain being powered by a system power supply voltage and the memory power domain being powered by a memory power supply voltage; a pass transistor configured to: conduct in response to assertion of both a memory select signal and the system clock signal to pass the memory power domain inverted clock signal to form a latch input signal on an input signal node; a memory power domain latch configured to: latch the latch input signal to provide a self-timed memory clock signal for the memory; as well as a system power domain latch configured to latch the memory select signal to form a pass transistor control signal, wherein the system power domain latch is configured to be transparent when the memory power domain inverted clock signal is discharged and a reset signal is not asserted, and to be closed when the system clock signal is charged to the system supply voltage, and wherein the pass transistor is configured to turn on in response to assertion of the pass transistor control signal by the system power domain latch.

2. The level-shift pulse latch according to claim 1 , further comprising: A reset circuit is configured to charge the latch input signal to the memory supply voltage in response to assertion of the reset signal.

3. The level-shift pulse latch according to claim 2, wherein: The reset circuit includes a p-type metal oxide semiconductor (PMOS) transistor having a source connected to a power supply node for the memory power supply voltage and a drain connected to the input signal node.

4. The level-shift pulse latch according to claim 1, wherein: The memory power domain latch is configured to invert the input latch signal to form the self-timed memory clock signal.

5. The level-shift pulse latch according to claim 2, wherein: The pass transistor is a first n-type metal oxide semiconductor (NMOS) transistor having a drain connected to the input signal node, and wherein the level shift inverter includes a second NMOS transistor having a source connected to ground, a drain connected to the drain of the first NMOS transistor, and a gate connected to a node of the system clock signal.

6. The level-shift pulse latch according to claim 1, wherein: The system power domain latch includes a NOR gate configured to NOR the self-timed memory clock signal with an inverted latch input signal to generate the pass transistor control signal.

7. The level-shift pulse latch according to claim 6, wherein: The reset signal is an active low reset signal.

8. The level-shift pulse latch according to claim 7 , further comprising: a clock path circuit comprising a first logic gate and a first inverter, the first logic gate being configured to invert the system clock signal to form a first internal clock signal, the first inverter being configured to invert the first internal clock signal to form a second internal clock signal, and wherein the system power domain latch is configured to be transparent in response to the first internal clock signal being charged to the system power supply voltage and the second internal clock signal being discharged.

9. The level-shift pulse latch according to claim 8, further comprising: a NAND gate configured to: perform a NAND operation on the memory selection signal and a scan input signal to form a latch input signal; a second inverter formed by a first NMOS transistor connected in series with a first PMOS transistor, and the second inverter is configured to: invert the latch input signal to form the inverted latch input signal; a second NMOS transistor having a source connected to ground and a drain connected to the drain of the first NMOS transistor, wherein a gate of the second NMOS transistor is configured to be controlled by the first internal clock signal; as well as A second PMOS transistor has a source connected to a power supply node of the system power supply voltage and has a drain connected to the source of the first PMOS transistor, wherein a gate of the first PMOS transistor is configured to be controlled by the second internal clock signal.

10. The level-shift pulse latch according to claim 8, wherein: The clock path circuit comprises: a second inverter configured to invert the memory power domain inverted clock signal; a second logic gate configured to process an output signal from the second inverter using the self-timed memory clock signal; a memory power domain to system power domain level shifter configured to level shift an output signal from the second logic gate into a level-shifted output signal; A third inverter is configured to invert the level-shifted output signal, wherein the first logic gate is configured to process the system clock signal and the output signal from the third inverter to form the first internal clock signal.

11. The level-shift pulse latch according to claim 10, wherein: The first logic gate is a first NOR gate, and the second logic gate is a second NOR gate.

12. The level-shift pulse latch according to claim 9, wherein: The system power domain and the memory power domain are integrated into a system on chip.

13. The level-shift pulse latch according to claim 12, wherein: The system on chip is integrated into a cellular phone.

14. A method for operating a level-shifted pulse latch, comprising: inverting and level shifting a system clock signal from a system power domain powered by a system supply voltage to form a memory power domain inverted clock signal for a memory power domain powered by a memory supply voltage; in response to assertion of both a memory select signal and the system clock signal, transmitting the memory power domain inverted clock signal to form a latch input signal; as well as inverting the latch input signal to provide a self-timed memory clock signal for the memory selected by the memory select signal, Transmitting the memory power domain inverted clock signal includes: The pass transistor is turned on in response to assertion of a pass transistor control signal by a system power domain latch, the system power domain latch being configured to latch the memory select signal to form the pass transistor control signal, wherein the system power domain latch is configured to be transparent when the memory power domain inverted clock signal is discharged and a reset signal is not asserted, and to be closed when the system clock signal is charged to the system supply voltage.

15. The method for operating a level-shifted pulse latch according to claim 14, further comprising: In response to assertion of the reset signal, the latch input signal is charged to the memory supply voltage to discharge the self-timed memory clock signal.

16. The method according to claim 15, further comprising: The reset signal is asserted in response to completion of a memory function after the assertion of the system clock signal.

17. The method according to claim 16, wherein The assertion of the reset signal includes discharging the reset signal to ground.

18. A level-shift pulse latch, comprising: a system power domain latch configured to: latch a memory select signal to form a pass transistor control signal; a clock path circuit configured to: generate a pair of internal clock signals to control the system power domain latch to be transparent when the system clock signal is discharged and the reset signal is not asserted, and to control the system power domain latch to be closed when the system clock signal is charged to a system power supply voltage; a pass transistor configured to conduct in response to assertion of the pass transistor control signal to pass an inverted version of the system clock signal to form a latched input signal on an input signal node, and The memory power domain latch is configured to latch the latch input signal to provide a self-timed memory clock signal for the memory.

19. The level-shifted pulse latch of claim 18, further comprising a reset circuit configured to charge the latch input signal to a memory supply voltage in response to assertion of the reset signal.

20. The level-shift pulse latch according to claim 18, further comprising: The level-shift inverter is configured to invert and level-shift the system clock signal into a memory power domain inverted clock signal to form the inverted version of the system clock signal.

21. The level-shift pulse latch according to claim 20, wherein: The clock path circuit comprises: A first inverter is configured to invert the inverted version of the system clock signal.

22. The level-shift pulse latch according to claim 21, wherein: The clock path circuit further includes: A first logic gate is configured to process the self-timed memory clock signal and an output signal from the first inverter.

23. The level-shift pulse latch according to claim 22, wherein: The clock path circuit further includes: The memory power domain to system power domain level shifter is configured to level shift the output signal from the first logic gate.

24. The level-shift pulse latch according to claim 18, further comprising: The NAND gate is configured to perform a NAND operation on the memory selection signal and a scan input signal to form a latch input signal for the system power domain latch.

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