Field effect transistor with improved layout

Abstract

The present invention relates to a field effect transistor, a packaged field effect transistor and an electronic device comprising the same. More specifically, the present invention relates to a field effect transistor having an improved gate finger and drain finger layout. The present invention proposes a new drain finger and gate finger layout such that the phase delay between signals passing through the transistor cell at different locations along the gate finger and the drain finger is minimized.

Description

Technical Field

[0001] This invention relates to a field-effect transistor, a packaged field-effect transistor, and an electronic device including the same. More specifically, this invention relates to a field-effect transistor having an improved gate finger and drain finger arrangement. Background Technology

[0002] Figure 1A A cross-section of a known laterally diffused metal-oxide-semiconductor 'LDMOS' transistor 1 is shown. The transistor includes a conductive semiconductor substrate 2, such as a p-type silicon substrate. Typically, a lightly doped p-type Si epitaxial layer 3 forms the upper portion of the semiconductor substrate 2. A p-type well 4 is formed beneath a gate oxide 5, which is covered by a polysilicon gate contact 6. A source contact 7 contacts a heavily doped n-type contact region 8, which can be formed using a suitable metal composition or alloy, such as polysilicon. This region extends beneath the gate oxide 5. The region directly beneath the gate oxide 5 and adjacent to the contact region 8 is referred to as the channel region 9. Furthermore, a heavily doped p-type sink 10 is provided to isolate adjacent transistors. Typically, the source of transistor 1 is grounded via the sink 10 connected to the substrate 2. More specifically, the source contact 7 is electrically connected to the contact region 8 and the sink 10.

[0003] A drain contact 11 is provided on the opposite side of the gate oxide 5. For this purpose, a highly doped n-type contact region 12 is provided. An n-type drift region 13 is disposed between the channel region 9 and the drain contact region 12. The drift region 13 enables the field-effect transistor 1 to operate at relatively high voltages.

[0004] Typically, metal layer stacking is used to provide access to field-effect transistor 1. Figure 1A An example of two metal layers L1 and L2 separated by a dielectric material is shown. Through-holes through the dielectric material are used to enable contact between the metal layers and between the metal layers and the gate, drain, and source contacts.

[0005] Current is preferably transmitted through metal layers L1 and L2 because the thickness of these layers and / or the conductivity of these layers are greater than those of the gate contact, drain contact and source contact connected to them.

[0006] Figure 1B A partial top view of the gate contact 6 is provided, showing that the gate contact 6 has an elongated shape. Gate islands 6a are preferably formed at regular intervals. These islands are used to establish connections between the gate contact 6 and metal tracks on the metal layers L1 and L2. The width of the gate contact 6 is typically on the micrometer scale (…). Figure 1B(Not shown to scale), while the minimum width of the vias is in the 50-100 micrometer range. The relatively large size of the gate island 6a allows for the use of vias 14 to establish a connection between the gate contact 6 and the metal layer L1. Vias 15 can be used to establish connections between metal layers L1 and L2 at the same or different locations. It should be further noted that the elongated structures in metal layers L1 and L2 have a thickness in the micrometer range and are not shown to scale relative to the gate contact, drain contact, and source contact. Other parts of the field-effect transistor 1 are also not shown to scale to allow visualization of all components in the same drawing.

[0007] The metal structures on metal layers L1 and L2 that connect to the gate contact 6 also have elongated shapes and are commonly referred to as gate runners. Drain contact 11 and source contact 7 are also connected to structures on metal layers L1 and L2. These metal structures also have elongated shapes. As shown in Figure 1, the metal structure connected to the source contact 7 is typically arranged between the gate runner and the metal structure connected to the drain contact 11. This improves the isolation between the gate and drain of the field-effect transistor 1.

[0008] Since both the gate contact 6 and the corresponding gate channel have elongated shapes, they will be referred to individually and collectively as gate fingers in the following text. A similar consideration applies to the drain contact and the corresponding metal structures on layers L1 and L2, which will be referred to individually or collectively as drain fingers in the following text.

[0009] Figure 2A A known arrangement of a field-effect transistor 1 is shown. Here, the field-effect transistor 1 includes three transistor cell arrays 16, each transistor cell array 16 including three adjacently arranged interconnected transistor cells 17. Each transistor cell 17 includes a first transistor cell unit 18 and an optional second transistor cell unit 19. Typically, the second transistor cell unit 19 is a mirror copy of the first transistor cell unit 18.

[0010] The field-effect transistor 1 also includes a gate strip 20 for receiving a signal to be amplified or otherwise processed, and a drain strip 21 for outputting the amplified or processed signal. As shown, both the gate strip 20 and the drain strip 21 extend along a first direction D1 and are spaced apart along a second direction D2.

[0011] Figure 2B It shows Figure 2AA known implementation of the arrangement is described. In this arrangement, the field-effect transistor 1 includes a single transistor cell array 16, which includes eight transistor cells 17, each transistor cell 17 including a first transistor cell unit 18 and a second transistor cell unit 19. Main gate fingers 22 extend toward the drain cell array 21 from the gate bar 20. Similarly, two main drain fingers 23 extend toward the gate bar 20 from the drain cell array 21. The main gate fingers 22 are connected to a plurality of gate fingers 24, and the main drain fingers 23 are connected to a plurality of drain fingers 25.

[0012] exist Figure 2B In each transistor cell unit 18, 19, there is a single gate finger 24 and a single drain finger 25. In other transistor cell units, multiple gate fingers and multiple drain fingers may be used.

[0013] The gate and drain fingers correspond to the respective active regions of the field-effect transistor 1 to form transistor cells. The combined effect of all transistor cells defines the electrical behavior of the field-effect transistor 1.

[0014] The second transistor cell unit 19 is a mirror copy of the first transistor cell unit 18. Further, the main gate finger 22 can be divided into multiple interconnected main gate finger segments, each segment being included in a corresponding transistor cell unit 18, 19, and wherein an outer segment is connected to the gate bar 20. A similar consideration applies to the main drain finger 23.

[0015] Several quality factors can be used to characterize the performance of field-effect transistors. One important quality factor is the large-signal gain at radio frequency (RF), hereinafter referred to as gain. Transistors with high gain can effectively amplify RF signals. When the gain of a transistor is low, the overall efficiency of the amplifier containing the transistor will decrease.

[0016] For high-power field-effect transistors, a large total gate length must be used, which is the number of fingers multiplied by the gate length of a single finger, to provide the required power. A large total gate width can be achieved by using many relatively long fingers in parallel.

[0017] The acceptable gate length for RF transistors is generally considered to be 600-700 micrometers. Finger lengths exceeding 1 mm or even 2 mm are sometimes used only in high-power transistors operating at frequencies below 1 GHz. Finger lengths exceeding 3 mm are not used due to instability issues.

[0018] Arranging numerous fingers in parallel is not without risk, as placing them very close together can cause thermal problems. This is because the respective transistor cells and their associated fingers and contacts are heated not only by their own current consumption but also by the current consumption of adjacent transistor cells. Therefore, sufficient distance should exist between transistor cells and, consequently, between gate fingers, to ensure reliable operation.

[0019] There is a continued demand for increasing the power density achievable using field-effect transistors. This power density is determined by the semiconductor technology used, such as GaN FETs or Si LDMOS, and the layout of the field-effect transistors themselves.

[0020] A field-effect transistor is known from US 6081006A. Another field-effect transistor is known from US 2018 / 190777A1. Summary of the Invention

[0021] According to the present invention, a field-effect transistor (FET) is provided that exhibits improved power density by using a different FET layout. The FET is characterized in that each first transistor cell further includes a main gate finger base connected to and extending from a main gate finger segment of the first transistor cell toward a main drain finger segment of the first transistor cell, wherein the main gate finger base is connected to one or more gate fingers. Similarly, each first transistor cell includes a main drain finger base connected to and extending from a main drain finger segment of the first transistor cell toward a main gate finger segment of the first transistor cell, wherein the drain gate finger base is connected to one or more drain fingers.

[0022] According to the invention, one or more gate fingers and main gate finger segments of each first transistor unit extend in the same direction, and one or more drain fingers and main drain finger segments of each first transistor unit extend in a direction opposite to the same direction. Furthermore, substantially all gate fingers electrically connected to the gate bar extend away from the base of the main gate finger connected to the gate finger in the same direction, and substantially all drain fingers electrically connected to the drain bar extend away from the base of the main drain finger connected to the drain finger in a direction opposite to the same direction.

[0023] In the context of this invention, if a vector starting from a point on one side of a component, such as a gate finger or drain finger, that connects to another component and terminating at a point on the opposite side of that component points in the same direction as a given direction, then that component can be said to extend away from the other component along said given direction. For example, a gate finger extending from the base of the main gate finger in a left-to-right direction corresponds to a gate finger disposed on the right side of the base of the main gate finger, while a gate finger extending from the base of the main gate finger in a right-to-left direction, i.e., in the opposite direction to the left-to-right direction, corresponds to a gate finger disposed on the left side of the base of the main gate finger.

[0024] The applicant has discovered that improved gain can be obtained by arranging the gate and drain fingers in the manner described above. The following will refer to... Figure 3 The following describes the improvement. In this figure, a first transistor unit 100 is shown, wherein the main gate finger segment 101 is connected to two gate fingers 102 via a main gate finger base 103. Similarly, the main drain finger segment 104 is connected to two drain fingers 105 via a main drain finger base 106. Together with the two active regions 107A and 107B, two transistor units are formed.

[0025] During operation, a gate signal is provided to the main gate finger segment 101 via the gate bar. For example, the gate signal will appear at point S1. This signal will propagate through the main gate finger base 103 and the gate finger 102. At the RF frequency, there will be a non-negligible phase delay between the signals at points p2 and p3. More specifically, the signal at point p3 will lag behind the signal at point p2. Therefore, locally, the drain signals at points p1 and p4 will be controlled by gate signals of different phases. For example, the control of the drain current at point p4 will lag behind the control of the drain current at point p1. However, due to the arrangement of the gate finger 102 and the drain finger 105, the drain currents will add up substantially in phase at point S2. More specifically, the smaller delay of the drain current between points S2 and p4 compared to the delay between points S2 and p1 substantially compensates for the time delay in controlling the drain current at point p4. Since the drain currents add in phase at point S2, the field-effect transistor will exhibit increased gain. Therefore, for the same current consumption, higher output power can be obtained. In other words, the field-effect transistor of this invention allows for increased power density.

[0026] Those skilled in the art will readily understand that the aforementioned advantageous behavior will also be achieved if only a few gate fingers and / or a few drain fingers are not arranged in the manner described above, while the remaining gate fingers and drain fingers are arranged in the manner described above. According to the invention, substantially all gate fingers electrically connected to the gate bar should be arranged in the manner described above. This also applies to drain fingers electrically connected to the drain bar. Here, it should be noted that the gate fingers are electrically connected to the gate bar via the base of the main gate finger and the main gate finger, and the drain fingers are electrically connected to the drain bar via the base of the main drain finger and the main drain finger.

[0027] The proposed arrangement of gate and drain fingers according to the present invention can sizing the size of an RF FET architecture that allows for more active regions on a single chip layout, thereby enabling increased die size and increased total output power per chip.

[0028] Preferably, more than 75% of the gate fingers electrically connected to the gate bar, more preferably more than 90%, and most preferably all gate fingers extend in the same direction. Furthermore, preferably, more than 75% of the drain fingers electrically connected to the drain bar, more preferably more than 90%, and most preferably all drain fingers extend in a direction opposite to the same direction.

[0029] The gate bar may extend along a first direction, and the drain bar may be spaced apart from the gate bar along a second direction perpendicular to the first direction, and may also extend along the first direction. Alternatively, each transistor cell array in at least one transistor cell array may be arranged between the gate bar and the drain bar.

[0030] The aforementioned same direction can correspond to the second direction. Furthermore, the main drain finger segment and the main gate finger segment of each first transistor cell unit can be spaced apart along the first direction. In this case, for each first transistor cell unit, the main gate finger base can extend from the main gate finger segment toward the main drain finger segment in a direction opposite to the second direction, while the main drain finger base extends from the main drain finger segment toward the main gate finger segment along the second direction. Alternatively, for each first transistor cell unit, the main gate finger base can extend from the main gate finger segment toward the main drain finger segment along the second direction, while the main drain finger base extends from the main drain finger segment toward the main gate finger segment in a direction opposite to the second direction.

[0031] A transistor cell may include a second transistor cell unit, wherein the second transistor cell unit is a mirror copy of the first transistor cell unit along a main gate finger segment of the first transistor cell unit, wherein the first and second transistor cell units are arranged adjacent to each other along a first direction and share the main gate finger segment. Alternatively, a transistor cell may include a second transistor cell unit, which is a mirror copy of the first transistor cell unit along a main drain finger segment of the first transistor cell unit, wherein the first and second transistor cell units are arranged adjacent to each other along a first direction and share the main drain finger segment.

[0032] Field-effect transistors can be easily scaled by comprising a plurality of transistor cell arrays arranged spaced apart from each other along a first direction. In this case, the field-effect transistor may comprise at least one pair of transistor cell arrays that share a main input finger segment or a main output finger segment.

[0033] To reduce the feedback capacitance of a field-effect transistor, one or more transistor cell arrays in at least one transistor cell array may include at least one first ground shield disposed on a semiconductor substrate, the at least one first ground shield being associated with a pair of adjacent first transistor cell units and disposed between the main drain finger base of one first transistor cell unit and the main gate finger base of the other first transistor cell unit. Alternatively, one or more transistor cell arrays in at least one transistor cell array may include at least one second ground shield disposed on a semiconductor substrate, the at least one second ground shield being associated with a pair of adjacent second transistor cell units and disposed between the main drain finger base of one second transistor cell unit and the main gate finger base of the other second transistor cell unit.

[0034] To reduce the feedback capacitance of the field-effect transistor (FET), for one or more transistor cell arrays in at least one transistor cell array, the FET may further include at least one third ground shield disposed on a semiconductor substrate between the drain bar and the main gate finger segment of the first transistor cell unit of the transistor cell directly adjacent to the drain bar in the one or more transistor cell arrays; and / or at least one fourth ground shield disposed on a semiconductor substrate between the gate bar and the main drain finger segment of the first transistor cell unit of the transistor cell directly adjacent to the gate bar in the one or more transistor cell arrays. For one or more transistor cell arrays in at least one transistor cell array, the FET may additionally or alternatively include at least one fifth ground shield disposed on a semiconductor substrate between the gate bar and the main gate finger segment of the second transistor cell unit of the transistor cell directly adjacent to the drain bar in the one or more transistor cell arrays; and / or at least one sixth ground shield disposed on a semiconductor substrate between the gate bar and the main drain finger segment of the second transistor cell unit of the transistor cell directly adjacent to the gate bar in the one or more transistor cell arrays.

[0035] Each first transistor cell unit and each second transistor cell unit (where applicable) may include one or more corresponding source fingers, the source fingers extending parallel to one or more gate fingers in the first or second transistor cell unit, respectively. Each source finger may be associated with a gate finger and a drain finger to form a transistor cell. Furthermore, the source finger may extend between its associated gate finger and drain finger.

[0036] The main gate finger segment, main drain finger segment, main gate finger base, main drain finger base, one or more gate fingers, one or more drain fingers, optional one or more source fingers, and optional first to sixth ground shields of each first transistor unit and / or second transistor unit may each be formed using one or more metals from the same metal stack.

[0037] The transistor can be a laterally diffused metal-oxide-semiconductor transistor, "LDMOS," preferably silicon-based LDMOS, or a high electron mobility transistor, "HEMT," preferably gallium nitride-based HEMT. However, other transistor technologies are not included. For example, the invention can also be applied to bipolar transistors. Typically, a transistor has an input and an output corresponding to the aforementioned gate and drain of a field-effect transistor, respectively. Therefore, the invention can be applied to any transistor technology, provided that in the above description, the term "gate" is replaced by "input" and the term "drain" is replaced by "output."

[0038] The combined length of all gate fingers can exceed 1 mm, and / or the combined length of all drain fingers can exceed 1 mm, and / or the operating frequency of the transistor can exceed 500 MHz.

[0039] According to a second aspect, the present invention provides a packaged transistor comprising a conductive substrate and a field-effect transistor as defined above, mounted on the conductive substrate. The packaged transistor further includes a gate lead and a drain lead, both of which are isolated from the conductive substrate by a dielectric separator. Furthermore, the packaged transistor includes one or more gate junction lines directly or indirectly connecting the gate strip of the field-effect transistor to the gate strip, and one or more drain junction lines directly or indirectly connecting the drain strip of the field-effect transistor to the drain strip.

[0040] According to a third aspect, the present invention provides an electronic device comprising a field-effect transistor or a packaged field-effect transistor as defined above. The device is preferably a base station for mobile telecommunications, radar, or a solid-state triggering (cocking) device. Attached Figure Description

[0041] The invention will now be described in more detail with reference to the accompanying drawings, in which:

[0042] Figure 1A and Figure 1B A top view of a cross-section of a known LDMOS transistor and its gate contacts is shown;

[0043] Figure 2A and Figure 2B A known arrangement of field-effect transistors and a known implementation of that arrangement are shown;

[0044] Figure 3 The transistor cell unit according to the present invention is shown;

[0045] Figures 4A-4C Three different arrangements of the field-effect transistor according to the present invention are shown, including... Figure 3 transistor units; and

[0046] Figure 5 A packaged transistor according to the present invention is shown. Detailed Implementation

[0047] Figure 4A A first arrangement of a field-effect transistor 150 according to the present invention is shown, including... Figure 3 The transistor 150 includes a transistor cell array comprising three transistor cells, each comprising a first transistor cell unit 100A and a second transistor cell unit 100B. The main gate finger segment of the first transistor cell unit 100A is electrically connected. Furthermore, on the left side, a connection is established between the main gate finger segment of the outer left first transistor cell unit 100A and the gate strip 108 using a connecting block 108A. Similarly, the main drain finger segment of the first transistor cell unit 100A is electrically connected. Furthermore, on the right side, a connection is established between the main drain finger segment of the outer right first transistor cell unit 100A and the drain strip 109 using a connecting block 109A.

[0048] An isolation shield (illustrated as a hash rectangle) is provided to isolate the gate and drain of transistor 150. For example, a shield 110A is provided between gate bar 108 and the main drain finger segment of outer left first transistor cell 100A. A shield 110B is also provided between drain bar 109 and the main gate finger segment of outer right first transistor cell 100A.

[0049] A shield 110C is also provided between the main gate finger base of the first transistor unit 100A and the main drain finger base of the adjacently arranged first transistor unit 100A. Finally, a shield 110D is also provided between the main drain finger segment of the first transistor unit 100A and the main gate finger segment of the second transistor unit 100B. It should be noted that, as explained, a shield can be provided for the second transistor unit 100B in a similar manner to that for the first transistor unit 100A. Furthermore, in each case, the shields 110A-100D can be implemented using a grounded metal structure in the upper layer of the metal stack.

[0050] Figure 4A It is shown that the second transistor unit 100B is a copy of the first transistor unit 100A. However, in Figure 4B In this configuration, the second transistor unit 100B is a mirror image of the first transistor unit 100A along a line passing through the main gate finger segment of the first transistor unit 100A. Furthermore, the main gate finger segments of the first and second transistor units 100A and 100B are shared. Figure 4CIn this configuration, the second transistor unit 100B is a mirror copy of the first transistor unit 100A along a line passing through the main drain finger segment of the first transistor unit 100A. Furthermore, the main drain finger segments of the first and second transistor units 100A and 100B are shared.

[0051] It can be easily verified that, for Figures 4A-4C Each arrangement in the design minimizes and / or avoids phase delay between signals, such as by combining Figure 3 The explanation given.

[0052] Figure 5 A packaged transistor 200 according to the present invention is shown. Figure 5 The illustrated packaged transistor 200 includes a semiconductor die 201 on which a field-effect transistor 202 is implemented, such as having Figures 4A-4C The field-effect transistor (FET) is arranged as shown. A semiconductor die 201 is mounted on a conductive substrate 203, such as copper or a copper-based flange. A connection between the FET 202 and the outside world is established using a bonding wire 204 that forms a connection between the gate and input lead 205 of the FET 202. Similarly, a connection is established between the drain and output lead 207 of the FET 202 using a bonding wire 206. In other embodiments, additional circuitry, such as matching circuitry, may be arranged within the package transistor 200 between the drain and output lead 207 of the FET 202 and / or between the input lead 205 and the gate of the FET 202.

[0053] Dielectric separators are used to separate leads 205, 207 from substrate 203. For example, ceramic rings or cured molding compounds can be used to electrically isolate leads 205, 207 from substrate 203. Typically, leads 206, 207 and substrate 203 are fixedly connected to such dielectric separators.

[0054] It should be noted that the present invention is not limited to the combination of Figure 5 Explanation of packaging technology. Other packaging technologies, such as Quadrature Flat No-Lead (QFN) or Dual Flat No-Lead (DFN) packages, can also benefit from the transistor arrangement of this invention.

[0055] The present invention is particularly advantageous when used in high-power RF applications such as RF power amplifiers. For example, the invention can be applied to silicon-based laterally diffused metal-oxide-semiconductor “LDMOS” transistors or gallium nitride-based field-effect transistors “FETs”. Such transistors can be configured to operate in a frequency range of 500 MHz to 100 GHz and at high power >10 W, thus the phase delay associated with large finger lengths must be taken into account.

[0056] This invention is not limited to field-effect transistors. Other transistor technologies that use input and output fingers in a similar manner can also benefit from this invention.

[0057] Finally, it should be noted that the present invention is not limited to the embodiments shown, but various modifications can be made to these embodiments without departing from the scope of the invention, which is defined by the appended claims and their equivalents.

Claims

1. A field-effect transistor (150) comprising a semiconductor substrate, wherein: At least one transistor cell array, each transistor cell array comprising a plurality of adjacently arranged interconnected transistor cells, each transistor cell comprising a first transistor cell unit (100), wherein, Each first transistor unit includes: Multiple gate fingers (102), main gate finger segments (101), multiple drain fingers (105) and main drain finger segments (104), wherein all of the multiple gate fingers, the main gate finger segments, the multiple drain fingers and the main drain finger segments extend in parallel; A main gate finger base (103) is connected to the main gate finger segment of the first transistor unit and extends from the main gate finger segment toward the main drain finger segment of the first transistor unit. The main gate finger base is connected to the plurality of gate fingers. A main drain finger base (106) is connected to a main drain finger segment of a first transistor unit and extends from the main drain finger segment toward a main gate finger segment of the first transistor unit. The main drain finger base is connected to the plurality of drain fingers, and the main drain finger base and the main gate finger base are arranged at a distance from and parallel to each other. The gate fingers extend from the main gate finger base toward the main drain finger base, and the drain fingers extend from the main drain finger base toward the main gate finger base. The gate fingers and the drain fingers are each sufficiently arranged in the space between the main gate finger base and the main drain finger base. The main gate finger segments of adjacent first transistor unit units are electrically connected to form main gate fingers, and the main drain finger segments of adjacent first transistor unit units are electrically connected to form main drain fingers. The field-effect transistor further includes a gate strip (108) connected to the main gate finger and a drain strip (109) connected to the main drain finger. Wherein, all gate fingers electrically connected to the gate bar extend in the same direction away from the base of the main gate finger connected to the gate finger; and Among them, all drain fingers electrically connected to the drain bar extend away from the base of the main drain finger connected to the drain finger in a direction opposite to the same direction.

2. The field-effect transistor according to claim 1, wherein, The gate bar and the drain bar extend in parallel, and wherein the drain bar is spaced apart from the gate bar in a direction corresponding to the same direction.

3. The field-effect transistor according to claim 2, wherein, Each of the at least one transistor cell arrays is arranged between the gate bar and the drain bar.

4. The field-effect transistor according to claim 2, wherein, The transistor unit includes a second transistor unit (100B), wherein the second transistor unit is a mirror copy of the first transistor unit along the main gate finger segment of the first transistor unit, wherein the first transistor unit and the second transistor unit share the main gate finger segment; or The transistor unit includes a second transistor unit, which is a mirror copy of the first transistor unit along the main drain finger segment of the first transistor unit, wherein the first transistor unit and the second transistor unit share the main drain finger segment.

5. The field-effect transistor according to claim 2, comprising a plurality of said transistor cell arrays.

6. The field-effect transistor of claim 5, wherein the plurality of transistor cell arrays comprises at least one pair of transistor cell arrays, the at least one pair of transistor cell arrays sharing a main gate finger segment or a main drain finger segment.

7. The field-effect transistor according to claim 1, wherein, One or more transistor cell arrays in the at least one transistor cell array include: At least one first ground shield (110C) is disposed on the semiconductor substrate, the at least one first ground shield being associated with a pair of adjacently arranged first transistor unit units and disposed between the main drain finger base of one first transistor unit unit and the main gate finger base of the other first transistor unit unit.

8. The field-effect transistor according to claim 4, wherein, One or more of the at least one transistor cell arrays include at least one second ground shield disposed on the semiconductor substrate, the at least one second ground shield being associated with a pair of adjacently arranged second transistor cell units and disposed between the main drain finger base of one second transistor cell unit and the main gate finger base of the other second transistor cell unit.

9. The field-effect transistor of claim 1, wherein for one or more transistor cell arrays in the at least one transistor cell array, the field-effect transistor further comprises: At least one third ground shield (110B) disposed on the semiconductor substrate between the main gate finger segments of the first transistor unit of the transistor unit directly adjacent to the drain bar in one or more transistor unit arrays, and / or at least one fourth ground shield (110A) disposed on the semiconductor substrate between the main drain finger segments of the first transistor unit of the transistor unit directly adjacent to the drain bar in one or more transistor unit arrays.

10. The field-effect transistor of claim 8, wherein for one or more transistor cell arrays in the at least one transistor cell array, the field-effect transistor further comprises: At least one fifth ground shield, the fifth ground shield being disposed on the semiconductor substrate between the main gate finger segment of the second transistor unit of the transistor unit directly adjacent to the drain bar in one or more transistor unit arrays; and / or at least one sixth ground shield, the sixth ground shield being disposed on the semiconductor substrate between the main drain finger segment of the second transistor unit of the transistor unit directly adjacent to the gate bar in one or more transistor unit arrays.

11. The field-effect transistor according to claim 1, wherein, Each first transistor unit includes a plurality of source fingers extending parallel to a plurality of gate fingers in the first transistor unit, each source finger being associated with a gate finger and a drain finger to form a transistor unit; The source finger extends between the gate finger and the drain finger associated with the source finger.

12. The field-effect transistor according to claim 1, wherein, Each of the main gate finger segment, main drain finger segment, main gate finger base, main drain finger base, multiple gate fingers, and multiple drain fingers of the first transistor unit is formed using one or more metals from the same metal stack.

13. The field-effect transistor according to claim 1, wherein, The field-effect transistor is a laterally diffused metal-oxide-semiconductor transistor "LDMOS" or a high electron mobility transistor "HEMT"; Wherein, the combined length of all gate fingers exceeds 1 mm, and / or the combined length of all drain fingers exceeds 1 mm, and / or the operating frequency of the field-effect transistor exceeds 500 MHz.

14. A packaged field-effect transistor (200), comprising: Conductive substrate (203); The field-effect transistor (202) as defined in any one of claims 1 to 13 is mounted on the conductive substrate; Gate lead (205) and drain lead (207), both of which are isolated from the conductive substrate by a dielectric separator; One or more gate bonding wires (204) directly or indirectly connect the gate strip of the field-effect transistor to the gate lead, and One or more drain connection wires (205) directly or indirectly connect the drain strip of the field-effect transistor to the drain lead.

15. An electronic device comprising a field-effect transistor as defined in any one of claims 1 to 13, wherein the device is a base station for mobile telecommunications, a radar, or a solid-state triggering device.

16. An electronic device comprising a packaged field-effect transistor according to claim 14, the device being a base station for mobile telecommunications, radar, or a solid-state triggering device.

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