Circuit used to transfer data from one clock domain to another

Abstract

The present invention relates to a circuit for transmitting data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal and receive such data by sampling the data signal synchronously with a target clock signal, wherein the conversion of the data signal is synchronized with a source clock signal; a phase comparator configured to determine the phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive the data signal and provide a synchronized data signal on this basis, wherein the conversion of the data signal is synchronized with the source clock signal, and the conversion of the synchronized data signal is synchronized with the target clock signal; wherein the data signal synchronization circuit is configured to switch between providing a synchronized data signal based on sampling of the data signal in response to a rising edge of the target clock signal and providing a synchronized data signal based on sampling of the data signal in response to a falling edge of the target clock signal according to the determined phase relationship between the source clock signal and the target clock signal; wherein the determined phase relationship between the source clock signal and the target clock signal is a predetermined frequency relationship between the source clock signal and the target clock signal.

Description

Technical Field

[0001] The present invention relates to a circuit for transferring data from one clock domain to another clock domain, a test apparatus for testing a device under test, and a method for transferring data from one clock domain to another clock domain. Background Art

[0002] As modern system-on-chip (SoC) designs continue to face increasing size and complexity challenges, multiple asynchronous clock domains have been adopted for different I / O interfaces. A CDC (clock domain crossing) based design is one in which one clock is asynchronous with another clock or has a variable phase relationship with another clock. Transferring signals between asynchronous clock domains may cause setup or hold timing violations. These violations may cause signals to be metastable. Even though synchronizers can eliminate metastability, improper usage, such as convergence of synchronization signals or incorrect synchronization protocols, may cause functional CDC errors. Functional verification of such SoC designs is one of the most complex and expensive tasks.

[0003] Within a clock domain, proper static timing analysis (STA) can ensure that data does not change during the clock setup and hold time. When a signal is transferred from one clock domain to another asynchronous domain, metastability cannot be avoided because the data may change at any time.

[0004] Since CDC errors are not addressed and verified early in the design cycle, many designs exhibit functional errors only late in their design cycle or during post-silicon verification. Several coverage metrics have been proposed to measure the adequacy and progress of verification, such as code-based coverage, finite state machine coverage, and functional coverage. However, these coverage metrics are not directly related to CDC issues.

[0005] Furthermore, in the system used to test the device, it has a signal driven by a flip-flop on the source domain (e.g. SYNCCLK), which is the start signal for the test, e.g. TEST_EN. This start signal must be transferred to the target clock domain, e.g. FIFOCLK, which has the same clock frequency as SYNCCLK, but with an unknown phase relationship to SYNCCLK. During testing, SYNCCLK will be turned on and off for each individual test run. This means that for each test, the phase relationship will be different, so it is not possible to solve the clock domain transition with a static solution, such as that done by STA, as this cannot adapt to phase changes.

[0006] The most common solution to the above problem is Fig.15 The dual trigger circuit solution shown in Fig.15The downside is that the received signal has a 2 clock cycle ambiguity in time when transitioning across clock domains. This happens whenever the signal changes in the setup / hold time window around the capture clock edge. In this case, it is unknown whether the old or new state of the signal is being captured. Metastability is not the only root cause of this randomness. Jitter, signal noise, and power noise also contribute to it. But ultimately, this means that it is not possible to start the test at the desired clock cycle.

[0007] The solution to remove this ambiguity is to use a PLL that shifts one of the two clock domains in phase (not frequency) so that the setup and hold time criteria of the receiving clock domain are met, such as Fig.15 The disadvantage of this is that the PLL settling time is very long (several milliseconds) and one PLL is required for each clock domain crossing. For high-speed testing, this is unacceptable.

[0008] In order to accurately verify clock domain crossings, it is necessary to avoid ambiguity in when the signal is sampled. This ambiguity occurs whenever the signal violates the setup / hold criteria at the capture FF. In this case, metastability may occur, making it impossible to predict the logic level being captured. This uncertainty lasts for one clock cycle. This results in a timely ambiguity in the captured signal of 2 clock cycles.

[0009] A conventional circuit for transferring data from one clock domain to another, such as the Fig.16 Shown and Fig.17 The circuit shown requires resynchronization at every phase change of SYNCCLK. That is, the synchronization / resynchronization of each new test run requires a PLL settling time of about 1ms. The first input data marks the beginning of the waveform, so strict timing is required at the data interface. That is, if Fig.15 As shown, FF 1 determines the enable transition and phase detector PD ensures known phase alignment. Clock 3 is delayed Clock 1 (n=1) or a multiple of Clock 1 (n>1).

[0010] It is therefore an object of the present invention to avoid these disadvantages and therefore to provide an improved circuit concept for transferring data from one clock domain to another with exact timing.

[0011] This object is solved by a circuit for transferring data from one clock domain to another clock domain according to the present application, a test device for testing a device under test according to the present application comprising a circuit according to the present application, and a method for transferring data from one clock domain to another clock domain according to the present application.

[0012] Some embodiments of the present invention also provide a computer program for executing the steps of the method of the present invention. Summary of the invention

[0013] According to a first aspect of the present application, a circuit for transferring data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal and receive such data by sampling the data signal synchronously with a target clock signal (e.g., a clock signal indicating a timing for receiving provided data), wherein the conversion of the data signal is synchronized with a source clock signal (e.g., a clock signal indicating a timing for outputting data based on input data values ​​associated with sampling times on a time grid (e.g., equidistant in time)); a phase comparator, for example, coupled to a processor to receive a synchronous clock signal, and coupled to a converter to receive a converter clock signal, wherein the phase comparator is configured to determine a phase relationship between the source clock signal and the target clock signal, that is, the phase comparator performs an upper phase comparison between the synchronous clock signal and the converter clock signal. A timing comparison of a rising edge or a falling edge, thereby performing a phase comparison between signals; and a data signal synchronization circuit, for example, comprising a first flip-flop FF, a selector and a second flip-flop FF, configured to receive a data signal (for example, provided synchronously with a synchronous clock signal) and provide a synchronous data signal on this basis, wherein the conversion of the data signal is synchronized with the source clock signal, and the conversion of the synchronous data signal is synchronized with the target clock signal; wherein the data signal synchronization circuit is configured to switch between providing a synchronous data signal based on sampling of the data signal in response to a rising edge of the target clock signal and providing a synchronous data signal based on sampling of the data signal in response to a falling edge of the target clock signal according to a determined phase relationship between the source clock signal and the target clock signal; wherein there is a predetermined frequency relationship between the source clock signal and the target clock signal, for example, locked at a predetermined value.

[0014] According to an embodiment of the present application, the data signal synchronization circuit is configured to select between the following items based on information about the phase relationship between the source clock signal and the target clock signal: a first mode, in which the data signal synchronized in time with the source clock signal is sampled at an edge of a first edge type of the target clock signal (for example, at a falling edge) to obtain an intermediate signal, and wherein the intermediate signal is sampled at an edge of a second edge type of the target clock signal (for example, a rising edge) to obtain a synchronized data signal synchronized in time with the target clock signal; and a second mode, in which the data signal synchronized in time with the source clock signal is sampled at an edge of a second edge type of the target clock signal (for example, a rising edge) to obtain a synchronized data signal synchronized in time with the target clock signal.

[0015] According to an embodiment of the present application, the data signal synchronization circuit includes: a first trigger circuit, configured to receive the data signal, for example, it is a test signal on a different clock domain from the converter clock signal and is provided by a processor for aligning the output timing of the signal data, wherein the first trigger circuit is configured to sample the data signal at a first sampling phase, for example, when the phase relationship indicates that the value of the phase difference between the synchronous clock signal and the converter clock signal is within a first predetermined range (for example, less than a predetermined value), if the phase difference has a potential risk of causing a metastable state, the phase of the sampling enable signal is inverted to make the sampling time away from the clock edge of the synchronous clock signal to obtain a sampling signal; a signal selector, configured to receive the data signal and couple to the first trigger circuit. A trigger circuit is provided to receive the sampling signal, wherein the signal selector is configured to select one of the received signals according to a phase relationship, for example, to obtain a selection signal; a second trigger circuit is coupled to the signal selector to receive the selection signal, wherein the second trigger circuit is configured to sample the selection signal (for example, a data signal, or a sampling signal) in a second sampling phase, for example, when the phase relationship is within a second predetermined range, the second predetermined range is different from the first predetermined range and generally does not overlap with the first predetermined range, and for example can indicate that the value of the phase difference between the synchronous clock signal and the converter clock signal is greater than a predetermined value; in this case, the edge of the sampling signal is synchronized with the converter clock signal, that is, the output timing of the signal is aligned, so there is no need to align the rising timing of the clock signal.

[0016] According to an embodiment of the present application, wherein the source clock signal is provided from or used by a device, for example, from a processor, or a memory, or a loopback interface, etc., wherein the digital circuit is a converter configured to convert data between analog and digital (for example, between digital representation and analog representation, for example, from digital representation to analog representation or from analog representation to digital representation), and wherein the data signal is an enable signal for analog / digital conversion of a trigger signal, that is, the enable signal is provided synchronously with the synchronization clock signal.

[0017] According to an embodiment of the present application, the data signal synchronization circuit also includes: a first-in-first-out circuit, coupled to a data source, such as the digital signal processor, to receive the signal data, and coupled to the second trigger circuit, which calculates a delay time based on a phase difference between an enable signal and a converter clock signal to receive an output signal of the second trigger, or a delayed version of the output signal of the second trigger circuit, for example, indicating the signal data output timing of the converter, wherein the first-in-first-out circuit provides signal data to the converter in response to the output signal of the second trigger circuit.

[0018] According to an embodiment of the present application, the first-in-first-out circuit is coupled to the output of the second flip-flop circuit via a delay circuit, and the delay circuit delays the output signal of the second flip-flop circuit, for example, according to the conversion data clock signal. In addition, the selector includes a multiplexer, wherein the multiplexer selects one of the input signals based on the information about the phase relationship.

[0019] According to an embodiment of the present application, the phase comparator comprises a phase digital converter, wherein the phase digital converter is configured to measure a phase difference between the source clock signal and the target clock signal for determining the phase relationship. In addition, the circuit comprises an oscillator, wherein an output signal of the oscillator is used as the target clock signal, or wherein the circuit is configured to derive the target clock signal from the output signal of the oscillator.

[0020] According to an embodiment of the present application, the circuit is configured to derive the source clock signal and the target clock signal from a common reference signal, such that the frequencies of the source clock signal and the target clock signal are in a predetermined relationship, for example, are adjusted to be in a predetermined relationship, and such that there is no phase lock between the phase of the source clock signal and the phase of the target clock signal, for example, such that the phases of the synchronization clock signal and the converter clock signal can float freely relative to each other. In addition, the converter is a digital-to-analog converter or an analog-to-digital converter.

[0021] In a second aspect of the present application, a test device for testing a device under test comprises a circuit according to the present application. According to an embodiment of the present application, the test device is configured to execute, for example, start a test process synchronously with the source clock signal, for example, a test process using multiple channel modules that provide signals to the device under test and evaluate signals received from the device under test.

[0022] According to an embodiment of the present application, the test device is configured to provide an analog signal obtained using the converter based on a signal value provided by the device to the device under test, for example, thereby simulating the device under test, and / or wherein the device is configured to obtain digital data, for example, provided by a data source (i.e., a digital signal processor), based on a digitized device under test signal obtained from a digital circuit using fractional delay filtering, and evaluate the digital data, for example, to characterize the device under test.

[0023] According to the third aspect of the present application, a method for transmitting data from one clock domain to another clock domain, the method comprising: receiving a source clock signal from or used by a device and a target clock signal used by a digital circuit; determining the phase relationship between the source clock signal and the target clock signal; receiving a data signal from the device and providing a synchronous data signal on this basis; and switching between providing a synchronous data signal based on sampling of the data signal in response to a rising edge of the target clock signal and providing a synchronous data signal based on sampling of the data signal in response to a falling edge of the target clock signal according to the determined phase relationship between the source clock signal and the target clock signal; wherein the frequency relationship between the source clock signal and the target clock signal is locked at a predetermined value.

[0024] According to a fourth aspect of the present application, a computer program is provided, wherein the computer program is configured to implement the above method when running on a computer or a microcontroller, so that the above method is executed by the computer program. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the following, embodiments of the present application are described in more detail with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic block diagram of a circuit for transmitting data from one clock domain to another clock domain according to a first embodiment of the present invention of the present application is shown;

[0027] Figure 2 shows a schematic timing diagram of a phase comparator according to a first embodiment of the present invention of the present application;

[0028] Figure 3 The invention according to the present application is shown Figure 2 A schematic block diagram of a phase comparator;

[0029] Figure 4 A block diagram of a circuit for transmitting data from one clock domain to another clock domain according to a second embodiment of the present invention of the present application is shown;

[0030] Figure 5 A schematic block diagram of a testing device for testing a device under test according to a third embodiment of the present invention of the present application is shown;

[0031] Figure 6 A schematic timing diagram is shown for explaining a normal resynchronization process without giving any ambiguity;

[0032] Figure 7 shows a schematic timing diagram of a third embodiment of the present invention according to the present application;

[0033] Figure 8 A schematic diagram showing the operation of a processing block that may be implemented in one of the embodiments of the present application;

[0034] Fig. 9 Shows Figure 8 A schematic timing diagram of operation situation 1 shown in the schematic diagram;

[0035] Fig.10 Shows Figure 8 A schematic timing diagram of operation situation 2 shown in the schematic diagram;

[0036] Fig.11 Shows Figure 8 A schematic timing diagram of operation situation 3 shown in the schematic diagram;

[0037] Fig.12 Shown Figure 8 Schematic diagram of the operating range for all three cases indicated in the schematic diagram of ;

[0038] Fig.13 A flowchart indicating steps of a method for transferring data from one clock domain to another clock domain according to a fourth embodiment of the inventive concept of the present application is shown;

[0039] Fig.14 A schematic block diagram showing a circuit for transferring data from one clock domain to another clock domain according to a modified embodiment of the present invention of the present application;

[0040] Fig.15 A schematic block diagram and a schematic timing diagram of an example according to the prior art are shown;

[0041] Fig.16 A schematic block diagram showing an example according to the prior art to avoid ambiguity; and

[0042] Fig.17 A schematic timing diagram according to the prior art is shown. DETAILED DESCRIPTION

[0043] The following description sets forth specific details such as particular embodiments, processes, techniques, etc. for purposes of explanation and not limitation. Those skilled in the art will appreciate that other embodiments may be employed in addition to these specific details. For example, although non-limiting example applications are used to facilitate the following description, the techniques may be used for any type of converter. In some cases, detailed descriptions of well-known methods, interfaces, circuits, and devices are omitted so as not to obscure the description with unnecessary detail.

[0044] Identical or equivalent elements having the same or equivalent functions are denoted by the same or equivalent reference numerals in the following description.

[0045] Figure 1 FIG. 1 is a schematic block diagram of a circuit for transmitting data from one clock domain to another clock domain according to a first embodiment of the present invention. The circuit 100 comprises a digital circuit 4 , a phase comparator PDC 6 and a data signal synchronization circuit 8 .

[0046] The digital circuit 4, i.e. another clock domain, is coupled to the PDC 6 and provides a target clock signal to the PDC 6. In addition, the digital circuit 4 is coupled to the data signal synchronization circuit 8 and receives a synchronized data signal, i.e. the digital circuit 4 is configured to generate data signal transitions synchronized with the source clock signal and receive such data by sampling the data synchronously with the target clock signal. The digital circuit may be a converter, i.e. a digital-to-analog or analog-to-digital converter.

[0047] The PDC 6 is coupled to the digital circuit 4 to receive a target clock signal, such as a converter clock signal in the case where the digital circuit 4 is a converter, and receives a source clock signal, such as a synchronous clock signal, which is a clock signal for indicating a timing for outputting data from one clock domain based on input data values ​​associated with sampling times on a time grid (e.g., equally spaced in time). The PDC 6 is configured to perform a timing comparison of a rising edge or a falling edge between the source clock signal (e.g., the synchronous clock signal) and the target clock signal (e.g., the converter clock signal), thereby performing a phase comparison between the signals. That is, the circuit 100 is configured to select between a first mode and a second mode based on information about a phase relationship between the synchronous clock signal and the converter clock signal, in which the enable signal that triggers data conversion between digital and analog and is synchronized in time with the synchronous clock signal is sampled at an edge of a first edge type (e.g., a falling edge) of the converter clock signal to obtain an intermediate signal, and the intermediate signal is sampled at an edge of a second edge type (e.g., a rising edge) of the converter clock signal to obtain the enable signal that is synchronized in time with the converter clock signal, and in which the enable signal that triggers data conversion between digital and analog and is synchronized in time with the synchronous clock signal is sampled at an edge of a second edge type of the converter clock signal to obtain the enable signal that is synchronized in time with the converter clock signal.

[0048] As described above, the PDC 6 detects, for example, a phase difference between the synchronization clock signal and the converter clock signal. Furthermore, the PDC 6 comprises a phase digitizer, wherein the phase digitizer is configured to measure the phase difference between the synchronization clock signal and the converter clock signal for determining the phase relationship.

[0049] The data signal synchronization circuit 8 is coupled to the PDC 6 to receive information about the phase relationship, such as the phase difference between the synchronization clock signal and the target clock signal, and is configured to receive a data signal provided in synchronization with the source clock signal, and provide a synchronized data signal based on this, wherein the transition of the data signal is synchronized with the source clock signal, and the transition of the synchronized data signal is synchronized with the target clock signal. In addition, the data signal synchronization circuit 8 is configured to switch between providing a synchronized data signal based on sampling of the data signal in response to a rising edge of the target clock signal and providing a synchronized data signal based on sampling of the data signal in response to a falling edge of the target clock signal according to the determined phase relationship between the source clock signal and the target clock signal.

[0050] Figure 2 shows a schematic timing diagram of the PDC 6, and Figure 3 FIG. 6 shows a schematic block diagram of PDC 6. Figure 2 and Figure 3As shown, the reference clock signal REFCLK / REF_CLK and the measurement clock signal MEASCLK / MEAS_CLK are provided to PDC 6. PDC 6 then passes the delay between the rising edge of REF_CLK (i.e., the rising edge of the reference clock signal) to the rising edge of MEAS_CLK (i.e., the rising edge of the measurement clock signal). As mentioned above, PDC 6 determines the phase difference between MEASCLK and REFCLK. This phase difference can be calculated as: Phase = Delay / Period. Delay is the absolute time difference between the two clock edges. Therefore, when the fractional nature of the digital signal processor DSP enters the game, PDC 6 must be accurate. For a simple decision of which clock edge to use to capture a data signal, the PDC accuracy does not have to be very high.

[0051] According to the first embodiment of the present invention, the phase difference between one clock domain (e.g., a device configured to provide a data signal, i.e., a processor, a memory, or a loopback interface) and another clock domain (e.g., a digital circuit 4) is measured by the PDC 6. In addition, based on the determined phase difference, the data signal synchronization circuit 8 can switch the provision of the synchronized data signal between the rising edge based on the target signal and the falling edge based on the target signal. Therefore, the cycle slip caused by the phase ambiguity can be avoided, and the data signal can be correctly transmitted with accurate timing.

[0052] Furthermore, for PDC 6 measurement, the measurement only takes a short time, for example 1 to 10 microseconds. In contrast, in the case of the PLL method in the known art, it is necessary to wait for a longer PLL settling time, for example 1 millisecond. Therefore, the circuit 100 can be executed faster.

[0053] Figure 4 A block diagram of a circuit for transmitting data from one clock domain to another clock domain according to a second embodiment of the present invention is shown. The difference from the first embodiment is device 2, that is, the circuit 200 according to the second embodiment also includes device 2, which is configured to provide or use a source clock signal. Therefore, device 2 is coupled to PDC 6 to provide a source clock signal, and is coupled to data signal synchronization circuit 8 to provide a data signal. The other configurations of circuit 200 are the same as circuit 100, and in order to avoid unnecessary repeated descriptions, they are not repeated.

[0054] The circuit 100, 200 may include an oscillator, such as a voltage-controlled sawtooth oscillator, wherein the output signal of the oscillator is used as the converter clock signal, or wherein the circuit is configured to derive the converter clock signal from the output signal of the oscillator. The circuit is configured to derive the synchronization clock signal and the converter clock signal from a common reference signal such that the frequencies of the synchronization clock signal and the converter clock signal are in a predetermined relationship.

[0055] Figure 5: shows a schematic block diagram of a third embodiment of the present invention. A test device for testing a device under test 5 connected to the output of a digital circuit (DAC) 4 is shown, comprising a circuit according to the present invention. Figure 5 As shown, the data signal synchronization circuit 8 includes a first flip-flop circuit FF 10, a signal selector (e.g., a multiplexer 12), a second flip-flop circuit FF 14, and a first-in, first-out circuit FIFO 16. The FIFO 16 is coupled to a data source, such as a digital signal processor, to receive signal data, and is coupled to the second FF 14 via an additional delay circuit ("delay N"), which is used to delay the output signal of the FF 14 by a programmable number of target clock signal cycles. The number of clock cycles is selected in such a way that the FIFO enable signal READ_EN becomes valid accurately at the right point in time, when there is enough data available in the FIFO and the device under test should receive data through the DAC, wherein the FIFO 16 provides the signal data to the converter in response to the output signal READ_EN of the delay circuit.

[0056] The first FF 10 is coupled to a device 2, such as a processor, a memory or a loopback interface, for receiving a data signal TEST_EN, which is, for example, a test signal on a source clock domain SYNCCLK different from the target clock signal FIFOCLK, and is provided from the device for aligning the output timing of the signal data, wherein the FF 10 is configured to sample the data signal at a first sampling phase when the phase relationship indicates that the value of the phase difference between the source clock signal and the target clock signal is within a first predetermined range (e.g., less than a predetermined value), and if the phase difference has a potential risk of causing a metastable state, the phase of the sampled data signal is inverted to make the sampling time away from the clock edge of the synchronous clock signal to obtain a sampled signal. Information about the phase relationship between the source clock domain SYNCCLK and the target clock domain FIFOCLK is measured by a phase digital converter (PDC) 6.

[0057] The signal selector (i.e., multiplexer 12) is coupled to the device 2 to receive the data signal TEST_EN, and is coupled to the first FF 10 to receive the sampling signal, wherein the multiplexer 12 is configured to select one of the received signals, for example, according to the phase relationship, to obtain the selection signal EN_SYNC. The multiplexer 12 selects one of the input signals based on information about the phase relationship.

[0058] The second FF 14 is coupled to the multiplexer 12 to receive the selection signal EN_SYNC, wherein the second FF 14 is configured to sample the data signal TEST_EN at a second sampling phase when the phase relationship is within a second predetermined range, the second predetermined range being, for example, different from the first predetermined range and generally not overlapping with the first predetermined range, and for example, indicating that the value of the phase difference between the synchronization clock signal and the converter clock signal is greater than a predetermined value; in this case, the edge of the sampling signal is synchronized with the converter clock signal, i.e., the output timing of the signals is aligned, and therefore there is no need to align the rising timing of the clock signal.

[0059] Figure 6 A schematic timing diagram is shown for explaining the normal resynchronization process without giving any ambiguity. Figure 6 As shown, when the test starts, the source clock signal SYNCCLK, the data signal and TEST_EN are synchronized, and the target clock signal FIFOCLK and the synchronous data signal EN_SYNCED are synchronized. In this example, the rising edge of the source clock signal is far away from the rising edge of the target clock signal. In this case, the multiplexer 12 will be switched to directly use TEST_EN as the source of the selected signal EN_SYNC, bypassing the trigger 10. Since the rising edges of the source clock signal and the target clock signal are far apart, the trigger 14 captures the EN_SYNC signal without ambiguity. The digital circuit (converter) 4 is able to receive the data signal with the correct timing.

[0060] Figure 7 FIG. 2 shows a schematic timing diagram according to a third embodiment of the present invention. Figure 6 The difference is that the clock edges of the source clock signal SYNCCLK and the target clock signal FIFOCLK are very close to each other. Figure 7As shown, the start of the waveform is determined by the data signal TEST_EN, so as shown by reference numeral 30, the rising edge of the source clock signal SYNCCLK can be matched with the rising edge of the data signal TEST_EN. In this case, the rising edge of the source clock signal and the rising edge of the data signal are very close. In this case, using the rising edge of the target clock signal to capture the TEST_EN signal will lead to ambiguity, because the setup / hold standard of the capture trigger is violated, and it is unclear at which clock cycle of the target clock signal the TEST_EN signal is captured. In order to overcome this situation, the signal TEST_EN is first captured with a trigger 10, and the trigger 10 captures data at the rising edge of N_FIFOCLK (equivalent to capturing at the falling edge of FIFOCLK) to generate a signal EN_SYNC. Then the second trigger 14 captures EN_SYNC at the rising edge of FIFOCLK to generate a signal EN_SYNCED. The synchronous data signal EN_SYNCED always responds to the rising edge of the target clock signal. The ambiguity is avoided by switching to a signal that has been captured by the inverted target clock signal N_FIFOCLK, that is, the ambiguity when sampling the data signal TEST_EN. Therefore, the data signal can be provided to the digital circuit at the correct timing.

[0061] As described above, the start of the waveform is determined by the data signal TEST_EN, so the timing requirement of the data interface is relatively loose.

[0062] Figure 8 It shows that it can be Fig.14 Decision diagram of the operation of the processing block implemented in an embodiment of the present application is shown. The block has the functionality to obtain measured phase values ​​from a PDC (eg PDC 6) to decide which operating situation is relevant and apply edge_select and delay_select accordingly.

[0063] Fig. 9 Shows Fig.14 The schematic diagram and Figure 8 Schematic timing diagram of operation case 1 indicated in the decision diagram of FIG. Operation case 1 represents a case where the signal en_r exhibits ambiguity. In addition, operation case 1 has the following criteria:

[0064] 0≤Phase<0.25,

[0065] edge_select = drop(1), and

[0066] delay_select = no (0).

[0067] Fig.10 Shows Fig.14 The schematic diagram and Figure 8Schematic timing diagram of operation case 2 indicated in the decision diagram of FIG. Operation case 2 represents a case where the signal en_f exhibits ambiguity. In addition, operation case 2 has the following criteria:

[0068] 0.25≤Phase<0.75

[0069] edge_select = rise(0)

[0070] delay_select = No (0)

[0071] Fig.11 Shows Fig.14 The schematic diagram and Figure 8 Schematic timing diagram of operation case 3 indicated in the decision diagram of FIG. Operation case 3 represents the case where the signal en_r exhibits ambiguity and an additional delay is applied. In addition, operation case 3 has the following criteria:

[0072] 0.75≤Phase<1

[0073] edge_select = descend(1)

[0074] delay_select = yes(1)

[0075] Fig.12 Shows instructions Fig.14 The schematic diagram and Figure 8 A schematic diagram of the operating range for all three cases indicated in the decision diagram. Fig.12 As shown, the rising edge of the synchronization signal fifo_en will appear one or two clock cycles after the rising edge of the source signal fifoen_s. Therefore, the ambiguity of each of the situations 1 to 3 is effectively avoided.

[0076] Fig.13 A flow chart indicating the steps of a method for transferring data from one clock domain to another clock domain according to a fourth embodiment of the present invention is shown.

[0077] First, a source clock signal and a target clock signal used by a digital circuit are received (step 10). That is, a phase comparator (e.g., Figure 1 The PDC 6 shown receives signals from a digital circuit (e.g. Figure 1 or Figure 2 The synchronous clock can be provided by the processor, memory or loopback interface.

[0078] Next, the phase relationship between the source clock signal and the target clock signal is determined (S12) and a data signal is received from the device (S14). That is, in the data signal synchronization circuit, e.g. Figure 1 or Figure 2 The data signal synchronization circuit 8 receives data signal transitions synchronized with the source clock signal.

[0079] Then, according to the determined phase relationship between the source clock signal and the target clock signal, the circuit switches between providing a synchronous data signal (e.g., EN_SYNCED) based on sampling of the data signal (e.g., TEST_EN) in response to the rising edge of the target clock signal (e.g., FIFOCLK) and providing a synchronous data signal EN_SYNCED based on sampling of the data signal TEST_EN in response to the falling edge of the target clock signal FIFOCLK (S16). That is, the data signal synchronization circuit selects the sampling type, e.g., Figure 7 As shown, the sample is sampled at the rising edge or the falling edge. The frequency relationship between the source clock signal and the target clock signal is locked at a predetermined value. Then, a synchronization data signal based on this, such as a synchronization data signal provided with a selection, such as EN_SYNCED, is provided to the digital circuit 4 through the FIFO 16 (S18).

[0080] According to a fourth aspect of the present application, a computer program is provided, wherein the computer program is configured to implement the above method when executed on a computer or a microcontroller, so that the above method is implemented by the computer program.

[0081] Fig.14 Schematic diagram of a modified example of the disclosed embodiment is shown. As described above, embodiments of the present application solve the ambiguity problem by using PDC to measure the phase difference between the two clock domains and then using a special receiving circuit that can capture the TEST_EN signal on the rising edge or falling edge of the receiving clock. The control logic decides which edge is appropriate. This avoids the ambiguity of the two clock cycles at the beginning of the test because it can be determined accurately which clock cycle is capturing the signal, such as Fig.14 shown.

[0082] Although some aspects have been described in the context of an apparatus, it is clear that these aspects also represent descriptions of corresponding methods, where blocks or devices correspond to method steps or features of method steps. Similarly, aspects described in the context of method steps also represent descriptions of corresponding blocks or items or features of corresponding apparatuses. Some or all of the method steps may be performed by (or using) hardware devices, such as microprocessors, programmable computers, or electronic circuits. In some embodiments, one or more of the most important method steps may be performed by such devices.

[0083] The data stream of the present invention may be stored on a digital storage medium, or may be transmitted on a transmission medium such as a wireless transmission medium or a wired transmission medium such as the Internet.

[0084] Depending on certain implementation requirements, embodiments of the present application may be implemented in hardware or software. This implementation may be performed using a digital storage medium having electronically readable control signals stored thereon, such as a floppy disk, DVD, Blu-ray, CD, ROM, PROM, EPROM, EEPROM, or flash memory, which cooperates (or is capable of cooperating) with a programmable computer system to enable the execution of the corresponding method. Therefore, the digital storage medium may be computer readable.

[0085] Some embodiments according to the invention comprise a data carrier having electronically readable control signals, which are capable of cooperating with a programmable computer system, such that one of the methods described herein is performed.

[0086] Generally, the embodiments of the present application can be implemented as a computer program product with a program code, and when the computer program product is run on a computer, the program code is used to perform one of the methods. For example, the program code can be stored on a machine-readable carrier.

[0087] Other embodiments comprise the computer program for performing one of the methods described herein, stored on a machine readable carrier.

[0088] In other words, an embodiment of the inventive method is, therefore, a computer program having a program code for performing one of the methods described herein, when the computer program runs on a computer.

[0089] A further embodiment of the inventive method is, therefore, a data carrier (or a digital storage medium, or a computer-readable medium) comprising, recorded thereon, the computer program for performing one of the methods described herein. The data carrier, the digital storage medium or the recorded medium are typically tangible and / or intangible.

[0090] Therefore, a further embodiment of the inventive method is a data stream or a sequence of signals representing the computer program for performing one of the methods described herein.For example, the data stream or the sequence of signals may be configured to be transmitted via a data communication connection (eg via the Internet).

[0091] A further embodiment comprises a processing means, for example a computer or a programmable logic device, configured to or adapted to perform one of the methods described herein.

[0092] A further embodiment comprises a computer having installed thereon the computer program for performing one of the methods described herein.

[0093] Another embodiment according to the invention comprises an apparatus or system configured to transmit (e.g., electronically or optically) a computer program for performing one of the methods described herein to a receiver. For example, the receiver may be a computer, a mobile device, a storage device, etc. For example, the apparatus or system may comprise a file server for transmitting the computer program to the receiver.

[0094] In some embodiments, a programmable logic device (e.g., a field programmable gate array) may be used to perform some or all of the functions of the methods described herein. In some embodiments, a field programmable gate array may collaborate with a microprocessor to perform one of the methods described herein. Typically, these methods are preferably performed by any hardware device.

[0095] The devices described herein may be implemented using hardware devices, or may be implemented using computers, or may be implemented using a combination of hardware devices and computers.

[0096] The apparatus described herein or any component of an apparatus described herein may be implemented at least partially in hardware and / or software.

[0097] The above embodiments are only used to illustrate the principles of the present invention. It should be understood that modifications and variations of the arrangements and detailed descriptions herein will be apparent to those skilled in the art. Therefore, it is intended that the scope of the present invention be limited only by the scope of the appended patent claims, rather than by the specific details presented in the description and explanation of the embodiments herein.

Claims

1. A circuit for transferring data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal and to receive such data by sampling the data signal synchronously with a destination clock signal, wherein transitions of the data signal are synchronous with a source clock signal; a phase comparator, wherein the phase comparator is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive a data signal and provide a synchronized data signal based thereon, wherein the transition of the data signal is synchronized with the source clock signal and the transition of the synchronized data signal is synchronized with the target clock signal; wherein the data signal synchronization circuit is configured to switch between providing the synchronized data signal based on sampling of the data signal in response to a rising edge of the target clock signal and providing the synchronized data signal based on sampling of the data signal in response to a falling edge of the target clock signal according to the determined phase relationship between the source clock signal and the target clock signal; The determined phase relationship between the source clock signal and the target clock signal is a predetermined frequency relationship between the source clock signal and the target clock signal. Wherein, the phase comparator comprises a phase digital converter, The phase digital converter is configured to calculate a phase difference between the source clock signal and the target clock signal for determining the phase relationship.

2. The circuit according to claim 1, wherein The data signal synchronization circuit is configured to select between: a first mode, wherein the data signal synchronized in time with the source clock signal is sampled at an edge of a first edge type of the target clock signal to obtain an intermediate signal, and wherein the intermediate signal is sampled at an edge of a second edge type of the target clock signal to obtain a synchronized data signal synchronized in time with the target clock signal, and A second mode, wherein the data signal synchronized in time with the source clock signal is sampled at an edge of a second edge type of the target clock signal to obtain a synchronized data signal synchronized in time with the target clock signal.

3. The circuit according to any one of claims 1 or 2, wherein: The data signal synchronization circuit comprises: A first trigger circuit is configured to receive the data signal, wherein the first trigger circuit is configured to sample the data signal in a first sampling phase to obtain a sampling signal; a signal selector configured to receive the data signal and coupled to the first flip-flop circuit to receive the sampling signal, wherein the signal selector is configured to select one of the received signals to obtain a selection signal; A second flip-flop circuit is coupled to the signal selector to receive the selection signal, wherein the second flip-flop circuit is configured to sample the selection signal in a second sampling phase.

4. The circuit according to claim 1 or 2, in, The source clock signal is provided by the device or used by the device, wherein the digital circuit is a converter configured to convert data between analog and digital, and The data signal is an enable signal for analog-to-digital conversion of a trigger signal.

5. The circuit according to claim 3, wherein: The data signal synchronization circuit also includes: A first-in-first-out circuit is coupled to a data source to receive signal data, and is coupled to the second flip-flop circuit to receive an output signal of the second flip-flop circuit, or a delayed version of the output signal of the second flip-flop circuit, wherein the first-in-first-out circuit provides signal data to the digital circuit in response to the output signal of the second flip-flop circuit.

6. The circuit according to claim 5, wherein: The first-in-first-out circuit is coupled to the output of the second flip-flop circuit via a delay circuit, and the delay circuit delays an output signal of the second flip-flop circuit.

7. The circuit according to claim 3, wherein: The selector comprises a multiplexer, wherein the multiplexer selects one of the input signals based on the information about the phase relationship.

8. The circuit according to any one of claims 1 or 2, wherein: The circuit comprises an oscillator, wherein an output signal of the oscillator is used as the target clock signal, or wherein the circuit is configured to derive the target clock signal from the output signal of the oscillator.

9. The circuit according to any one of claims 1 or 2, wherein: The circuit is configured to derive the source clock signal and the destination clock signal from a common reference signal such that the frequencies of the source clock signal and the destination clock signal are in a predetermined relationship and such that there is no phase lock between the phase of the source clock signal and the phase of the destination clock signal.

10. The circuit according to claim 4, wherein: The converter is a digital-to-analog converter.

11. The circuit according to claim 4, wherein: The converter is an analog-to-digital converter.

12. A test device for testing a device under test, Comprising a circuit according to any one of claims 1 or 2.

13. The testing device according to claim 12, in, The test device is configured to execute a test flow in synchronization with the source clock signal.

14. The testing device according to claim 13, in, The apparatus is configured to provide an analog signal obtained using a converter based on the value of a signal provided to the device under test, and / or The processor is configured to obtain digital data provided based on a digitized device under test signal obtained from the digital circuit using fractional delay filtering, and evaluate the digital data.

15. A method for transferring data from one clock domain to another clock domain, the method comprising: receiving a source clock signal and a destination clock signal used by a digital circuit; determining a phase relationship between the source clock signal and the target clock signal; Receive data signals and provide synchronous data signals based on them; and switching between providing the synchronous data signal based on sampling of the data signal in response to a rising edge of the target clock signal and providing the synchronous data signal based on sampling of the data signal in response to a falling edge of the target clock signal according to the determined phase relationship between the source clock signal and the target clock signal; wherein the frequency relationship between the source clock signal and the target clock signal is locked at a predetermined value, Wherein, determining the phase relationship between the source clock signal and the target clock signal includes using a phase digital converter to calculate a phase difference between the source clock signal and the target clock signal for determining the phase relationship.

16. A computer program product comprising instructions for performing the method according to claim 15 when the instructions are run on a computer or a microcontroller.

17. A computer readable medium comprising instructions for executing the method according to claim 15 when the instructions are executed on a computer or a microcontroller.

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