A method, apparatus, terminal and readable storage medium for processing executable code

Abstract

The present disclosure relates to a method, device, terminal and readable storage medium for processing executable code. The method comprises: sequentially obtaining code segments from off-chip memory of a processor of a set type according to running logic of the executable code; wherein the off-chip memory stores a plurality of code segments of the executable code; loading the obtained code segments into a set space in on-chip memory of the processor of the set type; and running the code segments in the set space. The method does not depend on a specific XIP supporting flash device, nor a specific MMU and MPU supporting processor, and uses a smaller memory of the processor to greatly expand the running space of the executable code, without occupying too many PIN pins of the processor, which is conducive to implementing a processor with small storage space but high processing speed in a complex application scenario, expanding the application scenario of the processor, and reducing the cost of the corresponding product.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of embedded electronic technology, and in particular, to a method and device for processing executable code and a readable storage medium. BACKGROUND

[0002] Advanced RISC Machines (ARM) processors are widely used in the field of embedded devices, and ARM processor products are divided into classic ARM processor series (ARM7-ARM11) and ARM Cortex processor series. System-on-a-chip solutions based on ARM Cortex processors are suitable for various embedded device submarkets, such as the Internet of Things, motor control, medical treatment, automobiles, home appliance automation, and the like. Cortex series processors are mainly developed for three product types, A series: high-end processors for mobile computing, smart phones, server markets, and the like; R series: high-performance processors for real-time applications; and M series: microcontrollers for low power consumption, determinism, and cost sensitivity. Cortex-M series processors are a series of upwardly compatible, high-energy efficient, and easy-to-use processors that provide more functions at a lower cost, increasing connectivity, and improving energy efficiency, and are much more powerful than traditional processors used in many microcontrollers.

[0003] In a computer system, a central processing unit (CPU) needs to extract machine instructions first, then decode, and finally execute the machine instructions. The machine instructions need to be stored on a memory that can be directly addressed by the CPU, so that the CPU can extract them. The memory that can be directly addressed by the CPU is generally on-chip random access memory (RAM), off-chip parallel bus RAM, or parallel bus flash memory with an executed in place (XIP) function. The unit storage space of such memory is relatively high in price, so the ARMCortex-M series processor generally does not configure a large-capacity memory that can store executable code. This limits the software functions that can be provided on the ARMCortex-M series processor. SUMMARY

[0004] To overcome the problems in the related art, the present disclosure provides a method and device for processing executable code and a readable storage medium.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for processing executable code is provided, applied to a terminal, and the method comprises:

[0006] According to the running logic of the executable code, the code segments are sequentially obtained from the off-chip memory of the processor of the set type;

[0007] The obtained code segments are loaded into the set space in the on-chip memory of the processor of the set type of the terminal;

[0008] The code segments are run in the set space.

[0009] In an exemplary embodiment, the storage capacity of the set space in the on-chip memory is greater than or equal to the information capacity of any code segment.

[0010] In an exemplary embodiment, the method further comprises:

[0011] After obtaining the code segment, the code segment is compiled, the first type of instruction in the code segment is replaced with a corresponding SVC instruction, and the executed code segment is loaded into the set space in the on-chip memory of the processor of the set type;

[0012] When running to the position of the system service call (SVC) instruction, a soft interrupt is generated, the first type of instruction corresponding to the SVC instruction is determined, and the first type of instruction is simulated to be executed.

[0013] The first type of instruction is an instruction related to the running position.

[0014] In an exemplary embodiment, the method further comprises:

[0015] A mapping relationship between the first type of instruction and the SVC instruction is determined.

[0016] In an exemplary embodiment, the method further comprises:

[0017] Before or at the same time as executing the SVC instruction, it is determined whether the execution of the SVC instruction will trigger a cross-segment jump.

[0018] In an exemplary embodiment, the simulation of the execution of the first type of instruction comprises:

[0019] In response to determining that the execution of the SVC instruction will trigger a cross-segment jump, and the SVC instruction corresponds to a first type of instruction of a load function, the load data corresponding to the SVC instruction is loaded into a corresponding register.

[0020] In an exemplary embodiment, the simulation of the execution of the first type of instruction comprises:

[0021] In response to determining that execution of the SVC instruction will cause a cross-segment jump, and the SVC instruction corresponds to a first type of instruction that does not require a return jump function, determining a code segment to which a target code corresponding to the jump belongs, loading the code segment to which the target code belongs into a designated space in the on-chip memory, and determining a current execution position as a position in the designated space corresponding to the target code.

[0022] In an exemplary embodiment, the simulating execution of the first type of instruction comprises:

[0023] In response to determining that execution of the SVC instruction will cause a cross-segment jump, and the SVC instruction corresponds to a first type of instruction that requires a return jump function, executing a transfer function to determine a return address, and when the return address is outside an address range corresponding to the designated space in the on-chip memory, determining a code segment corresponding to the return address, loading the code segment corresponding to the return address into the designated space in the on-chip memory, and relocating the return address to an address in the designated space.

[0024] In an exemplary embodiment, the method further comprises:

[0025] storing, in memory that is continuous with the designated space and located after the designated space, an SVC instruction for identifying a sequential cross-segment;

[0026] In response to executing the SVC instruction for identifying a sequential cross-segment, determining a next code segment of a code segment in the designated space in the off-chip flash memory, loading the next code segment into the designated space, and determining a current execution position as a position in the designated space corresponding to a first instruction.

[0027] According to a second aspect of embodiments of the present disclosure, a device for processing executable code is provided, and the device is applied to a terminal, and the device comprises:

[0028] an obtaining module configured to sequentially obtain code segments from an off-chip memory of a designated type of processor according to a running logic of the executable code; wherein the off-chip memory stores a plurality of code segments of the executable code;

[0029] a loading module configured to load the obtained code segments into a designated space in an on-chip memory of the designated type of processor of the terminal;

[0030] a running module configured to run the code segments in the designated space.

[0031] According to a third aspect of embodiments of the present disclosure, a terminal for processing executable code is provided, and the terminal comprises a designated type of processor, an on-chip memory, and an off-chip flash memory:

[0032] The setting type processor is configured to sequentially obtain code segments from an off-chip memory of the setting type processor according to a running logic of the executable code; wherein the off-chip memory stores a plurality of code segments of the executable code; is further configured to load the obtained code segments into a setting space in an on-chip memory of the setting type processor of the terminal; and is further configured to run the code segments in the setting space.

[0033] According to a fourth aspect of the embodiments of the present disclosure, a device for processing executable code is provided, comprising:

[0034] a processor;

[0035] a memory for storing processor-executable instructions;

[0036] The processor is configured to perform the method according to any one of the first aspect of the embodiments of the present disclosure.

[0037] According to a fifth aspect of the embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, when the instructions in the storage medium are executed by a processor of a device, the device is enabled to perform the method according to any one of the first aspect of the embodiments of the present disclosure.

[0038] The above method of the present disclosure has the following beneficial effects: executable code in the off-chip flash memory is dynamically loaded, the off-chip flash memory can be any SPI flash memory, and does not depend on a specific XIP supporting flash device, nor does it depend on a specific MPU supporting processor, using a smaller memory of the processor, the running space of the executable code can be greatly expanded, and the processor does not occupy too many PIN pin resources, which is conducive to realizing the processor with small storage space but high processing speed in complex application scenarios, expanding the application scenarios of the processor, and reducing the cost of the corresponding product.

[0039] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings, which are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0041] Figure 1 is a flowchart of a method for processing executable code according to an exemplary embodiment;

[0042] Figure 2 is a schematic diagram of a method for processing executable code according to an exemplary embodiment;

[0043] Figure 3is a specific flow chart of processing executable code according to an exemplary embodiment;

[0044] Figure 4 is a device block diagram of processing executable code according to an exemplary embodiment;

[0045] Figure 5 is a schematic diagram of a terminal processing executable code according to an exemplary embodiment;

[0046] Figure 6 is a block diagram of a terminal processing executable code according to an exemplary embodiment. DETAILED DESCRIPTION

[0047] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is made with reference to the accompanying drawings in which like reference numerals refer to like elements, and redundant description is omitted. The following exemplary embodiments described in the detailed description are illustrative of the principles of the present application. Other arrangements, which are within the scope of the present application, can be devised and carried out by those skilled in the art without departing from the scope of the present application. Accordingly, the present application is not limited to those embodiments described herein but instead has wide applicability to any device and method that fall within the scope of the appended claims.

[0048] In some possible embodiments, several schemes of storing executable code on ARM Cortex-M series processors have the following disadvantages:

[0049] (1) Stored on on-chip RAM, the unit storage space is expensive, and the on-chip RAM storage space is small;

[0050] (2) Stored on off-chip parallel bus RAM, the unit storage space is expensive, the storage space is small, and the off-chip parallel bus occupies the PIN (pin) resources of the processor, making the available I / O (Input / Output) resources less;

[0051] (3) Stored on off-chip parallel bus XIP-enabled Flash memory, the unit storage space is expensive, the storage space is small, and the off-chip parallel bus occupies the PIN resources of the processor, making the available I / O resources less;

[0052] (4) Stored on on-chip SPI (Serial Peripheral Interface) bus XIP-enabled Flash memory, it can be used to store executable code on specific SPI XIP Flash-enabled processors, but is limited to specific Flash memory and SPI XIP Flash-enabled processor devices.

[0053] In some possible embodiments, ARM Cortex-M series processors are limited in size of space directly storing executable codes, and it is difficult to store large capacity codes at low cost, and thus the ARM Cortex-M series processors are difficult to be applied to devices in complex application scenarios. This makes devices in complex application scenarios have to use classic ARM processor series with low chip performance, or high-cost processors such as Cortex-A series and Cortex-R series, and thus affect the cost performance of products.

[0054] In an exemplary embodiment of the present disclosure, a method for processing executable codes is provided, and the method is applied to a terminal including devices such as smart measurement devices, household appliances, and medical instruments with microcontrollers. Figure 1 is a flowchart of a method for processing executable codes according to an exemplary embodiment, as shown in Figure 1 The method includes steps S101-S102, as shown in

[0055] Step S101: sequentially obtaining code segments from off-chip memory of a processor of a set type according to running logic of executable codes; wherein the off-chip memory stores a plurality of code segments of the executable codes.

[0056] Step S102: loading the obtained code segments into a set space in on-chip memory of the processor of the set type in the terminal.

[0057] Step S103: running the code segments in the set space.

[0058] The plurality of code segments in step S101 are obtained by dividing the executable codes according to a preset size. Information capacity of each code segment can be the same, or information capacity of part of the code segments can be different from information capacity of other code segments. The information capacity is a size of a storage capacity occupied by the code segment, for example, a total amount of bits.

[0059] In an example, the size of the executable codes is N, N=4KB, and the executable codes are divided into N1, N2, …, Ni code segments and are sequentially stored in off-chip flash memory.

[0060] The processor of the set type is a processor that does not support a memory management unit (MMU), or a processor that does not support a memory protection unit (MPU), or a processor that does not support both the MMU and the MPU, and the processor of the set type has a small storage space but has a high energy efficiency, for example, an ARM Cortex-M series processor.

[0061] The off-chip flash memory is any SPI flash memory, and does not need to have an XIP function.

[0062] In step S102, the on-chip memory is an on-chip RAM, and the setting space of the on-chip memory can be set according to the storage space of the processor that can run the executable code, and the setting space is a space for storing and running the code segment.

[0063] Figure 2 FIG. 1 is a schematic diagram of a method for processing executable code according to an exemplary embodiment. A setting space is divided on the on-chip memory of a setting type processor, and corresponding code segments in a plurality of code segments stored on an off-chip flash memory are loaded into the setting space in sequence according to the running logic of the executable code, and the code segments are run in the setting space.

[0064] In order to ensure the storage space utilization rate of the on-chip memory, in some possible implementation manners, the storage capacity of the setting space in the on-chip memory is greater than or equal to the information capacity of any code segment.

[0065] When the code segment is run in the setting space, a preset instruction is triggered, the preset instruction includes sequential cross-segment, jump cross-segment, etc., the instructions and data of the code segment stored in the setting space are unloaded, and a code segment is loaded from the off-chip flash memory again, and the process is segment reloading.

[0066] Since the method loads part of the code segments in the off-chip flash memory into the setting space of the on-chip memory, each time the code segment is loaded, it is loaded to run at a fixed address, and the running address of the corresponding code is inconsistent with the compiling address, and therefore, the position independence of the code in the segment during running needs to be implemented. Since most ARM instructions are position independent, the ARM instructions related to the position are referred to as the first type of instructions. In the compiling stage, a system service call (SVC instruction) is used to replace the first type of instructions, so as to implement the position independence. For example:

[0067] In some possible implementation manners, the method further includes: after the code segment is acquired, the code segment is compiled, the first type of instructions in the code segment are replaced by corresponding SVC instructions, and the executed code segment after the replacement is loaded into the setting space in the on-chip memory of the setting type processor.

[0068] When the position of the SVC instruction is run, a soft interrupt is generated, the first type of instruction corresponding to the SVC instruction is determined, and the first type of instruction is simulated and executed.

[0069] The first type of instruction is an instruction related to the running position.

[0070] The executable code has been pre-processed before being stored into the off-chip flash memory of the processor of the given type. The pre-processing includes compiling the executable code and replacing first-type instructions in the compiled executable code with corresponding SVC instructions. The corresponding code segment after the replacement is executed is loaded into the given space in the on-chip memory of the processor of the given type to identify the SVC instructions for interrupt processing when the code segment is run.

[0071] The first-type instructions are position-related instructions, including load instructions and jump instructions. The load instructions include LDR and LDM related instructions, and the jump instructions include B, BX, BL and BLX instructions. After the executable code is compiled, the first-type instructions are obtained by extracting and analyzing a binary image file generated by the compilation of the executable code, and are replaced with SVC instructions. The SVC instruction is an interrupt instruction that can generate a function call request during the execution of the executable code. The setting is simple and is generally in the form of SVC#0. When the position of the SVC instruction is reached, a software interrupt is generated, the first-type instruction corresponding to the SVC instruction is determined, and the first-type instruction is simulated.

[0072] In some possible embodiments, the method further includes:

[0073] Determining a one-to-one mapping relationship between the first-type instructions and the SVC instructions.

[0074] The first-type instructions are divided in detail according to the machine code format of the first-type instructions in the executable code, and are divided into different types. An SVC service call number is set for first-type instructions of the same type. The first-type instructions are replaced according to the mapping relationship between the first-type instructions and the SVC instructions, and the mapping relationship table is stored in the off-chip flash memory. At the same time, the machine code and position of the replaced first-type instructions are saved in a table and stored in the off-chip flash memory, facilitating subsequent lookup and use.

[0075] In some possible embodiments, the method further includes:

[0076] Before or while the SVC instruction is executed, it is determined whether execution of the SVC instruction will trigger a cross-segment jump.

[0077] The cross-segment jump indicates that the current code segment needs to jump to another code segment for continuous execution during the execution of the current code segment. The cross-segment jump includes load cross-segment, jump cross-segment, sequential cross-segment and return cross-segment. The first-type instructions that can trigger the cross-segment jump include load instructions and jump instructions. Before or while the SVC instruction is executed, it is determined whether execution of the SVC instruction will trigger a cross-segment jump, which can ensure that the execution of the executable code is not interrupted, and at the same time, it is determined whether segment reloading is needed.

[0078] In some possible implementation manners, the simulating the first type of instruction comprises:

[0079] In response to determining that the execution of the SVC instruction will cause a cross-segment jump, and the SVC instruction corresponds to the first type of instruction with a load function, loading the load data corresponding to the SVC instruction into the corresponding register.

[0080] When the execution of the SVC instruction will cause a cross-segment jump, and the SVC instruction corresponds to the first type of instruction with a load function, no segment reload is needed. When simulating the first type of instruction, the machine code is parsed according to the mapping relationship between the first type of instruction and the SVC instruction, the source address of the data to be loaded and the corresponding register, i.e., the destination register, are calculated, the data at the source address is read from the off-chip flash memory and loaded into the corresponding register, i.e., the simulation of the first type of instruction with the load function is completed.

[0081] In some possible implementation manners, the simulating the first type of instruction comprises:

[0082] In response to determining that the execution of the SVC instruction will cause a cross-segment jump, and the SVC instruction corresponds to the first type of instruction without a return jump function, determining the code segment to which the target code corresponding to the jump belongs, loading the code segment to which the target code belongs into a set space in the on-chip memory, and determining the current execution position as the position of the target code in the set space.

[0083] When the execution of the SVC instruction will cause a cross-segment jump, and the SVC instruction corresponds to the first type of instruction without a return jump function, it is first determined whether segment reload is needed. When simulating the first type of instruction, the machine code is parsed according to the mapping relationship between the first type of instruction and the SVC instruction, and the destination address to which the jump is needed is calculated, so as to determine the target code corresponding to the jump.

[0084] According to the code segment to which the target code belongs, it is determined whether segment reload is needed, and the simulation process of the first type of instruction without a return jump function has the following two cases:

[0085] The first case: when the code segment to which the target code belongs is the code segment of the set space in the current on-chip memory, no segment reload is needed. The destination address of the first type of instruction without a return jump function is relocated as an address on the set space in the on-chip memory, and the address in the relocated set space is assigned to the PC register (Program Counter Register), so that the jump is performed to the address in the relocated set space, i.e., the simulation of the first type of instruction without a return jump function is completed.

[0086] Secondly, when the code segment to which the target code belongs is not the code segment of the set space in the current on-chip memory, segment reloading is needed. The code segment of the off-chip flash memory where the destination address of the first type of instruction without return jump function is located, i.e. the code segment to which the target code belongs, is loaded into the set space in the on-chip memory, i.e. segment reloading is performed. After segment reloading, the current execution position is determined as the position in the set space corresponding to the target code, i.e. the destination address of the first type of instruction without return jump function is relocated as an address on the set space in the on-chip memory, and the address in the set space after relocation is assigned to the PC register, so that the first type of instruction without return jump function is jumped to the address in the set space after relocation, i.e. the simulation execution of the first type of instruction without return jump function is completed.

[0087] In some possible implementation manners, the simulation execution of the first type of instruction comprises:

[0088] In response to determining that the execution of the SVC instruction will cause a cross-segment jump and the SVC instruction corresponds to the first type of instruction requiring a return jump function, a transfer function is executed to determine a return address, and when the return address is located outside the address range corresponding to the set space in the on-chip memory, it is determined that the code segment corresponding to the return address, and the code segment corresponding to the return address is loaded into the set space in the on-chip memory, and the return address is relocated as an address in the set space.

[0089] When the execution of the SVC instruction will cause a cross-segment jump and the SVC instruction corresponds to the first type of instruction requiring a return jump function, it is first determined whether segment reloading is needed. The simulation execution process of the jump across the segment is the same as described above, and will not be described again. Only the process of returning across the segment is described.

[0090] When the first type of instruction is simulated, according to the mapping relationship between the first type of instruction and the SVC instruction, the machine code is parsed, and the return address of the first type of instruction requiring a return jump function is calculated. A transfer function can be set, the transfer function is executed to return, the address of the transfer function is assigned to the LR register (Link Register, connection register), and the return address of the first type of instruction requiring a return jump function is recorded in the memory in a stack data structure. When the first type of instruction requiring a return jump function is run to return, the address of the transfer function saved in the LR register is assigned to the PC register, so that the PC register jumps to execute the transfer function, and the transfer function takes the return address of the first type of instruction requiring a return jump function from the memory.

[0091] According to the position of the return address of the first type of instruction requiring a return jump function, it is determined whether segment reloading is needed, and the simulation execution process of the first type of instruction requiring a return jump function has the following two cases:

[0092] The first kind: when the return address is in the address range of the set space in the on-chip memory, no segment reload is needed. The return address is relocated to the address in the set space in the on-chip memory, the address in the relocated set space is assigned to the PC register, and the jump is made to the address in the relocated set space, thus completing the simulation execution of the first instruction with the return jump function.

[0093] The second kind: when the return address is out of the address range of the set space in the on-chip memory, segment reload is needed. The code segment corresponding to the return address in the off-chip flash memory is determined, the code segment corresponding to the return address is loaded into the set space in the on-chip memory, thus performing a segment reload. After the segment reload, the return address is relocated to the address in the set space, the address in the relocated set space is assigned to the PC register, and the jump is made to the address in the relocated set space, thus completing the simulation execution of the first instruction with the return jump function.

[0094] In some possible embodiments, the method further comprises:

[0095] storing an SVC instruction for identifying a sequential cross-segment in the memory continuous with and after the set space;

[0096] when the SVC instruction for identifying a sequential cross-segment is executed, determining the next code segment of the code segment in the set space in the off-chip flash memory, loading the next code segment into the set space, and determining the current execution position as the position corresponding to the first instruction in the set space.

[0097] In order to run the process without interruption after the code segment in the set space in the on-chip memory is run to completion, an SVC instruction for identifying a sequential cross-segment is stored in the memory continuous with and after the set space, which is different from the above SVC instruction and is only used for identifying a sequential cross-segment, for example, set as SVC#100. When the SVC instruction for identifying a sequential cross-segment is executed, segment reload is needed. The next code segment of the code segment in the set space in the off-chip flash memory is determined, the next code segment is loaded into the set space, and the current execution position is determined as the position corresponding to the first instruction in the set space.

[0098] In an example, there are 1000 instructions in the setting space on the on-chip memory, when the 1000 instructions are sequentially executed, the 1001th instruction needs to be executed, and the 1001th instruction is not in the setting space, i.e., the content executed or read by the code segment exceeds the range of the current code segment, which is a segment out-of-bound. At this time, the SVC instruction for identifying sequential cross-segment needs to be stored in the memory continuous to the setting space and after the setting space to simulate the execution of sequential cross-segment, prevent the segment out-of-bound and interrupt the execution process of the executable code.

[0099] In the exemplary embodiment of the present disclosure, the multiple code segments corresponding to the executable code are stored in the off-chip flash memory of the setting type processor, and are dynamically loaded into the setting space in the on-chip memory to run the executable code. The off-chip flash memory can be any SPI flash memory, which does not depend on a specific XIP supporting flash device, and also does not depend on a specific MPU supporting processor. Using the smaller memory of the processor, the running space of the executable code can be greatly expanded, and the PIN pin resources of the processor are not occupied, which is beneficial to implement the complex application scenario on the processor with small storage space but high processing speed, expand the application scenario of the processor, and reduce the cost of the corresponding product.

[0100] The present disclosure provides a specific embodiment to implement the above-mentioned method of processing executable code in the form of logical units. The setting type processor takes the ARM Cortex-M processor as an example, the off-chip flash memory takes the SPI flash memory without XIP function as an example, and the on-chip memory takes the on-chip RAM as an example.

[0101] As shown in Figure 3 , seven logical units including a compiling logical unit, a preprocessing logical unit, a burning logical unit, a starting logical unit, an executing logical unit, an SVC service exception processing logical unit and an analog instruction executing logical unit. Among them, the compiling logical unit, the preprocessing logical unit and the burning logical unit belong to the embedded software development stage and run on the computer; the starting logical unit, the executing logical unit, the SVC service exception processing logical unit and the analog instruction executing logical unit are stored in the code storage memory supported by the ARM Cortex-M processor, such as the on-chip flash memory or ROM (Read-Only Memory).

[0102] Each logical unit performs the following steps:

[0103] Compile logic unit: the software developer configures the compiler's parameters to configure the compiled instruction set into Thumb-1 instructions, and configures the software corresponding to the start logic unit, the execution logic unit, the SVC service exception processing logic unit, and the simulated instruction execution logic unit, respectively, and the system and driver software, to be located on the code memory address space natively supported by the ARM Cortex-M processor, such as the on-chip flash memory address space. The application service software other than this, that is, the executable code to be processed by the present disclosure, is located on the off-chip flash address space without XIP function, and the binary image file of the target executable code generated by compilation is compiled.

[0104] Preprocessing logic unit: the binary image file generated by the compilation in the compile logic unit is extracted and parsed for machine instructions, and the location-related machine instructions located on the off-chip flash address space without XIP function are replaced with SVC system service call instructions. According to the machine code format of each location-related machine instruction, the same type of machine instruction needs to be further subdivided, and the subdivided machine instruction is correspondingly set with an SVC system service call number, such as replacing the instructions according to the mapping relationship corresponding to Table 1 below. The machine code and location of the replaced instructions are saved in a table.

[0105] Table 1

[0106]

[0107]

[0108] Burning logic unit: the software of the start logic unit, the execution logic unit, the SVC service exception processing logic unit, and the simulated instruction execution logic unit, and the system and driver software are burned to the code memory supported by the processor natively at the address specified during compilation. The modified binary image located on the off-chip flash address space without XIP function in the preprocessing logic unit is burned to the off-chip flash memory together with the table saving the machine code and location.

[0109] The starting logic unit: after the device is powered on, the system and device driver are initialized, the code segment space in the on-chip RAM is initialized, and the basic running environment such as software global variables is initialized. The application software entry address is obtained, and then the starting address of the application software in the off-chip flash memory is obtained according to the starting address of the application software stored in the off-chip flash memory. The off-chip flash memory is read, the code segment is loaded into the code segment space in the on-chip RAM, and the first segment reloading is completed. According to the application software entry address-off-chip flash memory code segment starting address-on-chip RAM code segment space starting address, the application software entry address in the on-chip RAM code segment space is calculated. The application software entry address obtained by repositioning is assigned to the PC register (Program Counter Register, program counter), so as to jump to the address and start executing the application software on the on-chip RAM. In addition, the starting logic unit also adds an SVC system service call instruction with a fixed service call number, such as SVC#100, at the end of the on-chip RAM code segment space, which is used to identify the sequential cross-segment.

[0110] The execution logic unit: the application software in the on-chip RAM code segment space is executed. When a non-SVC instruction is executed, it can be normally executed. When an SVC instruction is executed, an SVC exception is triggered, and the unified SVC system service program is entered, that is, the SVC service exception processing logic unit is entered.

[0111] The SVC service exception processing program logic unit: the LR register and the like when the exception occurs are saved to the stack, and then the machine code of the SVC instruction triggering the exception is taken out from the on-chip RAM code segment space according to the address of the position where the exception occurs. The service call number is parsed from the machine code. If it is a service call number that does not process the sequential cross-segment, the analog instruction execution logic unit is entered, and the instruction replaced by the SVC instruction is executed in a software manner. If it is a service call number that processes the sequential cross-segment, the off-chip flash memory is read, the next segment of the code segment is loaded into the on-chip RAM code segment space, and the segment reloading is completed. After the software analog instruction execution or the segment reloading is completed, the registers saved to the stack are popped, and then the execution logic unit is returned to execute the program;

[0112] The analog instruction execution program logic unit: according to the mapping relationship table of the position-related machine code and the SVC instruction, the instruction type before replacement is found, and then the machine code of the replaced instruction is found from the table of the saved machine code and the position of the replaced instruction stored in the off-chip flash memory according to the address of the position where the exception occurs.

[0113] If it is a load instruction (LDR, LDM instruction), the machine code is parsed, the source address and the destination register of the data to be loaded are calculated, and then the data at the source address is read from the off-chip flash memory and loaded into the destination register, i.e. the simulation execution of the load instruction is completed.

[0114] If it is a jump instruction (B, BX instruction) without L, i.e. a jump instruction without return, the machine code is parsed, the destination address to be jumped to is calculated, if the address is within the address range of the current off-chip flash memory loaded code segment, only the destination address of the jump is relocated to the address on the code segment space in the on-chip RAM, and then the relocated destination address on the RAM is assigned to the PC register, so that it jumps to the destination address on the RAM, i.e. the simulation execution of the instruction is completed; if the address is not within the address range of the current off-chip flash memory loaded code segment, the code segment of the off-chip flash memory where the destination address is located needs to be calculated and found, the off-chip flash memory is read, the code segment is loaded into the code segment space in the on-chip RAM, i.e. a segment reload is performed, then the destination address of the jump is relocated to the address on the code segment space in the on-chip RAM, and then the relocated destination address on the RAM is assigned to the PC register, so that it jumps to the destination address on the RAM, i.e. the simulation execution of the instruction is completed.

[0115] If it is a jump instruction containing L (BL, BLX instruction), i.e. a jump instruction that needs to return, it also needs to judge whether segment reloading is needed first, and then reposition the destination address of the jump to the address on the code segment space in the on-chip RAM. In addition, return across segments need to be identified and processed, and the simulation software sets a transfer function f, assigns the address of the transfer function f to the LR register, records the real return address in the memory in a stack data structure, and then assigns the repositioned destination address on the RAM to the PC register to make it jump to the destination address on the RAM. When a function returns, the address of the transfer function f saved in the LR register is assigned to the PC register to make it start executing the transfer function f. In the transfer function f, the real return address is taken out from the memory. If the return address is within the address range of the current off-chip flash loaded code segment, the return address only needs to be repositioned to the address on the code segment space in the on-chip RAM, and then the repositioned return address on the RAM is assigned to the PC register to make it jump to the return address on the RAM, i.e. the simulation execution of the instruction is completed. If the return address is not within the address range of the current off-chip flash loaded code segment, the code segment of the off-chip flash where the return address is located needs to be calculated and found, the off-chip flash is read, the code segment is loaded into the code segment space in the on-chip RAM, i.e. segment reloading is performed once, and then the return address is repositioned to the address on the code segment space in the on-chip RAM, and then the repositioned return address on the RAM is assigned to the PC register to make it jump to the return address on the RAM, i.e. the simulation execution of the instruction is completed.

[0116] In an example embodiment of the present disclosure, a device for processing executable code is provided, which is applied to a terminal, such as Figure 4 As shown in the figure, the device comprises:

[0117] The acquisition module 401 is configured to acquire code segments from the off-chip memory of the processor of the set type in sequence according to the running logic of the executable code; wherein the off-chip memory stores a plurality of code segments of the executable code;

[0118] The loading module 402 is configured to load the acquired code segments into a set space in the on-chip memory of the processor of the set type of the terminal;

[0119] The running module 403 is configured to run the code segments in the set space.

[0120] As to the device in the above-mentioned embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be described in detail here.

[0121] In an example embodiment of the present disclosure, a terminal for processing executable code is provided, which is applied to a terminal, such as Figure 5As shown, the terminal includes a set type processor 501, an on-chip memory 502 and an off-chip flash memory 503:

[0122] The set type processor 501 is configured to sequentially obtain code segments from the off-chip memory of the set type processor according to the running logic of the executable code; wherein the off-chip memory stores a plurality of code segments of the executable code; is further configured to load the obtained code segments into a set space in the on-chip memory of the set type processor of the terminal; is further configured to run the code segments in the set space.

[0123] Figure 6 is a block diagram of a terminal 600 processing executable code according to an exemplary embodiment.

[0124] Referring to Figure 6 , the terminal 600 can include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0125] The processing component 602 usually controls the overall operation of the terminal 600, such as operations associated with displaying, making phone calls, data communications, camera operations and recording operations. The processing component 602 can include one or more processors 620 to execute instructions to complete all or part of the steps of the methods described above. In addition, the processing component 602 can include one or more modules to facilitate interaction between the processing component 602 and other components. For example, the processing component 602 can include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0126] The memory 604 is configured to store various types of data to support the operation of the terminal 600. Examples of these data include instructions for any application or method operating on the terminal 600, contact data, phonebook data, messages, pictures, videos, etc. The memory 604 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0127] The power supply component 606 provides power for the various components of the terminal 600. The power supply component 606 can include a power management system, one or more power supplies, and other components associated with generating, managing and distributing power for the terminal 600.

[0128] The multimedia component 608 includes a screen providing an output interface between the terminal 600 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors for sensing a touch, a slide and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or a sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the terminal 600 is in an operation mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front and rear camera can be a fixed optical lens system or have a focal length and optical zooming capability.

[0129] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC) configured to receive external audio signals when the terminal 600 is in an operation mode, such as a call mode, a recording mode and a voice recognition mode. The received audio signals can be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0130] The I / O interface 612 provides an interface between the processing component 602 and peripheral interface modules, which can be a keypad, a click wheel, buttons and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button and a lock button.

[0131] The sensor component 614 includes one or more sensors for providing various state assessments for the terminal 600. For example, the sensor component 614 can detect an open / closed state of the terminal 600, relative positioning of components, such as a display and a keypad of the terminal 600, a change in position of the terminal 600 or a component of the terminal 600, presence or absence of user contact with the terminal 600, an orientation or acceleration / deceleration of the terminal 600, and a temperature change of the terminal 600. The sensor component 614 can include a proximity sensor configured to detect presence of a nearby object without any physical touch. The sensor component 614 can further include a light sensor, such as a CMOS or CCD image sensor, for use in an imaging application. In some embodiments, the sensor component 614 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor.

[0132] The communication component 616 is configured to facilitate wired or wireless communication between the terminal 600 and other devices. The terminal 600 can access a wireless network based on a communication standard, such as WiFi, 2G, or 3G, or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 further includes a Near Field Communication (NFC) module to facilitate close proximity communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technology.

[0133] In an exemplary embodiment, the terminal 600 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements, for performing the above-described methods.

[0134] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 604 including instructions, is also provided, which can be executed by the processor 620 of the terminal 600 to complete the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, and an optical data storage device, etc.

[0135] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of an apparatus, enables the apparatus to perform a method of adjusting a dark mode display state, the method including any of the above-described methods.

[0136] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

[0137] It is to be understood that the application is not limited to the precise construction herein described and as shown in the attached drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present application. The scope of the application is limited only by the claims that follow.

Claims

1. A method of processing executable code, applied to a terminal, characterized in that, The method comprises: obtaining code segments from the off-chip memory of the processor of the set type in sequence according to the running logic of the executable code; wherein the off-chip memory stores a plurality of code segments of the executable code; loading the obtained code segments into a set space in the on-chip memory of the processor of the set type of the terminal; running the code segments in the set space; The method further comprises: after obtaining the code segments, compiling the code segments, replacing the first type of instructions in the code segments with corresponding SVC instructions, the first type of instructions being instructions related to the running position.

2. The method of claim 1, wherein: The storage capacity of the set space in the on-chip memory is greater than or equal to the information capacity of any code segment.

3. The method of claim 1 or 2, wherein: The method further comprises: loading the executed and replaced code segments into the set space in the on-chip memory of the processor of the set type; when running to the position of the system service call (SVC) instruction, generating a software interrupt, determining the first type of instruction corresponding to the SVC instruction, and simulating the execution of the first type of instruction.

4. The method of claim 3, wherein, The method further comprises: determining the mapping relationship between the first type of instruction and the SVC instruction.

5. The method of claim 3, wherein, The method further comprises: determining whether the execution of the SVC instruction will trigger a cross-segment jump before or at the same time as the execution of the SVC instruction.

6. The method of claim 5, wherein, The simulating execution of the first type of instruction comprises: in response to determining that the execution of the SVC instruction will trigger a cross-segment jump, and the SVC instruction corresponding to the first type of instruction of the load function, loading the load data corresponding to the SVC instruction into the corresponding register.

7. The method of claim 5, wherein, The simulating execution of the first type of instruction comprises: in response to determining that the execution of the SVC instruction will trigger a cross-segment jump, and the SVC instruction corresponding to the first type of instruction of the no-return jump function, determining the code segment to which the target code corresponding to the jump belongs, loading the code segment to which the target code belongs into the set space in the on-chip memory, and determining the current execution position as the position of the target code corresponding in the set space.

8. The method of claim 5, wherein, The simulating execution of the first type of instruction comprises: in response to determining that the execution of the SVC instruction will trigger a cross-segment jump, and the SVC instruction corresponding to the first type of instruction of the return jump function, executing a transfer function to determine the return address, and when the return address is located outside the address range corresponding to the set space in the on-chip memory, determining the code segment corresponding to the return address, loading the code segment corresponding to the return address into the set space in the on-chip memory, and relocating the return address to an address within the set space.

9. The method of claim 1 or 2, wherein, The method further comprises: storing an SVC instruction for identifying sequential cross-segments in the memory continuous with and after the set space; when executing the SVC instruction for identifying sequential cross-segments, determining the next code segment of the code segment in the set space in the off-chip flash memory, loading the next code segment into the set space, and determining the current execution position as the position of the first instruction in the set space.

10. An apparatus for processing executable code, applied to a terminal, characterized in that, The device comprises: An acquisition module configured to acquire code segments from an off-chip memory of a processor of a specified type in sequence according to a running logic of executable code; wherein the off-chip memory stores a plurality of code segments of the executable code; A loading module configured to load the acquired code segments into a specified space in an on-chip memory of the processor of the specified type of the terminal; A running module configured to run the code segments in the specified space; The device is further configured to, after acquiring the code segments, compile the code segments, and replace first-type instructions in the code segments with corresponding SVC instructions, the first-type instructions being instructions related to a running position.

11. A terminal that processes executable code, characterized by, The terminal comprises a processor of a specified type, an on-chip memory and an off-chip flash memory: the processor of the specified type is configured to acquire code segments from an off-chip memory of a processor of a specified type in sequence according to a running logic of executable code; wherein the off-chip memory stores a plurality of code segments of the executable code; is further configured to load the acquired code segments into a specified space in an on-chip memory of the processor of the specified type of the terminal; is further configured to run the code segments in the specified space; and is further configured to, after acquiring the code segments, compile the code segments, and replace first-type instructions in the code segments with corresponding SVC instructions, the first-type instructions being instructions related to a running position.

12. An apparatus for processing executable code, characterized by: comprise: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the method of any one of claims 1-9.

13. A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of a device, enabling the device to perform the method of any one of claims 1-9.

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