Simulation method, system and equipment for VDMOS electromagnetic pulse effects

Abstract

This invention discloses a simulation method, system, simulation equipment, and storage medium for VDMOS electromagnetic pulse effects. It relates to the field of simulation technology. By incorporating ESD protection into the simulation structure of VDMOS devices, the self-conditions of VDMOS in responding to external electromagnetic pulses are made closer to reality, effectively guiding VDMOS electromagnetic pulse protection design. The simulation method includes: constructing a model, which includes a simulation model and a comparison model. The simulation model includes a first VDMOS and an electrostatic discharge (ESD) protection structure electrically connected to the first VDMOS; the comparison model includes a second VDMOS; applying an electromagnetic pulse to the second VDMOS included in the comparison model and obtaining a pulse curve to simulate the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse; simulating the electromagnetic pulse threshold condition for gate oxide layer breakdown in the second VDMOS included in the comparison model to determine the electromagnetic pulse threshold; and applying a current pulse to the electrodes included in the simulation model and obtaining a pulse curve to simulate the relationship between the peak electric field of the first VDMOS gate oxide layer and the electromagnetic pulse.

Description

Technical Field

[0001] This invention relates to the field of simulation technology, and in particular to a simulation method, system, simulation equipment, and storage medium for VDMOS electromagnetic pulse effects. Background Technology

[0002] A vertically diffused metal-oxide-semiconductor field-effect transistor (VDMOS) is a vertically double-diffused power MOSFET (field-effect transistor). Due to its fast switching speed, high breakdown voltage, and low on-state resistance, this device is widely used in many fields such as aerospace.

[0003] Traditional electromagnetic pulse research often directly considers the impact of electromagnetic pulse signals directly acting on devices, neglecting the role of electrostatic discharge (ESD) protection in actual circuits. This results in the simulation studies considering environmental conditions that do not match the actual situation, leading to low simulation accuracy. Summary of the Invention

[0004] The purpose of this invention is to provide a simulation method, system, simulation equipment, and storage medium for VDMOS electromagnetic pulse effects. By incorporating ESD protection into the simulation structure of VDMOS devices, the self-conditions of VDMOS in responding to external electromagnetic pulses are made closer to reality, which can effectively guide the design of VDMOS electromagnetic pulse protection.

[0005] Firstly, in order to achieve the above objectives, the present invention provides a simulation method for VDMOS electromagnetic pulse effects, comprising the following steps:

[0006] A model is constructed, which includes a simulation model and a comparison model. The simulation model includes a first VDMOS and an electrostatic protection structure electrically connected to the first VDMOS, while the comparison model includes a second VDMOS.

[0007] An electromagnetic pulse was applied to the second VDMOS included in the comparison model, and the pulse curve was obtained to simulate the relationship between the peak electric field of the gate oxide layer of the second VDMOS and the electromagnetic pulse.

[0008] The electromagnetic pulse threshold condition for gate oxide layer breakdown in the second VDMOS included in the comparative model is simulated to determine the electromagnetic pulse threshold.

[0009] Current pulses are applied to the electrodes included in the simulation model to obtain pulse curves, thereby simulating the relationship between the peak electric field of the first VDMOS gate oxide layer and the electromagnetic pulse.

[0010] In the above-mentioned technical solution, the electrostatic discharge (ESD) protection structure in front of the VDMOS power device is ignored in the traditional research on the impact of electromagnetic pulses (EMP) on power devices. This invention can make the simulation environment closer to actual conditions. In the EMP simulation part, voltage source pulses and current source pulses with a rise and fall time of 1ns are used to represent EMPs, and their respective effects on the devices are analyzed. Since voltage source pulses are not limited by diode protection when acting on devices, and the EMP protection structure in actual circuits can effectively resist EMPs, it is unreasonable to use voltage pulses as EMPs when simulating circuits with EMP protection. In order to reflect the role of EMP, this invention uses current source pulses as EMPs. The simulation analysis shows that the change law of the peak electric field of the gate oxide layer of the device under the action of EMP is consistent for both N-type and P-type devices. Moreover, when protected by diodes, the peak current pulse that the device can withstand is greatly increased. However, the peak current pulse that VDMOS and its protection circuit can withstand is limited by the reverse breakdown voltage of the diode in the protection circuit. When the reverse breakdown voltage of the diode is 2kV, the device can withstand an electromagnetic pulse of nearly 4mA without easily experiencing gate breakdown. When the maximum reverse breakdown voltage of the diode used is 2kV, the overall electromagnetic pulse tolerance of VDMOS and its protection circuit will be even stronger.

[0011] In one implementation, after building the model and before simulating the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse, the simulation method also includes:

[0012] The simulation model is calibrated so that the first attribute parameters of the simulation model meet the first preset parameters;

[0013] The comparison model is calibrated so that the second attribute parameters of the comparison model meet the second preset parameters.

[0014] In one implementation, the simulation model is calibrated using the experimental and simulation Id-Vg fitting curves of the simulation model; the comparison model is calibrated using the experimental and simulation Id-Vg fitting curves of the comparison model.

[0015] In one implementation, the electrostatic discharge (ESD) protection structure includes two diodes connected in series: a first diode and a second diode; the junction of the first diode and the second diode is electrically connected to the gate of the VDMOS, and an external electrode is connected to the junction for receiving electromagnetic pulses; the anode of the first diode is electrically connected to the source of the VDMOS, and the cathode of the second diode is electrically connected to the drain of the VDMOS.

[0016] In one implementation, an electromagnetic pulse is applied to the second VDMOS included in the comparative model, and a pulse curve is obtained to simulate the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse, including:

[0017] The second VDMOS has an on state and an off state. The curves of the peak electric field of the gate oxide layer of the second VDMOS under the action of electromagnetic pulse in the on state and the off state are obtained respectively.

[0018] Obtain the peak value of the gate oxide electric field of the second VDMOS in the turn-on state, and obtain the peak value of the gate oxide electric field of the second VDMOS in the turn-off state;

[0019] The MAX Electric field-Vpulse curve in the turn-on state is obtained based on the peak electric field of the gate oxide layer in the turn-on state, which is used to characterize the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse in the turn-on state.

[0020] The MAX Electric field-Vpulse curve in the off state is obtained based on the peak electric field of the gate oxide layer in the off state; it is used to characterize the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse in the off state.

[0021] In one implementation, the second VDMOS has an on state and an off state;

[0022] In the ON state, the electromagnetic pulse threshold for gate oxide breakdown of the second VDMOS is 14KV;

[0023] In the off state, the electromagnetic pulse threshold for gate oxide breakdown of the second VDMOS is 10.7KV.

[0024] Secondly, the present invention also provides a simulation system for the electromagnetic pulse effect of VDMOS, comprising: a model building module for building a simulation model and a comparison model, wherein the simulation model includes a first VDMOS and an electrostatic protection structure electrically connected to the first VDMOS, and the comparison model includes a second VDMOS;

[0025] The comparative model simulation unit is used to apply electromagnetic pulses to the second VDMOS included in the comparative model and obtain pulse curves to simulate the relationship between the peak electric field of the gate oxide layer of the second VDMOS and the electromagnetic pulse; it is also used to simulate the electromagnetic pulse threshold condition for the gate oxide layer breakdown of the second VDMOS included in the comparative model and determine the electromagnetic pulse threshold.

[0026] The simulation model simulation unit is used to apply current pulses to the electrodes included in the simulation model to obtain pulse curves, so as to simulate the relationship between the peak electric field of the first VDMOS gate oxide layer and the electromagnetic pulse.

[0027] Thirdly, the present invention also provides a simulation device, including a processor and a communication interface coupled to the processor; the processor is used to run computer programs or instructions to implement any of the above-mentioned simulation methods for VDMOS electromagnetic pulse effects.

[0028] Fourthly, the present invention also provides a storage medium storing instructions that, when executed, implement any of the above-mentioned simulation methods for VDMOS electromagnetic pulse effects. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0030] Figure 1 The device structure of VDMOS provided in the embodiments of the present invention;

[0031] Figure 2 Experimental and simulation IV curves of VDMOS provided for embodiments of the present invention;

[0032] Figure 3 Electromagnetic pulse simulation circuit diagram provided for embodiments of the present invention;

[0033] Figure 4 This is a simulation structural diagram of the electrostatic protection structure provided in an embodiment of the present invention;

[0034] Figure 5 The diode IV characteristics provided in the embodiments of the present invention are shown on the left: operating curve, and on the right: breakdown characteristic curve.

[0035] Figure 6 The voltage and current curves corresponding to the electromagnetic pulses provided for the embodiments of the invention;

[0036] Figure 7 The peak electric field of the gate oxide layer of an N / P type VDMOS without PN junction protection as provided in the embodiments of the invention changes with time under the action of an electromagnetic pulse. Left figure: On state, right figure: Off state;

[0037] Figure 8 The peak electric field of the gate oxide layer of an off-state N / P type VDMOS without PN junction protection provided in the embodiments of the invention varies with the peak value of the voltage pulse.

[0038] Figure 9The invention provides a variation of the peak electric field of the gate oxide layer of an on-state N / P type VDMOS with voltage pulse peak value when the PN junction is protected.

[0039] Figure 10 Circuit diagram of a simulation model with PN junction protection provided for embodiments of the invention;

[0040] Figure 11 With / without PN junction protection, the gate current of an N / P type VDMOS under the action of a current pulse. The solid line represents the gate current without diode protection, and the dashed line represents the gate current with diode protection.

[0041] Figure 12 The solid line represents the gate current of VDMOS under current pulse when there is no diode protection; the dashed line represents the gate current of VDMOS under current pulse when there is diode protection; the solid line represents the discharge current of the diode under pulse current when there is diode protection; the vertical axis of the left figure is a logarithmic scale, and the vertical axis of the right figure is a linear scale.

[0042] Figure 13 The change of peak electric field of gate oxide layer of N / P type VDMOS under current pulse with or without PN junction protection;

[0043] Figure 14 Without PN junction protection, the peak electric field of the gate oxide layer of VDMOS under the action of current pulse varies with the pulse intensity;

[0044] Figure 15 When protected by a PN junction, the peak electric field of the gate oxide layer of a VDMOS subjected to a current pulse varies with the pulse intensity. Detailed Implementation

[0045] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0048] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0049] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0050] In a first aspect, embodiments of the present invention provide a simulation method for VDMOS electromagnetic pulse effects, comprising the following steps:

[0051] S10. Construct a model, which includes a simulation model and a comparison model. The simulation model includes a first VDMOS and an electrostatic discharge protection structure electrically connected to the first VDMOS. The comparison model includes a second VDMOS.

[0052] In practical applications, such as Figure 1 As shown, the first VDMOS and the second VDMOS included in the simulation model and the comparison model can both be P-type VDMOS, with the source located on both sides, doped with boron at a concentration of 2E20cm⁻¹. -3 The EPI is a p-type epitaxial layer, and the drain below the EPI is boron-doped with a concentration of 1E18 cm⁻¹. -3 Nbase represents the arsenic-doped N-type base region, and N+ represents the arsenic doping concentration at 1E19cm⁻¹. -3 The ditch area.

[0053] After constructing the model, the simulation model is calibrated to ensure that its first attribute parameters meet a first preset parameter. The comparison model is then calibrated to ensure that its second attribute parameters meet a second preset parameter. Specifically, such as... Figure 2 As shown, calibration can be performed using experimental and simulated Id-Vg fitting curves of P-type VDMOS to determine whether the first attribute parameter of the simulation model is the same as or similar to the first preset parameter, and whether the second attribute parameter of the comparison model is the same as or similar to the second preset parameter. The first and second preset parameters include the structure, doping, and thickness of the models (simulation model and comparison model).

[0054] See Figure 3 In actual circuits, MOS devices are often externally protected against ESD (electrostatic discharge), typically using two diodes connected in series, namely the first diode and the second diode. The connection between the first and second diodes is electrically connected to the gate of the VDMOS device, and an external electrode is connected at this connection to receive electromagnetic pulses. The anode of the first diode is electrically connected to the source of the VDMOS device, and the cathode of the second diode is electrically connected to the drain of the VDMOS device. For electromagnetic pulse simulation of VDMOS devices, the TCAD simulation platform is used. The electromagnetic pulse signals encountered in practice are of two forms: voltage pulses and current pulses. In the simulation, voltage pulses with short rise times and current pulses with short fall times are used to represent electromagnetic pulses.

[0055] The electrostatic discharge (ESD) protection structure of the diodes (including the first and second diodes) ensures timely conduction to the VDD electrode after an ESD pulse, preventing damage to the device gate from high voltage. In the diagram, VDD is 8V, and the gate voltage bias is -5V (NMOS) and +5V (PMOS). Considering the actual diode breakdown voltage of 2kV in the TCAD simulation, the reverse breakdown voltage of the diodes (including the first and second diodes) is adjusted to 2kV by modifying the doping and dimensions. The diodes (including the first and second diodes) are shown below. Figure 4 As shown, its forward and reverse working characteristics are as follows: Figure 5 As shown. Since the N-type and P-type VDMOS have the same doping concentration, the simulation results show that the gate electric field under voltage pulse is consistent.

[0056] S11. Apply an electromagnetic pulse to the second VDMOS included in the comparison model and obtain a pulse curve to simulate the relationship between the peak electric field of the gate oxide layer of the second VDMOS and the electromagnetic pulse.

[0057] In practical applications, the effect of electromagnetic pulses on the peak electric field of the VDMOS gate oxide layer without diode protection was first simulated. A pulse with a rise time of 1 ns and a fall time of 1 ns was applied, and the pulse curve (similar to an actual electromagnetic pulse) is shown in the attached diagram. Figure 6 .

[0058] When an electromagnetic pulse acts directly on a device without being discharged through a diode, the circuit diagram is as follows: Figure 7 As shown in the figure, the peak electric field curve of the gate oxide layer obtained by simulation is as follows. Figure 8 As shown, the breakdown electric field of SiO2 is known to be 6 × 10⁻⁶. 6 V / cm. The peak pulse voltage was calculated to be 1×10 V / cm. 3 V, 5×10 2 V and 5×10 3 In case V, the highest value among the peak curves of the gate oxide layer electric field under pulsed action is taken, such as... Figure 7 The points marked with the middle circle are plotted as the MAX Electric field-Vpulse curve related to the electromagnetic pulse voltage, as shown below. Figure 8 , 9 As shown, Figure 8 When the gate oxide layer is in the off state, the peak electric field of the gate oxide layer changes under different peak voltage pulses. Figure 9 The peak electric field of the gate oxide layer varies under different peak voltage pulses in the on-state. It can be seen that regardless of whether the on-state or off-state is in operation, the electric field of the gate oxide layer changes significantly without PN junction protection, but none of these changes reach 6 × 10⁻⁶. 6 Gate oxide breakdown electric field of V / cm.

[0059] S12. Simulate the electromagnetic pulse threshold condition for gate oxide breakdown in the second VDMOS included in the comparative model to determine the electromagnetic pulse threshold. Simulation analysis shows that in the off state, the gate oxide electric field reaches a critical electric field when the electromagnetic pulse reaches 14kV; in the on state, the gate oxide breaks down when the electromagnetic pulse voltage reaches 10.7kV.

[0060] S13. Apply current pulses to the electrodes included in the simulation model to obtain pulse curves, so as to simulate the relationship between the peak electric field of the first VDMOS gate oxide layer and the electromagnetic pulse.

[0061] Circuit layout with diode protection as follows Figure 10As shown in the figure, the common node in the middle of the diodes is the protection node, which is connected to the gate of the VDMOS. Therefore, even if the diode can carry current under the action of a pulse voltage source, the voltage still applies to the device and will not change due to the presence or absence of the diode. Considering the limitations of voltage source pulse simulation results, which are not suitable for comparing the difference in the effect of the pulse source on VDMOS with and without diode protection, a current pulse source is used as the pulse input to analyze the gate current change with and without diode protection.

[0062] The simulation results of VDMOS gate current are as follows: Figure 11 As shown, the results for N-type and P-type diodes overlap, indicating that the diode can effectively discharge electromagnetic pulses simulated by a current source, reducing the device's susceptibility to electromagnetic pulses. The analysis results incorporating the diode's discharge current are shown below. Figure 12 When a diode discharges current, the current in the diode is consistent with the electromagnetic pulse curve.

[0063] Simulation results of the peak electric field of the VDMOS gate oxide layer changing with time are as follows: Figure 13 Simulation results of the peak electric field of the VDMOS gate oxide layer as a function of pulse intensity are shown in [the table]. Figure 14 , 15 It was found that without diode protection, the electromagnetic pulse caused a significant drop in the gate oxide breakdown voltage of the device, suggesting that the diode can effectively protect the gate oxide layer of the VDMOS.

[0064] In the above-mentioned technical solution, the electrostatic discharge (ESD) protection structure in front of the VDMOS power device is ignored in the traditional research on the impact of electromagnetic pulses (EMP) on power devices. This invention can make the simulation environment closer to actual conditions. In the EMP simulation part, voltage source pulses and current source pulses with a rise and fall time of 1ns are used to represent EMPs, and their respective effects on the devices are analyzed. Since voltage source pulses are not limited by diode protection when acting on devices, and the EMP protection structure in actual circuits can effectively resist EMPs, it is unreasonable to use voltage pulses as EMPs when simulating circuits with EMP protection. In order to reflect the role of EMP, this invention uses current source pulses as EMPs. The simulation analysis shows that the change law of the peak electric field of the gate oxide layer of the device under the action of EMP is consistent for both N-type and P-type devices. Moreover, when protected by diodes, the peak current pulse that the device can withstand is greatly increased. However, the peak current pulse that VDMOS and its protection circuit can withstand is limited by the reverse breakdown voltage of the diode in the protection circuit. When the reverse breakdown voltage of the diode is 2kV, the device can withstand an electromagnetic pulse of nearly 4mA without easily experiencing gate breakdown. When the maximum reverse breakdown voltage of the diode used is 2kV, the overall electromagnetic pulse tolerance of VDMOS and its protection circuit will be even stronger.

[0065] Secondly, the present invention also provides a simulation system for the electromagnetic pulse effect of VDMOS, comprising: a model building module for building a simulation model and a comparison model, wherein the simulation model includes a first VDMOS and an electrostatic protection structure electrically connected to the first VDMOS, and the comparison model includes a second VDMOS;

[0066] The comparative model simulation unit is used to apply electromagnetic pulses to the second VDMOS included in the comparative model and obtain pulse curves to simulate the relationship between the peak electric field of the gate oxide layer of the second VDMOS and the electromagnetic pulse; it is also used to simulate the electromagnetic pulse threshold condition for the gate oxide layer breakdown of the second VDMOS included in the comparative model and determine the electromagnetic pulse threshold.

[0067] The simulation model simulation unit is used to apply current pulses to the electrodes included in the simulation model to obtain pulse curves, so as to simulate the relationship between the peak electric field of the first VDMOS gate oxide layer and the electromagnetic pulse.

[0068] Thirdly, the present invention also provides a simulation device, including a processor and a communication interface coupled to the processor; the processor is used to run computer programs or instructions to implement any of the above-mentioned simulation methods for VDMOS electromagnetic pulse effects.

[0069] Fourthly, the present invention also provides a storage medium storing instructions that, when executed, implement any of the above-mentioned simulation methods for VDMOS electromagnetic pulse effects.

[0070] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0071] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0072] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A simulation method for VDMOS electromagnetic pulse effect, characterized in that, Includes the following steps: The model is constructed, comprising a simulation model and a comparison model. The simulation model includes a first VDMOS and an electrostatic discharge (ESD) protection structure electrically connected to the first VDMOS. The comparison model includes a second VDMOS. in, The electrostatic discharge protection structure includes two diodes connected in series: a first diode and a second diode; the connection between the first diode and the second diode is electrically connected to the gate of the VDMOS, and an external electrode is connected to the connection for receiving electromagnetic pulses; the positive terminal of the first diode is electrically connected to the source of the VDMOS, and the negative terminal of the second diode is electrically connected to the drain of the VDMOS. An electromagnetic pulse is applied to the second VDMOS included in the comparative model, and a pulse curve is obtained to simulate the relationship between the peak electric field of the gate oxide layer of the second VDMOS and the electromagnetic pulse, including: The second VDMOS has an on state and an off state. The peak electric field of the gate oxide layer of the second VDMOS in the on state and the off state are obtained as a function of time under the action of an electromagnetic pulse. Obtain the peak value of the gate oxide layer electric field of the second VDMOS in the on state, and obtain the peak value of the gate oxide layer electric field of the second VDMOS in the off state. The MAX Electric field-Vpulse curve in the on-state is obtained based on the peak electric field of the gate oxide layer during the on-state. This curve is used to characterize the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse during the on-state. The MAX Electric field-Vpulse curve in the off state is obtained based on the peak electric field of the gate oxide layer in the off state; it is used to characterize the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse in the off state. The electromagnetic pulse threshold condition for gate oxide layer breakdown in the second VDMOS included in the comparative model is simulated to determine the electromagnetic pulse threshold. A current pulse is applied to the electrodes included in the simulation model to obtain a pulse curve, thereby simulating the relationship between the peak electric field of the first VDMOS gate oxide layer and the electromagnetic pulse.

2. The simulation method for VDMOS electromagnetic pulse effect according to claim 1, characterized in that, After constructing the model, and before simulating the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse, the simulation method further includes: The simulation model is calibrated so that the first attribute parameters of the simulation model meet the first preset parameters; The comparison model is calibrated so that the second attribute parameters of the comparison model satisfy the second preset parameters.

3. The simulation method for VDMOS electromagnetic pulse effect according to claim 2, characterized in that, The simulation model is calibrated using the experimental and simulation Id-Vg fitting curves of the simulation model; the comparative model is calibrated using the experimental and simulation Id-Vg fitting curves of the comparative model.

4. The simulation method for VDMOS electromagnetic pulse effect according to claim 1, characterized in that, The second VDMOS has an on state and an off state; In the ON state, the electromagnetic pulse threshold for gate oxide breakdown of the second VDMOS is 14KV; In the off state, the electromagnetic pulse threshold for gate oxide breakdown of the second VDMOS is 10.7KV.

5. A simulation system for VDMOS electromagnetic pulse effect, characterized in that, include: The model building module is used to build a simulation model and a comparison model. The simulation model includes a first VDMOS and an electrostatic discharge (ESD) protection structure electrically connected to the first VDMOS. The comparison model includes a second VDMOS. in, The electrostatic discharge protection structure includes two diodes connected in series: a first diode and a second diode; the connection between the first diode and the second diode is electrically connected to the gate of the VDMOS, and an external electrode is connected to the connection for receiving electromagnetic pulses; the positive terminal of the first diode is electrically connected to the source of the VDMOS, and the negative terminal of the second diode is electrically connected to the drain of the VDMOS. The comparative model simulation unit is used to apply an electromagnetic pulse to the second VDMOS included in the comparative model and obtain a pulse curve to simulate the relationship between the peak electric field of the gate oxide layer of the second VDMOS and the electromagnetic pulse; it is also used to simulate the electromagnetic pulse threshold condition for the gate oxide layer breakdown of the second VDMOS included in the comparative model and determine the electromagnetic pulse threshold. The simulation model simulation unit is used to apply current pulses to the electrodes included in the simulation model to obtain pulse curves, so as to simulate the relationship between the peak electric field of the first VDMOS gate oxide layer and the electromagnetic pulse; in, An electromagnetic pulse is applied to the second VDMOS included in the comparative model, and a pulse curve is obtained to simulate the relationship between the peak electric field of the gate oxide layer of the second VDMOS and the electromagnetic pulse, including: The second VDMOS has an on state and an off state. The peak electric field of the gate oxide layer of the second VDMOS in the on state and the off state are obtained as a function of time under the action of an electromagnetic pulse. Obtain the peak value of the gate oxide layer electric field of the second VDMOS in the on state, and obtain the peak value of the gate oxide layer electric field of the second VDMOS in the off state. The MAX Electric field-Vpulse curve in the on-state is obtained based on the peak electric field of the gate oxide layer during the on-state. This curve is used to characterize the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse during the on-state. The MAX Electric field-Vpulse curve in the off state is obtained based on the peak electric field of the gate oxide layer in the off state; it is used to characterize the relationship between the peak electric field of the second VDMOS gate oxide layer and the electromagnetic pulse in the off state.

6. A simulation device, characterized in that, It includes a processor and a communication interface coupled to the processor; the processor is used to run computer programs or instructions to implement the simulation method of VDMOS electromagnetic pulse effect as described in claim 1.

7. A storage medium, characterized in that, The storage medium stores instructions that, when executed, implement the simulation method for the VDMOS electromagnetic pulse effect as described in claim 1.

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