Superconducting single flux quantum circuit layout and method

Abstract

A superconducting single-flux quantum circuit layout is provided, which includes a plurality of unit circuits, each of which includes at least one input port and at least one output port, and includes at each port: a Josephson junction, which includes a first end for connecting to the port, and a second end for connecting to ground; a first resistor, which includes a first end for connecting to the first end of the Josephson junction, and a second end for connecting to ground; wherein a bias line is arranged at the port connection between two adjacently connected unit circuits.

Description

Technical Field

[0001] The present invention relates to the field of superconducting single-flux quantum microprocessors in computer systems, and in particular to a superconducting single-flux quantum circuit layout and method thereof. Background Art

[0002] Today's mainstream microprocessors and computers all use CMOS technology. With the development of Moore's Law, the improvement of their performance-to-power ratio has gradually slowed down. In large computer systems, such as data centers and supercomputers, their power consumption has reached an unprecedented level. Therefore, in order to achieve a higher performance-to-power ratio, it is necessary to find other circuit technologies to overcome the above problems. High-speed single flux quantum (RSFQ) has become the most likely next-generation integrated circuit technology in some professional fields that have reached power consumption bottlenecks due to its ultra-high speed and ultra-low power consumption.

[0003] The working mechanism of RSFQ circuit is completely different from that of CMOS circuit. At the level of logic representation, compared with CMOS using level logic to realize binary, RSFQ uses pulse logic, that is, single flux quantum (SFQ) is used as the basic unit, and binary is realized by the presence or absence of pulse. Since it is based on pulse logic, RSFQ circuit is mainly described as a state machine structure. Therefore, compared with CMOS logic circuit, RSFQ circuit has a richer variety of circuits to realize the minimum subset of basic logic functions. At the physical level, since the operating frequency of RSFQ integrated circuits is much higher than that of CMOS integrated circuits, RSFQ integrated circuits cannot use a wiring method with a high degree of freedom like CMOS integrated circuits in wiring. Instead, it mainly adopts a highly unitized circuit design concept, that is, all functional circuits are standardized into small units of equal-sized structures, and large-scale construction of integrated circuits is realized through a unit splicing mode similar to building blocks. The design concept based on unit circuits often makes a trade-off and compromise between customization and consistency. Excessive customization will reduce the versatility and consistency of unit circuits, while excessive pursuit of consistency will often lead to low area utilization. Summary of the invention

[0004] Based on the above problems of the prior art, the present invention provides a superconducting single flux quantum circuit layout, which includes a plurality of unit circuits, each of which includes at least one input port and at least one output port, and at each port includes:

[0005] a Josephson junction including a first end for connection to the port and a second end for connection to ground;

[0006] a first resistor including a first end for connecting to the first end of the Josephson junction and a second end for connecting to ground;

[0007] A bias line is arranged at the port connection between two adjacently connected unit circuits.

[0008] Preferably, the bias line comprises a first end for connecting to the port junction, and a second end for connecting to a power injection point.

[0009] Preferably, the bias line is arranged on the left-hand side or the right-hand side of the port signal flow direction.

[0010] Preferably, the first resistor includes two second resistors, and the two second resistors are symmetrical with respect to a tangent direction of the port signal flow direction.

[0011] Preferably, the resistance of the second resistor is twice the resistance of the first resistor.

[0012] Preferably, when the bias line is not arranged, the circuit structure at the port junction is symmetrical with respect to the tangent direction and the normal direction of the port signal flow.

[0013] Preferably, the layout of the unit circuit is a rectangular structure.

[0014] Preferably, a complete center-injection type Josephson transmission line structure is formed at the port junction.

[0015] Preferably, the unit circuit is a Josephson transmission line, a superconducting device or a logic function circuit.

[0016] The present invention also provides a superconducting single flux quantum circuit layout method, the method comprising:

[0017] Arrange a plurality of unit circuits, wherein each of the unit circuits comprises at least one input port and at least one output port, and at each port comprises:

[0018] a Josephson junction including a first end for connection to the port and a second end for connection to ground;

[0019] a first resistor including a first end connected to the first end of the Josephson junction and a second end connected to ground; and

[0020] A bias line is arranged at the port connection between two adjacently connected unit circuits.

[0021] The unit circuit layout of the present invention adopts a standardized rectangular basic size to realize the large-scale construction of superconducting single-flux quantum integrated circuits. The unit circuit of the present invention adopts a consistent and symmetrical geometric structure, and the circuit parameters of the unit circuit have a high degree of consistency, which is the basis for realizing large-scale superconducting single-flux quantum integrated circuits. In addition, in the unit circuit layout and method of the present invention, the unit circuit design and power distribution are decoupled, and by making the bias line independent of the unit circuit design, uniform current distribution of the large-scale circuit network is achieved, thereby improving the working performance of the circuit. Compared with the prior art, the present invention can simultaneously meet the customization and consistency of the unit circuit, laying the foundation for designing reliable superconducting single-flux quantum integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a cascade schematic diagram of a Josephson transmission line circuit in the prior art.

[0023] Figure 2 It is a circuit diagram of a Josephson transmission line in the prior art.

[0024] Figure 3 Schematic diagram of a superconducting single flux quantum unit circuit according to an embodiment of the present invention.

[0025] Figure 4 yes Figure 3 Schematic diagram of the superconducting single flux quantum unit circuit layout shown.

[0026] Figure 5 A schematic diagram of a superconducting single flux quantum unit circuit according to another embodiment of the present invention is shown.

[0027] Figure 6 yes Figure 5 Schematic diagram of the superconducting single flux quantum unit circuit layout shown. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be noted that the embodiments given in the present invention are only for illustration and do not limit the protection scope of the present invention.

[0029] The present invention discloses an optimized superconducting single-flux quantum logic unit circuit layout and a layout method thereof. By taking into account the design concept of both customization and consistency, the logic unit circuit can achieve a better working state, providing a reference design basis for realizing stable and reliable large-scale superconducting single-flux quantum integrated circuits.

[0030] The unit circuit layout of the present invention uses a standardized basic rectangular unit size, and divides various logic functions into reusable unit circuits with consistent standardization at the layout level, such as 1x1, 2x1, 2x2, 3x1, 3x2, 3x3 and other unit length sizes. The connection between the ports of the unit circuits is located at the midpoint of each side of the unit circuit, and the overlapping vertices between the unit circuits are used as injection points for power supplies (sizes other than 1x1 can be regarded as a combination of multiple 1x1 sizes). The selection of the unit circuit size depends on the number of Josephson junctions in the unit circuit. Complex logic function circuits will use more Josephson junctions, thereby occupying a larger layout area than other unit circuits.

[0031] A highly consistent geometric structure is used at the port of the unit circuit, so as to achieve consistent circuit parameters at the joints between the unit circuits, so as to minimize the leakage current generated between the ports of the unit circuits and improve the stability of the circuit system. The unit circuit may include but is not limited to Josephson transmission lines, superconducting devices such as DFF, RDFF, NDRO, and complex logic function circuits composed of superconducting devices.

[0032] Figure 1 1 is a cascade diagram of a Josephson transmission line (JTL) circuit in the prior art, wherein, for the sake of clarity, the resistors in the JTL are omitted. The circuit in the dotted box is a circuit structure of a JTL 100. Figure 1 As shown, the JTL 100 includes current sources 105, 106 and Josephson junctions 103, 104. The first end of the current source 105 is connected to the ground GND, and the second end is connected to the first end of the Josephson junction 103, and the second end of the Josephson junction 103 is connected to the ground GND. The first end of the current source 106 is connected to the ground GND, and the second end is connected to the first end of the Josephson junction 104, and the second end of the Josephson junction 104 is connected to the ground GND. The first end of the Josephson junction 103 is connected to the first end of the Josephson junction 104. Figure 1 As shown, the current source 105 can be equivalent to a bias resistor R11 connected in series with a voltage source V11, the bias line 101 includes the bias resistor R11 and a wire connecting the bias resistor R11 to a section of the circuit, and the bias line 101 is used to provide a bias current for the Josephson junction 103. The current source 106 can be equivalent to a bias resistor R12 connected in series with a voltage source V12, the bias line 102 includes the bias resistor R12 and a wire connecting the bias resistor R12 to a section of the circuit, and the bias line 102 is used to provide a bias current for the Josephson junction 104.

[0033] Figure 1The equivalent inductance L11-L17 is also included, wherein the equivalent inductance L11-L14 is the equivalent inductance of the current source or the Josephson junction to the ground, i.e., the parasitic parameter in the Josephson transmission line. The equivalent inductance L15-L17 is the equivalent inductance between the superconducting elements, i.e., the design parameter in the Josephson transmission line. Therefore, the term "connection" used in the present invention includes electrical coupling, specifically includes coupling through equivalent inductance.

[0034] Figure 1 The JTL 100 in the figure presents a symmetrical circuit parameter, that is, the circuit parameters of the current sources 105, 106, the inductors L15, L17, and the Josephson junctions 103, 104 are all the same.

[0035] Figure 2 is a circuit diagram of a Josephson transmission line in the prior art, which is Figure 1 The JTL100 in is similar to the Figure 2 The resistor R s21 and R s22 , resistor R s21 connected in parallel to both ends of the Josephson junction 203, and the resistor R s22 Connected in parallel to both ends of the Josephson junction 204. Resistor R s21 and R s22 They are used to adjust the volt-ampere characteristic curves of the Josephson junctions 203 and 204 respectively so as to put them in a suitable working state.

[0036] Further, Figure 1 and Figure 2 The circuits shown differ in how the bias lines are used: Figure 2 The bias current of the bias line is Figure 1 In other words, Figure 1 From the structure in the dashed box, the two bias lines 101 and 107 near the left side of the dashed box are Figure 2 The bias lines 201 in the figure are equivalent circuits to each other, and the same is true on the right side.

[0037] Figure 1 and Figure 2 The JTLs shown in the figure are all center-injection type, such as Figure 2 As shown in , if the bias line is assigned to the inside of the JTL unit, the internal circuit structure of the divided unit will lose symmetry; Figure 1 As shown, if the bias line is strictly placed at the junction of adjacent JTL unit ports, in order to comply with the strict symmetry within the unit, a bias line must be configured at each port of the unit, which in turn increases the layout area.

[0038] Therefore, the present invention proposes a layout method for separating the bias line from the unit circuit as an independent unit component. After the bias line is separated from the unit circuit, from the perspective of the unit circuit, the structure at its input port and output port can ensure strict consistency. In addition, the bias line as an independent circuit component makes the placement of the bias line more flexible.

[0039] Figure 3 Schematic diagram of a superconducting single flux quantum unit circuit according to an embodiment of the present invention. Unit circuit 310 includes at least one input port and at least one output port. For convenience, the present invention is described by taking one input port and one output port as an example. Unit circuit 310 includes an input port IN for receiving an SFQ signal, and an output port OUT for outputting an SFQ signal. The input port IN and the output port OUT of the unit circuit 310 both include a half JTL circuit structure. The input port IN of the unit circuit 310 includes a current source 305, a Josephson junction 303, and a resistor R s31 , wherein the first end of the current source 305 is connected to the ground GND, the second end is connected to the first end of the Josephson junction 303, the first end of the Josephson junction 303 is connected to the input port IN of the unit circuit 310, the second end of the Josephson junction 303 is connected to the ground GND, the resistor R s31 The bias line 301 is connected in parallel to both ends of the Josephson junction 303 and is used to provide a bias current for the Josephson junction 303. The output port OUT of the unit circuit 310 includes a current source 306, a Josephson junction 304 and a resistor R s32 , wherein the first end of the current source 306 is connected to the ground GND, the second end is connected to the first end of the Josephson junction 304, the first end of the Josephson junction 304 is connected to the output port OUT of the unit circuit, the second end of the Josephson junction 304 is connected to the ground GND, the resistor R s32 Connected in parallel to both ends of the Josephson junction 304 .

[0040] Figure 4 yes Figure 3 The schematic diagram of the circuit layout of the superconducting single flux quantum logic unit is shown in FIG. Figure 4 As shown, the signal flows from the output port OUT of the unit circuit 411 to the input port IN of the unit circuit 410, and the signal flow direction is MM'. Figure 4 As shown, the Josephson junction is shown as a three-layer structure. Taking the Josephson junction 403 as an example, it includes a first layer (i.e., the first end of the Josephson junction), a second layer (i.e., the middle layer), and a third layer (i.e., the second end of the Josephson junction). The initial layout of the unit circuit 410 includes the Josephson junction 403, the resistor R s41 and Josephson junction 404, resistor R s42The Josephson junction 403 includes a first end for connecting to an input port IN of the unit circuit 410 and a second end for connecting to the ground; a resistor R s41 The Josephson junction 404 includes a first end connected to the first end of the Josephson junction 403 and a second end connected to the ground; the Josephson junction 404 includes a first end connected to the output port OUT of the unit circuit 410 and a second end connected to the ground; the resistor R s42 It includes a first end for connecting to the first end of the Josephson junction 404, and a second end for connecting to the ground. The structure at the output port OUT of the unit circuit 411 is the same as that of the unit circuit 410, and will not be repeated here. The bias line is not included in the initial layout of the unit circuits 410 and 411. After the unit circuit 411 is connected to the unit circuit 410, or after the layout of the entire circuit system is completed, the bias line 401 is arranged at the port connection between the output port OUT of the unit circuit 411 and the input port IN of the unit circuit 410 (i.e., the connection between the first end of the Josephson junction 407 and the first end of the Josephson junction 403). The bias line 401 includes a first end for connecting to the port connection, and a second end for connecting to a power injection point that provides power to the entire system. The bias line 401 includes a bias resistor R41, and the position R is the power injection point. For example, a voltage source can be arranged, one end of the voltage source is connected to the bias resistor R41, and the other end is connected to the ground.

[0041] like Figure 4 As shown, the input port IN of the unit circuit 410 and the output port OUT of the unit circuit 411 both include a half JTL circuit structure, so a complete JTL structure is formed at the port connection of the unit circuits 410 and 411. Figure 4 In the connection between the terminals of the unit circuit 410 and the unit circuit 411, a Josephson junction 407 and a resistor R s43 , Josephson junction 403, resistor R s41 and the bias line 401 constitute a complete JTL 420. Because the JTL adopts a symmetrical structure, there is no leakage current at the junction of the unit circuit ports, which avoids the need to consider the influence of leakage current in the design process of each independent unit circuit, simplifying the design process. From the perspective of physical layout, the JTL 420 is composed of the Josephson junctions 407 and 403 respectively contributed by the two unit circuits 410 and 411 near the port, and the bias line 401 injected at the center of the port junction to adjust the static operating point of the Josephson junctions 407 and 403. The unit circuits located near the port junction are geometrically symmetrical about the normal direction of the corresponding port signal flow MM', so there is a high degree of consistency between the circuit schematic and the physical layout.

[0042] The advantage of using the bias line as an independent circuit component is that the injection method of the bias line can be flexibly adjusted. The bias line can be set on the left hand side (L side) of the port signal flow direction, or it can be set on the right hand side (R side) of the port signal flow direction. For each port, the bias line can obtain current from the left hand side L of the port signal flow direction, or it can obtain current from its right hand side R. Reference Figure 4 The dotted boxes at the vertices of adjacent unit circuit grids (i.e., positions L and R) are power injection points, which are used to provide power to the entire system. On the physical layout plane, the circuit system can dynamically adjust the current distribution by adjusting the position where the bias line obtains the current, so that the power supply network can achieve a more uniform current density in the circuit area.

[0043] For a unit circuit layout, if the placement of all bias lines is considered, the number of layout types is equal to 2 n , where n is the number of unit circuit ports. Therefore, when extracting layout parameters, each case needs to be calculated to verify the consistency of circuit parameters. Since the circuit structure at the junction of the unit circuit ports is symmetrical (geometric structure without bias line), the difference between different cases is reduced. However, such symmetry is only symmetrical about the normal direction of the port signal flow, but not about the tangent direction of the port signal flow, which makes the parameter extraction results different between different cases.

[0044] In order to eliminate this difference, the present invention provides a physical layout of a symmetrical parallel resistor Josephson junction, so that the circuit structure near the port connection is a symmetrical structure with respect to the normal direction of the port signal flow and the tangent direction of the port signal flow, which can greatly eliminate the circuit parameter differences caused by different bias line placement positions.

[0045] Figure 5 FIG. 1 is a schematic diagram of a superconducting single flux quantum unit circuit according to another embodiment of the present invention. Figure 3 The same parts are not repeated here. The difference is that the two resistors R s51 and R s52 Connected in parallel to both ends of the Josephson junction 503, two resistors R s53 and R s54 Connected in parallel to both ends of the Josephson junction 504. Resistor R s51 =R s52 =2R s31 , R s53 =R s54 =2R s32 , preferably R s31 =R s32 .therefore Figure 3 and Figure 5 The equivalent circuit is exactly the same.

[0046] Figure 6 yes Figure 5 The schematic diagram of the superconducting single flux quantum unit circuit layout is shown in FIG. Figure 6 As shown, the signal flows from the output port OUT of the unit circuit 611 to the input port IN of the unit circuit 610, and the signal flow direction is MM'. The initial layout of the unit circuit 610 includes a Josephson junction 603, a resistor R s61 , R s62 and Josephson junction 604, resistor R s63 , R s64 The Josephson junction 603 includes a first end for connecting to an input port IN of the unit circuit 610 and a second end for connecting to the ground; a resistor R s61 The first end of the Josephson junction 603 is connected to the first end of the Josephson junction 603, and the second end of the Josephson junction 603 is connected to the ground; a resistor R s62 The Josephson junction 604 includes a first end connected to the first end of the Josephson junction 603 and a second end connected to the ground; the Josephson junction 604 includes a first end connected to the output port OUT of the unit circuit 610 and a second end connected to the ground; the resistor R s63 The first end of the Josephson junction 604 is connected to the first end of the Josephson junction 604, and the second end of the Josephson junction 604 is connected to the ground; a resistor R s64 The resistor R s61 , R s62 The resistor R is symmetrically distributed relative to the tangent direction of the port signal flow to MM'; s63 , R s64 The structure at the output port OUT of the unit circuit 611 is the same as that of the unit circuit 610, and will not be described in detail here. The bias line is not included in the initial layout of the unit circuits 610 and 611. After the output port OUT of the unit circuit 611 is connected to the input port IN of the unit circuit 610, the bias line 601 is arranged at the port connection between the output port OUT of the unit circuit 611 and the input port IN of the unit circuit 610 (i.e., the connection between the first end of the Josephson junction 607 and the first end of the Josephson junction 603).

[0047] like Figure 6As shown, at the port connection of the unit circuits 610 and 611, a complete center injection type JTL 620 is formed. The JTL 620 is symmetrical about the normal direction of the port signal flow, and when the bias line 601 is not placed, the JTL 620 is also symmetrical about the tangent direction of the port signal flow, so that the port connection between the unit circuits has a high degree of symmetry. Although two parallel resistors are used at each port of the unit circuit, part of the layout area is sacrificed, the symmetry and consistency achieved are a great advantage in the design of the unit circuit layout.

[0048] Preferably, the circuits at the input port and the output port of the unit circuit are consistent, so that the circuit structure at the port connection between the unit circuits is symmetrical with respect to both the tangent direction and the normal direction of the port signal flow.

[0049] Preferably, the unit circuit layout and the overall logic circuit layout of the present invention are both two-dimensional circuit layouts.

[0050] The present invention also provides a superconducting single flux quantum circuit layout method, the method comprising:

[0051] Arrange a plurality of unit circuits, wherein each of the unit circuits comprises at least one input port and at least one output port, and comprises at each port: a Josephson junction comprising a first end for connecting to the port, and a second end for connecting to ground; a first resistor comprising a first end for connecting to a first end of the Josephson junction, and a second end for connecting to ground; and

[0052] A bias line is arranged at the port connection between two adjacently connected unit circuits to form a complete center-injection JTL at the port connection.

[0053] The present invention provides a method for designing a logic unit device library of a superconducting single-flux quantum integrated circuit. Specifically, the present invention discloses an optimized superconducting single-flux quantum unit circuit layout and method thereof, which achieves better use effects of the unit circuit through a design concept that takes into account both customization and consistency, and provides a more stable design basis for the realization of large-scale superconducting single-flux quantum integrated circuits.

[0054] The unit circuit layout of the present invention adopts a standardized rectangular basic size to achieve large-scale construction of superconducting single-flux quantum integrated circuits. The unit circuit of the present invention adopts a consistent and symmetrical geometric structure. By using a consistent structure, the circuit parameters of the unit circuit have a high degree of consistency, which is the basis for realizing large-scale superconducting single-flux quantum integrated circuits. In addition, in the unit circuit layout and method of the present invention, the unit circuit design and power distribution are decoupled, and by making the bias line independent of the unit circuit design, uniform current distribution of the large-scale circuit network is achieved, thereby improving the working performance of the circuit. Compared with the prior art, the present invention can simultaneously meet the customization and consistency of the unit circuit, laying the foundation for designing reliable superconducting single-flux quantum integrated circuits.

[0055] Although the present invention has been described through preferred embodiments, the present invention is not limited to the embodiments described herein but includes various changes and modifications that may be made without departing from the scope of the present invention.

Claims

1. A superconducting single flux quantum circuit layout, comprising a plurality of unit circuits, each of the unit circuits comprising at least one input port and at least one output port, and at each port comprising: a Josephson junction including a first end for connection to the port and a second end for connection to ground; a first resistor including a first end for connecting to the first end of the Josephson junction and a second end for connecting to ground; A bias line is arranged at the port connection between two adjacently connected unit circuits; Wherein, the first resistor includes two second resistors, and the two second resistors are symmetrical with respect to the tangent direction of the port signal flow direction; Wherein, when the bias line is not arranged, the circuit structure at the port connection is symmetrical with respect to the tangent direction and the normal direction of the port signal flow.

2. The superconducting single flux quantum circuit layout according to claim 1, wherein: The bias line includes a first end for connecting to the port junction and a second end for connecting to a power injection point.

3. The superconducting single flux quantum circuit layout according to claim 1 or 2, wherein: The bias line is arranged on the left-hand side or the right-hand side of the port signal flow direction.

4. The superconducting single flux quantum circuit layout according to claim 1, wherein: The resistance of the second resistor is twice the resistance of the first resistor.

5. The superconducting single flux quantum circuit layout according to claim 1, wherein: The layout of the unit circuit is a rectangular structure.

6. The superconducting single flux quantum circuit layout according to claim 1, wherein: A complete center-injection type Josephson transmission line structure is formed at the port junction.

7. The superconducting single flux quantum circuit layout according to claim 1, wherein: The unit circuit is a Josephson transmission line, a superconducting device or a logic function circuit.

8. A superconducting single flux quantum circuit layout method, the method comprising: Arrange a plurality of unit circuits, wherein each of the unit circuits comprises at least one input port and at least one output port, and at each port comprises: a Josephson junction including a first end for connection to the port and a second end for connection to ground; a first resistor including a first end connected to the first end of the Josephson junction and a second end connected to ground; and Arranging a bias line at the port connection between two adjacently connected unit circuits; Wherein, the first resistor includes two second resistors, and the two second resistors are symmetrical with respect to the tangent direction of the port signal flow direction; Wherein, when the bias line is not arranged, the circuit structure at the port connection is symmetrical with respect to the tangent direction and the normal direction of the port signal flow.

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