Semiconductor memory device and method of operating the same

Abstract

The present disclosure relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory block including a plurality of memory strings, a pass-through circuit connected between a local word line of the memory block and a global word line and configured to connect the local word line to the global word line in response to a block selection signal, and a voltage supply circuit configured to generate an operating voltage during a program operation or a read operation, apply the operating voltage to the global word line, and discharge the global word line when the program operation or the read operation is completed, and the pass-through circuit is configured to control the local word line to be in a floating state after the program operation or the read operation is completed and before the global word line is discharged.

Description

TECHNICAL FIELD

[0001] The disclosure relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. BACKGROUND

[0002] Among semiconductor devices, semiconductor memory devices are roughly classified into volatile memory devices and nonvolatile memory devices.

[0003] Nonvolatile memory devices have relatively slow write and read speeds, however, the nonvolatile memory devices maintain stored data even if power supply is cut off. Accordingly, the nonvolatile memory devices are used to store data that is to be maintained regardless of power supply. The nonvolatile memory devices include read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. The flash memory is classified into NOR type and NAND type.

[0004] The flash memory has the advantages of freely programming and erasing data of the RAM and maintaining stored data even if power supply is cut off of the ROM. The flash memory is widely used as a storage medium of portable electronic devices such as digital cameras, personal digital assistants (PDAs), and MP3 players. SUMMARY

[0005] Embodiments of the disclosure provide a semiconductor memory device capable of preventing a channel of an operation storage block of a global word line of the semiconductor memory device from being boosted to a negative potential and an operating method thereof.

[0006] According to embodiments of the disclosure, a semiconductor memory device includes a storage block including a plurality of memory strings, a pass circuit connected between a local word line and a global word line of the storage block and configured to connect the local word line to the global word line in response to a block selection signal, and a voltage supply circuit configured to generate an operation voltage during a program operation or a read operation, apply the operation voltage to the global word line, and discharge the global word line upon completion of the program operation or the read operation, and the pass circuit is configured to control the local word line to be in a floating state after the program operation or the read operation is completed and before the global word line is discharged.

[0007] According to an embodiment of the present disclosure, a method of operating a semiconductor memory device includes electrically connecting local word lines of a memory block to global word lines, applying an operation voltage to the global word lines and transmitting the operation voltage to the local word lines, controlling the local word lines to be in a floating state by electrically interrupting the global word lines from the local word lines, and discharging the global word lines after the local word lines are controlled to be in the floating state.

[0008] According to an embodiment of the present disclosure, a method of operating a semiconductor memory device includes electrically connecting local word lines of a memory block to global word lines, applying a read voltage to selected local word lines among the local word lines through selected global word lines among the global word lines and applying a pass voltage to unselected local word lines through unselected global word lines, floating the local word lines by disconnecting the local word lines from the global word lines, and discharging the global word lines.

[0009] According to the present technology, by discharging the global word lines after the local word lines are controlled to be in a floating state by deactivating a pass circuit that controls connection between the global word lines and the local word lines during operation of a semiconductor memory device, it is possible to prevent a phenomenon in which a channel of a memory block is boosted to a negative potential. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is a circuit diagram illustrating a memory block and a pass circuit of Figure 1 according to an embodiment of the present disclosure.

[0012] Figure 3 is a block diagram illustrating control logic of Figure 2 according to an embodiment of the present disclosure.

[0013] Figure 4 is a flowchart illustrating a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 5 is a waveform diagram illustrating signals of a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 6 is a block diagram illustrating a memory system including a semiconductor memory device of Figure 1 according to an embodiment of the present disclosure.

[0016] Figure 7 is a block diagram illustrating an application example of a memory system of Figure 6 according to an embodiment of the present disclosure.

[0017] Figure 8 is a block diagram illustrating a semiconductor memory device according to an embodiment of the disclosure. Figure 7 A block diagram of a computing system of the memory system described. DETAILED DESCRIPTION

[0018] The specific structural or functional descriptions disclosed in accordance with embodiments of the concept disclosed in the present specification are illustrated to merely describe the embodiments of the concept according to the present disclosure. Embodiments of the concept according to the present disclosure can be implemented in various forms, and are not limited to the embodiments described in the present specification.

[0019] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings, so that those skilled in the art to which the present disclosure pertains can easily practice the technical spirit of the present disclosure.

[0020] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the disclosure.

[0021] Referring to Figure 1 , the semiconductor memory device 100 includes a memory block 110, a pass circuit 120, a voltage supply circuit 130, a block decoder 140, and control logic 150.

[0022] The memory block 110 can include a plurality of memory strings, and each of the plurality of memory strings can include a plurality of memory cells connected in series. In an embodiment, the plurality of memory cells can be non-volatile memory cells, and can be constituted by non-volatile memory cells having a vertical channel structure. The memory block 110 can be configured as an array of memory cells having a two-dimensional structure. According to an embodiment, the memory block 110 can be configured as an array of memory cells having a three-dimensional structure. Each of the plurality of memory cells can store at least one data bit. In an embodiment, each of the plurality of memory cells included in the memory block 110 can be a single-level cell (SLC) storing one data bit. In another embodiment, each of the plurality of memory cells included in the memory block 110 can be a multi-level cell (MLC) storing two data bits. In still another embodiment, each of the plurality of memory cells included in the memory block 110 can be a triple-level cell (TLC) storing three data bits. In yet another embodiment, each of the plurality of memory cells included in the memory block 110 can be a quad-level cell (QLC) storing four data bits. According to an embodiment, the memory block 110 can include a plurality of memory cells each storing five or more data bits. A detailed description of the configuration of the memory block 110 is described later.

[0023] The circuit 120 is connected between the global word line GWL and the local word line LWL of the memory block 110. The circuit 120 electrically connects the global word line GWL to the local word line LWL in response to the block word line signal BLKWL. For example, during the overall operation (e.g., a program operation or a read operation) of the semiconductor memory device 100, the circuit 120 can transmit an operation voltage transmitted through the global word line GWL to the local word line LWL in response to the block word line signal BLKWL. Also, after the program operation or the read operation of the semiconductor memory device 100 is completed, the circuit 120 can be deactivated in response to the block word line signal BLKWL to float the local word line LWL of the memory block 110 before discharging the potential of the global word line GWL. Thus, it is possible to prevent a phenomenon in which the channel of a memory string included in the memory block 110 is boosted to a negative level when the potential of the global word line GWL is discharged.

[0024] The voltage supply circuit 130 includes a voltage generation circuit 131, a global word line switch circuit 132, and a discharge circuit 133.

[0025] The voltage generation circuit 131 generates a plurality of operation voltages used during the overall operation of the semiconductor memory device 100 in response to a first voltage generation control signal VG_signals1 and a second voltage generation control signal VG_signals2.

[0026] For example, the voltage generation circuit 131 generates a turn-on voltage to be applied to the drain select line and the source select line among the local word lines LWL of the selected memory block in response to the first control signal VG_Signals1. During the program operation of the semiconductor memory device 100, the voltage generation circuit 131 generates a program voltage to be applied to the selected word line among the local word lines LWL of the selected memory block and a pass voltage to be applied to the unselected word line in response to the second control signal VG_signals2. Also, the voltage generation circuit 131 generates a turn-on voltage to be applied to the drain select line and the source select line among the local word lines LWL of the selected memory block in response to the first control signal VG_Signals1. During the read operation of the semiconductor memory device 100, the voltage generation circuit 131 generates a read voltage to be applied to the selected word line among the local word lines LWL of the selected memory block and a pass voltage to be applied to the unselected word line in response to the second control signal VG_signals2.

[0027] The global word line switch circuit 132 performs switching in response to a switch control signal SW_signals and transmits an operation voltage to be applied to the selected memory block to the global word line GWL. The operation voltage can be generated by the voltage generation circuit 131.

[0028] The discharge circuit 133 discharges the potential of the global word line GWL to a ground level after the completion of the overall operation of the semiconductor memory device 100. For example, when the programming operation or the read operation of the semiconductor memory device 100 is completed, the discharge circuit 133 discharges the potential of the global word line GWL to a ground level in response to the discharge signal Disch_signals after the global word line GWL and the local word line LWL of the memory block 110 are electrically disconnected from each other by the pass circuit 120 described above and thus the local word line LWL is controlled to be in a floating state.

[0029] The block decoder 140 generates the block selection signal BLKWL in response to the decoder control signal DC_signals. For example, when the memory block 110 is a selected memory block, the block decoder 140 generates and outputs the block selection signal BLKWL having a high potential in response to the decoder control signal DC_signals, and when the memory block 110 is an unselected memory block, the block decoder 140 deactivates the block selection signal BLKWL in response to the decoder control signal DC_signals. The block selection signal BLKWL having a high potential can activate the pass circuit 120 to electrically connect the global word line GWL to the local word line LWL of the memory block 110. The deactivated block selection signal BLKWL can cause the pass circuit 120 to be deactivated to electrically disconnect the global word line GWL from the local word line LWL of the memory block 110.

[0030] The control logic 150 controls the voltage supply circuit 130 and the block decoder 140 during the overall operation of the semiconductor memory device 100. For example, the control logic 150 can generate and output the first voltage generation control signal VG_signals1 and the second voltage generation control signal VG_signals2 for controlling the voltage generation circuit 131 to generate the operation voltage to be applied to the global word line GWL. For example, the control logic 150 can generate and output the switch control signal SW_signals for controlling the global word line switch circuit 132 to switch the operation voltage generated by the voltage generation circuit 131 to the global word line GWL. For example, the control logic 150 can generate and output the discharge signal DISCH_signals for controlling the discharge circuit 133 to discharge the global word line GWL. Further, the control logic 150 can generate and output the decoder signal DC_signals for controlling the block decoder 140.

[0031] In the above-described embodiments of the present disclosure, one memory block is shown and described, but the semiconductor memory device 100 can include a plurality of memory blocks. When the semiconductor memory device 100 includes a plurality of memory blocks, the semiconductor memory device 100 can further include a plurality of pass circuits and a plurality of block decoders corresponding to each of the plurality of memory blocks.

[0032] For example, a storage block may correspond to a circuit 120 and a block decoder, but it is not limited to this, and at least two storage blocks may share a block decoder.

[0033] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 The storage blocks and the circuit diagram through the circuit.

[0034] Reference Figure 2 , in response to Figure 1 The block select signal BLKWL output by the block decoder 140 is connected to the global word lines GDSL, GSSL, and GWL via circuit 120. <n:0>and local word lines DSL, SSL, and LWL of the memory block 110 <n:0>The global word line can include a global drain select line GDSL, a global source select line GSSL, and a plurality of global lines GWL <n:0>and the local word line can include a drain select line DSL, a source select line SSL, and a plurality of word lines LWL <n:0>For example, circuit 120 can connect the global drain select line GDSL and the global source select line GSSL to the drain select line DSL and the source select line SSL of memory block 110, respectively, in response to the block select signal BLKWL, and connect multiple global lines GWL. <n:0>are connected to a plurality of word lines LWL <n:0>Furthermore, when the block selection signal BLKWL is deactivated to a logic low level (e.g., a potential of 0V), the plurality of global lines GWL <n:0>and a plurality of word lines LWL <n:0>electrically disconnected to turn off a plurality of word lines LWL <n:0>The control is in a floating state.

[0035] The circuit 120 can include a plurality of transistors PT1 to PT4, and the plurality of transistors PT1 to PT4 can be depletion mode transistors. For example, the transistor PT1 is connected in series between the global drain select line GDSL and the drain select line DSL. The transistor PT2 is connected in series between the global line GWL <n>and word line WLW <n>between the transistor PT1 and the transistor PT2, between the transistor PT2 and the transistor PT3, and between the transistor PT3 and the transistor PT4. The transistors PT1 to PT4 are turned on or off in response to a block selection signal BLKWL.

[0036] The memory block 110 includes a plurality of word lines LWL <n:0>a plurality of memory cells MC <n:0>In addition, the memory block 110 includes a drain select transistor DST connected to a drain select line DSL and a source select transistor SST connected to a source select line SSL. Multiple source select transistors SST can share a source line SL. The drain select transistor DST, the multiple memory cells MC <n:0>And a source select transistor SST can be defined as one memory string. That is, the memory block 110 can include a plurality of memory strings corresponding to a plurality of corresponding bit lines BL1 to BLm.

[0037] Although not shown in Figure 1 and Figure 2 , a page buffer can be connected to each of the plurality of bit lines BL1 to BLm. The page buffer can apply a program enable voltage or a program inhibit voltage to the plurality of bit lines BL1 to BLm during a program operation. In addition, the page buffer can read data by sensing a potential or current amount of the plurality of bit lines BL1 to BLm during a read operation.

[0038] Figure 3 is a block diagram of control logic according to an embodiment of the disclosure. Figure 2 is a block diagram of control logic according to an embodiment of the disclosure.

[0039] Referring to Figure 3 , the control logic 150 can include a ROM 151, a voltage generation control circuit 152, a switch signal generation circuit 153, and a discharge signal generation circuit 154.

[0040] The ROM 151 stores an algorithm for performing overall operations of the semiconductor memory device. The ROM 151 generates and outputs first to fourth internal control signals int_cs1 to int_cs4 and decoder signals DC_signals according to the algorithm stored therein and a command signal CMD input from the outside (for example, from a host connected to the semiconductor memory device).

[0041] The voltage generation control circuit 152 can include a select line voltage control circuit 152A and a word line voltage control circuit 152B.

[0042] In response to the first internal control signal int_cs1, the select line voltage control circuit 152A generates and outputs a first voltage generation control signal VG_signals1 for controlling the voltage generation circuit 131 of Figure 1 to generate an operating voltage (for example, an on voltage or an off voltage to be applied to the drain select line and the source select line of the selected memory block).

[0043] In response to the second internal control signal int_cs2, the word line voltage control circuit 152B generates and outputs a second voltage generation control signal VG_signals2 for controlling the voltage generation circuit 131 of Figure 1 to generate an operating voltage (for example, a program voltage, a read voltage, or a pass voltage) to be applied to the word line of the selected memory block.

[0044] In response to the address signal ADDR and a third internal control signal int cs3, the switch signal generation circuit 153 generates and outputs a switch signal SW_signals for controlling Figure 1 the global word line switch circuit 132 to switch the operation voltage generated by the voltage generation circuit 131 to Figure 1 the switch control signal SW_signals of the global word line GWL.

[0045] In response to a fourth internal control signal int cs4, the discharge signal generation circuit 154 generates and outputs a discharge signal Disch_signals for controlling Figure 1 the discharge circuit 133 to discharge the potential of the global word line GWL to the ground level after the programming operation or the read operation of the semiconductor memory device is completed and the local word line LWL of the memory block 110 is controlled to be in the floating state by Figure 1 the pass circuit 120.

[0046] Figure 4 is a flowchart illustrating a read operation of the semiconductor memory device according to the embodiment of the present disclosure.

[0047] Figure 5 is a waveform chart of signals illustrating a read operation of the semiconductor memory device according to the embodiment of the present disclosure.

[0048] A method of operating the semiconductor memory device according to the embodiment of the present disclosure is described below with reference to Figures 1 to 5

[0049] The embodiment of the present disclosure describes a read operation among overall operations of the semiconductor memory device as an example.

[0050] ​In operation S410, in response to the block selection signal BLKWL, the global word line GWL is electrically connected to the local word line LWL of the memory block 110 by the circuit 120. For example, in response to the decoder control signal DC_signals, the block decoder 140 generates the block selection signal BLKWL having a high potential HV. The global word line GWL is electrically connected to the local word line LWL by the circuit 120 in response to the block word line signal BLKWL. The voltage generation circuit 131 generates the turn-on voltage Vturn-on to be applied to the drain selection line and the source selection line among the local word lines LWL of the selected memory block in response to the first control signal VG_signals1, and the global word line switch circuit 132 transmits the turn-on voltage Vturn-on to the global drain selection line GDSL and the global source selection line GSSL among the global word lines GWL in response to the switch control signal SW_signals. Accordingly, the turn-on voltage Vturn-on is applied to the drain selection line DSL and the source selection line SSL of the memory block 110, and the drain selection transistor DST and the source selection transistor SST of the memory block 110 are turned on.

[0051] Thereafter, the voltage generation circuit 131 generates the pass voltage Vpass in response to the second control signal VG_signals2, and the global word line switch circuit 132 applies the pass voltage Vpass to the global line GWL in response to the switch control signal SW_signal <n:0>Therefore, the voltage Vpass is applied to the word line LWL of the memory block 110 by the voltage Vpass <n:0>.

[0052] In operation S420, the bit line voltage VBL is applied to the plurality of bit lines BL1 to BLm, and thus each channel of the memory string has the level of the bit line voltage VBL. The read voltage Vread is applied to the selected word line (e.g., LWL<0>) of the memory block 110. For example, the voltage generation circuit 131 generates the read voltage Vread in response to the second control signal VG_signals2. The global word line switch circuit 132 applies the read voltage Vread to the selected global line (e.g., GWL<0>) in response to the switch control signal SW_signals. Thus, the read voltage Vread is applied to the selected word line LWL<0> of the memory block 110.

[0053] In operation S430, when the read operation of the semiconductor storage device is completed, the voltage generation circuit 131 generates the equalization voltage Veq in response to the second control signal VG_signals2. The global word line switch circuit 132 applies the equalization voltage Veq to the global line GWL <n:0>Thus, the word line LWL of the memory block 110 <n:0>The potential of the pass-through circuit 120 is adjusted to the level of the equalization voltage Veq. The equalization voltage Veq can be a voltage having a potential lower than the potential of the pass-through voltage Vpass.

[0054] In operation S440, the pass-through circuit 120 is deactivated to control the local word line of the memory block to be in a floating state. For example, the block decoder 140 deactivates the pass-through circuit 120 by discharging the block selection signal BLKWL having a high potential to 0V. Accordingly, the pass-through circuit 120 is deactivated to electrically disconnect the global word line GWL from the local word line LWL of the memory block 110. Accordingly, the word line LWL of the memory block 110 is controlled to be in a floating state. <n:0>is controlled to be in a floating state. At this time, the drain selection line DSL and the source selection line SSL can be discharged to 0 V as a cutoff voltage.

[0055] In operation S450, the word line LWL of the memory block 110 is controlled to be in a floating state. <n:0>After being controlled to be in the floating state, the discharge circuit 133 discharges the potential of the global word line GWL to the ground level in response to the discharge signal Disch_signals. At this time, since the word line LWL of the memory block 110 is in the floating state, the potential of the word line LWL is also discharged to the ground level. Thus, the potential of the word line WL of the memory cell 101 is discharged to the ground level. As a result, the memory cell 101 is controlled to be in the floating state. <n:0>The phenomenon in which the channels of the plurality of memory strings of the memory block 110 are boosted to a negative potential level of 0 V or less is prevented even if the potential of the global word line GWL is discharged to a ground level.

[0056] Figure 6 is a block diagram of a memory system including a semiconductor memory device according to an embodiment of the disclosure. Figure 1

[0057] Referring to Figure 6 , the memory system 1000 includes a semiconductor memory device 100 and a controller 1100.

[0058] The semiconductor memory device 100 is the same as the semiconductor memory device described with reference to Figure 1 Hereinafter, a repeated description is omitted.

[0059] The controller 1100 is connected to a host Host and the semiconductor memory device 100. The controller 1100 is configured to access the semiconductor memory device 100 in response to a request from the host Host. For example, the controller 1100 is configured to control a read operation, a write operation, and a background operation of the semiconductor memory device 100. The controller 1100 is configured to provide an interface between the semiconductor memory device 100 and the host Host. The controller 1100 is configured to drive firmware for controlling the semiconductor memory device 100.

[0060] The controller 1100 includes a random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 is used as at least one of an operation memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host Host, and a buffer memory between the semiconductor memory device 100 and the host Host. The processing unit 1120 controls all operations of the controller 1100. In addition, the controller 1100 can temporarily store program data provided from the host Host during a write operation.

[0061] ​The host interface 1130 includes a protocol for performing data exchange between the host Host and the controller 1100. In an embodiment, the controller 1100 is configured to communicate with the host Host through at least one of various interface protocols such as a Universal Serial Bus (USB) protocol, a Multi-Media Card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a Peripheral Component Interconnect-Express (PCI-Express) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA (SATA) protocol, a Parallel ATA (PATA) protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a proprietary protocol.

[0062] The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface includes a NAND interface or a NOR interface.

[0063] The error correction block 1150 is configured to detect and correct errors of data received from the semiconductor memory device 100 using an error correction code (ECC). The processing unit 1120 will control the semiconductor memory device 100 to adjust a read voltage and perform a read operation again according to an error detection result of the error correction block 1150. In an embodiment, the error correction block 1150 can be provided as a component of the controller 1100.

[0064] The controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device. In an embodiment, the controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CompactFlash card (CF), a Smart Media card (SM or SMC), a Memory Stick, a Multi-Media Card (MMC, RS-MMC, or micro-SD), an SD card (SD, mini-SD, micro-SD, or SDHC), and a Universal Flash Storage (UFS).

[0065] The controller 1100 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a semiconductor drive (Solid State Drive (SSD)). The semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), an operation speed of a host Host connected to the memory system 1000 is sharply increased.

[0066] As another example, the memory system 1000 is provided as one of various components of an electronic device such as a computer, an ultra-mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, and a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID device, or one of various components configuring a computing system.

[0067] In an embodiment, the semiconductor memory device 100 or the memory system 1000 can be mounted as various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 can be packaged and mounted in a method such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual-in-line package (PDIP), a wafer-level package, a wafer-level chip scale package (WCP), a wafer-level process package (WFP), or a wafer-level process package (WSP).

[0068] Figure 7 is a block diagram of an application example of a memory system according to an embodiment of the disclosure. Figure 6

[0069] Referring to Figure 7 , the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips is divided into a plurality of groups.

[0070] In Figure 7 , the plurality of groups respectively communicates with the controller 2200 through first to k-th channels CH1 to CHk. Each semiconductor memory chip can be configured and operated similarly to the semiconductor memory device described with reference to Figure 1

[0071] ​​Each group is configured to communicate with the controller 2200 through one common channel. The controller 2200 is similar to the controller 1100 described with reference to Figure 6 described with reference to

[0072] Figure 8 is a block diagram of a computing system including the memory system described with reference to Figure 7 described with reference to

[0073] described with reference to Figure 8 The computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and the memory system 2000.

[0074] The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0075] In Figure 8 , the semiconductor memory device 2100 is connected to the system bus 3500 through the controller 2200. However, the semiconductor memory device 2100 can be configured to be directly connected to the system bus 3500. At this time, the functions of the controller 2200 are performed by the central processing unit 3100 and the RAM 3200.

[0076] In Figure 8 , the memory system 2000 described with reference to Figure 7 is provided. However, the memory system 2000 can be replaced with the memory system 1000 described with reference to Figure 6 In an embodiment, the computing system 3000 can be configured to include both the memory system 1000 described with reference to Figure 6 and the memory system 2000 described with reference to Figure 7 .

[0077] Although the detailed description of the present disclosure describes specific embodiments, various changes are possible without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present disclosure and the appended claims.

[0078] Cross Reference to Related Applications

[0079] This application claims priority to Korean Patent Application No. 10-2020-0176739, filed on December 16, 2020, the entire contents of which are incorporated herein by reference. < / n> < / n>

Claims

1. A semiconductor memory device, comprising: a memory block including a plurality of memory strings; a pass-through circuit connected between a local word line of the memory block and a global word line, and connecting the local word line to the global word line in response to a block selection signal; and a voltage supply circuit generating an operation voltage during a program operation or a read operation, applying the operation voltage to the global word line, and discharging the global word line upon completion of the program operation or the read operation, wherein the pass-through circuit further disconnects the local word line from the global word line after the program operation or the read operation is completed, and wherein the pass-through circuit discharges the global word line when the local word line is disconnected from the global word line.

2. The semiconductor memory device according to claim 1, further comprising a block decoder: generating and outputting the block selection signal to the pass-through circuit at a high potential during the program operation or the read operation of the memory block, and deactivating the block selection signal to a ground level before discharging the global word line.

3. The semiconductor memory device of claim 1, wherein, the voltage supply circuit includes: a voltage generation circuit generating the operation voltage to be applied to the global word line during the program operation or the read operation; a global word line switch circuit switching the operation voltage generated by the voltage generation circuit to the global word line; and a discharge circuit discharging the global word line to a ground level.

4. The semiconductor memory device according to claim 3, wherein, the discharge circuit discharges the global word line after the local word line is in a floating state.

5. The semiconductor memory device according to claim 1, further comprising a control logic: controlling a block decoder and the voltage supply circuit during the program operation or the read operation, generating and outputting a first control signal to control the application of the operation voltage to the global word line during the program operation or the read operation, and generating and outputting a second control signal to control the global word line when the program operation or the read operation is completed.

6. The semiconductor memory device of claim 5, wherein, the control logic includes: a ROM storing an overall operation algorithm, and generating and outputting a plurality of internal control signals in response to a command received from the outside; a voltage generation control circuit generating the first control signal to control the voltage supply circuit in response to any one of the plurality of internal control signals; and a discharge signal generation circuit generating the second control signal to control a discharge circuit in response to any one of the plurality of internal control signals.

7. A method of operating a semiconductor memory device, comprising the steps of: electrically connecting a local word line of a memory block to a global word line; applying an operation voltage to the global word line and transferring the operation voltage to the local word line; controlling the local word line to be in a floating state by electrically disconnecting the global word line from the local word line; and discharging the global word line when the local word line is disconnected from the global word line.

8. The method of claim 7, further comprising the steps of: adjusting the operating voltage applied to the global word line to an equalization voltage level before electrically disconnecting the global word line from the local word line after applying the operating voltage to the local word line.

9. The method of claim 8, wherein, the step of applying the operating voltage to the global word line comprises the steps of: applying a read voltage to a selected global word line among the global word lines; and applying a pass voltage to the remaining unselected global word lines.

10. The method of claim 9, wherein, the pass voltage has a higher potential than the equalization voltage level.

11. A method of operating a semiconductor memory device, the method comprising the steps of: electrically connecting a local word line connected to a memory block to a global word line; applying a read voltage to a selected local word line among the local word lines through a selected global word line among the global word lines, and applying a pass voltage to an unselected local word line through an unselected global word line; floating the local word line by disconnecting the local word line from the global word line; and discharging the global word line when the local word line is disconnected from the global word line.

12. The method of claim 11, further comprising the steps of: adjusting the local word line to an equalization potential before floating the local word line.

13. The method of claim 12, wherein, the equalization potential is lower than a potential of the pass voltage.

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