Memory device detecting defects by measuring line resistance of word lines

Abstract

A memory device includes an array of memory cells including memory cells, a row decoder to select a word line in response to a received address, and control logic including a sense capacitor, a size of the sense capacitor proportional to a size of a word line capacitor associated with the selected word line. The control logic measures a line resistance of the selected word line by pre-charging the selected word line, performing a charge sharing operation between the selected word line and the sense capacitor after pre-charging the selected word line, and measuring a voltage of the sense capacitor after performing the charge sharing operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0175296, filed with the Korean Intellectual Property Office on December 15, 2020, the subject of which is incorporated herein by reference. Technical Field

[0003] The present invention typically relates to memory devices. Background Technology

[0004] Non-volatile memory devices in which memory cells are vertically stacked to improve integration density have been actively studied. Specifically, as the number of stacked stages increases, the height of one or more metal contacts connected to the word line board also increases. As a result, it may be difficult to perform the contact processes associated with the interconnect wires, and the resistance distribution may increase. Therefore, resistance defects in vertically stacked non-volatile memory devices may increase. Summary of the Invention

[0005] Embodiments of the present invention provide a memory device capable of detecting potential resistance defects by measuring the line resistance of (open node) word lines that include capacitive components.

[0006] According to one aspect of the present invention, a memory device includes: a memory cell array comprising memory cells respectively disposed in regions at the intersection of word lines and bit lines; a line decoder configured to select a word line (“selected word line”) from the word lines in response to a received address; and control logic including a sensing capacitor whose size is proportional to the size of a word line capacitor associated with the selected word line, wherein the control logic is configured to measure the line resistance of the selected word line by pre-charging the selected word line, performing a charge-sharing operation between the selected word line and the sensing capacitor after pre-charging the selected word line, and measuring the voltage of the sensing capacitor after performing the charge-sharing operation.

[0007] According to one aspect of the present invention, a memory device includes: a memory cell array comprising memory cells respectively disposed in regions where word lines and bit lines intersect; a line decoder configured to select a word line (“selected word line”) from the word lines in response to a received address; and control logic configured to measure the line resistance of the selected word line. The control logic includes: a sensing capacitor; a voltage driver providing a charging voltage; a first switch having a first terminal and a second terminal connected to the voltage driver; a second switch having a first terminal connected to the selected word line and a second terminal connected to the second terminal of the first switch; a third switch having a first terminal and a second terminal connected between the first switch and the second switch; a fourth switch connected in parallel with the sensing capacitor and connected to the second terminal of the third switch; and a comparator including a first input terminal receiving a sensed voltage from the sensing capacitor and a second input terminal receiving a reference voltage.

[0008] According to one aspect of the present invention, a memory device includes: a memory cell array comprising memory cells respectively disposed in regions where word lines and bit lines intersect; a line decoder configured to select a word line (“selected word line”) from the word lines in response to a received address; and control logic including a normalization unit and a test unit, the normalization unit being configured to perform at least one data access operation associated with a memory cell connected to the selected word line, the test unit including a sensing capacitor, wherein the test unit is configured to measure the line resistance of the selected word line and a leakage current associated with the selected word line by: performing a charge-sharing operation between the selected word line and the sensing capacitor; measuring the voltage of the sensing capacitor during a first time period after performing the charge-sharing operation to measure the line resistance of the selected word line; and measuring the voltage of the sensing capacitor during a second time period after the first time period to measure the leakage current associated with the selected word line. Attached Figure Description

[0009] The above and other aspects, features, and advantages of the inventive concept can be more clearly understood upon consideration of the detailed description and accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the concept of the present invention;

[0011] Figure 2 and Figure 3 These are, respectively, a partial equivalent circuit diagram and a cross-sectional view of a memory device according to an embodiment of the concept of the present invention;

[0012] Figure 4This is a waveform diagram illustrating the cell distribution of a memory device according to an embodiment of the present invention;

[0013] Figure 5 This is a block diagram illustrating a memory device according to an embodiment of the concept of the present invention, and Figure 6 yes Figure 5 Equivalent circuit diagram of the memory device;

[0014] Figure 7 , Figure 8 , Figure 9 and Figure 10 (Hereafter referred to as "") Figures 7 to 10 () is a set of related block diagrams and voltage waveform diagrams illustrating exemplary operation of a memory device according to an embodiment of the present invention;

[0015] Figure 11 This is a block diagram illustrating a memory device according to an embodiment of the concept of the present invention; and

[0016] Figure 12 This is a cross-sectional view of a memory device according to an embodiment of the present invention. Detailed Implementation

[0017] In the following description, certain embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0018] Figure 1 This is a block diagram illustrating a memory device 10 according to an embodiment of the present invention.

[0019] Reference Figure 1 The memory device 10 typically includes a cell area 20 and a peripheral circuit area 30. Here, the peripheral circuit area 30 may include a line decoder 31, a voltage generator 32, a page buffer 33, an input / output (I / O) circuit 34, and control logic 35.

[0020] Cell region 20 includes memory cells that can be divided into memory blocks (hereinafter, “blocks”) BLK1 to BLKn. Blocks BLK1 to BLKn are connected to row decoder 31 via common source line CSL, string select line SSL, word line WL, and ground select line GSL, and are also connected to page buffer 33 via bit line BL. For example, in each of blocks BLK1 to BLKn, memory cells disposed at the same height (e.g., physical level) above the substrate can be connected to the same word line in word line WL, and memory cells disposed at the same location in a plane parallel to the upper surface of the substrate can provide a string of memory cells sharing a single channel layer. Furthermore, some of the strings of memory cells respectively included in blocks BLK1 to BLKn can be connected to the same bit line BL.

[0021] In response to address ADDR and / or more control signals received from control logic 35, line decoder 31 can generate and transmit various voltages for selected word lines in the drive word line WL. For example, line decoder 31 can apply word line voltages generated by voltage generator 32 to (one or more) selected word lines in response to one or more control signals provided by control logic 35. In some embodiments, line decoder 31 can be connected to word line WL via transistors, and word line voltages can be applied to (one or more) selected word lines by turning on the corresponding transistors in the transistors.

[0022] Page buffer 33 can be connected to cell region 20 via bit line BL and can be used to read data stored in memory cells or write data to memory cells. Page buffer 33 may include column decoder, latching circuitry, etc. In this respect, the column decoder can select at least one of the bit lines BL, and the latching circuitry can read data from the memory cell connected to the bit line BL selected by the column decoder during a read operation.

[0023] I / O circuitry 34 can receive write data DATA provided externally during programming operations, which will be received by page buffer 33, and / or provide read data retrieved from cell area 20 by page buffer 33 during read operations. I / O circuitry 34 can also transmit addresses and / or commands received from external sources (e.g., memory controllers) to control logic 35.

[0024] Control logic 35 controls the overall operation (and interoperability) of the line decoder 31, voltage generator 32, page buffer 33, and I / O circuitry 34. In some embodiments, control logic 35 may operate in response to one or more control commands received from one or more external sources.

[0025] Voltage generator 32 can be used to generate control voltages (e.g., programming voltage, read voltage, erase voltage, pass voltage, etc.) required for the operation of memory device 10 with respect to an externally supplied power supply voltage. The voltage generated by voltage generator 32 can be provided to peripheral circuit area 30 and / or cell area 20 via line decoder 31, etc.

[0026] Three-dimensional (3D) memory devices, or vertically stacked memory devices, offer improved memory cell integration density. However, as the number of stacked levels in these 3D memory devices increases, the height of the metal contacts connecting to the word line board also increases. This increased height of the metal contacts can increase the resistance distribution associated with one or more manufacturing processes, thereby causing one or more resistance defects in the memory device.

[0027] Recognizing this specific failure probability and similar problems, methods have been proposed to detect and potentially correct defects in memory devices. These methods may involve programming data into memory cells and then determining whether the programmed data can be read correctly. However, the word lines formed by the gates are "open nodes" that include an inherent capacitor component (hereinafter referred to as "word line capacitors"), giving them a recovery characteristic where resistance decreases under high voltage. To program data into memory cells, a high voltage is typically applied, and in this case, if the memory device is tested using a programming / reading method, it may be detected as operating normally due to the recovery characteristic of the open nodes. However, in this scenario, the resistance may increase again after the data has been programmed into the memory cells and retained for an extended period. Subsequently, if a low voltage is applied to read the data programmed into the memory cells after a product including the memory device has been commercially released, the data may not be read correctly. Therefore, data reliability cannot be guaranteed.

[0028] Unfortunately, until the advent of this inventive concept, there was no available method for accurately measuring the line resistance of open nodes. Furthermore, when word lines are used for programming and reading data from memory cells, the line resistance of word lines is also difficult to measure accurately due to variations in the threshold voltages of one or more memory cells. However, embodiments of the inventive concept completely overcome this existing limitation and provide a method for accurately measuring (or determining) the line resistance of (open node) word lines, thereby enabling the identification of potential defects in memory devices.

[0029] Therefore, in Figure 1 In the memory device 10, the line resistance of the word lines can be accurately measured by adding a circuit system (e.g., a control logic circuit system) for measuring the line resistance of the word lines. In some embodiments, the circuit system for measuring the line resistance of the word lines may include a sensing capacitor and a switch for controlling the sensing capacitor, wherein the size of the sensing capacitor may be proportional to (or matched to) the size of the word line capacitor.

[0030] To measure the line resistance of a word line, a low voltage can initially be applied to the word line to provide charge in the word line capacitor. Subsequently, a charge-sharing operation can be performed, allowing the sensing capacitor to "share" the charge accumulated by the word line capacitor. After a specific period of time, the line resistance of the word line can then be accurately measured by determining the voltage across the sensing capacitor. Using this method, resistive defects in memory devices can be effectively detected.

[0031] Additionally, the leakage current associated with the word line capacitor can be measured by repeatedly measuring the voltage of the sensing capacitor. Therefore, the line resistance and leakage current of the word line can be measured accurately and simultaneously (e.g., at least partially overlapping in time).

[0032] Figure 2 It is a partial equivalent circuit diagram, and Figure 3 It is a cross-sectional view. Figure 2 and Figure 3 Together, a memory device according to an embodiment of the present invention is further illustrated.

[0033] Reference Figure 2 An exemplary memory block BLK may include a memory cell string CS, wherein at least some of the memory cell string CS share word lines WL1 to WLn and / or bit lines BL1 to BL3.

[0034] Each of the memory cell strings CS may include a memory cell MC connected between a first string select transistor SST1 and a second string select transistor SST2 and a ground select transistor GST. The first string select transistor SST1 and the second string select transistor SST2 are connected in series with each other, and the uppermost second string select transistor SST2 may be connected to one of bit lines BL1 to BL3. The ground select transistor GST may be connected to a common source line CSL. The memory cells MC included in each of the memory cell strings CS may share a channel region.

[0035] The memory cell MC can be connected in series between the first string selection transistor SST1, the second string selection transistor SST2, and the ground selection transistor GST. In some embodiments, the number of string selection transistors SST1 and SST2 and the ground selection transistor GST can vary, and each of the memory cell strings CS may also include at least one dummy memory cell. For example, the dummy memory cell may be connected between the first string selection transistor SST1 and the memory cell MC and / or connected between the ground selection transistor GST and the memory cell MC.

[0036] The gate electrode of the memory cell MC can be connected to word lines WL1 to WLn. Additionally, the gate electrode of the ground select transistor GST is connected to the ground select line GSL, and the gate electrodes of the first string select transistor SST1 and the second string select transistor SST2 can be connected to string select lines SSL11 to SSL23.

[0037] The ground select line GSL, word lines WL1 to WLn, and serial select lines SSL11 to SSL23 can be stacked vertically. The ground select line GSL, word lines WL1 to WLn, and serial select lines SSL11 to SSL23 can be penetrated by a channel structure including a channel region. The channel structure can be connected to one of the bit lines BL1 to BL3.

[0038] Reference Figure 3 According to an embodiment of the present invention, the memory device 100 may include a peripheral circuit region PA and a cell region CA. The memory device 100 may have a "peripheral-on-cell" or "peripheral-on-cell" (COP) structure. A COP structure is a structure in which the peripheral circuit region PA is disposed below the cell region CA. That is, at least a portion of the peripheral circuit region PA and at least a portion of the cell region CA may overlap in the vertical direction (e.g., the stacking direction or the Z-axis direction).

[0039] The peripheral circuit area PA may include a lower substrate 110, circuit elements 120 disposed on the lower substrate 110, circuit wiring 130 electrically connected to the circuit elements 120, and a lower insulating layer 140 covering the circuit elements 120 and the circuit wiring 130. Peripheral circuits required to drive the memory device 100 (e.g., line decoders, page buffers, etc.) may be disposed in the peripheral circuit area PA.

[0040] The lower substrate 110 may include a semiconductor substrate such as a silicon wafer. The circuit element 120 may refer to an integrated circuit including transistors, etc. The circuit wiring 130 may include a metal layer and metal contacts. The metal contacts can connect the circuit element 120 to the metal layer and can also connect the metal layer. The lower insulating layer 140 may include an insulating material such as silicon oxide or silicon nitride.

[0041] The cell region CA can provide at least one memory block. The cell region CA may include an upper substrate 210, a memory cell array MCA disposed on the upper substrate 210, and an upper insulating layer 200 covering the memory cell array MCA. At least a portion of the upper substrate 210 may be a common source line.

[0042] Word lines 231 to 238 (or collectively referred to as 230) may be stacked in a vertical direction substantially perpendicular to the upper surface of the upper substrate 210. Serial select lines 241 and 242 (or collectively referred to as 240) may be disposed above word line 230, ground select line 220 may be disposed below word line 230, and word line 230 may be disposed between serial select line 240 and ground select line 220. Ground select line 220, word line 230, and serial select line 240 may refer to the gate electrode layer.

[0043] The channel structure CH can extend vertically and penetrate word line 230, serial select line 240, and ground select line 220. The channel structure CH may include a data storage layer, a channel layer, and an embedded insulating layer, and the channel layer can be electrically connected to the bit line BL via bit line contacts. The bit line BL can extend in a first horizontal direction (e.g., the Y-axis direction) substantially parallel to the upper surface of the upper substrate.

[0044] Gate electrode layers 220, 230, and 240 may extend at different lengths in a second horizontal direction (e.g., the X-axis direction) that is also substantially parallel to the upper surface of the upper substrate 210 and intersects the first horizontal direction. Gate contact plugs 250, 255, 260, and 270 may be connected to each other in pads provided with the gate electrode layers 220, 230, and 240 extending at different lengths. For example, cell contact plugs 261 to 268 (or collectively referred to as 260) may be connected to each other in pads provided with the word line 230 extending at different lengths. Cell contact plug 260 may be electrically connected to circuit elements 120 that provide a line decoder in the peripheral circuit area PA.

[0045] Peripheral contact plug 280 can be electrically connected to at least one of the circuit elements 120 disposed in the peripheral circuit region PA. Peripheral contact plug 280, as well as gate contact plugs 250, 255, 260, and 270, can be connected to gate connection wiring 290 via metal contacts. For example, word line 230 can be connected to a line decoder included in the peripheral circuit region PA via cell contact plug 260, gate connection wiring 290, and peripheral contact plug 280. The line decoder can provide voltage to word line 230 for driving the word line.

[0046] As described above, as the number of stacked levels of the memory device increases, the height of the cell contact plugs 260 connected to the word line 230 may also increase. This can result in the formation of one or more resistive defects in the memory device 100. Therefore, it is necessary to accurately measure the line resistance of the word line 230.

[0047] In this detailed description, the phrase "line resistance of a word line" refers to the resistance associated with the path between a word line and the peripheral circuitry area. Specifically, the line resistance of a word line can refer to the resistance present in the path between the word line and the line decoder. For example, the line resistance of the first word line 231 can refer to the resistance present in the first unit contact plug 261, the gate connection wiring 290, and the peripheral contact plug 280, which form the path between the first word line 231 and the peripheral circuitry area PA. However, since the number of peripheral contact plugs 280 is very small compared to the number of unit contact plugs 260, several peripheral contact plugs 280 can be redundantly arranged and connected in parallel to reduce the impact on resistance caused by the peripheral contact plugs 280. Therefore, the resistance of the unit contact plug 260 has the greatest impact on the line resistance of the word line 230.

[0048] exist Figure 3 In the memory device 100, the line resistance of the word line 230 can be accurately measured by adding a sensing capacitor and a switch for controlling the sensing capacitor. Furthermore, the line resistance of the word line 230 and the leakage current of the word line 230 can be measured simultaneously by repeatedly measuring the voltage of the sensing capacitor.

[0049] Figure 4 This is a waveform diagram illustrating the cell distribution of a memory device according to an embodiment of the present invention. Figure 4 In the waveform diagram, the horizontal axis represents the threshold voltage Vth of the memory cell.

[0050] Here, it is assumed that the memory device includes a multilevel memory cell (MLC) capable of programming two or more bits in a single memory cell. Therefore, Figure 4The cell layout of a 2-bit MLC is shown, where the 2-bit MLC can be programmed into one of four possible states (“E”, “P1”, “P2”, and “P3”). The two bits programmed in a memory cell can include a high-order bit and a low-order bit. Pages for the high-order bits and pages for the low-order bits are programmed into memory cells connected to the same word line in the memory cell array. Before programming, all memory cells are in state “E”. When programming the first page of memory cells is performed, memory cells with a logical value of 0 for the corresponding bit are programmed to have state “P”, while memory cells with a logical value of 1 for the corresponding bit are maintained in state “E”. Subsequently, when programming the second page, the memory cell has one of states “E”, “P1”, “P2”, and “P3”. Here, memory cells with a logical value of 1 for the bit in the first page and a logical value of 1 for the bit in the second page are maintained in state “E”, and memory cells with a logical value of 1 for the bit in the first page and a logical value of 0 for the bit in the second page are programmed to have state “P1”. Furthermore, memory cells with a logical value of 0 in both the first and second pages are programmed from state "P" to state "P2", and memory cells with a logical value of 0 in both the first and second pages are programmed from state "P" to state "P3". In this way, memory cells whose first and second pages have been programmed have the following properties: Figure 4 The cell layout is shown. Read voltages VR1, VR21, and VR22 can be used to read their logic values. When read voltage VR1 is applied, memory cells in states "E" and "P1" are turned on, and memory cells in states "P2" and "P3" are turned off. By detecting this, it can be determined whether the bit value of the first page of the corresponding memory cell is 0 or 1. That is, when read voltage VR1 is applied, if the memory cell is turned on, the high-order bit of the data stored in the memory cell is 1, and if the memory cell is turned off, the high-order bit of the data stored in the memory cell is 0. Read voltages VR21 and VR22 can be used to determine the logic value of the second page. If the on / off state of the memory cell when read voltage VR21 is applied is the same as the on / off state of the memory cell when read voltage VR22 is applied, the low-order bit of the data stored in the memory cell is 1. If the on / off states are different, the low-order bit of the data stored in the memory cell is 0.

[0051] Because word lines, as open nodes, have recovery characteristics, their line resistance decreases when a high voltage is applied to them to program data in a memory cell, allowing for proper data programming within the memory device. However, over time, the line resistance increases again, and the read voltage may change when a low voltage is applied to them to read the data programmed into the memory cell.

[0052] For example, the first read voltage VR22 can be reduced to the second read voltage VR22' due to the line resistance of the word lines. Here, the portion of state P2 that exceeds the second read voltage VR22' can cause errors during the read process. In this case, data reliability cannot be guaranteed.

[0053] In some embodiments, a low voltage can be used to charge the word line capacitor, a charge-sharing operation can be performed to share charge between the word line capacitor and the sensing capacitor, and the voltage of the sensing capacitor can be measured to accurately measure the line resistance of the word line. In this way, resistive defects in the memory device can be detected. Furthermore, the line resistance of the word line and the leakage current associated with the word line can be measured simultaneously by repeatedly measuring the sensing voltage of the sensing capacitor.

[0054] Figure 5 This is a block diagram illustrating a memory device according to an embodiment of the concept of the present invention, and Figure 6 yes Figure 5 The equivalent circuit diagram of the memory device.

[0055] Reference Figure 5 The memory device 300 may include a memory cell array 310, a row decoder 320, a voltage generator 330, control logic 340, a page buffer 370, and I / O circuitry 380. The memory cell array 310 can be connected to the row decoder 320 via a common source line CSL, a serial select line SSL, a word line WL, and a ground select line GSL.

[0056] The memory cell array 310 may include memory cells arranged in regions where word lines and bit lines intersect. Here, the memory cell array 310 may have [specific features related to]... Figure 2 The described unit regions have essentially the same structure.

[0057] The line decoder 320 can receive an address from the control logic 340 and generate various voltages for driving the word line WL. In response to the control of the control logic 340, the line decoder 320 can input the word line voltage generated by the voltage generator 330 to the word line WL.

[0058] Control logic 340 may include a normalization unit 350 and a test unit 360. Here, the normalization unit 350 may be configured with respect to... Figure 1 The control logic described operates in essentially the same way and has similarities to that described above. Figure 1The control logic described is essentially the same structure. That is, the normal unit 350 can be used to control the execution of various data access operations (e.g., read operations, programming operations, and / or erase operations) using the line decoder 320, voltage generator 330, page buffer 370, and / or I / O circuitry 380 in response to externally provided control signals (one or more), addresses (one or more), and / or commands (one or more), in response to externally provided control signals, addresses (one or more), and / or commands (one or more)

[0059] Test unit 360 can be used to measure the line resistance of word line WL using a sensing capacitor. For example, line decoder 320 can select a first word line WL1 from word lines WL to have its line resistance measured in response to an address received from control logic 340. At this point, the first word line WL1 can be understood as the "selected word line". Test unit 360 can then precharge the first word line WL1 by providing a low voltage to it. That is, charge can be provided to the word line capacitor of the first word line WL1. Test unit 360 can then perform a charge-sharing operation to share the provided charge between the precharged first word line WL1 and the sensing capacitor. Test unit 360 can then measure the voltage of the sensing capacitor after the charge-sharing operation is complete. In this way, test unit 360 can use the voltage of the sensing capacitor to accurately measure the line resistance of the word line.

[0060] By considering Figure 6 The equivalent circuit can further clarify the path between test unit 360 and the first word line WL1. As mentioned above, since the resistance of the cell contact plug CP has the greatest impact on the line resistance of the word line, the path between test unit 460 and the word line can be represented by the cell contact plug CP, the word line capacitor WC, and the parasitic capacitor PC. Therefore, the term "word line capacitor" refers to the capacitive component ("capacitor") existing between the selected word line and (one or more) adjacent word lines (or (one or more) word lines close to the selected word line), while the term "parasitic capacitor" refers to the capacitive component ("capacitor") existing between the wiring connecting the selected word line and the adjacent wiring (or the wiring close to the wiring connecting the selected word line).

[0061] In some embodiments, the test unit 460 may include a voltage driver 461, a first switch 462, a second switch 463, a third switch 464, and a fourth switch 465 (hereinafter collectively referred to as "first switch 462 to fourth switch 465"), a sensing capacitor 466, and a comparator 467. The sensing capacitor 466 may refer to a transistor capacitor, a metal-insulator-metal (MIM) capacitor, etc. The size of the sensing capacitor 466 may be proportional to the size of the word line capacitor WC.

[0062] The output of voltage driver 461 can be connected to the first terminal of first switch 462, and the first node ND1 connected to the word line can be connected to the first terminal of second switch 463. The second terminals of first switch 462 and second switch 463 can be connected together. The first terminal of third switch 464 can be connected between first switch 462 and second switch 463. The second terminal of third switch 464 can be connected to sensing node ND2. Fourth switch 465 and sensing capacitor 466 can be connected in parallel and can be connected together to sensing node ND2.

[0063] The first switch 462 connects the word line to the voltage driver 461, and the third switch 464 connects the word line to the sensing capacitor 466. The fourth switch 465 initializes the sensing capacitor 466.

[0064] The first input of comparator 467 can be connected to the sensing node ND2 to receive the voltage from the sensing capacitor 466, and the second input of comparator 467 can receive the reference voltage V. REF Comparator 467 compares the voltage of sensing capacitor 466 with the reference voltage V. REF The comparison is performed, and a comparison signal corresponding to the comparison result is output.

[0065] Figures 7 to 10 These are a set of related block diagrams and voltage waveform diagrams illustrating exemplary operation of a memory device according to an embodiment of the present invention.

[0066] Here, an exemplary method for measuring the line resistance of word lines in a memory device will be described. In this regard, refer to... Figure 7 and Figure 9 During the pre-charging period D1, the first switch 462, the second switch 463, and the fourth switch 465 are turned on, and the third switch 464 is turned off. With the fourth switch 465 turned on, the sensing node ND2 can be initialized. With the first switch 462 and the second switch 463 turned on, a charging voltage can be supplied from the voltage driver 461 to the word line. For example, the charging voltage can be a low voltage in the range of 3V to 5V, but is not limited to this. Charge can be provided to the word line capacitor WC and the parasitic capacitor PC by the low voltage supplied from the voltage driver 461.

[0067] The voltage driver 461 can supply charge to the word line capacitor WC via the first path PATH1 and to the parasitic capacitor PC via the second path PATH2. The cell contact plug CP, which has the greatest impact on the line resistance of the word line, can be located on the first path PATH1. As mentioned above, if a high voltage is applied to the word line, a recovery characteristic of decreasing resistance of the cell contact plug CP may occur; therefore, to eliminate this recovery characteristic, a low voltage can be supplied to the word line.

[0068] As charge is supplied to the word line capacitor WC and the parasitic capacitor PC, the voltage at the first node ND1 will increase, as... Figure 9 The curve is shown as line 'a' in the graph.

[0069] Refer to together Figure 8 and Figure 9 During the sensing period D2, the first switch 462 and the fourth switch 465 can be turned off, and the second switch 463 and the third switch 464 can be turned on. With the second switch 463 and the third switch 464 turned on, a charge-sharing operation can be performed to share the previously provided charge among the word line capacitor WC, the parasitic capacitor PC, and the sensing capacitor 466.

[0070] The charge provided associated with word line capacitor WC can be shared by sensing capacitor 466 via the first path PATH1, and the charge provided associated with parasitic capacitor PC can be shared by sensing capacitor via the second path PATH2.

[0071] The voltage at the first node ND1 can drop sharply (almost instantaneously) and then gradually increase according to the voltage at the sensing node ND2. Therefore, the voltage at the sensing node ND2 can be as follows: Figure 9 The curves shown in the graph indicate an increase as indicated by line 'b' or 'c'. The cell contact plug CP, which has the greatest impact on the line resistance of the word line, can be associated with the first path PATH1. Furthermore, the size of the parasitic capacitor PC can be very small compared to the size of the word line capacitor WC. Therefore, the time constant of the voltage at sensing node ND2 can be determined by the resistance of the word line capacitor WC and the cell contact plug CP. Moreover, when the resistance of the cell contact plug CP is small, the voltage at sensing node ND2 increases relatively sharply as shown by curve 'b', and when the resistance of the cell contact plug CP is large, the voltage at sensing node ND2 increases relatively slowly as shown by curve 'c'.

[0072] After the charge-sharing operation is completed (after a predetermined time period), the third switch 464 can be turned off. The timing of turning the third switch 464 on / off can be determined by the word line capacitor and the normal line resistance value of the word line. After the third switch 464 is turned off, the comparator 467 can receive the voltage at the sensing node ND2 and the reference voltage V. REF Comparator 467 can compare the voltage of sensing node ND2 with the reference voltage V at a first time point t1 (or during a first time period). REF If, as a comparison result, the voltage at sensing node ND2 is greater than the reference voltage V... REF (Line 'b') indicates that the line resistance of the word line is small. Conversely, if the voltage at sensing node ND2 is less than the reference voltage V as a result of the comparison... REF(Curve 'c') indicates that the line resistance of the character line is high.

[0073] Figure 7 The memory device 400 can accurately measure the line resistance of the word line by measuring the voltage of the sensing capacitor 466. Therefore, when it is determined that the line resistance of the word line is large (line 'c'), it can be determined that a resistive defect has occurred in the word line.

[0074] Reference Figure 8 and Figure 10 When the line resistance of the word line is determined to be small, defects in the memory device can be further evaluated by measuring the leakage current associated with the word line. After the word line is pre-charged, leakage current may occur in the word line capacitor WC over time. Therefore, when the third switch 464 is turned on again, the voltage at the sensing node ND2 may decrease due to the leakage current. If the amount of leakage current occurring in the word line capacitor WC is large, the voltage at the sensing node ND2 may decrease as follows: Figure 10 The curve 'e' shows a relatively sharp decrease, and when the amount of leakage current occurring in the word line capacitor WC is small, the voltage at the sensing node ND2 can be as follows: Figure 10 The line 'd' in the curve graph shows a relatively gradual decrease.

[0075] Comparator 467 can receive the voltage at sensing node ND2 and the reference voltage V. REF After the third switch 464 is turned on again, the comparator 467 can compare the voltage of the sensing node ND2 with the reference voltage V at the second time point t2 (or during the second time period). REF A comparison is made. If the voltage at sensing node ND2 is greater than the reference voltage V as a result of the comparison... REF (Curve 'd') indicates that the amount of leakage current occurring in the word line capacitor WC is small. Conversely, if, as a comparison, the voltage at sensing node ND2 is less than the reference voltage V... REF (Curve 'e') indicates that the leakage current occurring in the word line capacitor WC is large.

[0076] Therefore, when curves 'b' and 'd', which show a relatively sharp increase and gradual decrease in the voltage of sensing node ND2, are met, it can be determined that the memory device is defect-free and operating normally.

[0077] When measuring the line resistance of the word line, the voltage of the sensing capacitor is sensitive to the time constant determined by the line resistance of the word line and the word line capacitor. This is because the line resistance of the word line is large. Therefore, when measuring the line resistance of the word line, the voltage of the sensing capacitor can be measured after the third switch 464 is turned off. However, when measuring the leakage current of the word line, it has been determined that the line resistance of the word line is small, therefore, the voltage of the sensing capacitor is not sensitive to the time constant.

[0078] Figure 11 This is a block diagram illustrating a memory device according to an embodiment of the present invention, and through comparison with... Figure 5 Presented through comparison.

[0079] Test unit ( Figure 5 Some components in 360 can be included in the line decoder ( Figure 5 In (320) of the middle. (Refer to) Figure 11 The line decoder 520 may include a voltage driver 561, a first switch 562, and a second switch 563. The output of the voltage driver 561 may be connected to a first terminal of the first switch 562, and a first terminal of the first word line WL1 may be connected to a first terminal of the second switch 563. The second terminals of the first switch 562 and the second terminal of the second switch 563 may be connected together. The line decoder 520 may supply a low voltage from the voltage driver 561 to the first word line WL1 by turning on the first switch 562 and the second switch 563. Charge may be supplied to the word line capacitor and parasitic capacitor by the low voltage provided by the voltage driver 561.

[0080] The test unit 560 included in the control logic may include a third switch 564, a fourth switch 565, a sensing capacitor 566, and a comparator 567. The first terminal of the third switch 564 can be connected to the line decoder 520, and the second terminal of the third switch 564 can be connected to the sensing node ND2. The fourth switch 565 and the sensing capacitor 566 can be connected in parallel and can be jointly connected to the sensing node ND2. The test unit 560 can initialize the sensing node ND2 by turning on the fourth switch 565.

[0081] The line decoder 520 can turn off the first switch 562 and turn on the second switch 563. The test unit 560 can turn off the fourth switch 565 and turn on the third switch 564. Therefore, the memory device 500 can perform charge sharing operation among the word line capacitor, parasitic capacitor, and sensing capacitor 566.

[0082] As described above, the time constant of the voltage at sensing node ND2 can be determined by the resistance of the word line capacitor and the cell contact plug CP. When the resistance of the cell contact plug CP is small, the voltage at sensing node ND2 increases relatively sharply, and when the resistance of the cell contact plug CP is large, the voltage at sensing node ND2 can increase relatively gradually.

[0083] After the charge-sharing operation is completed (after a predetermined time period), the third switch 564 can be turned off. After the third switch 564 is turned off, the comparator 567 can receive the voltage of the sensing node ND2 and the reference voltage V. REFComparator 567 can compare the voltage of sensing node ND2 with the reference voltage V at a certain point during the first time period. REF If, as a comparison result, the voltage at sensing node ND2 is greater than the reference voltage V... REF Then it can be determined that the line resistance of the word line is small. Conversely, if the voltage at sensing node ND2 is less than the reference voltage V as a result of the comparison... REF Then it can be determined that the line resistance of the word line is large.

[0084] In other words, the memory device 500 can accurately measure the line resistance of the word lines by measuring the voltage of the sensing capacitor 566. Therefore, the reliability of the data can be ensured by initially detecting (or screening) resistive defects in the memory device 500.

[0085] After the word line is pre-charged, leakage current may occur in the word line capacitor over time. Therefore, when the third switch 564 is turned on again, the voltage of sensing node ND2 may decrease. When the amount of leakage current occurring in the word line capacitor is large, the voltage of sensing node ND2 may decrease relatively sharply, and when the amount of leakage current occurring in the word line capacitor is small, the voltage of sensing node ND2 may decrease relatively gradually.

[0086] Comparator 567 can receive the voltage at sensing node ND2 and the reference voltage V. REF Comparator 567 can compare the voltage of sensing node ND2 with the reference voltage V at a certain point during a second time period following the first time period. REF If, as a comparison result, the voltage at sensing node ND2 is greater than the reference voltage V... REF This indicates that the amount of leakage current occurring in the word line capacitor is small. Conversely, if, as a comparison, the voltage at sensing node ND2 is less than the reference voltage V... REF If this is the case, it can be determined that the leakage current occurring in the word line capacitor is large.

[0087] In other words, the memory device 500 can measure the line resistance of word lines and the leakage current of word line capacitors to test for word line defects. These test operations can be performed at the wafer level and / or the chip level. For example, to ensure stable use of the solution product, these test operations can be used as defensive code to treat the corresponding memory block as a bad block when a word line defect is detected.

[0088] Therefore, the reliability of the data can be guaranteed, and the quality competitiveness can be ensured.

[0089] Figure 12 This is a cross-sectional view showing a memory device 1000 according to an embodiment of the present invention.

[0090] Reference Figure 12The memory device 1000 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure in which an upper chip including cell regions (CELLs) is fabricated on a first wafer, and a lower chip including peripheral circuit regions (PERIs) is fabricated on a second wafer different from the first wafer, and the upper and lower chips are connected to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0091] Each of the peripheral circuit area PERI and cell area CELL of the memory device 1000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0092] The Peripheral Circuit Area (PERI) may include a first substrate 1210, an interlayer insulating layer 1215, circuit elements 1220a, 1220b, and 1220c formed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c respectively connected to the circuit elements 1220a, 1220b, and 1220c, and second metal layers 1240a, 1240b, and 1240c formed on the first metal layers 1230a, 1230b, and 1230c. In an embodiment, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten, which has a relatively high resistivity, and the second metal layers 1240a, 1240b, and 1240c may be formed of copper, which has a relatively low resistivity.

[0093] In this disclosure, only the first metal layers 1230a, 1230b, and 1230c and the second metal layers 1240a, 1240b, and 1240c are shown and described, but the disclosure is not limited thereto, and at least one metal layer may be further formed on the second metal layers 1240a, 1240b, and 1240c. At least some of the one or more metal layers formed on the second metal layers 1240a, 1240b, and 1240c are formed of aluminum, which has a lower resistivity than copper, which forms the second metal layers 1240a, 1240b, and 1240c.

[0094] Interlayer insulating layer 1215 may be disposed on first substrate 1210 and includes insulating material such as silicon oxide or silicon nitride to cover circuit elements 1220a, 1220b and 1220c, first metal layers 1230a, 1230b and 1230c and second metal layers 1240a, 1240b and 1240c.

[0095] The lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit area PERI can be electrically connected to the upper bonding metals 1371b and 1372b of the cell area CELL by a bonding method, and the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b can be formed of aluminum, copper or tungsten.

[0096] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 1310 and a common source line 1320. On the second substrate 1310, word lines 1331 to 1338 (or collectively referred to as 1330) may be stacked vertically. A serial select line and a ground select line may be positioned above and below the word line 1330, respectively, and the word line 1330 may be positioned between the serial select line and the ground select line.

[0097] In the bit line bonding area BLBA, the channel structure CH can extend vertically to penetrate the word line 1330, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, and an embedded insulating layer, and the channel layer may be electrically connected to a first metal layer 1350c and a second metal layer 1360c. For example, the first metal layer 1350c may be a bit line contact, and the second metal layer 1360c may be a bit line. In some embodiments, the bit line 1360c may extend in a first horizontal direction.

[0098] like Figure 12 As shown, the area in which the channel structure CH and bit line 1360c are disposed can be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, bit line 1360c can be electrically connected to circuit element 1220c, which provides page buffer 1393 in the peripheral circuit area PERI. For example, bit line 1360c can be connected to upper bonding metals 1371c and 1372c in the cell area CELL, and upper bonding metals 1371c and 1372c can be connected to lower bonding metals 1271c and 1272c, which are connected to the circuit element 1220c of the page buffer 1393.

[0099] In the word line bonding area (WLBA), word lines 1330 may extend in a second horizontal direction (e.g., the X-axis direction) perpendicular to the first horizontal direction and parallel to the upper surface of the second substrate 1310, and may be connected to cell contact plugs 1341 to 1347 (or collectively referred to as 1340). Word lines 1330 and cell contact plugs 1340 may be connected to each other in pads provided with at least some of the word lines 1330 extending at different lengths in the second horizontal direction (e.g., the X-axis direction). A first metal layer 1350b and a second metal layer 1360b may be sequentially connected to the upper portion of the cell contact plugs 1340 connected to the word lines 1330. Cell contact plugs 1340 may be connected in the word line bonding area (WLBA) to the peripheral circuit area (PERI) via upper bonding metals 1371b and 1372b in the cell area (CELL) and lower bonding metals 1271b and 1272b in the peripheral circuit area (PERI).

[0100] The unit contact plug 1340 can be electrically connected to circuit element 1220b forming the line decoder 1394 in the peripheral circuitry area (PERI). In an embodiment, the operating voltage of circuit element 1220b forming the line decoder 1394 can be different from the operating voltage of circuit element 1220c forming the page buffer 1393. For example, the operating voltage of circuit element 1220c forming the page buffer 1393 can be greater than the operating voltage of circuit element 1220b forming the line decoder 1394.

[0101] A common source line contact plug 1380 can be disposed in the external pad bonding area PA. The common source line contact plug 1380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 1320. A first metal layer 1350a and a second metal layer 1360a can be sequentially stacked on the common source line contact plug 1380. For example, the area in which the common source line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed can be defined as the external pad bonding area PA.

[0102] Simultaneously, input / output (I / O) pads 1205 and 1305 can be located in the external pad bonding area PA. (See reference...) Figure 12A lower insulating layer 1201 covering the lower surface of the first substrate 1210 may be formed below the first substrate 1210, and a first I / O pad 1205 may be formed on the lower insulating layer 1201. The first I / O pad 1205 can be connected to at least one of the circuit elements 1220a, 1220b, and 1220c disposed in the peripheral circuit area PERI via a first I / O contact plug 1203, and can be separated from the first substrate 1210 via the lower insulating layer 1201. Furthermore, a side insulating layer may be disposed between the first I / O contact plug 1203 and the first substrate 1210 to electrically isolate the first I / O contact plug 1203 from the first substrate 1210.

[0103] Reference Figure 12 An upper insulating layer 1301 covering the lower surface of the second substrate 1310 can be formed on the second substrate 1310, and a second I / O pad 1305 can be disposed on the upper insulating layer 1301. The second I / O pad 1305 can be connected to at least one of the circuit elements 1220a, 1220b, and 1220c disposed in the peripheral circuit area PERI via a second I / O contact plug 1303. In an embodiment, the second I / O pad 1305 can be electrically connected to the circuit element 1220a.

[0104] In some embodiments, the second substrate 1310 and the common source line 1320 may not be located in the region where the second I / O contact plug 1303 is provided. Furthermore, the second I / O pad 1305 may not overlap with the word line 1330 in the vertical direction. (Refer to...) Figure 12 The second I / O contact plug 1303 can be horizontally separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310, and can be connected to the second I / O pad 1305 through the interlayer insulating layer 1315 of the cell region.

[0105] In some embodiments, a first I / O pad 1205 and a second I / O pad 1305 may be selectively formed. As an example, the memory device 1000 may include only the first I / O pad 1205 disposed on the lower insulating layer 1201 or only the second I / O pad 1305 disposed on the upper insulating layer 1301. Alternatively, the memory device 1000 may include both the first I / O pad 1205 and the second I / O pad 1305.

[0106] In each of the external pad bonding area PA and bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer can be a pseudo-pattern, or the uppermost metal layer can be empty.

[0107] exist Figure 12In the memory device 1000, in the external pad bonding area PA, a lower metal pattern 1273a having the same shape as the upper metal pattern 1372a of the cell area CELL can be formed on the uppermost metal layer of the peripheral circuit area PERI to correspond to the upper metal pattern 1372a formed on the uppermost metal layer of the cell area CELL. The lower metal pattern 1273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. Similarly, in order to correspond to the lower metal pattern 1273a formed on the uppermost metal layer of the peripheral circuit area PERI in the external pad bonding area PA, an upper metal pattern 1372a having the same shape as the lower metal pattern 1273a of the peripheral circuit area PERI can be formed on the uppermost metal layer of the cell area CELL.

[0108] Lower bonding metals 1271b and 1272b can be formed on the second metal layer 1240b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit area PERI can be electrically connected to the upper bonding metals 1371b and 1372b of the cell area CELL by bonding method.

[0109] Furthermore, in the bit line bonding area BLBA, in order to correspond to the lower metal pattern 1252 formed on the uppermost metal layer of the peripheral circuit area PERI, an upper metal pattern 1392 with the same shape as the lower metal pattern 1252 of the peripheral circuit area PERI can be formed on the uppermost metal layer of the cell area CELL. Contacts may not be formed on the upper metal pattern 1392 formed on the uppermost metal layer of the cell area CELL.

[0110] According to embodiments of the present invention, resistive defects can be initially detected by accurately measuring the line resistance of open nodes with capacitor components in a memory device. Therefore, data reliability can be guaranteed, and quality competitiveness can be ensured.

[0111] Although certain embodiments of the inventive concept have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, comprising: A memory cell array comprising memory cells respectively arranged in regions where word lines and bit lines intersect; A line decoder, configured to select a word line from the word lines as the selected word line in response to a received address; as well as The control logic includes a sensing capacitor whose size is proportional to the size of the word line capacitor associated with the selected word line. The control logic is configured to measure the line resistance of the selected word line by pre-charging the selected word line, performing a charge-sharing operation between the selected word line and the sensing capacitor after pre-charging the selected word line, and measuring the voltage of the sensing capacitor after performing the charge-sharing operation.

2. The memory device according to claim 1, wherein, The line resistance of the selected word line is the resistance in the path between the selected word line and the line decoder.

3. The memory device according to claim 1, wherein, The control logic further includes: initializing a first switch for the sensing capacitor, and connecting the selected word line to the sensing capacitor via a second switch.

4. The memory device according to claim 3, wherein, The control logic further includes a comparator configured to receive a sensed voltage from the sense capacitor, receive a reference voltage, compare the sensed voltage with the reference voltage, and provide a comparison result based on the comparison of the sensed voltage and the reference voltage. The control logic refers to the comparison result to measure the line resistance of the selected word line.

5. The memory device according to claim 3, wherein, The control logic also includes a voltage driver that provides a charging voltage, and a third switch that connects the selected word line to the voltage driver.

6. The memory device according to claim 5, wherein When the selected word line is connected to the voltage driver, the charging voltage is provided to the selected word line to provide charge to the word line capacitor, and When the selected word line is connected to the sensing capacitor, the sensing capacitor shares the charge supplied to the word line capacitor.

7. The memory device according to claim 6, wherein, The word line capacitor is a capacitor that exists between the selected word line and the adjacent word lines of the word line.

8. The memory device according to claim 3, wherein, The line decoder includes: a voltage driver that provides a charging voltage, and a third switch that connects the selected word line to the voltage driver.

9. The memory device according to claim 8, wherein When the selected word line is connected to the voltage driver, the charging voltage is provided to the selected word line to provide charge to the word line capacitor, and When the selected word line is connected to the sensing capacitor, the sensing capacitor shares the charge supplied to the word line capacitor.

10. The memory device according to claim 9, wherein, The word line capacitor is a capacitor located between the selected word lines and the word lines adjacent to the selected word line.

11. A memory device, comprising: A memory cell array comprising memory cells respectively arranged in regions where word lines and bit lines intersect; A line decoder, configured to select one word line from the word lines as the selected word line in response to a received address; as well as Control logic configured to measure the line resistance of the selected word line, wherein the control logic includes: Sensing capacitor; A voltage driver that provides the charging voltage; A first switch having a first terminal and a second terminal connected to the voltage driver; The second switch has a first end connected to the selected word line and a second end connected to the second end of the first switch; A third switch has a first end and a second end connected between the first switch and the second switch; A fourth switch, which is connected in parallel with the sensing capacitor and connected to the second terminal of the third switch; and The comparator includes a first input terminal that receives a sensed voltage from the sense capacitor and a second input terminal that receives a reference voltage.

12. The memory device according to claim 11, wherein, The control logic turns on the first switch and the second switch during the pre-charge period to provide the charging voltage from the voltage driver to the selected word line.

13. The memory device according to claim 12, wherein, The control logic turns on the fourth switch during the pre-charging period to initialize the sensing capacitor.

14. The memory device according to claim 13, wherein, The control logic turns off the first switch and the fourth switch and turns on the third switch during the sensing period following the pre-charging period to perform a charge-sharing operation between the selected word line and the sensing capacitor.

15. The memory device according to claim 14, wherein, Following the charge-sharing operation, the comparator compares the sensed voltage with the reference voltage to generate a comparison result, and The control logic refers to the comparison result to measure the line resistance of the selected word line.

16. A memory device, comprising: A memory cell array comprising memory cells respectively arranged in regions where word lines and bit lines intersect; A line decoder, configured to select a word line from the word lines as the selected word line in response to a received address; as well as The control logic includes a normalization unit and a test unit, the normalization unit being configured to perform at least one data access operation associated with a memory cell connected to the selected word line, and the test unit including a sensing capacitor. The test unit is configured to measure the line resistance of the selected word line and the leakage current associated with the selected word line by the following steps: A charge-sharing operation is performed between the selected word line and the sensing capacitor. During a first time period following the execution of the charge-sharing operation, the voltage of the sensing capacitor is measured to measure the line resistance of the selected word line. The voltage of the sensing capacitor is measured during a second time period following the first time period to measure the leakage current associated with the selected word line.

17. The memory device according to claim 16, wherein, The size of the sensing capacitor is proportional to the size of the word line capacitor associated with the selected word line.

18. The memory device according to claim 16, wherein, The test unit includes a switch, which is connected in parallel with the sensing capacitor and together with the sensing capacitor is connected to the sensing node.

19. The memory device according to claim 18, wherein, The test unit further includes a comparator, which comprises a first input terminal connected to the sensing node and receiving a sensed voltage from the sensing capacitor, and a second input terminal receiving a reference voltage. The comparator is configured to compare the sensed voltage with the reference voltage during the first time period to measure the line resistance of the selected word line, and is also configured to compare the sensed voltage with the reference voltage during the second time period to measure the leakage current associated with the selected word line.

20. The memory device according to claim 19, wherein, The control logic includes a voltage driver that applies a charging voltage to the selected word line to precharge the selected word line with charge, and thereafter... The charge-sharing operation shares the charge between the selected word line and the sensing capacitor.

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