Processing method of semiconductor memory structure

Abstract

The present application discloses a method for processing a semiconductor memory structure, comprising the following steps: providing the semiconductor memory structure, wherein the semiconductor memory structure comprises: a first isolation structure, wherein a plurality of discrete bit line structures are formed in the first isolation structure; a second isolation structure, located above the first isolation structure, wherein a plurality of discrete conductive structures are formed in the second isolation structure, and wherein one of the conductive structures is correspondingly arranged above each of the bit line structures; and cleaning the surface of the second isolation structure to remove conductive particles remaining on the surface of the second isolation structure during the formation of the semiconductor memory structure, wherein the cleaning comprises at least performing a heat treatment.

Description

Technical Field

[0001] The present application relates to the field of semiconductor memory structures, and in particular to a processing method for semiconductor memory structures. Background Art

[0002] During the production of semiconductor memory devices, it is often necessary to form an insulating layer between metal layers to form multiple individual metal plugs. In these cases, it is often necessary to roll back the insulating layer on the metal layer to expose the sidewalls of the metal plugs. In this case, a conductive trace composed of conductive particles can easily form on the upper surface of the insulating layer between the two metal plugs, resulting in a short circuit between the two metal plugs and causing electrical defects in the subsequently fabricated semiconductor memory structure. A new semiconductor memory fabrication method is urgently needed to reduce the probability of electrical defects. Summary of the Invention

[0003] In view of this, the present application provides a processing method for a semiconductor memory structure, which can reduce.

[0004] The present application provides a method for processing a semiconductor memory structure, comprising the following steps: providing the semiconductor memory structure, wherein the semiconductor memory structure comprises: a first isolation structure, wherein a plurality of discrete bit line structures are formed in the first isolation structure; a second isolation structure, located above the first isolation structure, wherein a plurality of discrete conductive structures are formed in the second isolation structure, and wherein one of the conductive structures is correspondingly arranged above each of the bit line structures; and cleaning the surface of the second isolation structure to remove conductive particles remaining on the surface of the second isolation structure during the formation of the semiconductor memory structure, wherein the cleaning comprises at least heat treatment.

[0005] Optionally, the cleaning of the surface of the second isolation structure further includes at least the following steps: performing at least one of wet cleaning and dry cleaning on the surface of the second isolation structure.

[0006] Optionally, the surface of the second isolation structure is firstly wet cleaned and then dry cleaned, or the surface of the second isolation structure is firstly dry cleaned and then wet cleaned.

[0007] Optionally, the heat treatment includes a first heat treatment and a second heat treatment, and the first heat treatment and the second heat treatment are respectively performed after wet cleaning and / or dry cleaning.

[0008] Optionally, the heat treatment includes: providing a gas environment with a preset temperature for the surface of the second isolation structure.

[0009] Optionally, the preset temperature is greater than or equal to 400° C., and / or the gas environment includes a nitrogen environment.

[0010] Optionally, the gas provided in the gas environment contains nitrogen-containing plasma.

[0011] Optionally, providing a gas environment with a preset temperature for the surface of the second isolation structure includes the following steps: introducing nitrogen into the chamber where the semiconductor memory structure is located, and the nitrogen flow rate is greater than or equal to 0.75 SLM.

[0012] Optionally, the wet cleaning includes using a hydrofluoric acid solution to clean the surface of the second isolation structure, and the ratio of hydrofluoric acid to water in the hydrofluoric acid solution is greater than or equal to 1:600, and / or, the dry cleaning includes: using a gas containing oxygen free radicals or oxygen ions to ash the surface of the second isolation structure, and the gas includes at least one of hydrogen or nitrogen.

[0013] Optionally, the total duration of the heat treatment is greater than or equal to 1 hour.

[0014] In this embodiment, after forming a plurality of discrete conductive structures, the surface of the second isolation structure is cleaned to remove conductive particles remaining on the surface of the second isolation structure during the formation of the semiconductor memory structure. Furthermore, since the cleaning includes at least heat treatment, the cleaning effect is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 1 is a flowchart of the steps of a processing method for a semiconductor memory structure according to an embodiment of the present application.

[0017] Figure 2 Schematic diagram of the structure of the semiconductor memory structure in one embodiment of the present application when the second isolation structure is not prepared.

[0018] Figure 3 This is a structural diagram of the semiconductor memory structure described in one embodiment of the present application when a second isolation structure is prepared.

[0019] Figure 4 This is a schematic diagram of the structure of the semiconductor memory structure after cleaning in one embodiment of the present application.

[0020] Figure 5 It is an enlarged schematic diagram of a portion of the structure of the semiconductor memory structure described in one embodiment of the present application. DETAILED DESCRIPTION

[0021] The processing method of the semiconductor memory structure is further described below with reference to the accompanying drawings and embodiments.

[0022] See also Figure 1 , is a flowchart of the steps of a processing method for a semiconductor memory structure described in one embodiment of the present application.

[0023] In this embodiment, the processing method of the semiconductor memory structure includes the following steps: Step S101: providing the semiconductor memory structure, the semiconductor memory structure including: a first isolation structure (131, 161, 162, 163), wherein a plurality of discrete bit line structures are formed in the first isolation structure (131, 161, 162, 163); a second isolation structure 201, located above the first isolation structure (131, 161, 162, 163), wherein a plurality of discrete conductive structures 200 are formed in the second isolation structure 201, and a conductive structure 200 is correspondingly arranged above each of the bit line structures; Step S102: cleaning the surface of the second isolation structure 201 to remove conductive particles remaining on the surface of the second isolation structure 201 during the process of forming the semiconductor memory structure, wherein the cleaning at least includes: performing a heat treatment.

[0024] In this embodiment, since the surface of the second isolation structure 201 is at least heat-treated during cleaning, it helps to wash away the conductive particles on the surface of the second isolation structure 201, thereby preventing short circuit problems caused by the conductive particles on the surface of the second isolation structure 201.

[0025] like Figure 2 As shown, the semiconductor memory device structure includes a substrate 101, an active area 1021 formed within the substrate 101, a shallow trench isolation structure 102, and multiple discrete bitline structures formed on the surface of the substrate 101. Each of the discrete bitline structures is separated by the first isolation structures (131, 161, 162, 163). A conductive structure 200 is formed on the bitline structure and can be connected to the bitline to serve as a pad for connecting the semiconductor memory to external electrical signals. The conductive structure 200 includes at least a portion located above the substrate 101.

[0026] The substrate 101 may include a semiconductor material and may include a Group IV semiconductor and / or a III-V compound semiconductor. For example, the substrate 101 may be or may include a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate, and may include multiple layers, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In addition, the substrate 101 may include one or more semiconductor layers or structures and may include an active or operable portion of a semiconductor device.

[0027] The shallow trench isolation structure 102 may include, for example, oxide (eg, silicon oxide (SiO 2 )), nitride (eg, silicon nitride (Si 3 N 4 )), or oxynitride (eg, silicon oxynitride (SiON)).

[0028] exist Figure 2 In the illustrated embodiment, the bitline structure includes a first material layer 130. The bottom surface of the first material layer 130 contacts the active area 1021 and is located between two shallow trench isolation structures. The first material layer 130 is a conductive material, such as impurity-doped polysilicon or undoped polysilicon. In practice, the first material layer 130 can also be other semiconductor materials doped with N-type or P-type dopant ions, such as a doped amorphous silicon layer. The specific material of the first material layer 130 can also be determined as needed.

[0029] The bit line structure further includes a metal layer 151 formed on the upper surface of the first material layer 130. The metal layer 151 may be a single metal layer or a stacked structure of multiple metal layers, and may be at least one of a titanium nitride layer, a tungsten layer, and a copper layer.

[0030] The first isolation structure (131, 161, 162, 163) is arranged between adjacent two bit line structures, and the first isolation structure (131, 161, 162, 163) includes a polysilicon layer 131, and a multi-layer isolation structure arranged between the bit line structure and the polysilicon layer, which includes a first isolation layer 161, a second isolation layer 162 and a third isolation layer 163.

[0031] A bit line capping layer 202 is also formed above the metal layer 151. The bit line capping layer 202 is arranged on the upper surface of the metal layer 151 of each bit line structure and can be formed of an insulating material, such as a nitride (such as silicon nitride (Si3N4)) or a nitride oxide (such as silicon oxynitride (SiON)).

[0032] The conductive structure 200 is formed on the upper surface of the bit line cap layer 202, or is located above the polysilicon layer 131, and is used to form a landing pad. Figures 2 to 4In the illustrated embodiment, an ohmic layer 207 and a diffusion-stop layer 206 are further formed between the conductive structure 200 and the polysilicon layer 131. The ohmic layer 207 is disposed adjacent to the polysilicon layer 131 and can be made of a metal silicide, such as CoSi2, to form an ohmic contact between the conductive structure 200 and the underlying polysilicon layer 131. The diffusion-stop layer 206 prevents the conductive structure 200 from diffusing into the polysilicon layer 131. The diffusion-stop layer 206 can be made of titanium nitride or tantalum nitride.

[0033] In some embodiments, the semiconductor memory structure further includes a first insulating layer 103, a second insulating layer 104, a third insulating layer 105, and a first conductive layer 106 disposed below the metal layer 151. The first insulating layer 103, the second insulating layer 104, the third insulating layer 105, and the first conductive layer 106 are sequentially distributed vertically upward from the surface of the substrate 101.

[0034] In one embodiment, the first conductive layer 106 is an amorphous silicon layer formed on the surface of the third insulating layer 105. In fact, the first conductive layer 106 can also be made of a semiconductor material doped with N-type or P-type dopant ions, such as doped polysilicon, doped amorphous silicon, etc.

[0035] See also Figure 3 , shows a structural schematic diagram of the semiconductor memory structure after the isolation structure is formed.

[0036] In this embodiment, Figure 2 After the trench 204 in the second isolation structure 201 is filled with an isolation material layer, the second isolation structure 201 is formed. The isolation material layer is located between two adjacent conductive structures 200 and includes at least one of silicon nitride, silicon carbon nitride (SiCN), and silicon nitride (Si3N4). When the trench 204 is filled with the isolation material layer, due to the high aspect ratio of the trench 204, the second isolation structure 201 formed between the two conductive structures may be recessed. Figure 5 As shown in the enlarged schematic diagram.

[0037] When preparing the second isolation structure 201, a mask must first be formed above the conductive structure 200 to protect the upper surface of the conductive structure 200. Then, the trenches 204 between adjacent conductive structures 200 are filled, and an insulating material layer is formed within the trenches 204. The mask is then removed, and the second isolation structure 201 that protrudes above the upper surface of the conductive structure 200 is etched back and / or chemically mechanically polished, etc., to lower the upper surface of the conductive structure 200 above the upper surface of the second isolation structure 201. This allows the upper surface of the conductive structure 200 to form the bottom electrode of the capacitor in the semiconductor memory structure.

[0038] The mask includes a photomask, a hard mask, etc. The mask removal method includes wet etching, etc. Those skilled in the art can select the specific type of the mask as needed and select the mask removal method according to the specific type of the mask.

[0039] During the process of etching back and chemical mechanical polishing of the second isolation structure 201, the conductive structure 200 may be separated by the etching solution or chemical mechanical polishing to produce conductive particles, which may be attached to the surface of the second isolation structure 201. When there are too many conductive particles on the surface of the second isolation structure 201, it will cause a short circuit between the two conductive structures 200. Figure 3 The conductive loop 203 is marked on the top, and the conductive loop is composed of conductive particles.

[0040] The conductive particles can be removed by cleaning the surface of the second isolation structure 201, thereby removing the conductive particles on the surface of the second isolation structure 201 to form a Figure 4 The schematic diagram shown. Figure 4 In the embodiment shown, the Figure 3 The conductive loop 203 marked above is removed together with the conductive particles, and no longer short-circuits the conductive structures 200 on both sides.

[0041] In some embodiments, the cleaning of the surface of the second isolation structure 201 further includes at least the following steps: performing at least one of wet cleaning and dry cleaning on the surface of the second isolation structure 201 .

[0042] The wet cleaning process includes wet cleaning the surface of the second isolation structure 201 using an RCA standard cleaning process or a hydrofluoric acid solution. RCA standard cleaning is a typical and widely used wet chemical cleaning process that is effective for removing various types of contaminants from silicon wafer surfaces. Typically, an SPM cleaning solution (comprising concentrated sulfuric acid, hydrogen peroxide, and water in a volume ratio of H2SO4:H2O2:H2O=5:1:1) is used. In practice, those skilled in the art can select a specific cleaning solution as needed.

[0043] In some embodiments, the wet cleaning includes using a hydrofluoric acid solution to clean the surface of the second isolation structure 201 , and the ratio of hydrofluoric acid to water in the hydrofluoric acid solution is greater than or equal to 1:600.

[0044] Research has found that using a hydrofluoric acid solution with a ratio of hydrofluoric acid to water greater than or equal to 1:500 to clean the conductive particles on the surface of the second isolation structure 201 has a better cleaning effect.

[0045] In some embodiments, the dry cleaning includes: performing an ashing process on the surface of the second isolation structure 201 using a gas containing oxygen radicals or oxygen ions, where the gas includes at least one of hydrogen or nitrogen.

[0046] In some embodiments, the surface of the second isolation structure 201 is wet cleaned and dry cleaned. In some embodiments, the surface of the second isolation structure 201 is wet cleaned first, and then dry cleaned.

[0047] In some other embodiments, the surface of the second isolation structure 201 is first dry-cleaned, and then the surface of the second isolation structure 201 is wet-cleaned.

[0048] In some embodiments, heat treatment is performed before or after dry cleaning and wet cleaning. In embodiments where both dry cleaning and wet cleaning are performed, the first heat treatment and the second heat treatment can be performed after the wet cleaning and / or dry cleaning, respectively.

[0049] In some embodiments, the heat treatment includes providing a gas environment with a preset temperature for the surface of the second isolation structure 201 .

[0050] Research has found that the higher the heat treatment temperature is, the less residual conductive particles are left on the surface of the second isolation structure 201. In some embodiments, the preset temperature is greater than or equal to 400°C.

[0051] Research has found that when the temperature is 615° C., the residual amount of conductive particles on the surface of the second isolation structure 201 is substantially removed, which can effectively prevent short circuits between two adjacent conductive structures 200 .

[0052] In some embodiments, the gas environment provided by the heat treatment includes a nitrogen environment. Providing a gas environment with a preset temperature for the surface of the second isolation structure 201 includes the following steps: introducing nitrogen into the chamber where the semiconductor memory structure is located, and the nitrogen flow rate is greater than or equal to 0.75 SLM.

[0053] Continuously introducing the nitrogen gas can sweep away the conductive particles on the surface of the second isolation structure 201 , and as the nitrogen gas flow rate increases, the cleaning force on the conductive particles on the surface of the second isolation structure 201 becomes greater.

[0054] The study found that when the flow rate of the nitrogen gas is 1 SLM, the cleaning force of the conductive particles on the surface of the second isolation structure 201 is better. Combined with the previous dry cleaning and / or wet cleaning, and the control of the nitrogen temperature, the residual amount of conductive particles on the surface of the second isolation structure 201 is basically removed, which can effectively prevent short circuits between adjacent conductive structures 200.

[0055] In some embodiments, the gas provided in the gas environment includes nitrogen-containing plasma, which can optimize the cleaning effect.

[0056] In one embodiment, when nitrogen is provided as the gas environment for heat treatment, the flow rate of the nitrogen is 1 SLM, and the temperature of the high-temperature gas environment is 615°C.

[0057] In some embodiments, the heat treatment is performed before and after dry cleaning and / or wet cleaning, respectively, so multiple heat treatments may be performed during one treatment process. In order to ensure a certain cleaning effect, the total duration of the heat treatment is greater than or equal to 1 hour.

[0058] Studies have shown that a longer total heat treatment time results in a better cleaning effect on the conductive particles on the surface of the second isolation structure 201. In some embodiments, to ensure both cleaning effect and treatment time, the total heat treatment time is typically controlled within 9 hours.

[0059] The study found that when the heat treatment time is 6 hours, the cleaning effect of the conductive particles on the surface of the second isolation structure 201 is better. Combined with the previous dry cleaning and / or wet cleaning, and the control of the nitrogen temperature, the residual amount of conductive particles on the surface of the second isolation structure 201 is basically removed, which can effectively prevent short circuits between adjacent conductive structures 200.

[0060] After cleaning, the semiconductor memory structure can be subjected to dispersion spectrum analysis. Dispersion spectrum analysis can measure and count the energy of X-ray photons of all elements within the analysis point at the same time, and can quickly obtain qualitative analysis results, which helps to obtain the cleaning effect of the semiconductor memory structure.

[0061] The study found that after the second isolation structure 201 was etched back, two 30-second wet cleanings and two 45-second wet cleanings with a hydrofluoric acid solution (the ratio of hydrofluoric acid to water was 1:500) were performed. Conductive particles still remained on the surface of the second isolation structure 201. Since a U-shaped groove was formed on the surface of the second isolation structure 201 after the etch-back treatment, the conductive particles adhered to the sidewall surface and bottom surface of the U-shaped groove, forming a U-shaped short circuit. The U-shaped short circuit electrically connected the conductive structures 200 on both sides of the U-shaped groove, which may cause electrical damage to the semiconductor memory structure. Figure 5 As shown, Figure 5 FIG. 1 is an enlarged schematic diagram of a partial structure of a semiconductor memory structure according to an embodiment. A conductive loop 203 formed by conductive particles is provided on the surface of a second isolation structure 201 between two conductive structures 200 .

[0062] Research has also found that when the second isolation structure 201 is cleaned according to the embodiment of the present application, the conductive particles on the surface of the second isolation structure 201 can be effectively removed, and the conductive loop 203 formed by the conductive particles can be cut off.

[0063] In some embodiments, after the etch-back treatment of the second isolation structure 201, two 30-second wet cleanings and two 45-second wet cleanings with a hydrofluoric acid solution (hydrofluoric acid to water ratio of 1:500) are performed, and a heat treatment in a nitrogen environment is performed. The heat treatment in the nitrogen environment corresponds to a treatment temperature of 615°C, a nitrogen flow rate of at least 1 SLM, and a total heat treatment duration of at least 1.78 hours.

[0064] Experiments have shown that after the above treatment, the conductive particles between the two conductive structures 200 are substantially eliminated.

[0065] In some embodiments, after the etch-back treatment of the second isolation structure 201, two 30-second wet cleanings and two 45-second wet cleanings with a hydrofluoric acid solution (hydrofluoric acid:water ratio of 1:500) are performed, and a heat treatment in a nitrogen environment is performed. The heat treatment in the nitrogen environment corresponds to a treatment temperature of 437.5°C, a nitrogen flow rate of at least 1 SLM, and a total heat treatment duration of at least 7.73 hours.

[0066] Experiments have found that after the above treatment, some conductive particles remain between the two conductive structures 200 , but the conductive loop 203 formed by the conductive particles is still cut off, which can effectively prevent short circuit between the two conductive structures 200 .

[0067] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for processing a semiconductor memory structure, characterized in that: The following steps are involved: The semiconductor memory structure is provided, and the semiconductor memory structure includes: a first isolation structure having a plurality of discrete bit line structures formed therein; a second isolation structure located above the first isolation structure, wherein a plurality of discrete conductive structures are formed in the second isolation structure, and wherein one of the conductive structures is correspondingly disposed above each of the bit line structures; Cleaning the surface of the second isolation structure to remove conductive particles remaining on the surface of the second isolation structure during the process of forming the semiconductor memory structure, the cleaning comprising at least: A heat treatment is performed, wherein the gas environment of the heat treatment is nitrogen and the temperature of the heat treatment is greater than or equal to 400°C.

2. The processing method according to claim 1, characterized in that The cleaning of the surface of the second isolation structure further comprises at least the following steps: At least one of wet cleaning and dry cleaning is performed on the surface of the second isolation structure.

3. The processing method according to claim 2, characterized in that Firstly wet-clean the surface of the second isolation structure, and then dry-clean the surface of the second isolation structure, or: The surface of the second isolation structure is firstly dry-cleaned, and then the surface of the second isolation structure is wet-cleaned.

4. The processing method according to claim 2, characterized in that The heat treatment includes a first heat treatment and a second heat treatment, and the first heat treatment and the second heat treatment are respectively performed after wet cleaning and / or dry cleaning.

5. The processing method according to claim 1, characterized in that The heat treatment comprises the following steps: The nitrogen gas is introduced into the chamber where the semiconductor memory structure is located, and the nitrogen gas flow rate is greater than or equal to 0.75 SLM.

6. The processing method according to claim 2, characterized in that The wet cleaning includes using a hydrofluoric acid solution to clean the surface of the second isolation structure, and the ratio of hydrofluoric acid to water in the hydrofluoric acid solution is greater than or equal to 1:600, and / or, The dry cleaning comprises: The surface of the second isolation structure is subjected to an ashing process using a gas containing oxygen radicals or oxygen ions, wherein the gas includes at least one of hydrogen and nitrogen.

7. The processing method according to claim 1, characterized in that The total duration of the heat treatment is greater than or equal to 1 hour.

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