Transparent display device

Abstract

The present application relates to a transparent display device. The transparent display device can minimize the size of a non-transmission area and improve light transmittance. The transparent display device includes a substrate provided with a transmission area and a plurality of sub-pixels disposed between the transmission areas; a first electrode disposed in each of the plurality of sub-pixels, including a first division electrode and a second division electrode; a connection electrode connecting the first division electrode and the second division electrode along a straight line; an organic light emitting layer disposed above the first electrode; and a second electrode disposed above the organic light emitting layer.

Description

Technical Field

[0001] This disclosure relates to transparent display devices. Background Technology

[0002] With the advancement of the information society, the demand for display devices for displaying images has increased in various forms. Recently, various types of display devices, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, organic light-emitting diode (OLED) devices, and quantum dot light-emitting diode (QLED) devices, have been widely used.

[0003] Recently, research has been actively conducted on transparent display devices, which allow users to view objects or images arranged on the opposite side of a transmission display device from behind the transmission display device.

[0004] A transparent display device includes a display area and a non-display area on which an image is displayed, wherein the display area may include a transmissive area and a non-transmissive area that can transmit external light. The transparent display device can have high light transmittance in the display area through the transmissive area.

[0005] A transparent display device may include multiple circuits and signal lines arranged vertically or horizontally in the non-transmissive area. To improve the light transmittance in a transparent display device, it is important to reduce the non-transmissive area and increase the transmissive area by efficiently arranging multiple circuits and signal lines. Summary of the Invention

[0006] This disclosure has been made in view of various technical problems including the above-mentioned issues, and various embodiments of this disclosure provide a transparent display device that can reduce or minimize the size of the non-transmissive area and improve light transmittance.

[0007] In addition to the technical benefits of this disclosure mentioned above, those skilled in the art will clearly understand from the following description of this disclosure additional technical benefits and features.

[0008] According to one aspect of this disclosure, the above and other technical benefits can be achieved by providing a transparent display device comprising: a substrate having a transmissive region and a plurality of sub-pixels disposed between the transmissive region; a first electrode disposed in each of the plurality of sub-pixels, the first electrode including a first segmenting electrode and a second segmenting electrode; a connecting electrode connecting the first segmenting electrode and the second segmenting electrode along a straight line (or substantially a straight line); an organic light-emitting layer disposed above the first electrode; and a second electrode disposed above the organic light-emitting layer.

[0009] According to another aspect of this disclosure, the above and other technical benefits can be achieved by providing a transparent display device, the transparent display device comprising: a substrate having a transmissive region and a non-transmissive region disposed between the transmissive region; a first signal line extending from the non-transmissive region along a first direction; a second signal line extending from the non-transmissive region along a second direction; a first sub-pixel overlapping at least a portion of the second signal line in the non-transmissive region; a second sub-pixel overlapping at least a portion of the first signal line in the non-transmissive region; a first electrode disposed in each of the first sub-pixel and the second sub-pixel, the first electrode comprising a first dividing electrode and a second dividing electrode; a first connecting electrode disposed in a first layer to connect the first dividing electrode and the second dividing electrode disposed in the second sub-pixel to each other; and a second connecting electrode disposed in a second layer to connect the first dividing electrode and the second dividing electrode disposed in the first sub-pixel to each other. Attached Figure Description

[0010] The above and other objects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure; Figure 2 This is a schematic plan view illustrating a transparent display panel according to one embodiment of the present disclosure; Figure 3 yes Figure 2 A magnified view of region A; Figure 4 yes Figure 3 A magnified view of region B; Figure 5 This is an example Figure 4 The graph of region C; Figure 6 This is an example Figure 4 The graph of region D; Figure 7 It is along Figure 4 A cross-sectional view taken from line I-I'; Figure 8 This is an example Figure 4 The diagram showing the region containing the black matrix; Figure 9 This is a diagram illustrating an example of pixel power lines with a grid structure; and Figure 10 It is along Figure 9 The cross-sectional view taken from line II-II'. Detailed Implementation

[0011] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following description of embodiments in conjunction with the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0012] The shapes, dimensions, scales, angles, and quantities disclosed in the drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the illustrated details. Throughout the specification, similar reference numerals refer to similar elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the essence of this disclosure. Where the terms “comprising,” “having,” and “including” are used in this specification, another component may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0013] When interpreting components, even if not explicitly described, the components are interpreted as including a range of error.

[0014] When describing positional relationships, such as "on," "above," "below," and "next to," one or more other parts may be arranged between the two parts unless "exactly" or "directly" is used.

[0015] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0016] In describing the elements of this disclosure, the terms “first,” “second,” etc., may be used. These terms are intended to distinguish the corresponding element from other elements, and the nature, order, or number of the corresponding elements is not limited by these terms. The expression “connected” or “attached” to another element should be understood as meaning that the element may be directly connected or attached to another element, but unless otherwise specified, it may be indirectly connected or adhered to another element or layer, or a third element may be inserted between the corresponding elements.

[0017] According to the embodiments disclosed herein, the term "symmetry" as used herein includes both the meaning of "symmetry" and "fundamental symmetry." That is, the word "symmetry" used alone is broad enough to include structures that are very similar to each other and / or generally symmetrical, without necessarily being perfectly symmetrical in every aspect or at every detailed, subtle level.

[0018] Features of the various embodiments of this disclosure may be linked or combined with each other in part or in whole, and may interoperate with each other in various ways and be technically driven, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other or may be implemented together in an interdependent manner.

[0019] In the following, examples of transparent display devices according to this disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0020] Figure 1 This is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure.

[0021] In the following text, the X-axis indicates a line parallel to the scan line, the Y-axis indicates a line parallel to the data line, and the Z-axis indicates the height direction of the transparent display device 100.

[0022] Although the specification has been described based on an embodiment of the transparent display device 100 according to this disclosure as an organic light-emitting display device, the transparent display device 100 may be implemented as a liquid crystal display device, a plasma display panel (PDP), a quantum dot light-emitting display (QLED) or an electrophoretic display device.

[0023] Reference Figure 1 According to one embodiment of the present disclosure, a transparent display device 100 includes a transparent display panel 110, a source driver integrated circuit (IC) 210, a flexible film 220, a circuit board 230, and a timing controller 240.

[0024] The transparent display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using semiconductor processes. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film. The first substrate 111 and the second substrate 112 may be made of transparent materials.

[0025] Scan drivers can be provided in the non-display areas on one side of the display area of ​​the transparent display panel 110 or on both peripheral sides of the transparent display panel 110 using a gated in-panel driver (GIP) method. Alternatively, the scan driver can be manufactured as a driver chip, mounted on a flexible film, and attached to one or both peripheral sides of the display area of ​​the transparent display panel 110 using a tape auto-bonding (TAB) method.

[0026] If the source driver IC 210 is manufactured as a driver chip, the source driver IC 210 can be mounted on the flexible film 220 by a chip-on-film (COF) method or a chip-on-plastic (COP) method.

[0027] Pads such as power pads and data pads can be provided in the pad area PA of the transparent display panel 110. Lines connecting the pads to the source driver IC 210 and lines connecting the pads to the circuit board 230 can be disposed in the flexible film 220. The flexible film 220 can be attached to the pads using an anisotropic conductive film, thereby allowing the pads to be connected to the lines of the flexible film 220.

[0028] Figure 2 This is a schematic plan view illustrating a transparent display panel according to one embodiment of the present disclosure, and Figure 3 yes Figure 2 A magnified view of region A.

[0029] Reference Figure 2 and Figure 3 The first substrate 111 may include a display area DA with pixels P for displaying images and a non-display area NDA for not displaying images.

[0030] The non-display area NDA can be configured with a pad area PA and at least one scan driver 205, with the pad PAD set in the pad area PA.

[0031] Scan driver 205 is connected to scan line SL and provides scan signals to scan line SL. Scan driver 205 can be configured via a strobe driver (GIP) method, located on one side of the display area DA of the transparent display panel 110 or in the non-display areas NDA on both peripheral sides of the transparent display panel 110. For example, as... Figure 2 As shown, the scan driver 205 can be disposed on both sides of the display area DA of the transparent display panel 110, but these scan drivers are not limited to this. The scan driver 205 can be disposed on only one side of the display area DA of the transparent display panel 110.

[0032] like Figure 3 As shown, the display area DA includes a transmissive area TA and a non-transmissive area NTA. The transmissive area TA is the area through which most of the external incident light passes, and the non-transmissive area NTA is the area through which most of the external incident light cannot pass. For example, the transmissive area TA can be an area with a transmittance greater than α% (e.g., about 90%), and the non-transmissive area NTA can be an area with a transmittance less than β% (e.g., about 50%). In this case, α is greater than β. Due to the transmissive area TA, the user can see objects or backgrounds arranged above the rear surface of the transparent display panel 110.

[0033] The non-transmissive region NTA may include multiple pixels P, multiple first signal lines SL1, and multiple second signal lines SL2 to provide signals to each of the multiple pixels P.

[0034] Multiple first signal lines SL1 may extend in a first direction (e.g., the X-axis direction). Multiple first signal lines SL1 may intersect with multiple second signal lines SL2. For example, each of the multiple first signal lines SL1 may include at least one scan line.

[0035] In the following text, when the first signal line SL1 comprises multiple lines, one first signal line SL1 may refer to a group of signal lines comprising multiple lines. For example, when the first signal line SL1 comprises two scan lines, one first signal line SL1 may refer to a group of signal lines comprising two scan lines.

[0036] Multiple second signal lines SL2 may extend in a second direction (e.g., the Y-axis direction). For example, each of the multiple second signal lines SL2 may include at least one of a data line, a pixel power line, a reference line, or a common power line.

[0037] In the following text, when the second signal line SL2 comprises multiple lines, one second signal line SL2 may refer to a signal line group comprising multiple lines. For example, when the second signal line SL2 comprises two data lines, a pixel power line, a common power line, and a reference line, one second signal line SL2 may refer to a signal line group comprising two data lines, a pixel power line, a common power line, and a reference line.

[0038] The transmission region TA can be positioned between adjacent first signal lines SL1. Furthermore, the transmission region TA can be positioned between adjacent second signal lines SL2. That is, the transmission region TA can be surrounded by two first signal lines SL1 and two second signal lines SL2. For example, the transmission region TA can have a rectangular shape surrounded by two first signal lines SL1 and two second signal lines SL2. The transmission region TA can have a rectangular shape including four corners. The transmission region TA can include a first corner V1, a second corner V2 facing the first corner V1 in a second direction, a third corner V3 facing the second corner V2 in a first direction, and a fourth corner V4 facing the first corner V1 in a first direction.

[0039] Pixel P can be configured to overlap with at least one of the first signal line SL1 and the second signal line SL2, thereby emitting predetermined light to display an image. The light-emitting region EA can correspond to the region in pixel P from which light is emitted.

[0040] Each pixel P may include at least one of a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The first sub-pixel P1 may include a first emitting region EA1 that emits green light. The second sub-pixel P2 may include a second emitting region EA2 that emits red light. The third sub-pixel P3 may include a third emitting region EA3 that emits white light. The fourth sub-pixel P4 may include a fourth emitting region EA4 that emits blue light. However, the emitting regions are not limited to this example. Each pixel P may also include sub-pixels that emit light of colors other than red, green, blue, and white. Furthermore, the arrangement order of sub-pixels P1, P2, P3, and P4 can be varied in various ways.

[0041] Furthermore, the light-emitting regions EA1, EA2, EA3, and EA4 respectively located in the multiple sub-pixels P1, P2, P3, and P4 can include light-emitting regions divided into multiple regions. Specifically, the first light-emitting region EA1 located in the first sub-pixel P1 can include two segmented regions, namely, a first segmented light-emitting region EA1-1 and a second segmented light-emitting region EA1-2. The second light-emitting region EA2 located in the second sub-pixel P2 can include two segmented regions, namely, a first segmented light-emitting region EA2-1 and a second segmented light-emitting region EA2-2. The third light-emitting region EA3 located in the third sub-pixel P3 can include two segmented regions, namely, a first segmented light-emitting region EA3-1 and a second segmented light-emitting region EA3-2. The fourth light-emitting region EA4 located in the fourth sub-pixel P4 can include two segmented regions, namely, a first segmented light-emitting region EA4-1 and a second segmented light-emitting region EA4-2.

[0042] In the following description, for ease of explanation, the first sub-pixel P1 is a green sub-pixel that emits green light, the second sub-pixel P2 is a red sub-pixel that emits red light, the third sub-pixel P3 is a white sub-pixel that emits white light, and the fourth sub-pixel P4 is a blue sub-pixel that emits blue light.

[0043] The second sub-pixel P2 and the fourth sub-pixel P4 can be configured to overlap with at least a portion of the first signal line SL1, and can be alternately configured along the first signal line SL1.

[0044] The first sub-pixel P1 and the third sub-pixel P3 can be configured to overlap with at least a portion of the second signal line SL2, and can be configured alternately along the second signal line SL2.

[0045] like Figure 3 As shown, the second sub-pixel P2 and the fourth sub-pixel P4 can be located in the area where the first signal line SL1 and the second signal line SL2 intersect or overlap, but are not limited thereto.

[0046] In another embodiment, the first sub-pixel P1 and the third sub-pixel P3 can be located in the area where the first signal line SL1 and the second signal line SL2 intersect or overlap. In this case, in the area where the first signal line SL1 and the second signal line SL2 intersect or overlap, the second sub-pixel P2 and the fourth sub-pixel P4 can be spaced apart from each other, and the first sub-pixel P1 and the third sub-pixel P3 are interposed between the second sub-pixel P2 and the fourth sub-pixel P4.

[0047] Each of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 may include circuit elements and light-emitting diodes. The circuit elements include capacitors, thin-film transistors, etc. The thin-film transistors may include switching transistors, sensing transistors, and driving transistors.

[0048] The switching transistor is switched on and off according to the scan signal provided to the scan line, so as to provide the data voltage provided from the data line to the driving transistor.

[0049] The sensing transistor is used to sense the threshold voltage deviation that drives the transistor and degrades image quality.

[0050] The driving transistor switches on and off according to the data voltage supplied from the switching thin-film transistor to generate a data current from the power supply provided by the pixel power line, thereby supplying the generated data current to the anode electrode of the sub-pixel. The driving transistor includes an active layer, a gate electrode, a source electrode, and a drain electrode.

[0051] A capacitor is used to maintain the data voltage supplied to the driving transistor within a frame. A capacitor may include two capacitor electrodes, but is not limited to this. In one embodiment, a capacitor may include three capacitor electrodes.

[0052] A transparent display panel 110 according to one embodiment of the present disclosure is characterized in that the capacitor has an L-shape. More specifically, the capacitor according to one embodiment of the present disclosure may include a first capacitor pattern portion longitudinally disposed in a first direction between a first signal line SL1 and a transmission region TA, and a second capacitor pattern portion extending from one end of the first capacitor pattern portion and longitudinally disposed in a second direction between a second signal line SL2 and the transmission region TA.

[0053] In the following text, reference will be made to Figures 4 to 8 Describe in detail the L-shaped capacitor, driving transistor, multiple signal lines, and light-emitting diode.

[0054] Figure 4 This is an example Figure 3 A magnified view of region B. Figure 5 This is an example Figure 4 The graph of region C, and Figure 6 This is an example Figure 4 The diagram of region D. Figure 7 It is along Figure 4 The cross-sectional view taken by line I-I', and Figure 8 This is an example Figure 4 The diagram shows the region containing the black matrix.

[0055] Reference Figures 4 to 8 As an example, a first signal line SL1 extending in a first direction (e.g., the X-axis direction) may be disposed in a non-transmissive region NTA and may include, but is not limited to, scan lines SCANL. As another example, the first signal line SL1 may include multiple scan lines SCANL, for example, two scan lines SCANL.

[0056] For example, a second signal line SL2 extending in a second direction (e.g., the Y-axis direction) can be disposed in a non-transmissive region NTA, and may include, but is not limited to, a first data line DL1, a second data line DL2, a pixel power line VDDL, a reference line REFL, a common power line VSSL, a third data line DL3, and a fourth data line DL4. As another example, the second signal line SL2 may consist of only two data lines, the pixel power line VDDL, the reference line REFL, and the common power line VSSL.

[0057] The scan line SCANL can provide scan signals to the sub-pixels P1, P2, P3 and P4 set in the display area DA.

[0058] The reference line REFL can provide a reference voltage (or initialization voltage or sensing voltage) to the driving transistor DT of each of the sub-pixels P1, P2, P3 and P4 in the display area DA.

[0059] Each of the first to fourth data lines DL1, DL2, DL3, and DL4 can provide a data voltage to at least one of the sub-pixels P1, P2, P3, or P4 disposed in the display area DA. For example, the first data line DL1 can provide a first data voltage to the first driving transistor DT1 of the first sub-pixel P1, the second data line DL2 can provide a second data voltage to the second driving transistor DT2 of the second sub-pixel P2, the third data line DL3 can provide a third data voltage to the third driving transistor DT3 of the third sub-pixel P3, and the fourth data line DL4 can provide a fourth data voltage to the fourth driving transistor DT4 of the fourth sub-pixel P4.

[0060] The pixel power line VDDL can provide a first power supply to the first electrode 120 of each of the sub-pixels P1, P2, P3, and P4. The common power line VSSL can provide a second power supply to the second electrode 140 of each of the sub-pixels P1, P2, P3, and P4.

[0061] When the second signal line SL2 includes a pixel power line VDDL and a common power line VSSL, since the voltage applied to the pixel power line VDDL and the common power line VSSL is higher than that of other signal lines, it is preferable that the pixel power line VDDL and the common power line VSSL have a wider area than other signal lines. Each of the pixel power line VDDL and the common power line VSSL can be formed as a double layer to ensure a wider area. For example, the pixel power line VDDL can include a first pixel power line VDDL-1 and a second pixel power line VDDL-2. Similarly, the common power line VSSL can include a first common power line VSSL-1 and a second common power line VSSL-2.

[0062] The transmission region TA can be set between adjacent first signal lines SL1 and between adjacent second signal lines SL2.

[0063] Each of the plurality of sub-pixels P1, P2, P3, and P4 may be disposed in the non-transmissive region NTA to overlap with at least one of the first signal line SL1 or the second signal line SL2. For example, the second sub-pixel P2 and the fourth sub-pixel P4 may be disposed to overlap with at least a portion of the first signal line SL1, and may be arranged alternately along the first signal line SL1. The first sub-pixel P1 and the third sub-pixel P3 may be disposed to overlap with at least a portion of the second signal line SL2, and may be arranged alternately along the second signal line SL2. Each of the plurality of sub-pixels P1, P2, P3, and P4 may be provided with a light-emitting diode.

[0064] The driving transistor DT and capacitor Cst can be positioned between the transmission region TA and the first signal line SL1 or between the transmission region TA and the second signal line SL2, and can be connected to the light-emitting diode of each of the multiple sub-pixels P1, P2, P3 and P4.

[0065] The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The capacitor Cst may include, but is not limited to, a first capacitor electrode CE1, a second capacitor electrode CE2, and a third capacitor electrode CE3. In another embodiment, the capacitor Cst may include only two of the first capacitor electrode CE1, the second capacitor electrode CE2, and the third capacitor electrode CE3.

[0066] Specifically, the active layer ACT can be disposed above the first substrate 111. The active layer ACT can be formed of a silicon-based semiconductor material or an oxide-based semiconductor material.

[0067] A light-shielding layer LS can be disposed between the active layer ACT and the first substrate 111. The light-shielding layer LS can serve as a light-shielding layer for shielding external light entering the active layer ACT. The light-shielding layer LS can be made of a conductive material. For example, the light-shielding layer LS can be formed as a single layer or multiple layers of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or alloys thereof. In this case, a buffer film BF can be disposed between the light-shielding layer LS and the active layer ACT.

[0068] Furthermore, the third capacitor electrode CE3 and at least one of the multiple signal lines can be disposed on the same layer as the light-shielding layer LS. For example, the third capacitor electrode CE3, the first data line DL1, the second data line DL2, the first pixel power line VDDL-1, the third data line DL3, and the first common power line VSSL-1 can be formed on the same layer as the light-shielding layer LS using the same material.

[0069] The gate insulating layer GI can be disposed above the active layer ACT. The gate insulating layer GI can be formed of an inorganic film (e.g., a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer film of SiOx and SiNx).

[0070] The gate electrode GE can be disposed above the gate insulating layer GI. The gate electrode GE can be formed as a single layer or multiple layers of any one of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or alloys thereof.

[0071] Furthermore, the first capacitor electrode CE1 and at least one of the multiple signal lines can be formed on the same layer as the gate electrode GE. For example, the first capacitor electrode CE1, the reference line REFL, and the fourth data line DL4 can be formed on the same layer as the gate electrode GE using the same material.

[0072] exist Figure 7 In this configuration, the reference line REFL and the fourth data line DL4 are disposed on the same layer as the gate electrode GE, and the first data line DL1, the second data line DL2, the first pixel power line VDDL-1, the third data line DL3, and the first common power line VSSL-1 are disposed on the same layer as the light-shielding layer LS, but are not limited thereto. Each of the first data line DL1, the second data line DL2, the reference line REFL, the first pixel power line VDDL-1, the first common power line VSSL-1, the third data line DL3, and the fourth data line DL4 can be formed on the same layer as any one of the light-shielding layer LS, the active layer ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE.

[0073] In the transparent display panel 110, to ensure high light transmittance, it is preferable to reduce the size of the non-transmissive region NTA and increase the size of the transmissive region TA. Therefore, the transparent display panel 110 can improve light transmittance by minimizing the width of the second signal line SL2 disposed in the non-transmissive region NTA.

[0074] In a transparent display panel 110 according to one embodiment of the present disclosure, in order to reduce or minimize the width of the second signal line SL2, the multiple signal lines included in the second signal line SL2 may not be formed in one layer, and may be as follows: Figure 7 The signal lines are distributed across multiple layers. Therefore, the transparent display panel 110 according to one embodiment of this disclosure can reduce or minimize the width of the second signal line SL2, and simultaneously minimize the parasitic capacitance between adjacent signal lines.

[0075] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, the signal lines disposed at the outermost portions of the plurality of signal lines included in the second signal line SL2 can be disposed on the same layer as the light-shielding layer LS. For example, when the first data line DL1 among the plurality of signal lines included in the second signal line SL2 is disposed on the outermost layer, the first data line DL1 can be formed on the same layer as the light-shielding layer LS.

[0076] During the manufacturing process, particles may appear on the upper surface of the signal line. When another signal line is deposited on top of the signal line with the particles and an insulating layer is inserted between them, a short circuit may occur between the signal line with the particles and the other signal line. In particular, when a short circuit occurs between the second capacitor electrode CE2 of the capacitor Cst, which is electrically connected to the driving transistor DT, and the signal line, the sub-pixel connected to the corresponding driving transistor DT and capacitor Cst may fail to emit light.

[0077] In a transparent display panel 110 according to one embodiment of the present disclosure, signal lines disposed adjacent to a capacitor Cst (specifically, the second capacitor pattern portion CP2 of the capacitor Cst) can be formed in a light-shielding layer LS to prevent short circuits between the capacitor Cst and the signal lines due to particles. Since multiple insulating layers BF, GI, and ILD are disposed between the second capacitor electrode CE2 of the capacitor Cst and the light-shielding layer LS, even if particles appear on the upper surface of the signal lines disposed in the light-shielding layer LS, short circuits between the signal lines and the second capacitor electrode CE2 of the capacitor Cst can be prevented.

[0078] exist Figure 4 and Figure 7In this configuration, the first data line DL1, the second data line DL2, the reference line REFL, the pixel power line VDDL, the third data line DL3, the fourth data line DL4, and the common power line VSSL are arranged in an appropriate order, but are not limited to this. The arrangement order of the signal lines included in the second signal line SL2 can be changed in various ways.

[0079] The interlayer dielectric layer (ILD) can be disposed above the gate electrode (GE). The ILD can be made of inorganic films (e.g., silicon oxide films (SiOx), silicon nitride films (SiNx), or multilayer films of SiOx and SiNx).

[0080] The source electrode SE and drain electrode DE can be disposed above the interlayer dielectric layer ILD. The source electrode SE and drain electrode DE can be connected to the active layer ACT through contact holes passing through the gate insulating layer GI and the interlayer dielectric layer ILD.

[0081] The source electrode SE and drain electrode DE can be made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or their alloys, in single or multiple layers.

[0082] Furthermore, the second capacitor electrode CE2 and at least one of the multiple signal lines can be disposed on the same layer as the source electrode SE and the drain electrode DE. For example, the second capacitor electrode CE2, the second pixel power line VDDL-2, and the second common power line VSSL-2 can be formed on the same layer as the source electrode SE and the drain electrode DE using the same material.

[0083] Specifically, the second capacitor electrode CE2 of capacitor Cst can extend from either the source electrode SE or the drain electrode DE. Therefore, the second capacitor electrode CE2 of capacitor Cst can be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT.

[0084] The passivation layer PAS used to protect the driving transistor DT can be placed above the source electrode SE and the drain electrode DE.

[0085] A planarization layer PLN, used to flatten the step difference caused by the driving transistor DT, can be disposed above the passivation layer PAS. The planarization layer PLN can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0086] The following section will describe in detail an example consisting of a first signal line SL1, a second signal line SL2, a driving transistor DT, and a capacitor Cst.

[0087] As described above, the display area DA includes a transmissive area TA and a non-transmissive area NTA. The transmissive area TA may have a rectangular shape including four corners. The transmissive area TA may include a first corner V1, a second corner V2 facing the first corner V1 in a second direction, a third corner V3 facing the second corner V2 in a first direction, and a fourth corner V4 facing the first corner V1 in a first direction.

[0088] The non-transmissive region NTA includes a first non-transmissive region NTA1 extending between adjacent transmissive regions TA in a first direction (e.g., the X-axis direction), and a second non-transmissive region NTA2 extending between adjacent transmissive regions TA in a second direction (e.g., the Y-axis direction).

[0089] The first signal line SL1, the driving transistor DT of each of the sub-pixels P1, P2, P3, and P4, and the first capacitor pattern portion CP1 of the capacitor Cst can be disposed in the first non-transmissive region NTA1. The second signal line SL2 and the second capacitor pattern portion CP2 of the capacitor Cst of each of the sub-pixels P1, P2, P3, and P4 can be disposed in the second non-transmissive region NTA2.

[0090] A transparent display panel 110 according to one embodiment of the present disclosure includes a capacitor Cst having an L-shape. Specifically, the capacitor Cst includes a first capacitor pattern portion CP1 and a second capacitor pattern portion CP2. The first capacitor pattern portion CP1 may be disposed in a first non-transmissive region NTA1 between a first signal line SL1 and a transmissive region TA and formed longitudinally along a first direction (e.g., the X-axis direction). When the first signal line SL1 includes a scan line SCANL, the first capacitor pattern portion CP1 may be disposed between the scan line SCANL and the transmissive region TA.

[0091] The second capacitor pattern portion CP2 can extend from one end of the first capacitor pattern portion CP1. The second capacitor pattern portion CP2 can be disposed in the second non-transmissive region NTA2 between the second signal line SL2 and the transmissive region TA and formed longitudinally along a second direction (e.g., the Y-axis direction). When the second signal line SL2 includes multiple signal lines, the second capacitor pattern portion CP2 can be disposed between the signal line disposed at the outermost part of the multiple signal lines and the transmissive region TA.

[0092] The width W2 of the second capacitor pattern portion CP2 can be smaller than the width W1 of the first capacitor pattern portion CP1. The first capacitor pattern portion CP1 can be disposed along the first signal line SL1 in the first non-transmissive region NTA1, and the second capacitor pattern portion CP2 can be disposed along the second signal line SL2 in the second non-transmissive region NTA2. In this case, the first signal line SL1 only includes the scan line SCANL, while the second signal line SL2 can include a large number of signal lines, such as the first data line DL1, the second data line DL2, the pixel power line VDDL, the reference line REFL, the common power line VSSL, the third data line DL3, and the fourth data line DL4. Therefore, the width of the second signal line SL2 becomes larger than the width of the first signal line SL1.

[0093] In a transparent display panel 110 according to one embodiment of the present disclosure, the width W2 of the second capacitor pattern portion CP2 is smaller than the width W1 of the first capacitor pattern portion CP1, thereby making the first non-transparent region NTA1 and the second non-transparent region NTA2 similar to each other by reducing the width difference between the first non-transparent region NTA1 and the second non-transparent region NTA2.

[0094] In a transparent display panel 110 according to one embodiment of the present disclosure, the second sub-pixel P2 and the fourth sub-pixel P4 disposed along the first non-transmissive region NTA1, and the first sub-pixel and the third sub-pixel P1 and P3 disposed along the second non-transmissive region NTA2, can be formed to have similar light-emitting areas. Therefore, in the transparent display panel 110 according to one embodiment of the present disclosure, the difference between the horizontal and vertical lengths of the transmissive region TA can be reduced, and preferably, the transmissive region TA can be implemented as a square shape. Among squares with the same area, the square shape has the shortest perimeter. When the transmissive region TA is implemented as a square shape, the perimeter of the transmissive region TA can be reduced or minimized. As described above, the transparent display panel 110 can include a black matrix BM located between the sub-pixels P1, P2, P3, and P4 and the transmissive region TA, and as the area used to form the black matrix BM increases, the light transmittance decreases.

[0095] In a transparent display panel 110 according to one embodiment of the present disclosure, the transmissive region TA is formed in a square shape, thereby reducing or minimizing the area used to form the black matrix BM. Therefore, the transparent display panel 110 according to one embodiment of the present disclosure can improve light transmittance.

[0096] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, the transmissive region TA is formed in a square shape, thereby preventing diffraction of light passing through the transmissive region TA.

[0097] According to diffraction, as light passes through the slit, light corresponding to a plane wave can become a spherical wave, and interference may occur in the spherical wave. Therefore, constructive and destructive interferences occur in the spherical wave, resulting in irregular light intensities for the external light passing through the slit. As a result, the sharpness of objects or images on opposite sides of the transparent display panel 110 may be reduced.

[0098] This diffraction phenomenon can occur when external light passes through a slit, an elongated linear or rectangular transmission area TA. According to one embodiment of this disclosure, the transparent display panel 110 can form a square-shaped transmission area TA, thereby preventing diffraction and improving image clarity.

[0099] In addition, a capacitor Cst including a first capacitor pattern portion CP1 and a second capacitor pattern portion CP2 and a driving transistor DT can be provided for each of the sub-pixels P1, P2, P3 and P4.

[0100] The capacitor Cst may include a first capacitor Cst1 connected to the first sub-pixel P1, a second capacitor Cst2 connected to the second sub-pixel P2, a third capacitor Cst3 connected to the third sub-pixel P3, and a fourth capacitor Cst4 connected to the fourth sub-pixel P4.

[0101] In addition, the driving transistor DT may include a first driving transistor DT1 connected to the first sub-pixel P1, a second driving transistor DT2 connected to the second sub-pixel P2, a third driving transistor DT3 connected to the third sub-pixel P3, and a fourth driving transistor DT4 connected to the fourth sub-pixel P4.

[0102] The first capacitor Cst1 can be configured to correspond to a first corner V1 of each of the plurality of transmission regions TA, and can be formed in an L-shape along the outside of the transmission region TA. Specifically, the first capacitor pattern portion CP1 of the first capacitor Cst1 can be disposed between the first signal line SL1 and the transmission region TA at a first side of the first signal line SL1. The first capacitor pattern portion CP1 of the first capacitor Cst1 can be disposed along the outside from the first corner V1 of the transmission region TA toward the fourth corner V4.

[0103] The second capacitor pattern portion CP2 of the first capacitor Cst1 can be disposed between the second signal line SL2 and the transmission region TA on the first side of the first signal line SL1. The second capacitor pattern portion CP2 of the first capacitor Cst1 can be bent at one end of the first capacitor pattern portion CP1 and can be disposed outside along the first corner V1 of the transmission region TA toward the second corner V2.

[0104] The first capacitor Cst1 can be connected to the first electrode 120 of the first sub-pixel P1 in the second capacitor pattern portion CP2.

[0105] Furthermore, the first driving transistor DT1 can be spaced apart from the second signal line SL2 in the first non-transmissive region NTA1, and the first capacitor Cst1 is inserted therebetween. Therefore, the first driving transistor DT1 connected to the first sub-pixel P1 can be spaced apart from the first sub-pixel P1, with the first capacitor Cst1 inserted therebetween, and can overlap with at least one of the second sub-pixel P2 and the fourth sub-pixel P4. For example, the first driving transistor DT1 can overlap with the second sub-pixel P2.

[0106] The first driving transistor DT1 can be disposed between the first signal line SL1 and the transmission region TA, and thus connected to the other end of the first capacitor pattern portion CP1 of the first capacitor Cst1. The gate electrode GE of the first driving transistor DT1 can be configured to extend from the first capacitor electrode CE1 disposed in the first capacitor pattern portion CP1 of the first capacitor Cst1. The source electrode SE or drain electrode DE of the first driving transistor DT1 can be configured to extend from the second capacitor electrode CE2 of the first capacitor pattern portion CP1 of the first capacitor Cst1. The first driving transistor DT1 can be electrically connected to the first electrode 120 of the first sub-pixel P1 through the first capacitor Cst1.

[0107] The second capacitor Cst2 can be configured to correspond to the second corner V2 of each of the plurality of transmission regions TA, and can be formed symmetrically with the first capacitor Cst1. Specifically, the first capacitor pattern portion CP1 of the second capacitor Cst2 can be disposed between the first signal line SL1 and the transmission region TA at the second side of the first signal line SL1. The first capacitor pattern portion CP1 of the second capacitor Cst2 can be disposed outward from the second corner V2 of the transmission region TA toward the third corner V3. In this case, the first capacitor pattern portion CP1 of the second capacitor Cst2 can be configured to be symmetrical with the first capacitor pattern portion CP1 of the first capacitor Cst1 based on the first signal line SL1.

[0108] The second capacitor pattern portion CP2 of the second capacitor Cst2 can be disposed between the second signal line SL2 and the transmission region TA on the second side of the first signal line SL1. The second capacitor pattern portion CP2 of the second capacitor Cst2 can be bent at one end of the first capacitor pattern portion CP1 and can be disposed outside the transmission region TA from the second corner V2 toward the first corner V1.

[0109] The second capacitor Cst2 can be connected to the first electrode 120 of the second sub-pixel P2 in the first capacitor pattern portion CP1.

[0110] Furthermore, the second driving transistor DT2 can be spaced apart from the second signal line SL2 in the first non-transmissive region NTA1, and the second capacitor Cst2 is inserted therebetween. The second driving transistor DT2 connected to the second sub-pixel P2 can overlap with the second sub-pixel P2.

[0111] The second driving transistor DT2 can be configured to be symmetrical to the first driving transistor DT1 based on the first signal line SL1, and can be connected to the other end of the first capacitor pattern portion CP1 of the second capacitor Cst2. The gate electrode GE of the second driving transistor DT2 can be configured to extend from the first capacitor electrode CE1 disposed in the first capacitor pattern portion CP1 of the second capacitor Cst2. The source electrode SE or drain electrode DE of the second driving transistor DT2 can be configured to extend from the second capacitor electrode CE2 disposed in the first capacitor pattern portion CP1 of the second capacitor Cst2. The second driving transistor DT2 can be electrically connected to the first electrode 120 of the second sub-pixel P2 through the second capacitor Cst2 and the contact electrode CT.

[0112] The third capacitor Cst3 can be configured as a triangle V3 corresponding to each of the plurality of transmission regions TA, and can be formed symmetrically with the second capacitor Cst2. Specifically, the first capacitor pattern portion CP1 of the third capacitor Cst3 can be disposed between the first signal line SL1 and the transmission region TA on the second side of the first signal line SL1. The first capacitor pattern portion CP1 of the third capacitor Cst3 can be disposed along the outer edge from the triangle V3 of the transmission region TA toward the second angle V2. In this case, the first capacitor pattern portion CP1 of the third capacitor Cst3 can be configured to be symmetrical with the first capacitor pattern portion CP1 of the second capacitor Cst2 based on the second signal line SL2.

[0113] The second capacitor pattern portion CP2 of the third capacitor Cst3 can be disposed between the second signal line SL2 and the transmission region TA on the second side of the first signal line SL1. The second capacitor pattern portion CP2 of the third capacitor Cst3 can be bent at one end of the first capacitor pattern portion CP1 and can be disposed outside along the first triangle V3 of the transmission region TA toward the fourth corner V4.

[0114] The third capacitor Cst3 can be connected to the first electrode 120 of the third sub-pixel P3 in the second capacitor pattern portion CP2.

[0115] Furthermore, the third driving transistor DT3 can be spaced apart from the second signal line SL2 in the first non-transmissive region NTA1, and the third capacitor Cst3 is inserted therebetween. Therefore, the third driving transistor DT3 connected to the third sub-pixel P3 can be spaced apart from the third sub-pixel P3, with the third capacitor Cst3 inserted therebetween, and can overlap with at least one of the second sub-pixel P2 or the fourth sub-pixel P4. For example, the third driving transistor DT3 can overlap with the fourth sub-pixel P4.

[0116] The third driving transistor DT3 can be configured to be symmetrical to the second driving transistor DT2 based on the second signal line SL2, and can be connected to the other end of the first capacitor pattern portion CP1 of the third capacitor Cst3. The gate electrode GE of the third driving transistor DT3 can be configured to extend from the first capacitor electrode CE1 disposed in the first capacitor pattern portion CP1 of the third capacitor Cst3. The source electrode SE or drain electrode DE of the third driving transistor DT3 can be configured to extend from the second capacitor electrode CE2 disposed in the first capacitor pattern portion CP1 of the third capacitor Cst3. The third driving transistor DT3 can be electrically connected to the first electrode 120 of the third sub-pixel P3 through the third capacitor Cst3.

[0117] The fourth capacitor Cst4 can be positioned at the fourth corner V4 corresponding to each of the plurality of transmission regions TA, and can be formed symmetrically to the third capacitor Cst3. Specifically, the first capacitor pattern portion CP1 of the fourth capacitor Cst4 can be positioned between the first signal line SL1 and the transmission region TA at the first side of the first signal line SL1. The first capacitor pattern portion CP1 of the fourth capacitor Cst4 can be positioned outward from the fourth corner V4 of the transmission region TA toward the first corner V1. In this case, the first capacitor pattern portion CP1 of the fourth capacitor Cst4 can be configured to be symmetrical to the first capacitor pattern portion CP1 of the third capacitor Cst3 based on the first signal line SL1.

[0118] The second capacitor pattern portion CP2 of the fourth capacitor Cst4 can be disposed between the second signal line SL2 and the transmission region TA on the first side of the first signal line SL1. The second capacitor pattern portion CP2 of the fourth capacitor Cst4 can be bent at one end of the first capacitor pattern portion CP1 and can be disposed outside along the fourth corner V4 of the transmission region TA toward the third corner V3.

[0119] The fourth capacitor Cst4 can be connected to the first electrode 120 of the fourth sub-pixel P4 in the first capacitor pattern portion CP1.

[0120] Furthermore, the fourth driving transistor DT4 can be spaced apart from the second signal line SL2 in the first non-transmissive region NTA1, and the fourth capacitor Cst4 is inserted therebetween. The fourth driving transistor DT4 connected to the fourth sub-pixel P4 can overlap with the fourth sub-pixel P4.

[0121] The fourth driving transistor DT4 can be configured to be symmetrical to the third driving transistor DT3 based on the first signal line SL1, and can be connected to the other end of the first capacitor pattern portion CP1 of the fourth capacitor Cst4. The gate electrode GE of the fourth driving transistor DT4 can be configured to extend from the first capacitor electrode CE1 disposed in the first capacitor pattern portion CP1 of the fourth capacitor Cst4. The source electrode SE or drain electrode DE of the fourth driving transistor DT4 can be configured to extend from the second capacitor electrode CE2 disposed in the first capacitor pattern portion CP1 of the fourth capacitor Cst4. The fourth driving transistor DT4 can be electrically connected to the first electrode 120 of the fourth sub-pixel P4 through the fourth capacitor Cst4 and the contact electrode CT.

[0122] Return to reference Figure 7 A light-emitting diode including a first electrode 120, an organic light-emitting layer 130 and a second electrode 140, and a dam 125 are disposed above the planarization layer PLN.

[0123] The first electrode 120 can be disposed above the planarization layer PLN and connected to the driving transistor DT. The first electrode 120 can be provided for each of sub-pixels P1, P2, P3, and P4. One first electrode 120 can be disposed in the first sub-pixel P1, another first electrode 120 can be disposed in the second sub-pixel P2, another first electrode 120 can be disposed in the third sub-pixel P3, and another first electrode 120 can be disposed in the fourth sub-pixel P4. The first electrode 120 is not disposed in the transmission region TA.

[0124] The first electrode 120 can be formed of a highly reflective metallic material such as a deposition structure of aluminum and titanium (Ti / Al / Ti), a deposition structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, a deposition structure of Ag alloy and ITO (ITO / Ag alloy / ITO), a MoTi alloy, and a deposition structure of MoTi alloy and ITO (ITO / MoTi alloy / ITO). The Ag alloy can be an alloy of silver (Ag), palladium (Pb), and copper (Cu). The MoTi alloy can be an alloy of molybdenum (Mo) and titanium (Ti). The first electrode 120 can be an anode electrode.

[0125] The first electrode 120 included in each of the plurality of sub-pixels P1, P2, P3 and P4 may include a plurality of anode electrodes. For example, the first electrode 120 included in each of the plurality of sub-pixels P1, P2, P3 and P4 may include a first segmentation electrode 121, a second segmentation electrode 122 and a connection electrode ACE.

[0126] The first segmentation electrode 121 can be disposed in the first segmented light-emitting regions EA1-1, EA2-1, EA3-1 and EA4-1, and the second segmentation electrode 122 can be disposed in the second segmented light-emitting regions EA1-2, EA2-2, EA3-2 and EA4-2.

[0127] The first segmentation electrode 121 and the second segmentation electrode 122 can be spaced apart from each other in the same layer along a first direction or a second direction. Specifically, the first segmentation electrode 121 and the second segmentation electrode 122 respectively disposed in the first sub-pixel P1 and the third sub-pixel P3 can be spaced apart from each other along the second signal line SL2 in the second direction. The first segmentation electrode 121 and the second segmentation electrode 122 respectively disposed in the second sub-pixel P2 and the fourth sub-pixel P4 can be spaced apart from each other along the first signal line SL1 in the first direction.

[0128] The connecting electrode ACE can connect the first segmenting electrode 121 to the second segmenting electrode 122. The connecting electrode ACE may include a first connecting electrode ACE1 that connects the first segmenting electrode 121 and the second segmenting electrode 122 that are spaced apart from each other in a first direction, and a second connecting electrode ACE2 that connects the first segmenting electrode 121 and the second segmenting electrode 122 that are spaced apart from each other in a second direction.

[0129] like Figure 4 and Figure 5 As shown, the first connecting electrode ACE1 can extend from the first layer in a first direction to connect the first segmented electrode 121 and the second segmented electrode 122, which are spaced apart from each other in the first direction, to each other in a straight line (or substantially a straight line). Specifically, one end of the first connecting electrode ACE1 can be connected to the first segmented electrode 121 and its other end can be connected to the second segmented electrode 122 without protruding towards the transmission region TA. Furthermore, the boundary between the first connecting electrode ACE1 and the transmission region TA can form a straight line (or substantially a straight line) with the boundary between the first segmented electrode 121 and the transmission region TA, and the boundary between the second segmented electrode 122 and the transmission region TA.

[0130] The first connecting electrode ACE1 may include a first connecting portion ACE1-1 and a second connecting portion ACE1-2. The first connecting portion ACE1-1 may be connected to the first segmenting electrode 121 and extends a predetermined length from the first segmenting electrode 121 in the direction of the second segmenting electrode 122. The second connecting portion ACE1-2 may be connected to the second segmenting electrode 122 and extends a predetermined length from the second segmenting electrode 122 in the direction of the first segmenting electrode 121. The first connecting portion ACE1-1 and the second connecting portion ACE1-2 may be connected to each other in a straight line (or substantially a straight line). Therefore, the first segmenting electrode 121 can be electrically connected to the second segmenting electrode 122 through the first connecting electrode ACE1.

[0131] The first layer can be the same layer as the first segmenting electrode 121 and the second segmenting electrode 122. That is, the first connecting portion ACE1-1 and the second connecting portion ACE1-2 can be formed on the same layer as the first segmenting electrode 121 and the second segmenting electrode 122. Alternatively, the first connecting portion ACE1-1 and the second connecting portion ACE1-2 can be integrally formed with the first segmenting electrode 121 and the second segmenting electrode 122.

[0132] The first electrode 120 can be electrically connected to the second capacitor electrode CE2 of the capacitor Cst via the contact electrode CT. More specifically, a portion of the plurality of capacitors Cst1 may include a first portion of the first capacitor pattern portion CP1. In one embodiment, the first portion includes a retracted portion. Figure 5 and Figure 6 Examples of sample retraction portions CC1, CC2, and CC3 are shown. In another embodiment, the first portion includes a recessed portion. That is, the first portion can have various formations, and the recessed portion is an example shape of the first portion. For example, each of the second capacitor Cst2 connected to the second sub-pixel P2 and the fourth capacitor Cst4 connected to the fourth sub-pixel P4 may include a first recessed portion CC1 in the first capacitor pattern portion CP1, wherein the first recessed portion CC1 is formed in a recessed region in the direction from the transmission region TA toward the first signal line SL1. In this case, as Figure 4 and Figure 5 As shown, at least a portion of the first connecting electrode ACE1 may overlap with the recessed region of the first capacitor pattern portion CP1 of each of the second capacitor Cst2 and the fourth capacitor Cst4.

[0133] Furthermore, the contact electrode CT can protrude from the first recessed portion CC1 of the first capacitor pattern portion CP1 toward the transmission region TA, and a portion thereof can overlap with the first connecting electrode ACE1. At this time, the contact electrode CT can protrude from the second capacitor electrode CE2 disposed in the first capacitor pattern portion CP1.

[0134] The first connecting electrode ACE1 can be connected to the contact electrode CT through the first contact hole CH1 in the area overlapping with the contact electrode CT. Since the second capacitor electrode CE2 of the capacitor Cst is electrically connected to the source electrode SE or drain electrode DE of the driving transistor DT, the first electrode 120 can be electrically connected to the source electrode SE or drain electrode DE of the driving transistor DT through the first connecting electrode ACE1, the contact electrode CT, and the second capacitor electrode CE2 of the capacitor Cst.

[0135] As described above, in a transparent display panel 110 according to one embodiment of the present disclosure, a first cutting region C1 and a second cutting region C2 may be disposed in the first connecting electrode ACE1. In some embodiments, the first cutting region C1 may also be referred to as a first cutting line C1. Similarly, the second cutting region C2 may also be referred to as a second cutting line C2. This is due to the fact that one method of repairing defects in the display device is to apply laser cutting through the cutting line. The repair process will be described below.

[0136] Reference Figure 5 The first connecting electrode ACE1 may include a first cutting region C1 between the first contact hole CH1 and the first dividing electrode 121, and may include a second cutting region C2 between the first contact hole CH1 and the second dividing electrode 122.

[0137] In a transparent display panel 110 according to one embodiment of the present disclosure, when either the first segmented electrode 121 or the second segmented electrode 122, which are spaced apart from each other in a first direction, causes an operational error due to particles (e.g., external foreign particles, debris, etc.) that may appear during the manufacturing process (or any other process), the corresponding electrode can be repaired by laser cutting at least one of the first connecting portion ACE1-1 or the second connecting portion ACE1-2 of the first connecting electrode ACE1.

[0138] For example, in a transparent display panel 110 according to one embodiment of the present disclosure, when an error such as a short circuit occurs between the first electrode 120 and the second electrode 140 due to particles in the region where the first dividing electrode 121 is provided, the transparent display panel 110 can be repaired by laser cutting the first cutting area C1 of the first connecting portion ACE1-1.

[0139] In another example, in a transparent display panel 110 according to one embodiment of the present disclosure, when an error such as a short circuit occurs between the first electrode 120 and the second electrode 140 due to particles in the region where the second dividing electrode 122 is provided, the transparent display panel 110 can be repaired by laser cutting the second cutting area C2 of the second connecting portion ACE1-2.

[0140] The transparent display panel 110 according to one or more embodiments of this disclosure has the following technical advantages. One technical advantage is the ability to reduce the light loss rate caused by dark spots. For example, even if dark spots appear due to external particles, the problem can be repaired by laser cutting to short-circuit one of the corresponding segmented electrodes among the plurality of segmented electrodes (e.g., the first segmented electrode 121 and the second segmented electrode 122). That is, only the corresponding segmented electrodes among the plurality of segmented electrodes 121, 122 can be short-circuited by laser cutting.

[0141] Additionally, in a transparent display panel 110 according to one embodiment of the present disclosure, a third cutting region C3 may be provided in the contact electrode CT. Specifically, the contact electrode CT may include a third cutting region C3 between the first contact hole CH1 and the first capacitor pattern portion CP1.

[0142] In a transparent display panel 110 according to one embodiment of the present disclosure, when a specific sub-pixel malfunctions due to a driving transistor DT, the sub-pixel can be repaired by laser cutting the third cutting region C3 of the contact electrode CT.

[0143] like Figure 4 and Figure 6 As shown, the second connecting electrode ACE2 can extend from the second layer in a second direction to connect the first segmenting electrode 121 and the second segmenting electrode 122, which are spaced apart from each other in the second direction, to each other along a straight line (or substantially a straight line). Specifically, one end of the second connecting electrode ACE2 can be connected to the first segmenting electrode 121 and its other end can be connected to the second segmenting electrode 122 without protruding towards the transmission region TA. Furthermore, the boundary between the second connecting electrode ACE2 and the transmission region TA can form a straight line (or substantially a straight line) with the boundary between the first segmenting electrode 121 and the transmission region TA, and the boundary between the second segmenting electrode 122 and the transmission region TA.

[0144] The second layer can be a layer different from the first layer on which the first connecting electrode ACE1 is disposed. The second layer can be a layer disposed between the first layer and the first substrate 111.

[0145] In one embodiment, the second layer may be the same layer as at least one of the first capacitor electrode CE1 or the second capacitor electrode CE2 of the second capacitor pattern portion CP2. For example, the second layer may be the same layer as the second capacitor electrode CE2 of the second capacitor pattern portion CP2, but is not limited thereto. The second layer may be a double layer that is the same layer as each of the first capacitor electrode CE1 and the second capacitor electrode CE2 of the second capacitor pattern portion CP2. In this case, the second connecting electrode ACE2 may be integrally disposed with at least one of the first capacitor electrode CE1 or the second capacitor electrode CE2 of the second capacitor pattern portion CP2.

[0146] The second connecting electrode ACE2 can be connected via a contact hole to the first segmented electrode 121 and the second segmented electrode 122, which are spaced apart from each other in the second direction.

[0147] The second connecting electrode ACE2 can be connected to the first dividing electrode 121 at one end through the second contact hole CH2. The second connecting electrode ACE2 can extend a predetermined length from the first dividing electrode 121 toward the second dividing electrode 122 in a straight line (or substantially a straight line), and can be connected to the second dividing electrode 122 at the other end through the third contact hole CH3. Therefore, the first dividing electrode 121 can be electrically connected to the second dividing electrode 122 through the second connecting electrode ACE2.

[0148] Furthermore, the first electrode 120 can be electrically connected to the second capacitor electrode CE2 of the capacitor Cst via the second connecting electrode ACE2. Specifically, the second connecting electrode ACE2 can be integrally formed with the second capacitor electrode CE2 of the second capacitor pattern portion CP2. Therefore, the first electrode 120, including the first segmented electrode 121 and the second segmented electrode 122 connected to the second connecting electrode ACE2 via contact holes CH2 and CH3, can be electrically connected to the second capacitor electrode CE2 of the second capacitor pattern portion CP2. Since the second capacitor electrode CE2 of the capacitor Cst is electrically connected to the source electrode SE or drain electrode DE of the driving transistor DT, the first electrode 120 can be electrically connected to the source electrode SE or drain electrode DE of the driving transistor DT via the second capacitor electrode CE2 of the capacitor Cst and the second connecting electrode ACE2.

[0149] As described above, in a transparent display panel 110 according to one embodiment of the present disclosure, a fourth cutting region C4 and a fifth cutting region C5 may be provided in the first electrode 120. Specifically, the first dividing electrode 121 may include the fourth cutting region C4 between the second contact hole CH2 and the second signal line SL2. The first dividing electrode 121 disposed above the second capacitor pattern portion CP2 may include a second recessed portion CC2, which forms a recessed area in the direction from the transmission region TA toward the second signal line SL2 to expose a portion of the second connecting electrode ACE2. The first dividing electrode 121 can be connected to the second connecting electrode ACE2 via the second contact hole CH2 through the second recessed portion CC2 on one side of the recessed area. In this case, the fourth cutting region C4, whose width is reduced by the second recessed portion CC2, may be disposed between the area overlapping the second contact hole CH2 and the area overlapping the second signal line SL2.

[0150] The second segmented electrode 122 may include a fifth cut region C5 between the third contact hole CH3 and the second signal line SL2. The second segmented electrode 122, disposed above the second capacitor pattern portion CP2, may include a third recessed portion CC3, which forms a recessed area in the direction from the transmission region TA toward the second signal line SL2 to expose a portion of the second connecting electrode ACE2. The second segmented electrode 122 can be connected to the second connecting electrode ACE2 via the third contact hole CH3 and the third recessed portion CC3 on one side of the recessed area. In this case, a fifth cut region C5, with a width reduced by the third recessed portion CC3, can be provided between the area overlapping with the third contact hole CH3 and the area overlapping with the second signal line SL2.

[0151] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, a sixth cutting region C6 and a seventh cutting region C7 may be provided in the second connecting electrode ACE2. Specifically, the second connecting electrode ACE2 may include the sixth cutting region C6 exposed by the second recessed portion CC2 of the first dividing electrode 121 and the seventh cutting region C7 exposed by the third recessed portion CC3 of the second dividing electrode 122.

[0152] In a transparent display panel 110 according to one embodiment of the present disclosure, when either the first dividing electrode 121 or the second dividing electrode 122, which are spaced apart from each other in a second direction, malfunctions due to particles that may appear during the process, the corresponding electrode can be repaired by laser cutting at least a portion of the second connecting electrode ACE2, the first dividing electrode 121, or the second dividing electrode 122.

[0153] For example, in a transparent display panel 110 according to one embodiment of the present disclosure, when a short circuit occurs between the first electrode 120 and the second electrode 140 due to particles in the region where the first dividing electrode 121 is disposed, the transparent display panel 110 can be repaired by laser cutting the fourth cutting region C4 of the first dividing electrode 121 or the sixth cutting region C6 of the second connecting electrode ACE2.

[0154] In another example, in a transparent display panel 110 according to one embodiment of the present disclosure, when a short circuit occurs between the first electrode 120 and the second electrode 140 due to particles in the region where the second dividing electrode 122 is disposed, the transparent display panel 110 can be repaired by laser cutting the fifth cutting region C5 of the second dividing electrode 122.

[0155] In a transparent display panel 110 according to one embodiment of the present disclosure, even if dark spots appear due to particles, laser cutting can be used to short-circuit only the corresponding dividing electrodes among the plurality of dividing electrodes 121 and 122, thereby reducing the light loss rate due to the appearance of dark spots.

[0156] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, when a specific sub-pixel malfunctions due to a driving transistor DT, the sub-pixel can be repaired by laser cutting the seventh cutting region C7 of the second connecting electrode ACE2.

[0157] A dam 125 may be disposed above the planarization layer PLN. Furthermore, dams 125 may be provided between the first electrodes 120. The dams 125 may be configured to cover or at least partially cover the edges of each first electrode 120 and expose a portion of each first electrode 120. Therefore, the dams 125 can prevent degradation of luminous efficiency due to current concentrated at each end of the first electrode 120.

[0158] The embankment 125 can define the light-emitting regions EA1-1, EA1-2, EA2-1, EA2-2, EA3-1, EA3-2, EA4-1, and EA4-2 for each of the sub-pixels P1, P2, P3, and P4. The light-emitting regions EA1-1, EA1-2, EA2-1, EA2-2, EA3-1, EA3-2, EA4-1, and EA4-2 for each of the sub-pixels P1, P2, P3, and P4 refer to the regions in which a first electrode 120, an organic light-emitting layer 130, and a second electrode 140 are sequentially deposited such that holes from the anode electrode 120 and electrons from the second electrode 140 recombine with each other in the organic light-emitting layer 130 to emit light. In this case, since the area where the dam 125 is formed does not emit light, the area can be a non-luminescent area, and the area where the dam 125 is not formed and the first electrode 120 is exposed can be luminescent areas EA1-1, EA1-2, EA2-1, EA2-2, EA3-1, EA3-2, EA4-1 and EA4-2.

[0159] The embankment 125 may be formed of an organic layer (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.).

[0160] An organic light-emitting layer 130 may be disposed above the first electrode 120. The organic light-emitting layer 130 may include a hole transport layer, a light-emitting layer, and an electron transport layer. In this case, if a voltage is applied to the first electrode 120 and the second electrode 140, holes and electrons move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and recombine with each other in the light-emitting layer to emit light.

[0161] In one embodiment, the organic light-emitting layer 130 may be a common layer shared by sub-pixels P1, P2, P3, and P4. For example, the organic light-emitting layer 130 may be a white light-emitting layer that emits white light.

[0162] In another embodiment, the organic light-emitting layer 130 may include light-emitting layers disposed for each sub-pixel P1, P2, P3, and P4. For example, a green light-emitting layer emitting green light may be disposed in the first sub-pixel P1, a red light-emitting layer emitting red light may be disposed in the second sub-pixel P2, a white light-emitting layer emitting white light may be disposed in the third sub-pixel P3, and a blue light-emitting layer emitting blue light may be disposed in the fourth sub-pixel P4. In this case, the light-emitting layers of the organic light-emitting layer 130 are not disposed in the transmission region TA.

[0163] The second electrode 140 may be disposed above the organic light-emitting layer 130 and the embankment 125. The second electrode 140 may be disposed in the transmissive region TA and the non-transmissive region NTA including the light-emitting region EA, but is not limited thereto. The second electrode 140 may be disposed only in the non-transmissive region NTA including the light-emitting region EA, but may not be disposed in the transmissive region TA to improve transmittance.

[0164] The second electrode 140 may be a common layer disposed in sub-pixels P1, P2, P3, and P4 to apply the same voltage. The second electrode 140 may be formed of a conductive material that can transmit light. For example, the second electrode 140 may be formed of a low-resistance metallic material (e.g., Ag or an alloy of Mg and Ag). The second electrode 140 may be a cathode electrode.

[0165] An encapsulation layer 150 may be disposed above the light-emitting diode. The encapsulation layer 150 may be disposed above the second electrode 140 to cover the second electrode 140. The encapsulation layer 150 is used to prevent oxygen or moisture from penetrating into the organic light-emitting layer 130 and the second electrode 140. For this purpose, the encapsulation layer 150 may include at least one inorganic layer and at least one organic layer.

[0166] Furthermore, despite Figure 5 and Figure 6 It is not shown in the figure, but a capping layer may be additionally provided between the second electrode 140 and the encapsulation layer 150.

[0167] The color filter CF can be disposed above the encapsulation layer 150. The color filter CF can be disposed above a surface of the second substrate 112 facing the first substrate 111. In this case, the first substrate 111 with the encapsulation layer 150 and the second substrate 112 with the color filter CF can be bonded to each other by the adhesive layer 160. At this time, the adhesive layer 160 can be an optically clear resin (OCR) layer or an optically clear adhesive (OCA) film.

[0168] The color filter CF can be configured to pattern each of sub-pixels P1, P2, P3, and P4. Specifically, the color filter CF can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 can be configured to correspond to the light-emitting area EA1 of the first sub-pixel P1, and can be a green filter that transmits green light. The second color filter CF2 can be configured to correspond to the light-emitting area EA2 of the second sub-pixel P2, and can be a red filter that transmits red light. The third color filter CF3 can be configured to correspond to the light-emitting area EA4 of the fourth sub-pixel P4, and can be a blue filter that transmits blue light.

[0169] The color filter CF may also include a fourth color filter, which is configured to correspond to the light-emitting region EA3 of the third sub-pixel P3. In this case, the fourth color filter may be made of a transparent organic material that transmits white light.

[0170] Furthermore, a black matrix BM can be set between color filters (CF) and between the color filters (CF) and the transmission region (TA). Specifically, the black matrix BM can be set between sub-pixels P1, P2, P3, and P4 to prevent color mixing between adjacent sub-pixels P1, P2, P3, and P4. For this purpose, a black matrix BM can be set between the color filters (CF). For example... Figure 8 As shown, the black matrix BM can be positioned between the second color filter of the second sub-pixel P2 and the third color filter of the fourth sub-pixel P4, which are alternately arranged along the first signal line SL1. The black matrix BM can also be positioned between the first color filter of the first sub-pixel P1 and the fourth color filter of the third sub-pixel P3, which are alternately arranged along the second signal line SL2.

[0171] Furthermore, the black matrix BM can be positioned between sub-pixels P1, P2, P3, and P4 and the transmission region TA to prevent light emitted from each of the sub-pixels P1, P2, P3, and P4 from appearing as a different color depending on the viewing angle. For example, light emitted from a green sub-pixel can be perceived as white light on one side.

[0172] In a transparent display panel 110 according to one embodiment of the present disclosure, a black matrix BM can be disposed between sub-pixels P1, P2, P3, and P4 and the transmissive region TA, such that light emitted from sub-pixels P1, P2, P3, and P4 does not move to one side (e.g., the transmissive region TA). However, when the black matrix BM is disposed between sub-pixels P1, P2, P3, and P4 and the transmissive region TA, the size of the transmissive region TA decreases, thereby potentially reducing light transmittance. In a transparent display panel 110 according to one embodiment of the present disclosure, as... Figure 6 As shown, the black matrix BM can be omitted between the third sub-pixel P3 (specifically, the white sub-pixel) and the transmission area TA, thereby reducing or minimizing the transmittance loss caused by the black matrix BM.

[0173] Black matrix (BM) can include light-absorbing materials, such as black dyes that completely absorb the wavelength range of visible light.

[0174] In a transparent display panel 110 according to one embodiment of the present disclosure, the first connecting electrode ACE1 and the second connecting electrode ACE2 connecting the two dividing electrodes 121 and 122 do not protrude toward the transmission region TA, thereby preventing the size of the transmission region TA from being reduced due to the first connecting electrode ACE1 and the second connecting electrode ACE2. In other words, the transparent display panel 110 according to one embodiment of the present disclosure can prevent the light transmittance from being reduced by the first connecting electrode ACE1 and the second connecting electrode ACE2.

[0175] Furthermore, in the transparent display panel 110 according to one embodiment of the present disclosure, the first connecting electrode ACE1 and the second connecting electrode ACE2 are formed as straight lines (or substantially straight lines), thereby the boundary of the transmission region TA may not have an uneven shape. Therefore, in the transparent display panel 110 according to one embodiment of the present disclosure, haze can be reduced and image readability can be improved.

[0176] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, a recessed region may be provided in a first capacitor pattern portion CP1, which is a portion of a plurality of capacitors Cst, and a first connecting electrode ACE1 may be provided in the recessed region of the first capacitor pattern portion CP1. In the transparent display panel 110 according to one embodiment of the present disclosure, because a recessed region is provided in the first capacitor pattern portion CP1, the size of the first capacitor pattern portion CP1 may be reduced, thereby potentially reducing the capacitor capacity. However, the transparent display panel 110 according to one embodiment of the present disclosure includes a second capacitor pattern portion CP2 extending from one end of the first capacitor pattern portion CP1 in a second direction, thereby ensuring that the total area of ​​the capacitors Cst is not reduced.

[0177] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, a second capacitor pattern portion CP2, which is a part of a plurality of capacitors Cst, can be used as a second connecting electrode ACE2. Therefore, in a transparent display panel 110 according to one embodiment of the present disclosure, since it is not necessary to ensure separate space for the second connecting electrode ACE2, the size of the second capacitor pattern portion CP2 does not need to be reduced.

[0178] As a result, the transparent display panel 110 according to one embodiment of the present disclosure can sufficiently ensure the capacitance of the capacitor Cst, while having high light transmittance through the first connecting electrode ACE1 and the second connecting electrode ACE2, which are set as straight lines (or substantially straight lines).

[0179] In a transparent display panel 110 according to one embodiment of the present disclosure, the first to fourth driving transistors DT1, DT2, DT3, and DT4 can be configured to be symmetrical to each other. Specifically, the first driving transistor DT1 of the first sub-pixel P1 can be symmetrical to the second driving transistor DT2 of the second sub-pixel P2 based on a first axis (e.g., the X-axis). The third driving transistor DT3 of the third sub-pixel P3 can be symmetrical to the fourth driving transistor DT4 of the fourth sub-pixel P4 based on a first axis (e.g., the X-axis). The first driving transistor DT1 of the first sub-pixel P1 and the second driving transistor DT2 of the second sub-pixel P2 can be symmetrical based on a second axis (e.g., the Y-axis), while the third driving transistor DT3 of the third sub-pixel P3 and the fourth driving transistor DT4 of the fourth sub-pixel P4 are symmetrical.

[0180] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, the first to fourth capacitors Cst1, Cst2, Cst3, and Cst4 can be configured to be mutually symmetrical. Specifically, the first capacitor Cst1 of the first sub-pixel P1 can be symmetrical with the second capacitor Cst2 of the second sub-pixel P2 based on a first axis (e.g., the X-axis). The third capacitor Cst3 of the third sub-pixel P3 can be symmetrical with the fourth capacitor Cst4 of the fourth sub-pixel P4 based on a first axis (e.g., the X-axis). The first capacitor Cst1 of the first sub-pixel P1 and the second capacitor Cst2 of the second sub-pixel P2 can be symmetrical with the third capacitor Cst3 of the third sub-pixel P3 and the fourth capacitor Cst4 of the fourth sub-pixel P4 based on a second axis (e.g., the Y-axis).

[0181] In the transparent display panel 110 according to an exemplary embodiment of the present disclosure, the first capacitor pattern portion CP1 of the driving transistor DT and capacitor Cst of each of the first to fourth sub-pixels P1, P2, P3 and P4 can be disposed between the overlapping areas of the first non-transparent region NTA1 and the second non-transparent region NTA2 in the first non-transparent region NTA1. That is, in the transparent display panel 110 according to one embodiment of the present disclosure, the driving transistor DT is not disposed in the second non-transparent region NTA2. Therefore, in the transparent display panel 110 according to one embodiment of the present disclosure, the driving transistor DT is spaced apart from the second signal line SL2 (specifically, the pixel power line VDDL and the common power line VSSL), thereby preventing parasitic capacitance or reducing or minimizing the parasitic capacitance between the driving transistor DT and the second signal line SL2.

[0182] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, the second capacitor pattern portion CP2 of the capacitor Cst can be disposed in the second non-transmissive region NTA2, but can be thinner than the first capacitor pattern portion CP1. Therefore, the transparent display panel 110 according to one embodiment of the present disclosure can reduce or minimize the width of the second non-transmissive region NTA2 and improve light transmittance.

[0183] Furthermore, in the transparent display panel 110 according to one embodiment of the present disclosure, the capacitor Cst has an L-shape. Therefore, even if the driving transistor DT of each of the first to fourth sub-pixels P1, P2, P3 and P4 is disposed in the first non-transmissive region NTA1, the driving transistor DT can be connected to the first electrode 120 of the sub-pixels P1 and P3 disposed in the second non-transmissive region NTA2.

[0184] Specifically, in a transparent display panel 110 according to one embodiment of the present disclosure, a first capacitor pattern portion CP1 and a second capacitor pattern portion CP2 of capacitor Cst are disposed along the outside of the transmissive region TA, thereby increasing the design freedom of the contact electrode CT for connection to the first electrode 120 of each of the first sub-pixels P1, P2, P3 and P4.

[0185] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, the capacitor Cst does not overlap with the first signal line SL1 and the second signal line SL2. Specifically, in a transparent display panel 110 according to one embodiment of the present disclosure, the capacitor Cst is not disposed between multiple signal lines included in the second signal line SL2, thereby reducing or minimizing parasitic capacitance caused by the signal lines.

[0186] Furthermore, in a transparent display panel 110 according to one embodiment of the present disclosure, four driving transistors DT1, DT2, DT3, and DT4 can be arranged together. Specifically, the driving transistors DT1 and DT2 for the first sub-pixel P1 and the second sub-pixel P2 of a pixel P, and the driving transistors DT3 and DT4 for the third sub-pixel P3 and the fourth sub-pixel P4 of another pixel P adjacent to a pixel P along a first direction, can be arranged together. In this case, since the spacing between the four driving transistors DT1, DT2, DT3, and DT4 is small, the pixel power lines VDDL for providing a first power supply to each of the four driving transistors DT1, DT2, DT3, and DT4 can be interconnected to form a grid structure.

[0187] In the following text, reference will be made to Figure 9 and Figure 10 Detailed description of the pixel power line VDDL with a grid structure.

[0188] Figure 9 This is a diagram illustrating an example of pixel power lines with a grid structure, and Figure 10 It is along Figure 9 The cross-sectional view taken from line II-II'.

[0189] Reference Figure 9 and Figure 10 The pixel power line VDDL can include the main pixel power line MVDDL and the branch pixel power line BVDDL.

[0190] The main pixel power line MVDDL can extend from the second non-transmissive region NTA2 in a second direction. The main pixel power line MVDDL can be formed as a double layer to ensure a wide area. For example, the main pixel power line VDDL can include a first pixel power line VDDL-1 and a second pixel power line VDDL-2 disposed above the first pixel power line VDDL-1, such as... Figure 10 As shown. For example, the first pixel power line VDDL-1 can be formed on the same layer as the light-shielding layer LS, and the second pixel power line VDDL-2 can be formed on the same layer as the source electrode SE or the drain electrode DE. The first pixel power line VDDL-1 and the second pixel power line VDDL-2 can be electrically connected to each other through multiple contact holes.

[0191] The branch pixel power line BVDDL can branch from the main pixel power line MVDDL and extend from the first non-transmissive region NTA1 in a first direction. At this time, the branch pixel power line BVDDL can connect the main pixel power lines MVDDL that are adjacent to each other in the first direction.

[0192] The branch pixel power line BVDDL may include multiple lines that connect adjacent main pixel power lines MVDDL in a first direction. Specifically, the branch pixel power line BVDDL may include a first branch pixel power line BVDDL1, a second branch pixel power line BVDDL2, and a third branch pixel power line BVDDL3.

[0193] The first branch pixel power line BVDDL1 can be disposed in the region where the first non-transparent region NTA1 and the second non-transparent region NTA2 overlap, and can extend in a first direction to partially overlap with the main pixel power line MVDDL. The first branch pixel power line BVDDL1 can be connected to the main pixel power line MVDDL through the fifth contact hole CH5. For example, the first branch pixel power line BVDDL1 can be formed on the same layer as the source electrode SE or the drain electrode DE, and the second pixel power line VDDL-2 can form an opening region in the region where the first non-transparent region NTA1 and the second non-transparent region NTA2 overlap. In this case, the first branch pixel power line BVDDL1 can be connected to the first pixel power line VDDL-1 of the main pixel power line MVDDL disposed on the same layer as the light-shielding layer LS through the fifth contact hole CH5.

[0194] The second branch pixel power line BVDDL2 and the third branch pixel power line BVDDL3 can connect the first branch pixel power lines BVDDL1 that are adjacent to each other in the first direction.

[0195] The second branch pixel power line BVDDL2 can be disposed above one or more layers to connect with the first branch pixel power line BVDDL1, and can have a structure that connects to the first branch pixel power line BVDDL1 through a contact hole. For example, the second branch pixel power line BVDDL2 can include a first line BVDDL2-1 disposed on the same layer as the light-shielding layer LS in the region where it intersects with the scan line SCANL, and a second line BVDDL2-2 disposed on the same layer as the source electrode SE or the drain electrode DE and extending parallel to the scan line SCANL. The first line BVDDL2-1 can be connected to the first branch pixel power line BVDDL1 at one end through a sixth contact hole CH6, and can be connected to the second line BVDDL2-2 at the other end through a seventh contact hole CH7. In this case, the second line BVDDL2-2 can be disposed on the first side of the scan line SCANL, and can be connected to the active layer ACT of the driving transistor DT disposed on the first side of the scan line SCANL through the seventh contact hole CH7. The second line BVDDL2-2 can transmit the first power supplied from the main pixel power line MVDDL to the drive transistor DT located on the first side of the scan line SCANL.

[0196] The third branch pixel power line BVDDL3 can also be disposed above one or more layers to connect with the first branch pixel power line BVDDL1, and can have a structure that connects to the first branch pixel power line BVDDL1 through a contact hole. For example, the third branch pixel power line BVDDL3 may include a first line disposed on the same layer as the light-shielding layer LS in the region where it intersects with the scan line SCANL, and a second line disposed on the same layer as the source electrode SE or drain electrode DE and extending parallel to the scan line SCANL. The first line can be connected to the first branch pixel power line BVDDL1 at one end through the sixth contact hole CH6, and to the second line at the other end through the eighth contact hole CH8. In this case, the second line can be disposed on the second side of the scan line SCANL, and can transmit the first power supplied from the main pixel power line MVDDL to the driving transistor DT disposed on the second side of the scan line SCANL.

[0197] In a transparent display panel 110 according to one embodiment of the present disclosure, the pixel power lines VDDL may include main pixel power lines MVDDL extending from a second non-transparent region NTA2 along a second direction and branch pixel power lines BVDDL extending from a first non-transparent region NTA1 in a first direction to connect adjacent main pixel power lines MVDDL in the first direction. That is, in the transparent display panel 110 according to one embodiment of the present disclosure, the pixel power lines VDDL may have a grid structure, allowing the voltage of the pixel power lines VDDL to be uniformly distributed, thereby improving the brightness uniformity of sub-pixels P1, P2, P3, and P4. Furthermore, in the transparent display panel 110 according to one embodiment of the present disclosure, the size of the pixel power lines VDDL may be increased to reduce resistance, thereby reducing voltage drop.

[0198] The following advantages can be obtained from this disclosure.

[0199] In this disclosure, since the connecting electrode used to connect the two segmented electrodes does not protrude towards the transmission region, the size of the transmission region is not reduced by the connecting electrode. In other words, in this disclosure, a decrease in light transmittance due to the connecting electrode can be prevented.

[0200] Furthermore, since the connecting electrodes are formed in a straight line (or substantially a straight line), the boundary of the transmission region does not need to have an uneven shape. Therefore, in this disclosure, haze can be reduced and image readability can be improved.

[0201] Furthermore, in this disclosure, the circuit region of the sub-pixel is not disposed between multiple signal lines, thereby reducing or minimizing parasitic capacitance caused by the signal lines and reducing the size of the non-transmissive region. Specifically, in this disclosure, all driving transistors of the sub-pixel are disposed in a first non-transmissive region with fewer signal lines rather than in a second non-transmissive region with more signal lines, thereby reducing the size of the second non-transmissive region.

[0202] Furthermore, in this disclosure, since the capacitor of the sub-pixel can be formed in an L-shape, even if all the driving transistors of the sub-pixel are disposed in the first non-transmissive region, the connection between the driving transistor of the sub-pixel disposed in the second non-transmissive region and the first electrode can be realized.

[0203] Furthermore, the capacitor is formed in an L-shape along the outside of the transmission region, which increases the design freedom of the contact electrode used to contact each sub-pixel.

[0204] Furthermore, the width of the second capacitor pattern portion disposed in the second non-transmissive region is thinner than the width of the first capacitor pattern portion disposed in the first non-transmissive region, thereby reducing or minimizing the width difference between the first and second non-transmissive regions. Therefore, in this disclosure, the sub-pixels disposed in the first and second non-transmissive regions can have similar light-emitting areas, and the transmissive region can be formed into a square shape. According to this disclosure, since the transmissive region is formed into a square shape, the area used to form the black matrix can be reduced or minimized, and the light transmittance can be improved. Additionally, in this disclosure, diffraction of light passing through the transmissive region can be prevented, and the clarity of image quality can be improved.

[0205] It will be apparent to those skilled in the art that this disclosure is not limited to the above-described embodiments and drawings, and that various substitutions, modifications, and variations can be made to this disclosure without departing from its spirit or scope. Therefore, the scope of protection of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this disclosure.

Claims

1. A transparent display device, the transparent display device comprising: A substrate, the substrate including a transmissive region and a plurality of sub-pixels disposed between the transmissive region; A first electrode is disposed in each of the plurality of sub-pixels, the first electrode comprising a first segmenting electrode and a second segmenting electrode spaced apart from each other. A connecting electrode is provided, which connects the first segmenting electrode and the second segmenting electrode along a straight line; An organic light-emitting layer is disposed above the first electrode; as well as The second electrode is disposed above the organic light-emitting layer. The boundary between the connecting electrode and the transmission region forms a straight line with the boundary between the first dividing electrode and the transmission region, and the boundary between the second dividing electrode and the transmission region.

2. The transparent display device according to claim 1, further comprising: A first signal line extends along a first direction between the transmission regions; A second signal line extends along a second direction between the transmission regions; as well as The capacitor includes a first capacitor pattern portion disposed longitudinally along the first direction between the first signal line and the transmission region, and a second capacitor pattern portion extending from one end of the first capacitor pattern portion and disposed longitudinally along the second direction between the second signal line and the transmission region.

3. The transparent display device according to claim 2, wherein, At least one first dividing electrode and at least one second dividing electrode of the plurality of sub-pixels are configured to be spaced apart from each other in the first direction on the first capacitor pattern portion and the first signal line, and The connection electrode includes a first connection electrode that extends from the first layer along the first direction to connect the first segment electrode and the second segment electrode, which are spaced apart from each other in the first direction, to each other.

4. The transparent display device according to claim 3, wherein, The first layer is the same layer as the first segmented electrode and the second segmented electrode.

5. The transparent display device according to claim 3, wherein, The first capacitor pattern portion includes a first recessed portion forming a recessed region in a direction from the transmission region toward the first signal line, and at least a portion of the first connecting electrode overlaps with the recessed region of the first capacitor pattern portion.

6. The transparent display device according to claim 5, further comprising a contact electrode protruding from the first recessed portion of the first capacitor pattern portion toward the transmissive region to at least partially overlap with the first connecting electrode. in, The contact electrode is connected to the first connecting electrode through the first contact hole.

7. The transparent display device according to claim 6, wherein, The first connecting electrode includes a first cutting region disposed between the first contact hole and the first dividing electrode, and a second cutting region disposed between the first contact hole and the second dividing electrode. The contact electrode includes a third cut region disposed between the first contact hole and the first capacitor pattern portion.

8. The transparent display device according to claim 6, wherein, The first capacitor pattern portion includes a first capacitor electrode and a second capacitor electrode disposed above the first capacitor electrode, and The contact electrode extends from the second capacitor electrode of the first capacitor pattern portion.

9. The transparent display device according to claim 2, wherein, The second signal line includes multiple signal lines, and The second capacitor pattern portion of the capacitor is disposed between the outermost signal line and the transmission area among the plurality of signal lines.

10. The transparent display device according to claim 2, wherein, The first and second dividing electrodes disposed in at least one sub-pixel of the plurality of sub-pixels are spaced apart from each other in the second direction on the second capacitor pattern portion and the second signal line, and The connecting electrode includes a second connecting electrode that extends from the second layer along the second direction to connect the first segmented electrode and the second segmented electrode, which are spaced apart from each other in the second direction, to each other.

11. The transparent display device according to claim 10, wherein, The second capacitor pattern portion includes a first capacitor electrode and a second capacitor electrode disposed above the first capacitor electrode, and The second layer is the same layer as the second capacitor electrode.

12. The transparent display device according to claim 11, wherein, The second connecting electrode and the second capacitor electrode of the second capacitor pattern portion are integrated.

13. The transparent display device according to claim 10, wherein, The second connecting electrode is connected to the first dividing electrode through the second contact hole, and to the second dividing electrode through the third contact hole.

14. The transparent display device according to claim 13, wherein, The first dividing electrode includes a fourth cutting region disposed between the second contact hole and the second signal line, or the second dividing electrode includes a fifth cutting region disposed between the third contact hole and the second signal line.

15. The transparent display device according to claim 10, wherein, The first segmented electrode disposed above the second capacitor pattern portion includes a second recessed portion, the second recessed portion forming a recessed area in the direction from the transmission region toward the second signal line to expose a portion of the second connection electrode, and The second segmented electrode, disposed above the second capacitor pattern portion, includes a third recessed portion that forms a recessed area in the direction from the transmission region toward the second signal line to expose a portion of the second connection electrode.

16. The transparent display device according to claim 15, wherein, The second connection electrode includes a sixth cutting region exposed by the second recessed portion and a seventh cutting region exposed by the third recessed portion.

17. A transparent display device, the transparent display device comprising: A substrate having a transmissive region and a non-transmissive region disposed between the transmissive region; A first signal line extends from the non-transmissive region along a first direction; A second signal line extends from the non-transmissive region along a second direction; A first sub-pixel, wherein the first sub-pixel overlaps with at least a portion of the second signal line in the non-transmissive region; The second sub-pixel overlaps with at least a portion of the first signal line in the non-transmissive region; A first electrode is disposed in each of the first sub-pixel and the second sub-pixel, the first electrode comprising a first segmented electrode and a second segmented electrode spaced apart from each other; A first connecting electrode is disposed in a first layer to connect the first segmenting electrode and the second segmenting electrode disposed in the second sub-pixel to each other. as well as A second connecting electrode is disposed in the second layer to connect the first segmentation electrode and the second segmentation electrode disposed in the first sub-pixel to each other. Wherein, the boundary between the first connecting electrode and the transmission region forms a straight line with the boundary between the first segmenting electrode and the transmission region of the second sub-pixel, and the boundary between the second segmenting electrode and the transmission region of the second sub-pixel. Wherein, the boundary between the second connecting electrode and the transmission region forms a straight line with the boundary between the first segmenting electrode and the transmission region of the first sub-pixel and the boundary between the second segmenting electrode and the transmission region of the first sub-pixel.

18. The transparent display device according to claim 17, wherein, The first segmentation electrode and the second segmentation electrode in the first sub-pixel are configured to be spaced apart from each other on the second signal line in the second direction, and the first segmentation electrode and the second segmentation electrode in the second sub-pixel are configured to be spaced apart from each other on the first signal line in the first direction.

19. The transparent display device according to claim 17, wherein, The first layer is the same layer as the first dividing electrode and the second dividing electrode, and the second layer is a layer disposed between the first dividing electrode and the second dividing electrode and the substrate.

20. The transparent display device according to claim 17, further comprising a capacitor, the capacitor including a first capacitor pattern portion disposed longitudinally along the first direction between the first signal line and the transmissive region and a second capacitor pattern portion disposed longitudinally along the second direction between the second signal line and the transmissive region.

21. The transparent display device according to claim 20, wherein, The capacitor includes: A first capacitor, the first capacitor having a first capacitor pattern portion disposed on a first side of the first signal line between the first signal line and the transmission region, the first capacitor being connected to the first sub-pixel; and The second capacitor is disposed on the second side of the first signal line, and is symmetrically arranged between the first signal line and the first capacitor and connected to the second sub-pixel.

22. The transparent display device according to claim 20, wherein, The first capacitor pattern portion of the capacitor connected to the second sub-pixel includes a first recessed portion forming a recessed region in a direction from the transmission region toward the first signal line, and at least a portion of the first connecting electrode overlaps with the recessed region of the first capacitor pattern portion.

23. The transparent display device of claim 22, further comprising a contact electrode protruding from the first recessed portion of the first capacitor pattern portion toward the transmissive region to at least partially overlap with the first connecting electrode. in, The contact electrode is connected to the first connecting electrode through the first contact hole.

24. The transparent display device according to claim 23, wherein, The first connecting electrode includes a first cutting region disposed between the first contact hole and the first dividing electrode, and a second cutting region disposed between the first contact hole and the second dividing electrode. The contact electrode includes a third cut region disposed between the first contact hole and the first capacitor pattern portion.

25. The transparent display device according to claim 20, wherein, The second connecting electrode and the second capacitor pattern portion of the capacitor connected to the first sub-pixel are integrated.

26. The transparent display device according to claim 17, wherein, The second connecting electrode is connected to the first dividing electrode through the second contact hole, and to the second dividing electrode through the third contact hole.

27. The transparent display device according to claim 17, wherein, The first segmentation electrode of the first sub-pixel includes a second recessed portion, the second recessed portion forming a recessed region in the direction from the transmission region toward the second signal line to expose a portion of the second connection electrode, and The second segmentation electrode of the first sub-pixel includes a third recessed portion, which forms a recessed region in the direction from the transmission region toward the second signal line to expose a portion of the second connection electrode.

28. The transparent display device according to claim 27, wherein, The second connection electrode includes a sixth cutting region exposed by the second recessed portion and a seventh cutting region exposed by the third recessed portion.

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