A direct-current stabilized power supply circuit of a switching power supply driving chip

Abstract

The application provides a DC voltage stabilizing power supply circuit of a switching power supply driving chip, which comprises a charging control circuit, a detection control circuit and a digital logic circuit, a high-voltage DC power supply is connected with the charging control circuit, the output end of the charging control circuit is connected with the detection control circuit, the output end of the detection control circuit is connected with the digital logic circuit, and the output end of the digital logic circuit is connected with the charging control circuit; a junction field effect transistor is used for reducing voltage and controlling the working or non-working of the charging control circuit, the output end of the junction field effect transistor is connected with a resistor R5 and a MOS transistor M3, the MOS transistor M3 is connected with a MOS transistor M2 and a capacitor C, the output signal Y of the digital logic circuit controls the on-off of the MOS transistor M2, thereby controlling the on-off of the M3, the charging of the capacitor C is controlled through the MOS transistor M3, the detection control circuit is used for voltage detection and controlling the charging and discharging of the capacitor C, so that the capacitor C outputs a stable voltage VCC as the DC voltage stabilizing power supply of the driving chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more particularly to a DC regulated power supply circuit for a switching power supply driver chip. Background Art

[0002] The driver chip of the switching power supply usually contains a high-voltage circuit module and a low-voltage circuit module, wherein the low-voltage circuit module requires a low-voltage power supply. For example, the flyback AC / DC switching power supply topology circuit, such as Figure 1 As shown, the flyback AC / DC switching power supply system converts 220V AC mains V AC Converted to 5V or other stable DC voltage V required by the load O The driving control circuit in the driver chip operates in a low-voltage state, so a DC regulated power supply is required in the chip. The DC regulated power supply determines the working performance of the driver chip and even the switching power supply, and also directly affects the cost of the driver chip and the switching power supply.

[0003] There are two common design approaches for the DC regulated power supply circuit of a switching power supply driver chip: high-voltage LDO power supply and auxiliary winding power supply. The high-voltage LDO power supply first steps down the input high voltage. The resulting voltage serves as the power supply voltage for the high-voltage LDO, and the high-voltage LDO output voltage becomes the DC voltage that powers the low-voltage circuit module. High-voltage LDOs offer excellent load and line regulation, and their output voltage is stable. However, high-voltage LDOs require several high-voltage components, such as high-voltage MOSFETs and resistors. These components typically occupy a large chip area and consume significant power during operation. The auxiliary winding power supply method adds an additional winding to the transformer. The auxiliary winding operates at a fixed voltage through the transformer, which is then connected to and charged by a bypass capacitor. An internal voltage regulator on the chip stabilizes the voltage on the bypass capacitor, which then powers the low-voltage module. Using an auxiliary winding power supply reduces the number of high-voltage components on the chip, but increases the cost of the peripheral circuitry.

[0004] In view of this, the present application provides a DC regulated power supply circuit for a switching power supply driver chip. The DC regulated power supply circuit is applied to the driver chip of the switching power supply. The DC regulated power supply circuit only uses a small number of high-voltage devices to reduce the area and power consumption of the driver chip. Summary of the Invention

[0005] The object of the present invention is to provide a DC regulated power supply circuit for a switching power supply driver chip. The DC regulated power supply circuit is applied to the driver chip of the switching power supply. The DC regulated power supply circuit only uses a small number of high-voltage devices, reducing the area and power consumption of the driver chip.

[0006] The application discloses a direct-current stabilized power supply circuit of a switching power supply driving chip, and relates to the technical field of switching power supply driving chips.

[0007] In some embodiments, the gate of the junction field effect transistor JFET is grounded, the drain is connected with the drain of the power tube M1, the source is connected with one end of the resistor R5 and the drain of the NMOS tube M3, the other end of the resistor R5 is connected with the gate of the NMOS tube M3 and the drain of the NMOS tube M2, the source of the NMOS tube M3 is connected with one end of the capacitor C, and a wire outputting a stable voltage VCC of the capacitor C is connected with the source of the NMOS tube M3 and the wire between the capacitor C, the other end of the capacitor C is connected with the source of the NMOS tube M2 and then grounded, and the gate of the NMOS tube M2 is connected with the output end of the digital logic circuit.

[0008] Further, the wire connected with the gate of the junction field effect transistor JFET is a D terminal, the D terminal is connected with the drain of the power tube M1, and the D terminal is an input terminal of the high-voltage direct-current power supply, and the voltage of the high-voltage direct-current power supply is 100V-700V.

[0009] Further, the junction field effect transistor JFET is an N-channel junction field effect transistor, the gate of which is directly grounded, so that VGS thereof is less than 0. After voltage reduction by the junction field effect transistor JFET, the source output voltage VS of the junction field effect transistor JFET is dozens of volts. According to the device characteristics of the junction field effect transistor JFET, the junction field effect transistor JFET works in a saturation region and is in a conducting state.

[0010] Further, the resistor R5 is a high-resistance resistor, which has a protection function of preventing the driving chip from being burnt out and a function of reducing power consumption; the MOS tube M2 and the MOS tube M3 are high-voltage NMOS tubes, and the NMOS tube M2 is used as a switching tube.

[0011] In some embodiments, when the power tube M1 is in the on state, the drain of the power tube M1 is pulled to a low potential, the junction field effect transistor JFET is cut off, and the charging control circuit does not work; when the power tube M1 is in the off state (cut off), the D end (drain) of the junction field effect transistor JFET is a high voltage DC voltage, the junction field effect transistor JFET is turned on, and the charging control circuit works.

[0012] Further, when the power tube M1 is in the off state, if the signal Y is low, the MOS tube M2 is cut off, the gate end potential of the MOS tube M3 is pulled high, the MOS tube M3 is turned on, and the high voltage DC power supply charges the capacitor C through the MOS tube M3; if the signal Y is high, the MOS tube M2 is turned on, the gate end voltage of the MOS tube M3 is pulled low, the MOS tube M3 is cut off, and the charging of the capacitor C is stopped.

[0013] In some embodiments, the detection control circuit includes a plurality of resistors and three comparators, which are used to detect the voltage VCC on the capacitor C, and the digital logic circuit is used to process the detection results of the detection control circuit and output the signal Y, and the detection control circuit and the digital logic circuit are used to ensure that the voltage VCC works at the stable voltage point V2.

[0014] In some embodiments, the detection control circuit is composed of an operational amplifier C1, an operational amplifier C2, an operational amplifier C3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a MOS tube M4, which control the discharge of the capacitor C; the resistor R1, the resistor R2, the resistor R3, and the resistor R4 are connected in series, the stable voltage VCC output by the capacitor C is connected to one end of the resistor R1 and the source of the MOS tube M4, the positive electrode of the operational amplifier C1 is connected to the wire between the resistor R1 and the resistor R2, the positive electrode of the operational amplifier C2 is connected to the wire between the resistor R2 and the resistor R3, the positive electrode of the operational amplifier C3 is connected to the wire between the resistor R3 and the resistor R4, the other end of the resistor R4 and the drain of the MOS tube M4 are grounded, and the negative electrodes of the operational amplifier C1, the operational amplifier C2, and the operational amplifier C3 are connected to the reference voltage V BG The output ends of the operational amplifier C1 and the operational amplifier C2 are connected to the digital logic circuit, and the output end of the operational amplifier C3 is connected to the digital logic circuit and the gate of the MOS tube M4.

[0015] Further, the reference voltage V BG from the band gap reference circuit, which does not change with temperature, the potentials of the under-voltage point, the stable voltage point, and the over-voltage point of the DC voltage stabilizing power supply driving the chip are V1, V2, and V3 in sequence. When the power supply voltage VCC rises to the under-voltage point V1, the operational amplifier C1 flips; when the power supply voltage VCC rises to the stable voltage point V2, the operational amplifier C2 flips; and when the power supply voltage VCC rises to the over-voltage point V3, the operational amplifier C3 flips.

[0016] Further, the resistance ratio between the resistors R1, R2, R3 and R4 is determined by the formulas S1, S2 and S3, respectively:

[0017]

[0018]

[0019]

[0020] wherein R1, R2, R3 and R4 are the resistance values of the resistors R1, R2, R3 and R4, respectively, V1, V2 and V3 are the potentials of the under-voltage point, the stable-voltage point and the over-voltage point of the DC voltage stabilizer, respectively, and V BG is the reference voltage.

[0021] In some embodiments, the digital logic circuit is composed of simple gate circuits, including NAND gate, NOR gate and NOT gate, and is used to generate the charge-discharge control signal Y according to the output of the detection control circuit, which can determine the magnitude of the power supply voltage to control the charge-discharge of the capacitor C, ensure the capacitor C to keep the charged state when the power supply voltage is under-voltage, ensure the capacitor C to keep the discharged state when the power supply voltage is over-voltage, and keep the power supply voltage in the stable state according to the on-off of the power tube when the power supply voltage is near the stable-voltage point V2.

[0022] In some embodiments, when the system is powered on, the power tube M1 is off, the voltage VCC is 0V, the signal Y is low, and the charge control circuit charges the capacitor C. With the on-off of the power tube M1, the capacitor C is continuously charged, and the voltage VCC is continuously raised. When the voltage VCC is lower than the stable-voltage point V2, the signal Y is low, and the charge control circuit charges the capacitor C. When the voltage VCC is higher than the stable-voltage point V2, the signal Y is high, and the charge control circuit stops charging the capacitor C.

[0023] Further, the MOS tube M4 is composed of multiple PMOS tubes in parallel to meet the large current discharge and heat dissipation requirements. When the VCC reaches the over-voltage point V3, the signal Y is high, the charge control circuit stops charging the capacitor C, and the operational amplifier C3 outputs a low level to control the MOS tube M4 to be turned on. The capacitor C is quickly discharged through the MOS tube M4, and the voltage VCC is reduced.

[0024] Further, when the voltage VCC is higher than the under-voltage potential V1, the power tube M1 is turned on, and the switching power supply system enters the working mode.

[0025] Further, if the mains fluctuates and the voltage VCC drops to the under-voltage potential V1, the power tube M1 is turned off, and the switching power supply system stops working.

[0026] Compared with the prior art, the application has the advantages that:

[0027] (1) The discharge is controlled by using a simple high-voltage charging control circuit and a detection control circuit, the number of high-voltage devices is reduced, and the power consumption and area of the driving chip are reduced.

[0028] (2) The detection control circuit and the digital logic circuit ensure that the DC power supply stably works at a stable voltage point, and have an under-voltage and over-voltage protection function.

[0029] (3) The charging control circuit can realize high-voltage difference step-down, and complete charging of the capacitor C, the circuit design is simplified, and the chip power consumption and cost are reduced. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 It is a topology circuit diagram of a flyback AC / DC switching power supply of the prior art.

[0031] Figure 2 It is a circuit diagram of a DC voltage stabilizing power supply circuit of a switching power supply driving chip of the application.

[0032] Figure 3 It is a circuit diagram of a detection control circuit and a digital logic circuit of a DC voltage stabilizing power supply circuit of a switching power supply driving chip of the application.

[0033] Figure 4 It is a logic control signal waveform diagram of a DC voltage stabilizing power supply circuit of a switching power supply driving chip of the application. DETAILED DESCRIPTION

[0034] The following embodiments are described to aid in the understanding of the application. The embodiments are not intended to and should not be construed as limiting the scope of the application.

[0035] In the following description, those skilled in the art will appreciate that the components can be described as separate functional units (which can include sub-units), but those skilled in the art will appreciate that various components or parts thereof can be divided into separate components, or can be integrated together (including integrated into a single system or component).

[0036] In addition, the connection between the components or systems is not intended to be limited to direct connection. On the contrary, the data between these components can be modified, reformatted, or otherwise changed by intermediate components. In addition, additional or fewer connections can be used. It should also be noted that the term "coupled", "connected", or "input" should be understood to include direct connection, indirect connection through one or more intermediate devices, and wireless connection.

[0037] Embodiment 1:

[0038] A direct-current stabilized power supply circuit of a switching power supply driving chip, comprising Figures 2-4 The direct-current stabilized power supply circuit is applied to the driving chip of the switching power supply, and comprises a charging control circuit, a detection control circuit and a digital logic circuit. A high-voltage direct-current power supply is connected with the charging control circuit, the output end of the charging control circuit is connected with the detection control circuit, the output end of the detection control circuit is connected with the digital logic circuit, and the output end of the digital logic circuit is connected with the charging control circuit. The high-voltage direct-current power supply is connected with a junction field effect transistor of the charging control circuit, the junction field effect transistor is used for voltage reduction and control of the working or non-working of the charging control circuit, the output end of the junction field effect transistor is connected with a resistor R5 and a MOS transistor M3, the MOS transistor M3 is connected with a MOS transistor M2 and a capacitor C, the output signal Y of the digital logic circuit controls the on-off of the MOS transistor M2 and thus controls the on-off of the MOS transistor M3, the charging of the capacitor C is controlled through the MOS transistor M3, and the detection control circuit is used for voltage detection and control of the charging and discharging of the capacitor C, so that the capacitor C outputs a stable voltage VCC as the direct-current stabilized power supply of the driving chip.

[0039] The gate of the junction field effect transistor JFET is grounded, the drain is connected with the drain of the power transistor M1, the source is connected with one end of the resistor R5 and the drain of the NMOS transistor M3, the other end of the resistor R5 is connected with the gate of the NMOS transistor M3 and the drain of the NMOS transistor M2, the source of the NMOS transistor M3 is connected with one end of the capacitor C, and the wire outputting the stable voltage VCC of the capacitor C is connected with the wire between the source of the NMOS transistor M3 and the capacitor C, the other end of the capacitor C is connected with the source of the NMOS transistor M2 and then grounded, and the gate of the NMOS transistor M2 is connected with the output end of the digital logic circuit. The wire connected with the gate of the junction field effect transistor JFET is the D end, the D end is connected with the drain of the power transistor M1, and the D end is the input end of the high-voltage direct-current power supply. The voltage of the high-voltage direct-current power supply is 100V-700V. The junction field effect transistor JFET is an N-channel junction field effect transistor, the gate is directly grounded, so that VGS<0. After voltage reduction through the junction field effect transistor JFET, the source output voltage VS of the junction field effect transistor JFET is dozens of volts. According to the device characteristics of the junction field effect transistor JFET, the junction field effect transistor JFET works in the saturation region and is in the on state. The resistor R5 is a high-resistance resistor, which has the functions of protection against burning of the driving chip and reduction of power consumption; the MOS transistor M2 and the MOS transistor M3 are high-voltage NMOS transistors, and the NMOS transistor M2 is used as a switching transistor.

[0040] When the power tube M1 is in the on state, the drain of the power tube M1 is pulled to a low potential, the junction field effect transistor JFET is cut off, and the charging control circuit does not work; when the power tube M1 is in the off state (cut off), the D end (drain) of the junction field effect transistor JFET is a high voltage DC voltage, the junction field effect transistor JFET is turned on, and the charging control circuit works. When the power tube M1 is in the off state, if the signal Y is low, the MOS tube M2 is cut off, the gate end potential of the MOS tube M3 is pulled high, the MOS tube M3 is turned on, and the high voltage DC power supply charges the capacitor C through the MOS tube M3; if the signal Y is high, the MOS tube M2 is turned on, the gate end voltage of the MOS tube M3 is pulled low, the MOS tube M3 is cut off, and the charging of the capacitor C is stopped.

[0041] The detection control circuit includes a plurality of resistors and three comparators, which are used to detect the voltage VCC on the capacitor C, and the digital logic circuit is used to process the detection result of the detection control circuit and output a signal Y, and the detection control circuit and the digital logic circuit are used to ensure that the voltage VCC works at the stable voltage point V2. The detection control circuit is composed of an operational amplifier C1, an operational amplifier C2, an operational amplifier C3, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a MOS tube M4, and controls the discharge of the capacitor C; the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are connected in series, the stable voltage VCC output by the capacitor C is connected with one end of the resistor R1 and the source of the MOS tube M4, the positive electrode of the operational amplifier C1 is connected with the wire between the resistor R1 and the resistor R2, the positive electrode of the operational amplifier C2 is connected with the wire between the resistor R2 and the resistor R3, the positive electrode of the operational amplifier C3 is connected with the wire between the resistor R3 and the resistor R4, the other end of the resistor R4 and the drain of the MOS tube M4 are grounded, and the negative electrodes of the operational amplifier C1, the operational amplifier C2 and the operational amplifier C3 are connected with a reference voltage V BG The detection control circuit includes a plurality of resistors and three comparators, which are used to detect the voltage VCC on the capacitor C, and the digital logic circuit is used to process the detection result of the detection control circuit and output a signal Y, and the detection control circuit and the digital logic circuit are used to ensure that the voltage VCC works at the stable voltage point V2. The detection control circuit is composed of an operational amplifier C1, an operational amplifier C2, an operational amplifier C3, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a MOS tube M4, and controls the discharge of the capacitor C; the resistor R1, the resistor R2, the resistor R3 and the resistor R4 are connected in series, the stable voltage VCC output by the capacitor C is connected with one end of the resistor R1 and the source of the MOS tube M4, the positive electrode of the operational amplifier C1 is connected with the wire between the resistor R1 and the resistor R2, the positive electrode of the operational amplifier C2 is connected with the wire between the resistor R2 and the resistor R3, the positive electrode of the operational amplifier C3 is connected with the wire between the resistor R3 and the resistor R4, the other end of the resistor R4 and the drain of the MOS tube M4 are grounded, and the negative electrodes of the operational amplifier C1, the operational amplifier C2 and the operational amplifier C3 are connected with a reference voltage V BG from a band gap reference circuit, the potentials of the under-voltage point, the stable voltage point and the over-voltage point of the DC voltage stabilizing power supply driving the chip are V1, V2 and V3 in sequence. When the power voltage VCC rises to the under-voltage point V1, the operational amplifier C1 flips; when the power voltage VCC rises to the stable voltage point V2, the operational amplifier C2 flips; when the power voltage VCC rises to the over-voltage point V3, the operational amplifier C3 flips. The resistance ratio between the resistor R1, the resistor R2, the resistor R3 and the resistor R4 is determined by formulas S1, S2 and S3, and the formulas S1, S2 and S3 are respectively:

[0042]

[0043]

[0044]

[0045] Wherein, R1, R2, R3 and R4 are resistance R1, resistance R2, resistance R3 and resistance R4 respectively, V1, V2 and V3 are the potential of the under-voltage point, the stable voltage point and the over-voltage point of the DC regulated power supply respectively, V BG is a reference voltage.

[0046] The digital logic circuit is composed of simple gate circuits, including NAND gate, NOR gate and NOT gate, and is used to generate a charge-discharge control signal Y according to the output of the detection control circuit, which can judge the size of the power supply voltage to control the charge-discharge of the capacitor C, ensure the capacitor C to keep the charged state when the power supply voltage is under-voltage, ensure the capacitor C to keep the discharged state when the power supply voltage is over-voltage, and keep the power supply voltage in the stable state according to the on-off of the power tube when the power supply voltage is near the stable voltage point V2. When the system is powered on, the power tube M1 is cut off, the voltage VCC is 0V, the signal Y is low, and the charge control circuit charges the capacitor C. With the on-off of the power tube M1, the capacitor C is continuously charged, and the voltage VCC is continuously raised. When the voltage VCC is lower than the stable voltage point V2, the signal Y is low, and the charge control circuit charges the capacitor C. When the voltage VCC is higher than the stable voltage point V2, the signal Y is high, and the charge control circuit stops charging the capacitor C. The MOS tube M4 is a plurality of PMOS tubes in parallel, which meets the requirements of large current discharge and heat dissipation. When the VCC reaches the over-voltage point V3, the signal Y is high, the charge control circuit stops charging the capacitor C, and the operational amplifier C3 outputs a low level to control the MOS tube M4 to be turned on. The capacitor C is quickly discharged through the MOS tube M4, and the voltage VCC is reduced. When the voltage VCC is higher than the under-voltage potential V1, the power tube M1 is turned on, and the switching power supply system enters the working mode. If the mains fluctuates, the voltage VCC drops to the under-voltage potential V1, the power tube M1 is turned off, and the switching power supply system stops working.

[0047] Although the present application has disclosed several aspects and embodiments, other aspects and embodiments will be apparent to those skilled in the art without departing from the concept of the present application, and several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. The aspects and embodiments disclosed in the present application are only used for illustration, and are not intended to limit the present application, and the actual protection scope of the present application is subject to the claims.

Claims

1. A DC regulated power supply circuit for a switching power supply driver chip, wherein the DC regulated power supply circuit is applied to a switching power supply driver chip, and is characterized in that: The DC regulated power supply circuit includes: a charging control circuit, a detection control circuit, and a digital logic circuit. The high-voltage DC power supply is connected to the charging control circuit, the output end of the charging control circuit is connected to the detection control circuit, the output end of the detection control circuit is connected to the digital logic circuit, and the output end of the digital logic circuit is connected to the charging control circuit. The high-voltage DC power supply is connected to the junction field effect transistor of the charging control circuit. The junction field effect transistor is used to reduce the voltage and control the operation or non-operation of the charging control circuit. The output end of the junction field effect transistor is connected to the resistor R5 and the MOS transistor M3. The MOS transistor M3 is connected to the MOS transistor M2 and the capacitor C. The output signal Y of the digital logic circuit controls the on-off of the MOS transistor M2, thereby controlling the on-off of the MOS transistor M3. The charging of the capacitor C is controlled by the MOS transistor M3. The detection control circuit is used for voltage detection and controlling the charging and discharging of the capacitor C, so that the capacitor C outputs a stable voltage VCC as the DC regulated power supply for the driver chip. The gate of the junction field effect transistor JFET is grounded, the drain is connected to the drain of the power transistor M1, and the source is connected to one end of the resistor R5. The first end of the resistor R5 is connected to the drain of the NMOS tube M3, the other end of the resistor R5 is connected to the gate of the NMOS tube M3 and the drain of the NMOS tube M2, the source of the NMOS tube M3 is connected to one end of the capacitor C, and the wire that outputs the stable voltage VCC of the capacitor C is connected to the source of the NMOS tube M3 and the wire between the capacitor C, the other end of the capacitor C is connected to the source of the NMOS tube M2 and then grounded, the gate of the NMOS tube M2 is connected to the output end of the digital logic circuit, when the power tube M1 is in the on state, the drain end of the power tube M1 is When the power tube M1 is in the off state, the D terminal of the junction field effect tube JFET is a high voltage DC voltage, the junction field effect tube JFET is turned on, and the charging control circuit works; when the power tube M1 is in the off state, if the signal Y is at a low level, the MOS tube M2 is turned off, the gate terminal potential of the MOS tube M3 is pulled high, the MOS tube M3 is turned on, and the high voltage DC power supply charges the capacitor C through the MOS tube M3; if the signal Y is at a high level, the MOS tube M2 is turned on, the gate terminal voltage of the MOS tube M3 is pulled low, the MOS tube M3 is turned off, and the charging of the capacitor C is stopped; the detection control circuit includes a plurality of resistors and three comparators, which are used to detect the voltage VCC on the capacitor C, and the digital logic circuit is used to process the detection result of the detection control circuit and output a signal Y, a reference voltage V BG From the bandgap reference circuit, its size does not change with temperature. The potentials of the undervoltage point, stabilization point and overvoltage point of the DC regulated power supply of the driver chip are V1, V2 and V3 respectively; the detection control circuit and the digital logic circuit are used to ensure that the voltage VCC works at the potential V2 of the stabilization point. The detection control circuit is composed of an operational amplifier C1, an operational amplifier C2, an operational amplifier C3, a resistor R1, a resistor R2, a resistor R3, a resistor R4 and a MOS tube M4 to control the discharge of the capacitor C; the resistors R1, R2, Resistors R3 and R4 are connected in series. The capacitor C outputs a stable voltage VCC connected to one end of the resistor R1 and the source of the MOS tube M4. The positive pole of the op amp C1 is connected to the wire between the resistor R1 and the resistor R2. The positive pole of the op amp C2 is connected to the wire between the resistor R2 and the resistor R3. The positive pole of the op amp C3 is connected to the wire between the resistor R3 and the resistor R4. The other end of the resistor R4 and the drain of the MOS tube M4 are grounded. The negative poles of the op amps C1, C2 and C3 are all connected to the reference voltage V BG The output ends of the operational amplifiers C1 and C2 are connected to the digital logic circuit, and the output end of the operational amplifier C3 is connected to the digital logic circuit and the gate of the MOS tube M4.

2. The DC regulated power supply circuit of the switching power supply driver chip according to claim 1, characterized in that: The wire connected to the gate of the junction field effect transistor JFET is the D terminal, which is connected to the drain of the power tube M1. The D terminal is the input terminal of the high-voltage DC power supply, and the voltage of the high-voltage DC power supply is 100V-700V; the junction field effect transistor JFET is an N-channel junction field effect transistor, and its gate is directly grounded, so its VGS is less than 0; the resistor R5 is a high-resistance resistor, which plays a protective function to prevent the driver chip from burning and reduce power consumption; the MOS tubes M2 and MOS tubes M3 are high-voltage NMOS tubes, among which the NMOS tube M2 is used as a switch tube.

3. The DC regulated power supply circuit of the switching power supply driver chip according to claim 1, characterized in that: When the power supply voltage VCC rises to the undervoltage point potential V1, the op amp C1 flips; when the power supply voltage VCC rises to the voltage regulation point potential V2, the op amp C2 flips; when the power supply voltage VCC rises to the overvoltage point potential V3, the op amp C3 flips.

4. The DC regulated power supply circuit of the switching power supply driver chip according to claim 1, wherein: The resistance ratios among the resistors R1, R2, R3, and R4 are determined by formulas S1, S2, and S3, which are: （S1） （S2） （S3） Wherein, R1, R2, R3 and R4 are the resistance values ​​of resistors R1, R2, R3 and R4 respectively, V1, V2 and V3 are the potentials of the undervoltage point, voltage stabilization point and overvoltage point of the DC regulated power supply respectively, V BG is the reference voltage.

5. The DC regulated power supply circuit of the switching power supply driver chip according to claim 1, wherein: The digital logic circuit is composed of simple gate circuits, which include: NAND gates, NOR gates and NOT gates. The digital logic circuit is used to generate a charge and discharge control signal Y based on the output of the detection control circuit. The signal Y can determine the size of the power supply voltage and thus control the charge and discharge of the capacitor C. When the power supply voltage is undervoltage, it can ensure that the capacitor C remains in a charged state. When the power supply voltage is overvoltage, it can ensure that the capacitor C remains in a discharged state. When the power supply voltage is near the potential V2 of the voltage stabilization point, it can maintain the power supply voltage in a stable state according to the on and off of the power tube.

6. The DC regulated power supply circuit of the switching power supply driver chip according to claim 1, characterized in that: comprising one or more features selected from the group consisting of: a. When the system is powered on, power tube M1 is cut off, voltage VCC is 0V, signal Y is at a low level, and the charging control circuit charges capacitor C. As power tube M1 is turned on and off, capacitor C is continuously charged, and voltage VCC continuously increases. When voltage VCC is lower than the voltage stabilization point potential V2, signal Y is at a low level, and the charging control circuit charges capacitor C. When voltage VCC is higher than the voltage stabilization point potential V2, signal Y is at a high level, and the charging control circuit stops charging capacitor C. b. MOS transistor M4 uses multiple PMOS transistors connected in parallel to meet the requirements of high-current discharge and heat dissipation. When VCC reaches the overvoltage point V3, signal Y is high, the charging control circuit stops charging capacitor C, and op amp C3 outputs a low level, controlling MOS transistor M4 to turn on. Capacitor C is quickly discharged through MOS transistor M4, and voltage VCC decreases. c. When the voltage VCC is higher than the undervoltage potential V1, the power tube M1 is turned on and the switching power supply system enters the working mode; d. If the mains power fluctuates, causing the voltage VCC to drop to the undervoltage potential V1, the power tube M1 is disconnected and the switching power supply system stops working.

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