A single - ended input differential output radio frequency active phase shifter

Abstract

A single-ended input differential output radio frequency active phase shifter relates to electronic systems such as radio frequency transceivers and phased arrays, and is particularly applicable to the fields of broadband active and high-precision phased arrays. The present invention comprises a quadrature coupler formed by a coupled line; an amplitude adjustment module formed by a common-gate NMOS transistor array, which realizes the phase shift function through a digital control unit array; an active inductor module formed by a common-gate NMOS transistor array, which realizes phase fine-tuning and input matching at the same time; and an output module formed by an inductor and resistor network, which realizes broadband matching. The present invention is applicable to the CMOS process, eliminates the phase accuracy error caused by the fixed digital algorithm of the active phase shifter, realizes input matching at the same time, and reduces the power transmission reflection. Finally, an active radio frequency phase shifter with 360° phase adjustment, 6-bit phase shift, precision correction and high bandwidth is realized.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency integrated circuits, and relates to a single-ended input differential-output radio frequency active phase shifter, and particularly relates to the technical field of high-precision phased array systems. Background Art

[0002] Driven by factors such as cost, integration level, and power consumption, the CMOS process technology has advanced by leaps and bounds. The cut-off frequency of CMOS transistors can meet the integrated circuit design in frequency bands above several GHz. With the development of 5G phased array technology, active phase shifters have received extensive attention due to advantages such as flexible design, high phase shift accuracy, and convenient calibration. With multi-array antennas and beamforming technology becoming the key technologies for 5G communication, the phased array communication system has developed rapidly.

[0003] As a key module of the phased array system, the phase shifter realizes the electronic beam scanning function by adjusting the phase of the signals transmitted and received by the antennas of the phased array units. With users' higher requirements for insertion loss and phase shift accuracy, as well as requirements for integration level and system area, active phase shifters have developed greatly. An active phase shifter generally consists of three parts: a quadrature network, an amplitude control array unit, and a vector synthesis adder. Radio frequency integrated circuits, especially millimeter-wave integrated circuits, are generally implemented using compounds. However, the compound process is expensive, it is difficult to implement complex logic control units, and it cannot be compatible with the CMOS process. In the future civil markets such as 5G mobile communication, vehicle-mounted, and unmanned aerial vehicle-mounted radars, the demand for small volume, high precision, and low cost has given rise to silicon-based active phase shifters with excellent performance.

[0004] At present, for higher frequency bands, the switch array technology is mostly used to achieve the amplitude of orthogonal signals, so as to achieve the purpose of phase shift. However, the current technology mainly has the following problems: ① The leakage current of the switch's non-ideal characteristics in the microwave band will cause deviation of the amplitude of the orthogonal signal, thus causing additional phase shift and resulting in a decrease in phase shift accuracy. ② In the vector synthesis adder, the reactance of inductance and capacitor components changes with frequency, which leads to the change of system gain with frequency. This will cause the user's directivity power to change with frequency, resulting in the deviation of beam power or phase angle with the change of operating frequency. ③ The general approach is to use a transformer to convert the phase shifter into a single-ended output, and the subsequent drive amplifier is designed as a single-ended one for cascade matching. This design method will sacrifice chip area. ④ The vector network is usually implemented in a differential manner. Therefore, for a single-ended input, a balun is usually used to convert it into a differential signal, and the subsequent stage uses a dual transformer to convert it into two pairs of orthogonal differential signals (as described in patent CN110212887A). However, the dual transformer orthogonal network is very difficult to design due to mutual coupling in the microwave band, and the design almost depends on the accuracy of electromagnetic simulation software. ⑤ Currently, the array current fine-tuning technology will improve the phase shift accuracy. At the same time, the parasitic capacitance introduced at the input end of the vector adder will deteriorate the input matching and limit the significant improvement of the phase shift accuracy. Summary of the Invention

[0005] Object of the Invention: Aiming at the above technical deficiencies, the present invention provides a high-gain flatness and high-precision active phase shifter applicable to CMOS process, with a 360° phase shift range, 6-bit phase shift, single-ended input, differential output.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A single-ended input differential output radio frequency active phase shifter, the radio frequency active phase shifter includes an orthogonal coupler and a balun network 100, a first amplitude control module 200 and a second amplitude control module 300 composed of transistor arrays respectively controlling the amplitudes of orthogonal two-way signals, a first active inductor module 500 and a second active inductor module 600 composed of transistor arrays respectively performing phase fine-tuning, and an output load matching network 400; the input signal is connected to the signal input end of the orthogonal coupler and the balun network 100, and the orthogonal differential signal output ends of the orthogonal coupler and the balun network 100 are respectively connected to the signal input ends of the first active inductor module 500, the first amplitude control module 200, the second active inductor module 600 and the second amplitude control module 300; the signal output ends of the first active inductor module 500, the first amplitude control module 200, the second active inductor module 600 and the second amplitude control module 300 are respectively connected to the signal input ends of the output load matching network 400.

[0008] Further, the orthogonal coupler and the balun network 100 include a first orthogonal coupler 101, a first transformer 102, a second transformer 103, a first transistor 104, a second transistor 105, and a first resistor 106;

[0009] The input end of the first orthogonal coupler 101 is connected to the signal RF_IN, the isolation end is connected to the first resistor 106, the coupling end is connected to one end of the primary coil of the first transformer 102, and the through end is connected to one end of the primary coil of the second transformer 103; the other end of the primary coil of the first transformer 102 is grounded, one end of the secondary coil is connected to VIN+, the other end is connected to VIN-, and the center tap is connected to the drain of the first transistor 104; the other end of the primary coil of the second transformer 103 is grounded, one end of the secondary coil is connected to VQN+, the other end is connected to VQN-, and the center tap is connected to the drain of the second transistor 105; the sources of the first transistor 104 and the second transistor 105 are respectively grounded, and the gates are simultaneously connected to the bias voltage V bias .

[0010] Further, the first amplitude control module 200 and the second amplitude control module 300 respectively include 20 parallel common-gate transistor array units, and each common-gate transistor array unit includes a third transistor 201, a fourth transistor 202, a fifth transistor 203, a sixth transistor 204, a first inverter 205, a second inverter 206, a second resistor 207, and a third resistor 208;

[0011] The sources of the third transistor 201 and the fourth transistor 202 are commonly connected to the positive end of the differential signal input terminal; the sources of the fifth transistor 203 and the sixth transistor 204 are commonly connected to the negative end of the differential signal input terminal; the input end of the first inverter 205 is connected to the digital control signal, the output end is connected to one end of the second resistor 207, the other end of the second resistor 207 is connected to the input end of the second inverter 206, and the input end of the second inverter 206 is simultaneously connected to the gates of the third transistor 201 and the sixth transistor 204; the output end of the second inverter 206 is connected to one end of the third resistor 208, the other end of the third resistor 208 is connected to the gates of the fourth transistor 202 and the fifth transistor 203; the drains of the third transistor 201 and the fifth transistor 203 are commonly connected to VOUT+, and the drains of the fourth transistor 202 and the sixth transistor 204 are commonly connected to VOUT-.

[0012] Further, the first active inductor module 500 and the second active inductor module 600 respectively include 20 switch-controlled common-gate transistor array units; each common-gate transistor array unit includes a seventh transistor 501, an eighth transistor 502, a third inverter 503, and a fourth resistor 504;

[0013] The input terminal of the third inverter 503 is connected to a digital control signal, and the output terminal is connected to one end of the fourth resistor 504. The other end of the fourth resistor 504 is respectively connected to the gates of the seventh transistor 501 and the eighth transistor 502. The drains of the seventh transistor 501 and the eighth transistor 502 are respectively connected to the power supply voltage. The source of the seventh transistor 501 is connected to the positive terminal of the differential signal input, and the source of the eighth transistor 502 is connected to the negative terminal of the differential signal input.

[0014] Furthermore, the fourth resistor 504 is a radio frequency resistor in the process. When the output terminal of the third inverter 503 is at a high level, the seventh transistor 501, the eighth transistor 502, the third inverter 503, and the fourth resistor 504 form an active inductor.

[0015] Furthermore, the output load matching network 400 includes a first inductor 401, a second inductor 402, a fifth resistor 403, a sixth resistor 404, a third inductor 405, and a fourth inductor 406. The first inductor 401, the fifth resistor 403, and the third inductor 405, as well as the second inductor 402, the sixth resistor 404, and the fourth inductor 406, respectively form differential loads. One end of the first inductor 401 and the second inductor 402 are simultaneously connected to the power supply VDD, and the other ends are respectively connected to one end of the fifth resistor 403 and one end of the sixth resistor 404. The other ends of the fifth resistor 403 and the sixth resistor 404 are respectively connected to the output signal terminals VoutP and VoutN. The output signal terminals VoutP and VoutN are respectively connected to one end of the third inductor 405 and the fourth inductor 406. The other ends of the third inductor 405 and the fourth inductor 406 are respectively connected to VOUT- and VOUT+.

[0016] Through the novel phase shifter structure of the present invention, the phase shift accuracy is effectively improved, and at the same time, the gain flatness is enhanced. In the range of 8 GHz - 12 GHz, the phase shift accuracy is better than 3°, and the phase shift amplitude modulation is less than 0.5 dB. Brief Description of the Drawings

[0017] The following further elaborates the present invention in detail in conjunction with the drawings and specific embodiments:

[0018] Figure 1 is the schematic circuit diagram of the active phase shifter proposed by the present invention;

[0019] Figure 2 is the equivalent circuit of the active inductor of the transistor array unit for phase fine-tuning;

[0020] Figure 3 is the simulation result of the 64-state phase shift of the active phase shifter proposed by the present invention;

[0021] Figure 4 is the simulation result of the root mean square error of the 64-state phase shift of the active phase shifter proposed by the present invention;

[0022] Figure 5 These are the simulation results of phase shift and amplitude modulation of the active phase shifter proposed by the present invention. Detailed implementation manners

[0023] To further illustrate the technical solutions disclosed by the present invention, the following will be elaborated in detail in combination with the specification drawings and specific embodiments. Those skilled in the art should know that the optimized designs and improvement methods made without violating the spirit of the invention fall within the protection scope of the present invention, and the conventional techniques in this field will not be described in detail in this specific embodiment.

[0024] Embodiment 1

[0025] As Figure 1 shown, the single - ended input differential output radio - frequency active phase shifter provided by the present invention is composed of an orthogonal coupler and a balun network 100, a first amplitude control module 200 and a second amplitude control module 300 composed of transistor arrays for respectively controlling the amplitudes of two orthogonal signals, a first active inductor module 500 and a second active inductor module 600 composed of transistor arrays for respectively performing phase fine - tuning, and an output load matching network 400.

[0026] The above - mentioned orthogonal coupler and balun network 100 include a first orthogonal coupler 101, a first transformer 102, a second transformer 103, a first transistor 104, a second transistor 105 and a first resistor 106. The input end of the first orthogonal coupler 101 is connected to the signal RF_IN, the isolation end is connected to the first resistor 106, the coupling end is connected to one end of the primary coil of the first transformer 102, and the through - end is connected to one end of the primary coil of the second transformer 103; the other end of the primary coil of the first transformer 102 is grounded, one end of the secondary coil is connected to VIN +, the other end is connected to VIN -, and the center tap is connected to the drain of the first transistor 104; the other end of the primary coil of the second transformer 103 is grounded, one end of the secondary coil is connected to VQN +, the other end is connected to VQN -, and the center tap is connected to the drain of the second transistor 105; the sources of the first transistor 104 and the second transistor 105 are respectively grounded, and the gates are simultaneously connected to the bias voltage V bias .

[0027] The transistor arrays that respectively control the amplitudes of two orthogonal signals constitute the first amplitude control module 200 and the second amplitude control module 300, each of which includes 20 parallel-connected common-gate transistor array units. Each common-gate transistor array unit includes a third transistor 201, a fourth transistor 202, a fifth transistor 203, a sixth transistor 204, a first inverter 205, a second inverter 206, a second resistor 207, and a third resistor 208; the sources of the third transistor 201 and the fourth transistor 202 are commonly connected to the positive terminal of the differential signal input; the sources of the fifth transistor 203 and the sixth transistor 204 are commonly connected to the negative terminal of the differential signal input; the input terminal of the first inverter 205 is connected to the digital control signal, and the output terminal is connected to one end of the second resistor 207. The other end of the second resistor 207 is connected to the input terminal of the second inverter 206, and the input terminal of the second inverter 206 is simultaneously connected to the gates of the third transistor 201 and the sixth transistor 204; the output terminal of the second inverter 206 is connected to one end of the third resistor 208, and the other end of the third resistor 208 is connected to the gates of the fourth transistor 202 and the fifth transistor 203; the drains of the third transistor 201 and the fifth transistor 203 are commonly connected to VOUT+, and the drains of the fourth transistor 202 and the sixth transistor 204 are commonly connected to VOUT-.

[0028] Furthermore, the present invention has 63 phase shift states and can achieve 360° phase shift with a step accuracy of 5.625°. By controlling the digits of the switching transistors of the first amplitude control module 200 and the second amplitude control module 300, the amplitude change of the orthogonal signals can be realized, and different phase shift states are generated through the vector summation of the vector adder. Taking an array unit of the first amplitude control module as an example, when the digital control bit connected to the first inverter is at a high level, the number of unit currents is 1; when the digital control bit connected to the first inverter is at a low level, the number of unit currents is -1. The number of currents of this amplitude control module is the vector sum of the array currents. At the same time, by controlling the positive and negative directions of the switches of the first amplitude control module and the second amplitude control module, it is very easy to realize the positive and negative of the orthogonal signals on the coordinate axes, and the tangent and cotangent functions are complementary. Therefore, only the number of currents of the first amplitude control module and the second amplitude control module during the phase transformation from 0° to 45° in the first quadrant is given here, and the other phase angles can be easily obtained.

[0029] Table 1 Number of Currents and Realized Phase Angles

[0030]

[0031] The transistor arrays for phase fine-tuning constitute the first active inductor module 500 and the second active inductor module 600, each of which includes 20 switch-controlled common-gate transistor array units. Each common-gate transistor array unit includes a seventh transistor 501, an eighth transistor 502, a third inverter 503, and a fourth resistor 504; the input terminal of the third inverter 503 is connected to a digital control signal, the output terminal is connected to one end of the fourth resistor 504, and the other end of the fourth resistor 504 is respectively connected to the gates of the seventh transistor 501 and the eighth transistor 502; the drains of the seventh transistor 501 and the eighth transistor 502 are respectively connected to the power supply voltage, the source of the seventh transistor 501 is connected to the positive end of the differential signal input terminal, and the source of the eighth transistor 502 is connected to the negative end of the differential signal input terminal. The connection relationships of I-channel VIN +, VIN- with the first active inductor module 500 and the first amplitude control module 200, and Q-channel VQN +, VQN- with the second active inductor module 600 and the second amplitude control module 300 are consistent. When the digital control signal connected to the signal input terminal of the first inverter is at a low level, the active inductor module shunts the first amplitude control module and the second amplitude control module, thereby causing a change in the amplitude of the output quadrature signal of the amplitude control module, thus slightly affecting the phase shift accuracy. Compared with a general amplitude calibration unit, this unit forms an active inductor at the same time, which cancels out the parasitic capacitance. When the active inductor network is turned on, the equivalent circuit in the system of half of the circuit of the transistor array unit for phase fine-tuning is as shown in Figure 2 shown.

[0032] Looking up from Figure 2 the VIN + marked, the input impedance obtained

[0033]

[0034] wherein, R s represents the resistance value of the resistor 504, c gs represents the gate-source capacitance of the transistor 501, g m represents the transconductance value of the transistor 501, and V1 represents the gate-source voltage of the transistor 501. In the low-frequency case, Z out is approximately equal to 1 / g m ; at high frequencies, Z out is approximately equal to R s . Generally, 1 / g m < R s . Therefore, the transistor array unit for phase fine-tuning exhibits inductive characteristics.

[0035] When the inductance value is equal to the parasitic capacitance of the array transistor, the parasitics of the array transistor are manifested as a resistance that does not change with frequency. This technology ensures good broadband matching characteristics at the input terminal of the amplitude control module and simultaneously realizes fine-tuning of the phase.

[0036] The above output load matching network 400 includes a first inductor 401, a second inductor 402, a fifth resistor 403, a sixth resistor 404, a third inductor 405, and a fourth inductor 406; the first inductor 401, the fifth resistor 403, and the third inductor 405, and the second inductor 402, the sixth resistor 404, and the fourth inductor 406 respectively form differential loads; one ends of the first inductor 401 and the second inductor 402 are simultaneously connected to the power supply VDD, and the other ends are respectively connected to one ends of the fifth resistor 403 and the sixth resistor 404; the other ends of the fifth resistor 403 and the sixth resistor 404 are respectively connected to the output signal terminals VoutP and VoutN; the output signal terminals VoutP and VoutN are respectively connected to one ends of the third inductor 405 and the fourth inductor 406, and the other ends of the third inductor 405 and the fourth inductor 406 are respectively connected to VOUT- and VOUT+.

[0037] The output terminal adopts a parallel inductor resonance technology. The current flowing through the load resistor is extended due to the action of the inductors 401 / 402, which can reduce the charging rate of the load capacitor. The action of the inductors 405 / 406 further delays the time for the current to flow into other networks, thereby increasing the system bandwidth. Here we only give the final derivation conclusion:

[0038]

[0039] In the above formula, L represents the values of 401 / 402 / 403 / 404, R represents the values of the resistors 403 / 404, and C l represents the load capacitor at the output terminal. k is a reference coefficient, and the value of k affects the maximum flatness delay of the system. Generally, k is about 0.5.

[0040] Figure 1 The NMOS and PMOS transistors in [[ ]] all use RF transistors supported by the CMOS process, and the gate length is selected as the minimum size supported by the process; the inductor uses a common on-chip planar spiral structure, the resistor is a polysilicon resistor, and the capacitor is a MOM capacitor. Table 2 lists Figure 1 the parameter values of the key devices in the corresponding embodiments.

[0041] Table 2. Device Parameters of the Active Phase Shifter Embodiment

[0042]

[0043] As Figures 3 - 5 shown are respectively the 64-state phase shift simulation results of the active phase shifter proposed by the present invention; the root mean square error simulation results of the 64-state phase shift of the active phase shifter; the phase shift amplitude modulation simulation results of the phase shift of the active phase shifter.

Claims

1. A single - ended input differential output radio - frequency active phase shifter, characterized in that: The radio frequency active phase shifter includes a quadrature coupler and a balun network (100), a first amplitude control module (200) and a second amplitude control module (300) composed of transistor arrays for respectively controlling the amplitudes of two orthogonal signals, a first active inductor module (500) and a second active inductor module (600) composed of transistor arrays for respectively performing phase fine-tuning, and an output load matching network (400); an input signal is connected to the signal input end of the quadrature coupler and the balun network (100), and the quadrature differential signal output ends of the quadrature coupler and the balun network (100) are respectively connected to the signal input ends of the first active inductor module (500), the first amplitude control module (200), the second active inductor module (600) and the second amplitude control module (300); the signal output ends of the first active inductor module (500), the first amplitude control module (200), the second active inductor module (600) and the second amplitude control module (300) are respectively connected to the signal input ends of the output load matching network (400). Wherein, the quadrature coupler and the balun network (100) include a first quadrature coupler (101), a first transformer (102), a second transformer (103), a first transistor (104), a second transistor (105) and a first resistor (106). The input terminal of the first quadrature coupler (101) is connected to the signal RF_IN, the isolation terminal is connected to the first resistor (106), the coupled terminal is connected to one end of the primary coil of the first transformer (102), and the through terminal is connected to one end of the primary coil of the second transformer (103); the other end of the primary coil of the first transformer (102) is grounded, one end of the secondary coil is connected to VIN+, the other end is connected to VIN-, and the center tap is connected to the drain of the first transistor (104); the other end of the primary coil of the second transformer (103) is grounded, one end of the secondary coil is connected to VQN+, the other end is connected to VQN-, and the center tap is connected to the drain of the second transistor (105); the sources of the first transistor (104) and the second transistor (105) are grounded respectively, and the gates are connected to the bias voltage V bias .

2. The single-ended input differential output radio frequency active phase shifter according to claim 1, characterized in that: The first amplitude control module (200) and the second amplitude control module (300) respectively include 20 parallel-connected common-gate transistor array units, and each common-gate transistor array unit includes a third transistor (201), a fourth transistor (202), a fifth transistor (203), a sixth transistor (204), a first inverter (205), a second inverter (206), a second resistor (207) and a third resistor (208). The sources of the third transistor (201) and the fourth transistor (202) are commonly connected to the positive end of the differential signal input; the sources of the fifth transistor (203) and the sixth transistor (204) are commonly connected to the negative end of the differential signal input; the input end of the first inverter (205) is connected to a digital control signal, the output end is connected to one end of the second resistor (207), the other end of the second resistor (207) is connected to the input end of the second inverter (206), and the input end of the second inverter (206) is simultaneously connected to the gates of the third transistor (201) and the sixth transistor (204); the output end of the second inverter (206) is connected to one end of the third resistor (208), the other end of the third resistor (208) is connected to the gates of the fourth transistor (202) and the fifth transistor (203); the drains of the third transistor (201) and the fifth transistor (203) are commonly connected to VOUT+, and the drains of the fourth transistor (202) and the sixth transistor (204) are commonly connected to VOUT-.

3. The single-ended input differential-output radio frequency active phase shifter according to claim 1, wherein: The first active inductor module (500) and the second active inductor module (600) each include 20 switch-controlled common-gate transistor array units; each common-gate transistor array unit includes a seventh transistor (501), an eighth transistor (502), a third inverter (503), and a fourth resistor (504). The input terminal of the third inverter (503) is connected to a digital control signal, the output terminal is connected to one end of the fourth resistor (504), and the other end of the fourth resistor (504) is respectively connected to the gates of the seventh transistor (501) and the eighth transistor (502); the drains of the seventh transistor (501) and the eighth transistor (502) are respectively connected to the power supply voltage, the source of the seventh transistor (501) is connected to the positive terminal of the differential signal input, and the source of the eighth transistor (502) is connected to the negative terminal of the differential signal input.

4. The single-ended input differential output radio frequency active phase shifter according to claim 3, characterized in that: The fourth resistor (504) is a radio frequency resistor in the process. When the output terminal of the third inverter (503) is at a high level, the seventh transistor (501), the eighth transistor (502), the third inverter (503), and the fourth resistor (504) form an active inductor.

5. The single-ended input differential-output radio frequency active phase shifter according to claim 1, wherein: The output load matching network (400) includes a first inductor (401), a second inductor (402), a fifth resistor (403), a sixth resistor (404), a third inductor (405), and a fourth inductor (406); the first inductor (401), the fifth resistor (403), and the third inductor (405), and the second inductor (402), the sixth resistor (404), and the fourth inductor (406) respectively form differential loads; one ends of the first inductor (401) and the second inductor (402) are simultaneously connected to the power supply VDD, and the other ends are respectively connected to one ends of the fifth resistor (403) and the sixth resistor (404); the other ends of the fifth resistor (403) and the sixth resistor (404) are respectively connected to the output signal terminals VoutP and VoutN; the output signal terminals VoutP and VoutN are respectively connected to one ends of the third inductor (405) and the fourth inductor (406), and the other ends of the third inductor (405) and the fourth inductor (406) are respectively connected to VOUT- and VOUT+.

Images