Supporting atomic memory accesses across consecutive granule boundaries in processor-based devices

Abstract

Atomic memory access across consecutive granule boundaries is supported in a processor-based device. In this regard, the processor-based device includes a plurality of processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute consecutive granule ("cogran") pair atomic access (CPAA) tokens. To perform an atomic memory access on a cogran pair, a PE must hold a CPAA token for an address block containing one of the cogran pair before the PE can acquire exclusive state on each cogran in the cogran pair. Because a CPAA token must be acquired before exclusive access to at least one of the cogran pair is obtained, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlock and livelock between PEs seeking access to the same cogran can be avoided.

Description

TECHNICAL FIELD

[0001] The techniques of this disclosure relate to memory access operations in processor-based devices, and more specifically, to atomic memory accesses that can occur across coherence granule boundaries. BACKGROUND

[0002] An “atomic memory access” performed by a processor-based device refers to a memory access operation (e.g., as non-limiting examples, a memory read operation or a memory write operation) in which all of the accessed data bytes are simultaneously observable. An atomic memory access ensures that, even if multiple agents attempt to perform conflicting operations on the same memory location, the resulting value stored at that memory location will be either the entire previous value or the entire final value, and never a combination of the two. Depending on the memory model supported by the instruction set architecture (ISA) of the processor-based device, the processor-based device can expect or require that some or all types of memory access operations be performed atomically. For example, the system memory of a processor-based device can be organized into subdivisions called “coherence granules,” which represent the alignment size (in bytes) at which the processor-based device manages cache coherency, and the processor-based device can require that all memory access operations within a single coherence granule be performed atomically.

[0003] However, problems can arise when an atomic memory access crosses a boundary between two coherence granules. Consider the following scenario in which the bytes at memory addresses 0 to 63 within the system memory are located within a first coherence granule, while the bytes at memory addresses 64 to 127 are located within a second coherence granule. Thus, a memory store operation that writes four (4) bytes of data starting at memory address 62 will need to write the first two (2) bytes to the first coherence granule and the last two (2) bytes to the second coherence granule. To perform the memory store operation atomically, both coherence granules need to be acquired in an exclusive state simultaneously. Once a processing element (PE) (e.g., a processor or processor core) obtains exclusive access to both coherence granules, the memory store operation can be completed, and then another PE can access one or both of the coherence granules.

[0004] However, suppose two PEs each attempt to atomically perform memory storage operations on the same two coherent particles at approximately the same time. The first PE can acquire the first coherent particle exclusively and then deny other PEs access to it until it can acquire the second coherent particle exclusively. Simultaneously, the second PE can acquire the second coherent particle exclusively and deny other PEs access to the first coherent particle until it can acquire it exclusively. This results in a deadlock, where each PE refuses to relinquish its coherent particle until other PEs do so. One technique to avoid this deadlock is to prohibit PEs from holding their respective coherent particles in the manner described above and require each PE to wait until it acquires exclusive access to both coherent particles before completing its memory storage operation. However, this technique may lead to a livelock, where each PE repeatedly relinquishes its coherent particle to other PEs upon request.

[0005] One conventional technique for atomic memory access across coherent granular boundaries involves a processor-based device detecting a memory access operation that crosses a coherent granular boundary, and, to handle this situation, the processor "locks the bus" or restricts access to the interconnect bus for the PE seeking to perform the memory access operation. The interconnect bus is unlocked after the PE has gained exclusive access to both coherent granules and has atomically completed the memory access operation. However, locking the bus can lead to significant performance penalties because the interconnect bus can only be accessed by one PE while it is locked. Another conventional technique involves the underlying ISA of the processor-based device, which does not guarantee that memory access operations will be performed atomically when crossing coherent granular boundaries. In this case, software must detect whether a memory access operation crosses a coherent granular boundary and attempt to handle the memory access operation by implementing a software-based bus locking mechanism by stopping all other executing threads in the PE. However, this software-based approach can be more complex and less reliable than the hardware-based approach.

[0006] Therefore, a more efficient mechanism is needed to support atomic memory access across coherent particle boundaries. Summary of the Invention

[0007] The exemplary embodiments disclosed herein include supporting atomic memory access across cogran boundaries in a processor-based device. In this regard, in one exemplary embodiment, the processor-based device, including a plurality of processing elements (PEs), also includes a dedicated central sorting point (SPCOP) configured to issue cogran pair atomic access (CPAA) tokens. In order to perform atomic memory access on a cogran pair, a PE must hold a CPAA token for a memory-aligned address block containing at least one cogran in the cogran pair before the PE can request exclusive access to the cogran pair. Each cogran in the cogran can be considered “even” or “odd” based on, for example, the value of the least significant bit used to select the cogran memory address. Thus, in the embodiment described herein where each address block contains exactly one (1) cogran, the SPCOP can associate the CPAA token with each address block containing only “even” cogran (or only “odd” cogran). Because CPAA tokens are always associated with address blocks containing an "even" number of coherent particles (or an "odd" number, depending on the implementation), and SPCOP allows only one CPAA token to be active for a given address block at a time, deadlocks and livelocks between multiple PEs seeking access to the same coherent particle for atomic memory access can be avoided. Once a PE obtains a CPAA token for an address block containing the first coherent particle in the coherent particle pair, the PE acquires the first coherent particle in the pair in an exclusive state, and then acquires the second coherent particle in the pair in an exclusive state. The PE then completes the atomic memory access request and returns the CPAA token to SPCOP. Some embodiments may further specify that SPCOP includes a CPAA access queue for tracking requests to access coherent particles protected by CPAA tokens, while in some embodiments, SPCOP may include a CPAA reservation queue for tracking multiple requests for CPAA tokens for a given coherent particle.

[0008] In another exemplary embodiment, a processor-based device is provided. The processor-based device includes a system memory and an SPCOP, the system memory including a plurality of address blocks and a plurality of coherent particles, and the SPCOP including SPCOP logic circuitry. The processor-based device also includes a plurality of PEs, each PE including memory access logic circuitry. The memory access logic circuitry of a first PE among the plurality of PEs is configured to: detect an atomic memory access request spanning a boundary between a first coherent particle and a second coherent particle in the system memory. The memory access logic circuitry of the first PE is further configured to: send a request to the SPCOP for a CPAA token, the CPAA token being for an address block containing the first coherent particle. The memory access logic circuitry of the first PE is further configured to: receive from the SPCOP a CPAA token for the address block containing the first coherent particle, the CPAA token indicating that the first PE among the plurality of PEs is permitted to protect the address block containing the first coherent particle. The memory access logic circuitry of the first PE is further configured to: acquire the first and second coherent particles in an exclusive state. The memory access logic circuitry of the first PE is further configured to complete the atomic memory access request. The memory access logic circuitry of the first PE is also configured to send a request to return a CPAA token to the SPCOP for the address block containing the first coherent granules.

[0009] In another exemplary embodiment, a method for supporting atomic memory access across a coherent particle boundary is provided. The method includes: a first PE (Processor Provider) of a plurality of PEs (Processors Providers) of a processor-based device detecting an atomic memory access request across a boundary between a first coherent particle and a second coherent particle in the system memory of the processor-based device. The method further includes: the first PE sending a first request to an SPCOP for a CPAA token, the CPAA token being for an address block containing the first coherent particle. The method further includes: the first PE receiving from the SPCOP a CPAA token for the address block containing the first coherent particle, the CPAA token indicating that the first PE of the plurality of PEs is permitted to protect the address block containing the first coherent particle. The method further includes: the first PE acquiring the first and second coherent particles in an exclusive state. The method further includes: the first PE fulfilling the atomic memory access request. The method further includes: the first PE sending a request to return a CPAA token for the address block containing the first coherent particle to the SPCOP.

[0010] In another exemplary embodiment, a non-transient computer-readable medium is provided. The computer-readable medium stores computer-executable instructions thereon that, when executed by a processor, cause the processor to detect an atomic memory access request spanning the boundary between a first coherent particle and a second coherent particle of system memory. The computer-executable instructions also cause the processor to send a request for a CPAA token to the processor's SPCOP for an address block containing the first coherent particle. The computer-executable instructions also cause the processor to receive a CPAA token from the SPCOP for the address block containing the first coherent particle, the CPAA token indicating that the processor is permitted to protect the address block containing the first coherent particle. The computer-executable instructions further cause the processor to acquire the first and second coherent particles in an exclusive state. The computer-executable instructions further cause the processor to complete the atomic memory access request. The computer-executable instructions further cause the processor to send a request to the SPCOP to return a CPAA token for the address block containing the first coherent particle.

[0011] After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement additional embodiments thereof. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] Figure 1 This is a block diagram illustrating an exemplary processor-based device according to some embodiments, the processor-based device including a dedicated central sort point (SPCOP) configured to support atomic memory access across coherent particle boundaries;

[0014] Figure 2 The diagram shows SPCOP and Figure 1 A message flow graph of an exemplary communication flow between PEs of a processor-based device, used to request a coherent granule (“cogran”) pair atomic access (CPAA) token and to obtain exclusive access to the coherent granule pair to perform an atomic memory access operation.

[0015] Figure 3 More detailed illustrations Figure 1 A block diagram of an exemplary embodiment of SPCOP;

[0016] Figures 4A-4B It is a diagram. Figure 1 A message flow diagram illustrating the exemplary communication flow between SPCOP and multiple PEs, each requesting a CPAA token;

[0017] Figures 5A-5C It is a diagram.Figure 1 A message flow graph of an exemplary communication flow between SPCOP and multiple PEs, used to record attempts to access coherent granules protected by active CPAA tokens using SPCOP's CPAA access queue.

[0018] Figure 6A and Figure 6B The diagram is located at Figure 1 A message flow diagram illustrating the exemplary communication flow between multiple SPCOPs and PEs on multiple dies of a processor-based device;

[0019] Figure 7A and Figure 7B The illustrations are based on some embodiments. Figure 1 The flowchart illustrates an exemplary operation of the PE for requesting a CPAA token, obtaining exclusive access to the corresponding coherent granular pair, and performing atomic memory access operations.

[0020] Figure 8 It is a diagram. Figure 1 A flowchart of an exemplary operation of SPCOP for using CPAA access queues to process memory access to coherent granules protected by active CPAA tokens.

[0021] Figure 9 It is a diagram. Figure 1 A flowchart illustrating an exemplary operation of SPCOP, used to reserve CPAA tokens using a CPAA reservation queue and for the subsequent distribution of the reserved CPAA tokens; and

[0022] Figure 10 These are exemplary processor-based devices (such as...) Figure 1 A block diagram of a processor-based device configured to support atomic memory access across coherent particle boundaries. Detailed Implementation

[0023] The exemplary embodiments disclosed herein include supporting atomic memory access across cogran boundaries in a processor-based device. In this regard, in one exemplary embodiment, the processor-based device including a plurality of processing elements (PEs) further includes a dedicated central sorting point (SPCOP) configured to issue cogran pair atomic access (CPAA) tokens. In order to perform atomic memory access on a cogran pair, a PE must hold a CPAA token for a memory-aligned address block containing at least one cogran in the cogran pair before the PE can request exclusive access to the cogran pair. Each cogran in the cogran can be considered “even” or “odd” based on, for example, the value of the least significant bit of the memory address used to select the cogran. Thus, in the embodiment described herein where each address block contains exactly one (1) cogran, the SPCOP can associate the CPAA token with each address block containing only “even” cogran (or only “odd” cogran). Because CPAA tokens are always associated with address blocks containing an "even" number of coherent particles (or an "odd" number, depending on the implementation), and SPCOP allows only one CPAA token to be active for a given address block at a time, deadlocks and livelocks between multiple PEs seeking access to the same coherent particle for atomic memory access can be avoided. Once a PE obtains a CPAA token for an address block containing the first coherent particle in the coherent particle pair, the PE acquires the first coherent particle in the pair in an exclusive state, and then acquires the second coherent particle in the pair in an exclusive state. The PE then completes the atomic memory access request and returns the CPAA token to SPCOP. Some embodiments may further specify that SPCOP includes a CPAA access queue for tracking requests to access coherent particles protected by CPAA tokens, while in some embodiments, SPCOP may include a CPAA reservation queue for tracking multiple requests for CPAA tokens for a given coherent particle.

[0024] in this regard, Figure 1 An exemplary processor-based device 100 is illustrated, which provides a plurality of processing elements (PEs) 102(0)-102(P) for processing executable instructions. Each PE among the PEs 102(0)-102(P) may include a central processing unit (CPU) having one or more processor cores, or may include a single processor core including a logic execution unit and associated cache and functional units. Figure 1In the example, each PE in PEs 102(0)-102(P) includes a corresponding execution pipeline 104(0)-104(P), which is configured to perform out-of-order execution of an instruction stream comprising computer-executable instructions. As a non-limiting example, each of the execution pipelines 104(0)-104(P) may include: a fetch stage for retrieving instructions for execution, a decode stage for converting the fetched instructions into control signals for instruction execution, a rename stage for allocating physical register file (PRF) registers, a dispatch stage for issuing instructions for execution, an execution stage for sending instructions and operands to the execution unit, and / or a commit stage for irrevocably updating the architectural state of the corresponding PE 102(0)-102(P) based on the result of instruction execution.

[0025] Figure 1 The processor-based device 100, with PEs 102(0)-102(P), interconnected with each other via interconnect bus 108 and with system memory 106. For example... Figure 1 As seen, system memory 106 is subdivided into multiple coherent particles 110(0)-110(C), each coherent particle representing the smallest memory unit (e.g., 64 bytes, as a non-limiting example) maintained by processor-based device 100. System memory 106 is also divided into address blocks 111(0)-111(A). Figure 1 In the example, address blocks 111(0)-111(A) each contain a corresponding coherent particle in coherent particles 110(0)-110(C). According to some embodiments, the processor-based device 100 may also provide a snooping filter 112 to monitor traffic on the interconnect bus 108 to track the coherence status of cache lines (not shown) of PE 102(0)-102(P). In some embodiments, the processor-based device 100 may also provide a central sorting point 114 for sorting, for example, cache misses and invalid requests.

[0026] Figure 1 The processor-based device 100 and its constituent elements may encompass any of known digital logic elements, semiconductor circuits, processing cores and / or memory structures, as well as other elements or combinations thereof. The embodiments described herein are not limited to any particular element arrangement, and the disclosed techniques can be readily extended to various structures and layouts on semiconductor sockets or packages. It should be understood that some embodiments of the processor-based device 100 may include, in addition to… Figure 1Components other than those shown. For example, each PE in PE 102(0)-102(P) may also include one or more functional units, instruction caches, unified caches, memory controllers, interconnect buses and / or additional memory devices, cache and / or controller circuitry, for clarity, from Figure 1 They are omitted. Additionally, in some embodiments, PEs 102(0)-102(P) may all be co-located on a single die 116(0) among a plurality of dies 116(0)-116(D) of the processor-based device 100. In such embodiments, each die 116(1)-116(D) includes a plurality of PEs corresponding to PEs 102(0)-102(P) of die 116(0).

[0027] As described above, PE 102(0)-102(P) may encounter problems when attempting to perform atomic memory access across the boundary between two coherent particles in coherent particles 110(0)-110(C). For example, suppose PE 102(0) and PE 102(P) each attempt to perform an atomic memory storage operation across coherent particle 110(0) and coherent particle 110(1). PE 102(0) can acquire coherent particle 110(0) in an exclusive state and then deny PE 102(P) access to coherent particle 110(0) until PE 102(0) can acquire coherent particle 110(1) in an exclusive state. Simultaneously, PE 102(P) can acquire coherent particle 110(1) in an exclusive state and refuses PE 102(0) access to coherent particle 110(1) until PE 102(P) can acquire coherent particle 110(0) in an exclusive state. This results in a deadlock, where each PE 102(0), 102(P) refuses to relinquish its coherent particles 110(0), 100(1). A livelock could also occur under similar circumstances if PE 102(0) and 102(P) continuously exchange holdings of coherent particles 110(0) and 110(1).

[0028] in this regard, Figure 1The processor-based device 100 is configured to support atomic memory access across coherent particle boundaries. Specifically, the embodiments described herein target memory access operations requiring exclusive access to two (2) coherent particles (e.g., coherent particles 110(0) and 110(1) as a non-limiting example) of coherent particles 110(0)-110(C). It should be understood that memory access operations can use virtual addresses to store and load data, and therefore, memory access operations across coherent particle boundaries can cross physical page boundaries (i.e., a memory access operation can begin within the last coherent particle of one physical page and end within the first coherent particle of another physical page). Furthermore, although virtual addresses can be contiguous (i.e., a memory access operation begins in one coherent particle and ends in the next sequential coherent particle), the corresponding physical addresses may not be contiguous.

[0029] Each of PEs 102(0)-102(P) provides a corresponding memory access logic circuit 118(0)-118(P), which works in conjunction with a dedicated central sorting point (SPCOP) 120 to support atomic memory access across coherent particle boundaries. Each memory access logic circuit 118(0)-118(P) may exist as a discrete element of the corresponding PE 102(0)-102(P), or may be integrated into one or more elements of the corresponding PE 102(0)-102(P), such as execution pipelines 104(0)-104(P). In exemplary operation, and using PE 102(0) as an example, memory access logic circuit 118(0) is configured to first detect an atomic memory access request 122 that crosses the boundary between coherent particle 110(0) and coherent particle 110(1). The memory access logic circuit 118(0) of PE 102(0) is configured to request a CPAA token for address block 111(0), which contains the first coherent particle 110(0) of the coherent particle pair 110(0) and 110(1) to which atomic memory access is to be performed, before PE 102(0) can obtain exclusive access to the coherent particle pair 110(0) and 110(1). Therefore, the memory access logic circuit 118(0) then requests a CPAA token from SPCOP 120. SPCOP 120 is configured to allow only one CPAA token to be active for a given non-overlapping address block 111(0)-111(A) at a time, but in some embodiments, multiple CPAA tokens may be allowed to be active for different address blocks 111(0)-111(A) simultaneously.

[0030] exist Figure 1In the example, the size of address block 111(0)-111(A) is equal to the size of coherent particle 110(0)-110(C), such that each coherent particle in coherent particle pair 110(0), 110(1) is located within a different address block 111(0), 111(1). Therefore, the CPAA token is always associated with a specific address block in any given address block pair 111(0), 111(1). As a non-limiting example, each coherent particle in coherent particle 110(0)-110(C) can be determined as an “even” or “odd” coherent particle 110(0)-110(C) based, for example, the value of the least significant bit in the memory address of coherent particle 110(0)-110(C). Therefore, the memory access logic circuit 118(0) of PE 102(0) can be configured to always deterministically select the address block 111(0) containing “even” coherent particles 110(0) (or the address block 111(1) containing “odd” coherent particles 110(1), depending on the implementation) as the address block for which a CPAA token is requested.

[0031] It should be understood that in some embodiments, each of PEs 102(0)-102(P) may provide a single SPCOP, or may provide multiple SPCOPs, each SPCOP being associated with a specified range of the entire address space of system memory 106. In some embodiments, upon receiving a request for a CPAA token, SPCOP 120 records the memory address for selecting a first coherent particle (e.g., coherent particle 110(0) in this example), and the identifier of the PE 102(0) requesting the CPAA token, and then distributes the CPAA token to PE 102(0).

[0032] Once PE 102(0) obtains the CPAA token, it can request exclusive access to the first coherent particle 110(0). Upon obtaining the first coherent particle 110(0) in exclusive status, a "CPAA protection window" is established for the first coherent particle 110(0). The CPAA protection window allows PE 102(0) to protect its holding of the first coherent particle 110(0) until it makes progress toward obtaining the second coherent particle 110(1). After PE 102(0) obtains the second coherent particle 110(1) in exclusive status, PE 102(0) completes the atomic memory access request 122 and then returns a CPAA token to SPCOP 120 for the address block 111(0) containing the first coherent particle 110(0). Because PE 102(0) must hold the CPAA token for the address block containing the first coherent particle 110(0) to protect the address block containing the first coherent particle 110(0) until it acquires the second coherent particle 110(1) in an exclusive state, deadlock can be avoided. Similarly, because once PE 102(0) acquires the CPAA token for the address block containing the first coherent particle 110(0), PE 102(0) is allowed to protect the address block containing the first coherent particle 110(0) until it acquires the second coherent particle 110(1) in an exclusive state, livelock can also be avoided.

[0033] In some embodiments, when PE 102(0) has a CPAA protection window opened for the first coherent particle 110(0), and (e.g. from Figure 1 When PE 102(P) receives a snooping request indicating an attempt to access the first coherent particle 110(0), its memory access logic 118(0) is configured to send a response instructing PE 102(P) to send its request to SPCOP 120 before it is allowed to return to the normal path. This prevents access to the coherent particle covered by the CPAA protection window for the duration of the CPAA protection window. Otherwise, there is a possibility of starvation if the second coherent particle 110(1) should need to be served by the same system resources that process the first coherent particle 110(0). For example, if requests directed to the first coherent particle 110(0) are not directed to SPCOP 120 when they are retransmitted, their presence in the normal request path can prevent PE 102(0) from making progress in obtaining the second coherent particle 110(1) in an exclusive state.

[0034] To illustrate, based on an example Figure 2 The communication stream between components of the processor-based device 100 for requesting CPAA tokens and performing atomic memory access operations provides Figure 2For clarity, in the description Figure 1 Time Reference Figure 2 Components. In Figure 2 In the example, it is assumed that the size of each address block 111(0)-111(A) is the same as the size of each coherent particle 110(0)-110(C). Figure 2 As seen in the diagram, message flow diagram 200 shows PE 102(0), COP114, and SPCOP 120 represented by vertical lines, with communication between these components illustrated by arrows with headings. Note that although in Figure 2 In the example, COP 114 is shown to serve both the first coherent particle 110(0) and the second coherent particle 110(1), but some embodiments may specify that the first coherent particle 110(0) and the second coherent particle 110(1) may be mapped to different COPs.

[0035] exist Figure 3 In this configuration, the operation begins with PE 102(0) sending a request 202 to SPCOP 120 for a CPAA token for address block 111(0) containing the first coherent granule 110(0). SPCOP 120 responds by distributing a CPAA token 204 for address block 111(0) containing the first coherent granule 110(0). This initiates a period during which the CPAA token is considered "active". In some embodiments, SPCOP 120 may distribute the CPAA token 204 by sending a response to the first PE 102(0) including the CPAA token 204. Some embodiments may specify that SPCOP 120 distributes the CPAA token 204 by sending a response to the first PE 102(0) instructing the first PE 102(0) to retry its request 202 for the CPAA token 204 for the first coherent granule 110(0). According to some embodiments, SPCOP 120 may distribute CPAA token 204 only if one of the following conditions is met: (1) request 202 does not match an active CPAA token and an available CPAA token exists; or (2) a request is made from the next PE 102(0)-102(P) in the CPAA reservation queue of SPCOP 120 (as per [reference]). Figure 3 (Discussed in more detail), and the request does not correspond to an active CPAA token.

[0036] After receiving CPAA token 204, PE 102(0) then sends request 206 to COP (COP 114 in this example) to obtain the first coherent particle 110(0) in exclusive status. When the first coherent particle 110(0) becomes available, COP 114 sends response 208 to PE 102(0) granting exclusive access to the first coherent particle 110(0), thereby opening the CPAA protection window. Next, PE 102(0) sends request 210 to COP 114 to obtain the second coherent particle 110(0) in exclusive status. When the second coherent particle 110(0) becomes available, COP 114 sends response 212 granting exclusive access to the second coherent particle 110(1). At this point, the CPAA protection window ends, and the normal protection window that PE 102(0) was able to complete during its time, the atomic memory access request 122, is opened. After completing atomic memory access request 122, PE 102(0) sends request 214 to return CPAA token 204 to SPCOP 120. When SPCOP 120 receives request 214, the CPAA token 204 for address block 111(0) containing the first coherent granule 110(0) is deemed invalid. SPCOP 120 then sends response 216 indicating that CPAA token 204 has been returned.

[0037] To avoid starvation of CPAA tokens from other PEs 102(0)-102(P), once PE 102(0) has completed its atomic memory access for coherent particle pairs 110(0) and 110(1), PE 102(0) must request a new CPAA token when it wants to perform an atomic memory access for the second coherent particle pairs 110(0)-110(C).

[0038] In some embodiments, the atomic memory access to be performed by PE 102(0) may be for a non-cacheable memory location. In such an embodiment, as part of the process of acquiring coherent granules 110(0) and 110(1) in an exclusive state, PE 102(0) registers an atomic memory access request 122 with snooping filter 112 to indicate that when processing a subsequent access to a non-cacheable memory location by another PE 102(0)-102(P), snooping filter 112 causes a snooping request to be sent to PE 102(0). PE 102(0) can then follow the process described above regarding obtaining the CPAA token and performing the atomic memory access.

[0039] Figure 1 A more detailed illustration is provided. Figure 3The constituent elements of an exemplary embodiment of the SPCOP 120. It should be understood that some embodiments of the SPCOP 120 may include components that are more advanced than those described above. Figure 3 The diagram shows some or fewer of the constituent elements. For example... Figure 2 As seen herein, SPCOP 120 provides SPCOP logic circuitry 300, which is configured to provide functionality belonging to SPCOP 120 as described herein. SPCOP 120 may also provide CPAA token buffer 302, which may be used to store data for one or more CPAA tokens (e.g., as a non-limiting example, the memory address of the coherent granule associated with the CPAA token and / or the identifier of the PE requesting the CPAA token).

[0040] In some embodiments, SPCOP 120 may provide a CPAA access queue 304, which is used to track requests for access to coherent granules (e.g., as described above, when PE 102(P) is instructed to resend its request to SPCOP 120). If SPCOP 120 receives such a request, it may first determine whether the request matches an active CPAA token. If not, SPCOP 120 sends a response indicating that the requesting PE 102(P) will return to regular memory coherent processing by, for example, resending its request using a regular channel. However, if the request does match an active CPAA token such as CPAA token 204, SPCOP 120 may record the identifier for the request and the corresponding CPAA token slot in an entry in CPAA access queue 304. When CPAA token 204 is eventually returned to SPCOP 120, SPCOP 120 sends a response indicating that the requesting PE 102(P) will return to regular memory coherent processing. If the CPAA access queue 304 is full when SPCOP 120 attempts to add a new entry, SPCOP 120 may send a response to PE102(P) instructing PE102(P) to retry its request to SPCOP 120.

[0041] Finally, according to some embodiments, SPCOP 120 may include a CPAA reservation queue 306 to allow CPAA tokens to be reserved by requesting PEs 102(0)-102(P). When SPCOP 120 receives a request for a CPAA token (such as, Figure 4AWhen request 202 is received, SPCOP 120 may add request 202 to CPAA reservation queue 306 if any of the following conditions are met: (1) request 202 does not match an active CPAA token, but no CPAA token is available for distribution; (2) request 202 matches an active CPAA token; or (3) the request comes from PE 102(0)-102(P), which is the next in CPAA reservation queue 306, but the memory address of the request matches the memory address of the active CPAA token (i.e., the memory address needs to access address block 111(0)-111(A), for which the active CPAA token is outstanding).

[0042] When SPCOP 120 subsequently has an available CPAA token, it can distribute the CPAA token as described above with respect to CPAA token 204. Specifically, in some embodiments, SPCOP 120 may send a response including the CPAA token to the next PE 102(0)-102(P) in the CPAA reservation queue 306. Such embodiments require SPCOP 120 to store the memory addresses of the coherent granules requested by the PEs in the CPAA reservation queue 306, which may not scale well if a large number of PEs 102(0)-102(P) can attempt to request CPAA tokens. According to some embodiments, SPCOP 120 may send a response to the next PE 102(0)-102(P) in the CPAA reservation queue 306, indicating that the PE 102(0)-102(P) should retry its request to obtain the CPAA token. In such an embodiment, SPCOP 120 can check before distributing available CPAA tokens to ensure that the identifiers of PEs 102(0)-102(P) for an incoming request for a CPAA token match the next PE 102(0)-102(P) in the CPAA reservation queue 306. This allows SPCOP 120 to obtain the memory addresses of the coherent granules for the CPAA token and also maintains the reservation of PEs 102(0)-102(P) without recording the complete memory addresses of the coherent granules for each entry in the CPAA reservation queue 306.

[0043] Some embodiments may specify that the CPAA reservation queue 306 includes a bit vector whose size is one less than the number of PEs 102(0)-102(P) expected to perform atomic memory accesses. In such an embodiment, SPCOP 120 can limit the number of concurrent CPAA tokens per PE 102(0)-102(P) to one (1), and can use the bit vector to record each request in the CPAA reservation queue 306 instead of storing the complete identifier of each PE 102(0)-102(P) for each CPAA token request. In this way, the scalability of the CPAA reservation queue 306 can be increased.

[0044] To prevent denial-of-service (DoS) attacks by malicious proxies, in some embodiments, SPCOP 120 can be configured to copy CPAA reservation queue 306 to the next active queue 308. Then, when a CPAA token becomes available, SPCOP 120 can select PEs 102(0)-102(P) from the next active queue 308, while simultaneously recording newly arrived requests for CPAA tokens in CPAA reservation queue 306. Subsequently, when the next active queue 308 is emptied, CPAA reservation queue 306 can be copied to the next active queue 308. Such embodiments ensure that each PE 102(0)-102(P) has a chance to obtain a CPAA token before any PE 102(0)-102(P) is allowed to receive a second CPAA token.

[0045] Figure 4B and Figure 1 The diagram illustrates multiple PEs 102(0), 102(1), and 102(P) with... Figure 4A An exemplary communication flow between SPCOP 120s, where PE 102(0), 102(1), and 102(P) each attempt to obtain a CPAA token (assuming only a single CPAA token is available in this example). For clarity, in the description Figure 4B and Figure 1 Time Reference Figure 3 and Figure 4A Components. In Figure 4B and Figure 4A In the message flow diagram 400, PE 102(0), 102(1), and 102(P) and SPCOP 120 are shown, represented by vertical lines. Communication between these elements is illustrated by arrows with headings, and the operations performed by each element are described by boxes with headings. Assuming... Figure 4B and Figure 3SPCOP 120 in the CPAA reservation queue 306 uses a bit vector or another implementation of the CPAA reservation queue where the identifiers of PE 102(0), 102(1), and 102(P) or the identifier of the CPAA token are not recorded. Figure 4A (CPAA reserved queue 306).

[0046] exist Figure 4B The operation begins with PE 102(P) sending a request 402 for a CPAA token to SPCOP 120, followed by PE 102(0) sending a request 404 for a CPAA token to SPCOP 120. SPCOP 120 distributes the CPAA token 406 to PE 102(P). Because SPCOP 120 also receives request 404 from PE 102(0), PE 102(0) is added to SPCOP 120's CPAA reservation queue 306, as indicated by box 407. Shortly thereafter, PE 102(1) also sends its own request 408 for a CPAA token and is also added to SPCOP 120's CPAA reservation queue 306, as indicated by box 409. After PE102(P) completes its atomic memory access, PE102(P) sends request 410 to return CPAA token 406 to SPCOP120. SPCOP120 confirms the return of CPAA token 406 by sending response 412 to PE102(P).

[0047] Then, SPCOP 120 reserves a CPAA token for the next PE (i.e., PE 102(0)) in the CPAA reservation queue 306 and begins communication exchange to distribute the CPAA token to PE 102(0). Therefore, SPCOP 120 sends a response 414 to PE 102(0) to retry its request 404 for the CPAA token. After receiving the response 414, PE 102(0) sends a request 416 for the CPAA token to SPCOP 120. SPCOP 120 then distributes the CPAA token 418 to PE 102(0). Communication then continues... Figure 4B Continued.

[0048] Turn now Figure 1After completing its atomic memory access, PE 102(0) sends request 420 to return CPAA token 418 to SPCOP 120. SPCOP 120 acknowledges the return of CPAA token 418 by sending response 422 to PE 102(0) and then sends response 424 to the next PE in the CPAA reservation queue 306 (i.e., PE 102(1)) to notify PE 102(1) to retry its request 408 for the CPAA token. Thus, PE 102(1) sends another request 426 for the CPAA token, and SPCOP 120 responds by distributing CPAA token 428. After completing its atomic memory access, PE 102(1) sends request 430 to return its CPAA token 428, and SPCOP 120 sends response 432 to acknowledge that CPAA token 428 has been returned.

[0049] It should be understood that, depending on the implementation of the CPAA reservation queue 306, SPCOP 120 may distribute tokens to PE 102(0) and 102(1) in an order different from the order in which the corresponding requests 404 and 408 of PE 102(0) and 102(1) are received by SPCOP 120. For example, suppose that the CPAA reservation queue 306 is implemented as a bit vector, and that request 408 of PE 102(1) is received before request 404 of PE 102(0). This would result in both bits indicating PE 102(1) and 102(0) being set in the CPAA reservation queue 306 when SPCOP 120 receives the corresponding requests 408 and 404 of PE 102(1) and 102(0). However, SPCOP 120 can still process the bits representing PE 102(0) and 102(1) in sequence, resulting in PE 102(0) issuing its CPAA token 418 before issuing its CPAA token 428 to PE 102(1).

[0050] For illustration Figures 5A-5C An exemplary communication flow between the SPCOP 120 and multiple PEs 102(0) and 102(P) provides Figures 5A-5C This example communication flow is used to log attempts to access coherent granules protected by active CPAA tokens using CPAA access queue 304 of SPCOP120. For clarity, in the description... Figure 1 Time Reference Figure 3 and Figures 5A-5C Components. In Figures 5A-5C In the example, it is assumed that the size of each address block 111(0)-111(A) is the same as the size of each coherent particle 110(0)-110(C). Figure 5AIn the message flow diagram 500, PE 102(0) and 102(P), COP 114 and SPCOP 120 are represented by vertical lines. The communication between these elements is illustrated by arrows with titles, and the operations performed by each element are described by boxes with titles.

[0051] exist Figure 1 In this process, the operation begins with PE 102(0) sending a request 502 to SPCOP 120 for a CPAA token. As a result of receiving request 502, SPCOP distributes the CPAA token 504 to PE 102(0). Then, PE 102(0) sends request 506 to obtain the first coherent particle in an exclusive state (e.g., Figure 5B The first coherent particle 110(0)). Around the same time, PE102(P) also sends request 508 to obtain the first coherent particle 110(0) in exclusive status. COP114 responds to PE102(0) by sending response 510, which grants exclusive access to the first coherent particle 110(0). Additionally, upon receiving request 508 from PE102(P), COP114 sends a snooping request 512 to PE102(0) for the first coherent particle 110(0) (which PE102(0) now holds in exclusive status). Simultaneously, PE102(0) sends request 514 to COP114 to seek exclusive access to the second coherent particle (e.g., coherent particle 110(1)). Communication then proceeds in Figure 5B Continued.

[0052] Now for reference Figure 5C Upon receiving the snooping request 512, PE 102(0) sends a response 516 to COP 114, instructing the requesting PE (i.e., PE 102(P)) to retry its request 508 to SPCOP 120. COP 114 then forwards a response 518 to PE 102(P), thereby notifying PE 102(P). COP 114 also sends a response 520 to PE 102(0), granting exclusive access to the second coherent particle 110(1). At this point, PE 102(0) can continue to perform its atomic memory accesses on the first coherent particle 110(0) and the second coherent particle 110(1).

[0053] Since a response 518 has been received from COP 114, PE 102(P) sends a request 522 to SPCOP 120 to seek exclusive access to the first coherent particle 110(0). SPCOP 120 determines that the request 522 from PE 102(P) corresponds to the active CPAA token 504, and therefore adds PE 102(P) to the CPAA access queue 304, as indicated by box 523. PE 102(0) (which has now completed its atomic memory access) sends a request 524 to return the CPAA token 504 to SPCOP 120, and SPCOP 120 sends a response 526 acknowledging that the CPAA token 504 has been returned. Since CPAA token 504 is no longer active, SPCOP 120 determines that PE 102(P) is no longer at risk of having an active CPAA token and therefore sends response 528 to PE 102(P), instructing it to retry its request 508 on the regular memory coherent processing path. PE 102(P) then sends request 530 to COP 114 to acquire the first coherent particle 110(0) in an exclusive state. Communication then proceeds... Figure 5C Continued.

[0054] Turn now Figure 1 As a result of receiving request 530, COP 114 sends a snooping request 532 to PE 102(0) for the first coherent particle 110(0). Then, PE 102(0) sends a response 534 indicating that PE 102(P) can obtain the desired access to the first coherent particle 110(0).

[0055] As mentioned above, Figure 1 Some embodiments of the processor-based device 100 may include a plurality of dies 116(0)-116(D), each of the dies 116(0)-116(D) may include a PE and an SPCOP, the PE and SPCOP being coupled with... Figure 6A The PE 102(0)-102(P) and SPCOP 120 of the 116(0) die are compatible. In this respect, Figure 6B and Figure 1 Message flow diagram 600 is provided, which illustrates the process located at... Figure 6A An exemplary communication flow between multiple SPCOPs and PEs on multiple dies 116(0)-116(D) of a processor-based device 100. For clarity, in the description Figure 6B and Figure 1 Time Reference Figure 1 The components. In this example, consider two dies, die A and die B, each of which can be coupled with... Figure 1It corresponds to one of the dies 116(0)-116(D). Die A includes PE 602 and SPCOP 604, which are functionally related to... Figure 1 The PE 102(0)-102(P) and SPCOP 120 correspond to these. Similarly, die B includes PE 606 and SPCOP 608, which are functionally also related to... Figure 6A PE 102(0)-102(P) and SPCOP 120 correspond to each other. SPCOP 604 and SPCOP 608 each ensure that the PE on their respective dies receives a CPAA token from system SPCOP 610 in turn, which in turn ensures that SPCOP 604 and SPCOP 608 receive a CPAA token in turn. In some embodiments, system SPCOP 610 may include one of SPCOPs, SPCOP 604 or SPCOP 608, or may include another SPCOP on another die. Figure 6B and Figure 6A As seen, each of the PE 602 and 606, SPCOP 604 and 608, and system SPCOP 610 is represented by a vertical line, and communication between these components is illustrated by arrows with headings.

[0056] exist Figure 6B In this process, the operation begins with PE 602 sending a request 612 for a CPAA token to SPCOP 604 of die A. SPCOP 604 forwards the request 612 to system SPCOP 610. Approximately simultaneously, PE 606 sends a request 614 for a CPAA token to SPCOP 608 of die B. SPCOP 608 forwards the request 614 to system SPCOP 610. System SPCOP 610 chooses to distribute CPAA token 616 to SPCOP 604, which then forwards CPAA token 616 to PE 602. System SPCOP 610 also adds SPCOP 608 to its own CPAA reservation queue, as indicated by box 617. After PE 602 completes its atomic memory access, PE 602 sends request 618 to return CPAA token 616. SPCOP 604 forwards CPAA token 616 to system SPCOP 610. System SPCOP 610 sends response 620 to SPCOP 604, acknowledging the return of CPAA token 616, which is then forwarded by SPCOP 604 to PE 602.

[0057] Then, system SPCOP 610 identifies SPCOP 608 as the next SPCOP to receive the CPAA token and therefore sends response 622 to SPCOP 608, instructing SPCOP 608 to retry its request for the CPAA token. SPCOP 608 then sends a request 624 for the CPAA token to system SPCOP 610. Communication then continues... Figure 6B Continued.

[0058] Now for reference Figure 1 System SPCOP 610 distributes CPAA token 626 to SPCOP 608, which forwards CPAA token 626 to PE 606. After PE 606 completes its atomic memory access, PE 606 sends request 628 to return CPAA token 626 to SPCOP 608, which forwards request 628 to system SPCOP 610. SPCOP 610 sends response 630 to SPCOP 608, acknowledging the return of CPAA token 626, and SPCOP forwards response 630 to PE 606.

[0059] To explain Figure 7A Exemplary operation of PE 102(0)-102(P) according to some embodiments, Figure 7B and Figure 7A Flowchart 700 is provided, illustrating these exemplary operations for requesting a CPAA token, obtaining exclusive access to the corresponding coherent particle pair 110(0)-110(C), and performing atomic memory access operations. For clarity, in the description... Figure 7B and Figure 1 Time Reference Figure 2 , Figures 5A-5C and Figure 7A Components. Figure 2 The operation begins when the first PE 102(0) of the plurality of PEs 102(0)-102(P) of the processor-based device 100 detects an atomic memory access request 122 that crosses the boundary between a first coherent particle 110(0) and a second coherent particle 110(1) of the system memory 106 of the processor-based device 100, wherein the least significant bit of the memory address used to select the first coherent particle 110(0) is the inverse of the least significant bit of the memory address used to select the second coherent particle 110(1) (box 702). The first PE 102(0) then sends a request for a CPAA token (such as...) to SPCOP 120. Figure 2 Request 202), the CPAA token is for address block 111(0) containing the first coherent particle 110(0) (box 704).

[0060] Subsequently, the first PE 102(0) receives from SPCOP 120 a CPAA token for address block 111(0) containing the first coherent granule 110(0). Figure 5A The CPAA token 204 indicates that a first PE 102(0) of a plurality of PEs 102(0)-102(P) is permitted to protect an address block 111(0) containing a first coherent particle 110(0) (box 706). In some embodiments, while the first PE 102(0) holds the CPAA token 204, the first PE 102(0) may receive a first snooping request (such as...) for the first coherent particle 110(0) from a second PE 102(P) of the plurality of PEs 102(0)-102(P). Figure 5C The spying request 512 (box 708). In response to receiving the first spying request 512 for the first coherent particle 110 (0), the first PE 102 (0) may send a first response to the second PE 102 (P) (i.e., Figure 7B In response 516), the first response 516 indicates that the second PE102(P) should redirect all requests for the first coherent granule 110(0) to SPCOP 120 until the CPAA token 204 is returned (box 710). Then, processing in Figure 7B Continue at frame 712.

[0061] Turn now Figure 8 The first PE 102(0) then acquires the first coherent particle 110(0) and the second coherent particle 110(1) in an exclusive state (box 712). According to some embodiments, if atomic memory access request 122 indicates a non-cacheable memory location, the first PE 102(0) may register atomic memory access request 122 with snoop filter 112 to indicate that a snoop request should be sent to the first PE 102(0) due to subsequent accesses to the non-cacheable memory location by the second PE 102(P) of the plurality of PEs 102(0)-102(P) (box 714). The first PE 102(0) then completes atomic memory access request 122 (box 716). Finally, the first PE 102(0) sends request 214 to return CPAA token 204 for the first coherent particle 110(0) to SPCOP (box 718).

[0062] Figure 1 Flowchart 800 is provided for illustration Figure 3 Exemplary operations of SPCOP 120, these exemplary operations are used to access queues (such as CPAA) Figure 1The CPAA access queue 304) is used to process coherent granularities protected by active CPAA tokens (e.g., Figure 8 Memory access of consecutive particles 110(0)-110(C)). For clarity, in the description Figure 1 Time Reference Figures 5A-5C and Figure 8 Components. In Figure 8 In the example, it is assumed that only one CPAA token can be active at a given time. Figure 1 In this process, the operation begins with SPCOP (such as...). Figure 5B SPCOP 120 receives a second request (such as PE 102(P)) from a second PE (such as PE 102(P)) for the first coherent particle 110(0). Figure 5A Request 522 (box 802). Then, SPCOP 120 determines whether the memory address of the second request 522 corresponds to an active CPAA token (such as...). Figure 1 The CPAA token 504 (box 804). If not, SPCOP 120 sends a second response to the second PE 102(P), which indicates that the second PE 102(P) should return to normal memory coherent processing (box 806).

[0063] If SPCOP 120 determines at decision box 804 that the memory address of the second request 522 does indeed correspond to the active CPAA token 504, then SPCOP 120 next determines whether its CPAA access queue 304 is full (box 808). If not, SPCOP records the identifier of the second PE 102(P) in the CPAA access queue 304 (box 810). Subsequently, when the first PE (e.g., Figure 1 When PE 102(P) returns CPAA token 504, SPCOP 120 sends a fourth response to PE 102(P) based on the identifier of PE 102(P) in CPAA access queue 304. The fourth response indicates that PE 102(P) should return to normal memory coherence processing (box 812). However, if SPCOP 120 determines at decision box 808 that CPAA access queue 304 is full, SPCOP 120 sends a third response to PE 102(P) indicating that PE 102(P) should retry second request 522 (box 814).

[0064] To explain Figure 9 Exemplary operation of SPCOP 120, Figure 3 Flowchart 900 is provided, and these exemplary operations are used to... Figure 9The CPAA reservation queue 306 is used to reserve CPAA tokens and for the subsequent distribution of reserved CPAA tokens. For clarity, in the description... Figure 1 Time Reference Figures 4A-4B and Figure 9 Components. In Figure 1 In this process, the operation begins with SPCOP (such as...). Figure 4A SPCOP 120) receives requests for CPAA tokens (such as...) from the first PE 102(0). Figure 4A Request 404 (box 900). SPCOP 120 determines whether the CPAA token is available (box 902). If not, SPCOP adds the first PE 102(0) to the CPAA reservation queue 306 (box 904).

[0065] If SPCOP 120 determines at decision box 902 that a CPAA token is available, then SPCOP 120 next determines whether atomic memory access request 122 corresponds to an active CPAA token (such as...). Figure 10 If so, the process continues at box 904. If SPCOP 120 determines at decision box 906 that atomic memory access request 122 does not correspond to active CPAA token 406, then SPCOP 120 determines whether the first PE 102(0) is the next in SPCOP 120's CPAA reservation queue 306 (box 910). If not, the process continues at box 904. However, if SPCOP 120 determines at decision box 910 that the first PE 102(0) is the next in the CPAA reservation queue 306, then SPCOP 120 distributes a CPAA token (i.e., CPAA token 418) to the first PE 102(0) (box 912). In some embodiments, the operation of distributing CPAA token 418 in box 912 may include: SPCOP 120 sending a response including CPAA token 418 to the first PE 102(0) (box 914). Some embodiments may specify that the operation of distributing the CPAA token 418 in block 912 may include SPCOP 120 sending a response (such as response 414) to the first PE 102(0) indicating that the first PE 102(0) should retry request 404 for the CPAA token for the address block containing the first coherent granule 110(0) (block 916). For example, the operation of block 916 may be performed in an embodiment in which the first PE 102(0) is the next in the CPAA reservation queue 306, and the CPAA reservation queue 306 is implemented such that the identifier of the first PE 102(0) is not stored, and therefore is not known to SPCOP 120 when the CPAA token 418 is to be distributed.

[0066] Figure 1 It is an exemplary processor-based device 1000 (such as...) Figure 1 A block diagram of a processor-based device 1000 that supports atomic memory access across coherent particle boundaries. The processor-based device 1000 can be one or more circuits including: an electronic board such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing board, a mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based device 1000 includes a processor 1002. The processor 1002 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc., and can correspond to... Figure 10 PE 102(0)-102(P). Processor 1002 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, processor 1002 includes an instruction cache 1004 for temporary fast access memory storage of instructions, and instruction processing circuitry 1010. Instructions fetched or prefetched from memory (such as from system memory 1008 via system bus 1006) are stored in instruction cache 1004. Instruction processing circuitry 1010 is configured to process instructions fetched into instruction cache 1004 and process the instructions for execution.

[0067] Processor 1002 and system memory 1008 are coupled to system bus 1006 and can be coupled to peripheral devices included in processor-based device 1000. It is well known that processor 1002 communicates with these other devices by exchanging address, control, and data information via system bus 1006. For example, processor 1002 can transmit bus transaction requests to memory controller 1012 in system memory 1008, which is an example of a peripheral device. Although... Figure 10 Not shown, but multiple system buses 1006 may be provided, each forming a different architecture. In this example, memory controller 1012 is configured to provide memory access requests to memory array 1014 in system memory 1008. Memory array 1014 includes an array of storage bit cells for storing data. As a non-limiting example, system memory 1008 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0068] Other devices can be connected to system bus 1006. For example... Figure 10As shown, for example, these devices may include system memory 1008, one or more input devices 1016, one or more output devices 1018, modem 1024, and one or more display controllers 1020. The input devices 1016 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 1018 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 1024 may be any device configured to allow data exchange with network 1026. Network 1026 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetext. TM Networks and the Internet. Modem 1024 can be configured to support any type of desired communication protocol. Processor 1002 can also be configured to access multiple display controllers 1020 via system bus 1006 to control information sent to one or more displays 1022. The multiple displays 1022 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0069] ​ The processor-based device 1000 may include a set of instructions 1028, which may be encoded using a reach-based explicit consumer naming model for execution by the processor 1002 for any application desired according to the instructions. The instructions 1028 may be stored in system memory 1008, the processor 1002, and / or instruction cache 1004 (as an example of non-transient computer-readable medium 1030). The instructions 1028 may also reside wholly or at least partially in system memory 1008 and / or within the processor 1002 during their execution. The instructions 1028 may also be transmitted or received via a network 1026 via a modem 1024, such that the network 1026 includes the computer-readable medium 1030.

[0070] Although the computer-readable medium 1030 is shown as a single medium in the exemplary embodiment, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions 1028. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions that, when executed by a processing device, causes the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0071] The embodiments disclosed herein include various steps. These steps can be formed by hardware components or embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with those instructions to perform the steps. Alternatively, these steps can be performed by a combination of hardware and software processes.

[0072] The embodiments disclosed herein can be provided as a computer program product or software process, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.).

[0073] Unless otherwise specifically stated and clearly understood from the foregoing discussion, it should be understood that throughout this specification, the use of terms such as “processing,” “calculating,” “determining,” and “displaying” refers to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities in the registers of the computer system into other data similarly represented as physical quantities in the computer system’s memory or registers or other such information storage, transmission, or display devices.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used in accordance with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will be clear from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0075] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of desired information. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this embodiment.

[0076] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0077] The embodiments disclosed herein can be embodied in hardware and in instructions stored in the hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0078] It should also be noted that the operational steps described in any exemplary embodiment herein are described to provide examples and discussion. The described operations can be performed in many different orders than those shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced in the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0079] Unless otherwise expressly stated, it is not intended to interpret any method described herein as requiring its steps to be performed in a particular order. Therefore, if a method claim does not actually describe the order in which its steps are followed, or if the claims or specification do not otherwise specifically state that these steps are limited to a particular order, then no particular order can be inferred.

[0080] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments that embody the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

Claims

1. A processor-based device, comprising: System memory, comprising multiple address blocks and multiple coherent granules; Dedicated central sorting point SPCOP, including SPCOP logic circuitry; as well as Multiple processing elements (PEs), each processing element including memory access logic circuitry; The memory access logic circuit of the first PE among the plurality of PEs is configured to: detect an atomic memory access request that crosses the boundary between a first coherent particle and a second coherent particle of the system memory. Send a request to the SPCOP for a Coherent Granule to Atomic Access CPAA token, the Coherent Granule to Atomic Access CPAA token being for an address block containing the first coherent granule. Receive the CPAA token from the SPCOP for the address block containing the first coherent granule, the CPAA token indicating that the first PE among the plurality of PEs is allowed to protect the address block containing the first coherent granule; The first coherent particle and the second coherent particle are obtained in an exclusive state; Complete the atomic memory access request; as well as A request is sent to the SPCOP to return the CPAA token for the address block containing the first coherent granule.

2. The processor-based device of claim 1, wherein the memory access logic circuitry of the first PE is further configured to: receive a first snooping request for the first coherent particle from a second PE of the plurality of PEs while the first PE holds the CPAA token; and In response to receiving the first snooping request for the first coherent particle, a first response is sent to the second PE, the first response instructing the second PE to redirect all requests for the first coherent particle to the SPCOP until the CPAA token is returned.

3. The processor-based device of claim 2, wherein the SPCOP logic circuit of the SPCOP is configured to: Receive a second request for the first coherent particle from the second PE; Determine whether the memory address requested by the second request corresponds to an active CPAA token; In response to determining that the memory address of the second request does not correspond to an active CPAA token, a second response is sent to the second PE, the second response indicating that the second PE should return to normal memory coherence processing; In response to determining that the memory address of the second request corresponds to an active CPAA token, it is determined whether the CPAA access queue of the SPCOP is full; In response to determining that the CPAA access queue of the SPCOP is full, a third response is sent to the second PE, the third response indicating that the second PE should retry the second request to the SPCOP; as well as In response to determining that the CPAA access queue of the SPCOP is not full: the identifier of the second PE is recorded in the CPAA access queue; as well as When the first PE returns the CPAA token, a fourth response is sent to the second PE based on the identifier of the second PE in the CPAA access queue. The fourth response indicates that the second PE should return to normal memory coherent processing.

4. The processor-based device of claim 1, wherein the SPCOP logic circuit of the SPCOP is configured to: receive a request for a CPAA token from the first PE; Determine if the CPAA token is available; In response to determining that a CPAA token is available, determine whether the atomic memory access request corresponds to an active CPAA token; as well as In response to determining that the atomic memory access request does not correspond to an active CPAA token, the CPAA token is distributed to the first PE.

5. The processor-based device of claim 4, wherein the SPCOP logic circuit of the SPCOP is configured to distribute the CPAA token to the first PE by being configured to send a response including the CPAA token to the first PE.

6. The processor-based device of claim 4, wherein the SPCOP logic circuit of the SPCOP is configured to distribute the CPAA token to the first PE by being configured to send a response to the first PE indicating that the first PE will retry requesting the CPAA token for the address block containing the first coherent granules.

7. The processor-based device of claim 4, wherein the SPCOP logic circuit of the SPCOP is further configured to: distribute the CPAA token to the first PE by being configured to perform the following operations: Determine whether the first PE is the next in the CPAA reservation queue of the SPCOP; and In response to determining that the first PE is the next in the CPAA reservation queue of the SPCOP, the CPAA token is distributed to the first PE.

8. The processor-based device of claim 7, wherein the SPCOP logic circuit of the SPCOP is further configured to: In response to determining that the CPAA token is unavailable, the first PE is added to the CPAA reservation queue; In response to determining that the atomic memory access request corresponds to an active CPAA token, the first PE is added to the CPAA reservation queue; and In response to determining that the first PE is not the next one in the CPAA reservation queue, the first PE is added to the CPAA reservation queue.

9. The processor-based device according to claim 1, wherein: The processor-based device also includes a spy filter; The atomic memory access request includes an atomic memory access request for a non-cacheable memory location. The memory access logic circuitry of the first PE is configured to exclusively acquire the first coherent particle and the second coherent particle by being configured to register the atomic memory access request to a snooping filter to indicate that the snooping request will be sent to the first PE when the second PE in the plurality of PEs subsequently accesses the non-cacheable memory location.

10. A method for supporting atomic memory access across coherent particle boundaries, comprising: An atomic memory access request is detected by a first PE among a plurality of processing elements PE of a processor-based device, the atomic memory access request crossing the boundary between a first coherent granularity and a second coherent granularity of the system memory of the processor-based device. The first PE sends a first request for a Coherent Granular to Atomic Access CPAA token to the Dedicated Central Sequencing Point (SPCOP), the Coherent Granular to Atomic Access CPAA token being for an address block containing the first coherent granule. The first PE receives from the SPCOP the CPAA token for the address block containing the first coherent particle, the CPAA token indicating that the first PE among the plurality of PEs is allowed to protect the address block containing the first coherent particle; The first coherent particle and the second coherent particle are obtained from the first PE in an exclusive state; The atomic memory access request is completed by the first PE; as well as The first PE sends a request to the SPCOP to return the CPAA token for the address block containing the first coherent granules.

11. The method of claim 10, further comprising: While the first PE holds the CPAA token, the first PE receives a first snooping request for the first coherent particle from the second PE among the plurality of PEs. as well as In response to receiving the first snooping request for the first coherent particle, the first PE sends a first response to the second PE, the first response instructing the second PE to redirect all requests for the first coherent particle to the SPCOP until the CPAA token is returned.

12. The method of claim 11, further comprising: The SPCOP receives a second request for the first coherent particle from the second PE; The SPCOP determines that the memory address of the second request does not correspond to an active CPAA token; as well as In response to determining that the memory address of the second request does not correspond to an active CPAA token, the SPCOP sends a second response to the second PE, the second response indicating that the second PE should return to normal memory coherence processing.

13. The method of claim 11, further comprising: The SPCOP receives a third request for the first coherent particle from the second PE; The SPCOP determines that the memory address of the third request corresponds to an active CPAA token; as well as In response to determining that the memory address of the third request corresponds to an active CPAA token, the SPCOP determines that its CPAA access queue is full. as well as In response to determining that the CPAA access queue of the SPCOP is full, the SPCOP sends a third response to the second PE, the third response indicating that the second PE should retry the third request to the SPCOP.

14. The method of claim 11, further comprising: The SPCOP receives a fourth request for the first coherent particle from the second PE; The SPCOP determines that the memory address of the fourth request corresponds to an active CPAA token; In response to determining that the memory address of the fourth request corresponds to an active CPAA token, the SPCOP determines that the CPAA access queue of the SPCOP is not full; as well as In response to determining that the CPAA access queue of the SPCOP is not full: the SPCOP records the identifier of the second PE in the CPAA access queue; as well as When the first PE returns the CPAA token, the SPCOP sends a fourth response to the second PE based on the identifier of the second PE in the CPAA access queue. The fourth response indicates that the second PE should return to normal memory coherent processing.

15. The method of claim 10, further comprising: The SPCOP receives the first request for the CPAA token from the first PE; The availability of the CPAA token is determined by the SPCOP. In response to determining that a CPAA token is available, the SPCOP determines that the atomic memory access request does not correspond to an active CPAA token; as well as In response to determining that the atomic memory access request does not correspond to an active CPAA token, the SPCOP distributes the CPAA token to the first PE.

16. The method of claim 15, wherein distributing the CPAA token to the first PE comprises: Send a response including the CPAA token to the first PE.

17. The method of claim 15, wherein distributing the CPAA token to the first PE comprises: A response is sent to the first PE, the response indicating that the first PE will retry requesting the CPAA token for the address block containing the first coherent granules.

18. The method of claim 15, further comprising: Determine that the first PE is the next one in the CPAA reservation queue of the SPCOP; In response to determining that the first PE is the next in the CPAA reservation queue of the SPCOP, the CPAA token is distributed to the first PE.

19. The method of claim 18, further comprising: The SPCOP receives a second request for the CPAA token from the first PE; The SPCOP determines that the CPAA token is unavailable; as well as In response to determining that the CPAA token is unavailable, the SPCOP adds the first PE to the CPAA reservation queue.

20. The method of claim 18, further comprising: The SPCOP receives a third request for the CPAA token from the first PE; The availability of the CPAA token is determined by the SPCOP. In response to determining that the CPAA token is available, it is determined that the atomic memory access request corresponds to an active CPAA token; as well as In response to determining that the atomic memory access request corresponds to an active CPAA token, the SPCOP adds the first PE to the CPAA reservation queue.

21. The method of claim 18, further comprising: The SPCOP receives a fourth request for the CPAA token from the first PE; The availability of the CPAA token is determined by the SPCOP. In response to determining that the CPAA token is available, it is determined that the atomic memory access request does not correspond to an active CPAA token; In response to determining that the atomic memory access request does not correspond to an active CPAA token, it is determined that the first PE is not the next one in the CPAA reservation queue; as well as In response to determining that the first PE is not the next one in the CPAA reservation queue, the SPCOP adds the first PE to the CPAA reservation queue.

22. The method of claim 10, wherein: The atomic memory access request includes an atomic memory access request for a non-cacheable memory location. as well as Obtaining the first coherent particle and the second coherent particle in an exclusive state includes: the first PE registering the atomic memory access request to a snooping filter to instruct the snooping request to be sent to the first PE in response to a subsequent access to the non-cacheable memory location by the second PE among the plurality of PEs.

23. A non-transient computer-readable medium having stored thereon computer-executable instructions, which, when executed by a processor, cause the processor to: Detect an atomic memory access request that crosses the boundary between a first coherent granule and a second coherent granule of the system memory, wherein the lowest order of the memory address used to select the first coherent granule is the inverse of the lowest order of the memory address used to select the second coherent granule. Send a request for a Coherent Granule to Atomic Access CPAA token to the dedicated central sorting point SPCOP of the processor, the Coherent Granule to Atomic Access CPAA token being for the address block containing the first coherent granule. Receive the CPAA token from the SPCOP for the address block containing the first coherent granule, the CPAA token indicating that the processor is allowed to protect the address block containing the first coherent granule; The first coherent particle and the second coherent particle are obtained in an exclusive state; Complete the atomic memory access request; as well as A request is sent to the SPCOP to return the CPAA token for the address block containing the first coherent granule.

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