Multi-output neural network slicing method, device, chip and storage medium

Abstract

The embodiment of the present application is applicable to the field of model processing technology, and provides a slicing method, device, chip and storage medium for a multi-output neural network. The method is applied to an intelligent chip, including: segmenting each terminal node in the multi-output neural network with other nodes respectively to generate multiple network subgraphs containing terminal nodes; for any network subgraph, slicing the output data of the terminal nodes of the network subgraph according to a plurality of preset slicing methods to obtain a plurality of slicing schemes of the network subgraph; for any slicing scheme of the network subgraph, obtaining the processing time of the network subgraph, and determining the target slicing scheme of the network subgraph according to the processing time; determining the slicing scheme of the multi-output neural network according to the target slicing scheme of each network subgraph. The above method can reduce the number of times the multi-output neural network graph accesses the external memory when processing input data.

Description

Technical Field

[0001] The present application belongs to the field of model processing technology, and in particular to a slicing method, device, chip and storage medium for a multi-output neural network. Background Art

[0002] The neural network compilation framework (Tensor Virtual Machine, TVM) is a unified software stack for different neural network frameworks and hardware platforms, which can deploy neural networks under different frameworks on the hardware platform.

[0003] Usually, a neural network processes input data in a smart chip to obtain output data. However, the available space inside a smart chip is often relatively small. For a neural network that requires a large amount of storage space to process data, the available space inside the smart chip is far from enough. Therefore, in the process of data processing, for any node included in the neural network, it is often necessary to store the output data of the node in an external memory first. Then, the input data of the node stored in the storage space at this time and the generated output data are deleted first. Finally, the output data of the node is obtained from the external memory and used as the input data of the next node to complete the data processing.

[0004] Therefore, in order to reduce the available space required by the neural network for data processing, the neural network needs to be segmented first to obtain network subgraphs. After that, the segmented network subgraphs are sliced ​​so that when the network subgraph processes data according to the slicing method, the available space required for each node in the network subgraph will be reduced, so that the output data generated by each node can be stored in the internal storage space, reducing the number of accesses to the external memory.

[0005] However, when the network subgraph is sliced ​​using the above slicing method, the current TVM scheduling primitive cannot support the output data of the forked node to be processed in multiple network subgraphs at the same time. As a result, there is no reasonable slicing scheme for slicing the network subgraph of a multi-output neural network in the prior art, so that when the existing multi-output neural network processes data, the output data of the forked node still needs to be stored in the external memory, and the number of accesses to the external memory cannot be reduced. Summary of the invention

[0006] The embodiments of the present application provide a slicing method, device, intelligent chip and storage medium for a multi-output neural network graph, which can solve the problem that the existing multi-output neural network graph needs to frequently access external memory when processing input data.

[0007] In a first aspect, an embodiment of the present application provides a slicing method for a multi-output neural network, the method being applied to a smart chip, the method comprising:

[0008] Each terminal node in the multi-output neural network is respectively divided from other nodes to generate a plurality of network subgraphs including the terminal nodes; the multi-output neural network includes at least two terminal nodes and at least one bifurcation node;

[0009] For any network subgraph, the output data volume of the output data of the terminal node of the network subgraph is sliced ​​according to a plurality of preset slicing methods to obtain a plurality of slicing schemes of the network subgraph;

[0010] For any slicing scheme of the network subgraph, obtain the processing time of the network subgraph, and determine the target slicing scheme of the network subgraph according to the processing time;

[0011] According to the target slicing scheme of each network subgraph, the slicing scheme of the multi-output neural network is determined.

[0012] In a second aspect, an embodiment of the present application provides a slicing device for a multi-output neural network, which is applied to a smart chip, and the device includes:

[0013] A segmentation module is used to segment each terminal node in the multi-output neural network from other nodes respectively to generate multiple network subgraphs containing terminal nodes; the multi-output neural network includes at least two terminal nodes and at least one bifurcation node;

[0014] A slicing module is used to slice the output data volume of the output data of the terminal nodes of any network subgraph according to a plurality of preset slicing methods to obtain a plurality of slicing schemes of the network subgraph;

[0015] A processing time acquisition module is used to acquire the processing time of the network subgraph for any slicing scheme of the network subgraph, and determine the target slicing scheme of the network subgraph according to the processing time;

[0016] The slicing scheme determination module is used to determine the slicing scheme of the multi-output neural network according to the target slicing scheme of each network subgraph.

[0017] In a third aspect, an embodiment of the present application provides an intelligent chip, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of the first aspect described above when executing the computer program.

[0018] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the method of the first aspect described above is implemented.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product, which, when executed on a computer, enables the computer to execute the method of the first aspect.

[0020] Compared with the prior art, the embodiment of the present application has the following beneficial effects: by characterizing the multi-output neural network in the form of a multi-output neural network graph, and then, for each terminal node in the multi-output neural network graph, the terminal node is respectively divided from other nodes to obtain a network subgraph corresponding to each node. Afterwards, in each network subgraph, the output data of the terminal node of each network subgraph is sliced ​​according to a preset plurality of slicing methods to control the amount of input and output data of each network subgraph when processing data, and obtain a plurality of slicing schemes. Afterwards, the target slicing scheme of the network subgraph is determined according to the processing time when the network subgraph processes the data. Finally, the slicing scheme of the multi-output neural network as a whole is obtained. In this way, when the multi-output neural network processes the data, the input and output data are processed according to the slicing scheme of the multi-output neural network, so that the output data between the nodes can be stored in the available space of the smart chip, and then, each node can directly obtain data from the available space when processing the data, so as to reduce the number of accesses of the smart chip to the external memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a flowchart of an implementation method of a multi-output neural network slicing method provided in one embodiment of the present application;

[0023] Figure 2 It is a schematic diagram of a multi-output neural network graph and a structure of a multi-output neural network graph in a multi-output neural network slicing method provided in an embodiment of the present application;

[0024] Figure 3 This is a schematic diagram of an implementation method of S101 of a multi-output neural network slicing method provided in an embodiment of the present application;

[0025] Figure 4 is a flowchart of an implementation method of a multi-output neural network slicing method provided in another embodiment of the present application;

[0026] Figure 5This is a schematic diagram of a processing scenario of a single-output neural network processing input data in a smart chip provided by an embodiment of the present application;

[0027] Figure 6 This is a schematic diagram of a processing scenario of a multi-output neural network graph processing input data in a smart chip provided by an embodiment of the present application;

[0028] Figure 7 It is a structural schematic diagram of a slicing device for a multi-output neural network graph provided in one embodiment of the present application;

[0029] Figure 8 It is a schematic diagram of the structure of a smart chip provided in one embodiment of the present application. DETAILED DESCRIPTION

[0030] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0031] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0032] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0033] The slicing method of a multi-output neural network provided in an embodiment of the present application can be applied to an intelligent chip. Among them, the intelligent chip is a chip that loads each model parameter in the multi-output neural network diagram, and processes the input data input to each node according to the model parameters under each node. Among them, since the output data calculated by a single node of the multi-output neural network diagram is usually large and cannot be stored in the internal memory of the intelligent chip, the output data needs to be directed to an external memory. Therefore, it is necessary to access an external memory to save the output data of a single node under the multi-output neural network diagram. And, since there are also multiple nodes in the neural network, based on this, when the intelligent chip performs neural network calculation processing on the input data of each node, the intelligent chip needs to frequently access the external memory.

[0034] The above-mentioned smart chip includes but is not limited to a central processing unit, a graphics processing unit, a neural network processor, etc. The above-mentioned internal memory is an on-chip memory of the smart chip. The above-mentioned external memory can be a double-rate synchronous dynamic random access memory. Usually, the storage space of the external memory is much larger than the storage space of the on-chip memory.

[0035] Based on this, see Figure 1 , Figure 1 The present invention shows a flowchart of a slicing method for a multi-output neural network provided in an embodiment of the present invention. The nodes in the multi-output neural network can be merged so that the merged multi-output neural network can reduce the number of accesses to the external memory when processing data. The method includes the following steps:

[0036] S101, the intelligent chip separates each terminal node in the multi-output neural network from other nodes respectively, and generates multiple network subgraphs containing terminal nodes; the multi-output neural network includes at least two terminal nodes and at least one bifurcation node.

[0037] In one embodiment, the multi-output neural network can be represented by a multi-output neural network graph. Figure 2 For example, Figure 2 It is a simple multi-output neural network diagram. The multi-output neural network diagram includes multiple nodes, each of which is used to represent a unit in the multi-output neural network that can be independently calculated on the smart chip. The arrows in the multi-output neural network diagram are used to represent the transmission direction of the output data between each node.

[0038] For example, refer to Figure 2 , Figure 2 X is a schematic diagram of the structure of a multi-output neural network. Figure 2 Y is a reference diagram of the network subgraph after multi-output neural network segmentation. Figure 2 It can be seen that the multi-output neural network graph includes 7 nodes, among which 3, 5, and 7 are output nodes (i.e., terminal nodes), 1 and 2 are bifurcation nodes, and 4 and 6 are ordinary nodes.

[0039] It should be noted that, in this embodiment, the above method is used to segment a multi-output neural network graph, so the multiple nodes include at least two terminal nodes and one bifurcation node. In this embodiment, there is no limit on the number of terminal nodes and bifurcation nodes.

[0040] In one embodiment, a segmented network subgraph includes an end node, so the segmented network subgraph includes at least two. The end node is segmented from other nodes, specifically: the smart chip uses a post-order traversal method to collect other nodes required by each end node according to the data transmission relationship between each node in the multi-output neural network graph, and segment them to obtain the corresponding network subgraph.

[0041] S102. The intelligent chip slices the output data of the terminal nodes of any network subgraph according to a plurality of preset slicing methods to obtain a plurality of slicing schemes of the network subgraph.

[0042] In the application, the above slicing method is specifically a method of slicing the output data volume of the output data of the terminal node. After slicing the output data volume, the output data volume size of the terminal node each time it outputs data can be determined. Based on the output data volume size, the network subgraph can determine the input data volume size each time the input data is processed, so that the smart chip can allocate enough available space for each node to process the input and output data.

[0043] Among them, the terminal node can output output data of any dimensional size. Therefore, when slicing the output data of the terminal node, there will be a variety of slicing schemes, which are not limited.

[0044] Exemplarily, the data processed by the multi-output neural network is usually image data, so the output data is explained using image data as an example.

[0045] In a specific embodiment, the information of the image data is usually represented by N, C, H, and W. Specifically, N represents the number of input image data; H represents the pixels of the image data in the vertical direction; W represents the pixels of the image data in the horizontal direction, and C represents the number of channels. Usually, if the entire image data is directly input into the node for processing, the output data volume of the output data will be very large. Therefore, in order to reduce the amount of data that the node processes each time the image data. The intelligent chip can slice the output data under the node to reduce the amount of input data when the terminal node and other nodes in the low network subgraph process the input data, as well as the amount of output data when outputting the data.

[0046] Exemplarily, when slicing the output data of the terminal node, the H axis is used for slicing, so that the size of the data processed by each node is the size of N, C, 1 / 2H, and W. Therefore, the node can only obtain data of half the image size as the input data of the node. Moreover, because only half the image size data is processed at a time, the output data of half the image size is also output by the terminal node at the end. Afterwards, the intelligent chip can first store the output data of half the image size in the internal memory, and if it is an end node, it can be output to the external memory; then, delete the half image size data processed by the fork node from the internal memory (because it does not need to be used, that is, the processed input data can be released); then, the data of the other half image size is processed again until the output data of the other half image size is obtained and saved. Based on this, the internal memory of the node finally needs to use the storage space of half the image size for storage in the process of generating the overall output data. If the node directly processes the input data of the entire image, the intelligent chip needs to allocate the storage space required for the node when the overall image data is input, and the storage space required when the output data of the overall image is generated.

[0047] Based on this, in one embodiment, multiple ways of slicing the output data of the terminal node include but are not limited to slicing C, H, and W respectively. That is, the above example is only one way of slicing the H axis.

[0048] Specifically, the method of slicing data can be: the smart chip obtains the minimum dimension of the output data that can be output by the terminal node, and the maximum dimension of the output data that can be output; the smart chip determines the output data of any dimension between the minimum dimension and the maximum dimension as the output data of the terminal node for slicing.

[0049] The above minimum dimension is the minimum dimension of image data that can be output by terminal nodes and non-forked nodes, and the above maximum dimension is the maximum dimension of image data that can be output by terminal nodes and non-forked nodes. Image data of each dimension is used as output data that can be output, that is, a slicing method for slicing terminal nodes and non-forked nodes.

[0050] The minimum dimension of the image data that can be output by the terminal node is usually 1 pixel, and the maximum dimension of the image data that can be output is usually the dimension of the entire image data.

[0051] Exemplarily, when the number of sheets N is 1 and the number of channels C is also 1, if the pixels H of the image data in the vertical direction have A slicing methods, that is, the image data is sliced ​​in the vertical direction with any dimension between [1, A]; and the pixels W of the image data in the horizontal direction have B slicing methods, that is, the image data is sliced ​​in the vertical direction with any dimension between [1, B], then the final slicing method for slicing the output data of the terminal node will have A*B types. In other embodiments, the number of channels C can also be multiple, for example, 3. Therefore, when the image data is segmented, the number of channels can also be segmented. Based on this, a variety of slicing methods in the network subgraph can be obtained, so that the smart chip can have more slicing schemes to choose from.

[0052] S103: For any slicing scheme of the network subgraph, the smart chip obtains the processing time of the network subgraph, and determines the target slicing scheme of the network subgraph according to the processing time.

[0053] In the application, the amount of input data when the network subgraph processes input data is different under each slicing scheme. Therefore, under each slicing scheme, the processing time of the network subgraph to process input data is usually different. Based on this, for multiple slicing schemes corresponding to any network subgraph, the smart chip can determine the slicing scheme with the shortest processing time as the target slicing scheme of the network subgraph, so as to improve the efficiency of the network subgraph in processing input and output data.

[0054] For example, refer to Figure 2 For the network subgraph after multi-output neural network segmentation, the intelligent chip can count all the valid slicing schemes of Figure A, and obtain the optimal slicing scheme with the lowest cycle and the shortest time through the chip costmodel as the target slicing scheme of the terminal node 3; and, count all the valid slicing schemes of Figure B, and obtain the optimal slicing scheme with the lowest cycle and the shortest time through the chip costmodel as the target slicing scheme of the terminal node 5; and, count all the valid slicing schemes of Figure C, and obtain the optimal slicing scheme with the lowest cycle and the shortest time through the chip costmodel as the target slicing scheme of the terminal node 7.

[0055] S104. The intelligent chip determines a slicing scheme for the multi-output neural network according to the target slicing scheme for each network subgraph.

[0056] It can be understood that after obtaining the target slicing scheme corresponding to each network subgraph one by one, each target slicing scheme is the slicing scheme of the multi-output neural network as a whole.

[0057] In this embodiment, a multi-output neural network is represented in the form of a multi-output neural network graph, and then, for each terminal node in the multi-output neural network graph, the terminal node is segmented from other nodes to obtain a network subgraph corresponding to each node. Afterwards, in each network subgraph, the output data of the terminal node of each network subgraph is sliced ​​according to a preset plurality of slicing methods to control the amount of input and output data of each network subgraph when processing data, and obtain a plurality of slicing schemes. Afterwards, the target slicing scheme of the network subgraph is determined according to the processing time when the network subgraph processes the data. Finally, the slicing scheme of the multi-output neural network as a whole is obtained. In this way, when the multi-output neural network processes the data, the input and output data are processed according to the slicing scheme of the multi-output neural network, so that the output data between the nodes can be stored in the available space of the smart chip, and then, each node can directly obtain data from the available space when processing the data, so as to reduce the number of accesses of the smart chip to the external memory.

[0058] See also Figure 3 , Figure 3 This is a schematic diagram of an implementation method of S101 of a multi-output neural network slicing method provided in an embodiment of the present application, which is described in detail as follows;

[0059] S1. The smart chip uses the end node as the first current node.

[0060] In one embodiment, the first current node is the node currently being processed. In this embodiment, since the multi-output neural network graph is processed using a subsequent traversal method, the first processed terminal node is the first current node.

[0061] S2. If the parent node of the first current node is a forked node, the smart chip determines whether the forked node has been segmented by the network subgraphs corresponding to other terminal nodes.

[0062] S3. If it is determined that the bifurcated node has been segmented by the network subgraphs corresponding to other terminal nodes, the intelligent chip segments each node between the first current node and the parent node to generate a network subgraph including the terminal node.

[0063] S4. If it is determined that the bifurcated node is not split by the network subgraphs corresponding to other terminal nodes, or if the parent node is a non-bifurcated node, the smart chip determines the parent node as the new first current node, and repeats S2-S4 until a network subgraph containing the terminal node is generated.

[0064] In one embodiment, Figure 2For example, when the first current node is terminal node 3, according to the data transmission relationship between the nodes in the multi-output neural network graph, the parent node is fork node 2. And fork node 2 is not split by the network subgraph corresponding to other terminal nodes at this time. Therefore, based on step S3, it can be seen that fork node 2 can be used as the new first current node, and steps S2-S4 are repeated until a network subgraph containing terminal node 3 is generated.

[0065] Among them, the situation of generating a network subgraph containing 3 can be the situation of step 2, or the situation that the new first current node has no parent node in the multi-output neural network graph. At this time, the smart chip can end the segmentation of the terminal node 3. Exemplarily, when segmenting the terminal node 3, if the new first current node is node 1, because node 1 is the starting node of the multi-output neural network graph, it has no parent node. Therefore, the network segmentation containing the terminal node 3 ends here, and a network subgraph containing nodes 1, 2, and 3 is obtained.

[0066] Afterwards, when the terminal node 5 is split, the initial first current node is the terminal node 5, and its parent node is the non-forked node 4. Therefore, based on step S4, the smart chip can use the non-forked node 4 as the new first current node. At this time, the previous node (that is, the new parent node) of the new first current node 4 is the forked node 2. However, based on the above description, it can be seen that the forked node 2 has been split by the network subgraph corresponding to the terminal node 3. Therefore, the smart chip will end the segmentation of the terminal node 5 and split the terminal node 5 and each node between the terminal node 5 and the new parent node 2 ( Figure 2 Only node 4) is split to generate a network subgraph containing the terminal node 5.

[0067] The segmentation method of terminal node 7 is similar to the segmentation method of terminal node 5, and no further description is given. It should be noted that the above example only takes terminal node 3 as the first terminal node to be processed. In other embodiments, terminal nodes 5 and 7 may also be taken as the first terminal nodes to be processed, respectively, and this is not limited.

[0068] Based on this, in this embodiment, each terminal node and other nodes are segmented in turn through a subsequent traversal method, so that a network subgraph corresponding to each terminal node can be accurately and quickly generated, thereby improving the efficiency of the intelligent chip in segmenting multi-output neural network graphs.

[0069] It should be noted that each network subgraph includes some nodes in the multi-output neural network graph. In addition, slicing the multi-output neural network graph is only to adjust the input and output data size processed by each node in the multi-output neural network graph, and does not divide the multi-output neural network graph into multiple parts.

[0070] In another embodiment, when executing the above step S102, each network subgraph will generally have multiple slicing schemes. However, when executing step S103 later, if the smart chip counts the processing time corresponding to the network subgraph under each slicing scheme, it will take a lot of time. Based on this, before executing S103, the smart chip can also pre-determine whether the slicing scheme is a valid slicing scheme, and when the slicing scheme is a valid slicing scheme, the step of obtaining the processing time of the network subgraph is executed to reduce the time required by the smart chip.

[0071] See also Figure 4 , Figure 4 This is a schematic diagram of an implementation method for determining whether a slicing scheme is a valid slicing scheme in a slicing method for a multi-output neural network provided in an embodiment of the present application, which is described in detail as follows:

[0072] S41. The intelligent chip reversely infers the input data and output data of each node according to the output data volume of the output data of the terminal node after slicing.

[0073] In the application, after slicing the output data volume of the terminal node's output data, the size of each output data of the terminal node can be limited. Thus, according to the calculation parameters and calculation formulas in the terminal node, the smart chip can reversely infer the size of each input data of the terminal node. Afterwards, because the input data of the terminal node is the output data of the previous node, the smart chip can reversely infer the input data and output data of each node.

[0074] S42: For any node, the smart chip determines the target output data of the previous node of the node.

[0075] S43. The intelligent chip determines the occupied space of the node when it is executed according to the target output data, the input data and the output data of the node.

[0076] In one embodiment, the previous node is a node that is before the node in the multi-output neural network, which can be determined based on the data transmission relationship between each node.

[0077] In applications, the input data of a node is the output data of the previous node. Therefore, in order to determine whether a slicing scheme is a valid slicing scheme, the smart chip can determine a slicing scheme in which each node of the network subgraph does not need to obtain input data from an external memory when processing input and output data as a valid slicing scheme.

[0078] However, if each node in the network subgraph does not need to obtain input data from external memory when processing input and output data, it means that under this slicing scheme, when each node processes input and output data, the internal memory of the smart chip can allocate enough available space for the node. Based on this, for any node in any network subgraph, the smart chip needs to calculate the occupied space required by the node when processing input and output data.

[0079] In a specific embodiment, the smart chip can determine the occupied space in the following manner: determine all forked nodes before the node and the output data of each forked node; determine whether the output data of each forked node can be released, and use the output data of all forked nodes that cannot be released as target output data.

[0080] Furthermore, the smart chip can determine whether the output data of the forked node can be released in the following manner: if the output data of the forked node is also used by other network subgraphs, then it is determined that the output data of the forked node cannot be released; otherwise, it is determined that the output data of the forked node can be released.

[0081] In one embodiment, in order to reduce the number of interactions with the external memory, each chip usually needs to store the output data in the internal memory when generating output data so that it can be called by the next node. Because the output data of a non-forked node is the input data of the next node, when calculating the occupied space of any node, it is only necessary to determine the sum of the output data volume of the output data of the node and the input data volume of the input data as the occupied space required by the node. That is, there is no target output data at this time.

[0082] However, if the node has a forked node before, and the output data of the forked node needs to be used by other network subgraphs. That is, the output data of the forked node needs to be stored in the internal memory all the time. Therefore, when calculating the required occupied space of the node, it is also necessary to add the output data amount of the output data of the forked nodes that cannot be released to obtain the occupied space required by the node. That is, the output data of the forked nodes that have not been released at this time is the target output data. Among them, the purpose of judging whether the output data of the forked node is releasable is: when judging that the output data is releasable, the output data is deleted from the internal memory to increase the available space allocated by the internal memory to the next node as much as possible, so that the next node does not need to store the output data in the external memory, reducing the number of interactions with the external memory.

[0083] S44. If the occupied space of any node is smaller than the available space allocated by the smart chip to the corresponding node, the smart chip determines the slicing scheme as a valid slicing scheme.

[0084] In an application, when the space required by a node to process input and output data is less than the available space allocated by the smart chip to the corresponding node, it indicates that the internal memory of the smart chip has enough space to store the input data required by the node and the output data generated by the node.

[0085] In applications, the available space may be the total space of the internal memory of the smart chip, or the space remaining in the internal memory after storing the calculation parameters of the node when processing data, and there is no limitation on this.

[0086] It is understandable that the advantage of using an effective slicing scheme to slice the output data of the terminal node is that it reduces the amount of input data processed by the node each time and the amount of output data generated, thereby reducing the space required for each node to process input and output data. Furthermore, the smart chip can store the output data generated by each node in the internal memory to reduce the number of interactions with the external memory.

[0087] For example, assume that the size of the internal memory of the smart chip is Q. Q is the remaining space in the internal memory after removing the space occupied by the calculation parameters of the node in the internal memory. The space required for processing data in each non-forked node generally includes: the space occupied by the input data and output data of the node. Figure 2 To explain in detail:

[0088] For any slicing scheme, the input data and output data of each node under the scheme are obtained. Figure 2 For network subgraph A (a subgraph consisting of terminal node 3, fork node 1 and fork node 2), the output data of terminal node 3 is sliced, and the space required in the internal memory is input data = Q3a, output data = Q3b, which is recorded as Q3 = Q3a + Q3b. The output data of fork node 2 cannot be released and sliced, so the space required in the internal memory is input data = Q2a, output data = Q2b, which is recorded as Q2 = Q2a + Q2b. The output data of fork node 1 cannot be released and sliced ​​either, and the space required in the internal memory is input data = Q1a, output data = Q1b, which is recorded as Q1 = Q1a + Q1b. The reason why the output data of fork nodes 1 and 2 cannot be released and sliced ​​is that the output data of fork nodes 1 and 2 need to be reused (both graph A and graph C have nodes that need the output data of fork node 1, and both graph A and graph B have nodes that need the output data of fork node 2).

[0089] Here, it should be noted that for each node in the multi-output neural network, when any node performs backward inference based on the output data and generates the input data instantaneously, the node contains both the input data and the output data. Therefore, each node in this multi-output neural network needs to meet the most basic requirement: when the node generates the input data, the sum of the input data volume and the output data volume is less than or equal to the available space allocated by the intelligent chip for the node.

[0090] Therefore, when calculating the space of the internal memory required by the fork node 1, it is necessary to satisfy Q1 < Q. Then calculate the occupied space required by the fork node 2, otherwise this slicing scheme is invalid. However, since the input data of the fork node 2 is the output data of the fork node 1, and in the actual processing process, after the fork node 1 calculates the output data based on the input data, the input data does not need to be stored in the internal memory. At this time, only the output data of the fork node 1 is stored in the internal memory. And because the input data of the fork node 2 is the output data of the fork node 1. Therefore, when calculating the occupied space required by the fork node 2, since the input data of the fork node 1 has been deleted and the output data of the fork node 1 is the input data of the fork node 2. Based on this, when calculating the occupied space required by the fork node 2, as long as Q2 < Q is satisfied, then calculate the end node 3, otherwise this slicing method is invalid. When calculating the occupied space required by the end node 3, the input data of the end node 3 is the output data of the fork node 2, and the output data of the fork node 1 also needs to be used by other nodes (the node 6 in Figure C needs to use it). Therefore, when calculating the occupied space required by the end node 3, it is necessary to satisfy Q3 + Q1b. If Q3 + Q1b < Q, then this slicing scheme is valid, otherwise this slicing scheme is invalid.

[0091] After slicing in Figure A, since the output data Q1b and Q2b of the fork node 1 and the fork node 2 will be referenced by Figures B and C, they cannot be released.

[0092] Figure B is a network sub - graph containing the end - node 5 and the non - branching node 4. Among them, for the non - branching node 4, the space of the internal memory it requires is that the input data of the non - branching node 4 = Q4a, and the output data = Q4b, denoted as Q4 = Q4a + Q4b. However, when slicing Figure A, Q1b of the branching node 1 and Q2b of the branching node 2 are not released, and the output data Q2b of the branching node contains the input data Q4a of the non - branching node 4. Therefore, the occupied space required for the non - branching node 4 to process the input data is: when Q4b + Q1b + Q2b < Q, the end - node 5 can be calculated; otherwise, the slicing scheme for the end - node 5 is invalid. When calculating the end - node 5, since the input data of the end - node 5 is exactly the output data of the non - branching node 4, and at this time the input data Q4a (i.e., Q2b) of the non - branching node 4 can be released (not needed in Figure C). Therefore, the second occupied space required for the end - node 5 needs to satisfy Q5+Q1b (the output data of the branching node 1 still needs to be used by Figure C and is not released). If Q5 + Q1b < Q, then this slicing method is valid; otherwise, this slicing method is invalid.

[0093] Similarly, after slicing Figure B, the output data Q2b of the branching node 2 has been released, but the output Q1b of the branching node 1 still cannot be released because Figure C still needs to use it. When slicing Figure C, Q1b is still needed. Among them, when using Figure C, it is necessary to judge whether the occupied space required by each node meets the available space of the intelligent chip, which is similar to the above, and will not be explained here.

[0094] It should be noted that in multiple network sub - graphs, if there is any network sub - graph without an effective slicing scheme, it indicates that the slicing of the entire multi - output neural network fails. In addition, the above - mentioned output data is the data when determining whether the slicing scheme is an effective slicing scheme, which is a reverse - deduction process from the output to the input; after the reverse - deduction ends, if during the reverse - deduction process, when slicing the output data with the X slicing scheme, the intelligent chip can allocate sufficient available space for each node. Then, when the multi - output neural network uses the same slicing method to limit the size of the input data processed by the node, the intelligent chip should also be able to allocate sufficient available space for each node to store the output data generated by each node.

[0095] In another embodiment, after determining the slicing scheme of the multi - output neural network, it is also necessary to set the operators that process the input and output data in the multi - output neural network so that the operators can process the input and output data according to the slicing scheme.

[0096] Specifically, each node respectively includes multiple operators that process the input data and / or output data, and each operator needs to call the corresponding scheduling statement for implementation. Among them, the slicing method of the multi - output neural network further includes:

[0097] For any node in the multi-output neural network graph, the intelligent chip obtains the starting operator among multiple operators that first processes the input data of the node, and the ending operator that last processes the output data of the node.

[0098] If the node is an end node, the smart chip calls a first scheduling statement to execute a first operation when running the starting operator; and, when running the ending operator, calls a second scheduling statement to execute a second operation, and a third scheduling statement to execute a third operation; the first operation is used to read input data from the available space of the smart chip to the starting operator; the second operation is used to write the output data generated by the ending operator into the internal memory; and the third operation is used to write the output data generated by the ending operator of the end node into the external memory.

[0099] If the node is a starting node in a multi-output neural network, the intelligent chip calls the fourth scheduling statement and the first scheduling statement for executing the fourth operation when running the starting operator of the starting node; and, when running the ending operator of the starting node, calls the second scheduling statement; the fourth scheduling statement is used to read input data from an external memory to the starting operator of the starting node.

[0100] If the node is an intermediate node, the smart chip calls the first scheduling statement when running the start operator in the intermediate node; and calls the second scheduling statement when running the end operator in the intermediate node.

[0101] In one embodiment, a node is the smallest processing unit in a multi-output neural network graph, which contains a calculation formula for input data. A node usually contains a large number of operators to process the input data.

[0102] When a node includes multiple operators, the first operator in the node that processes input data is the starting operator, and the last operator that generates output data is the ending operator.

[0103] In one embodiment, the first operation may specifically be an operation for processing by the starting operator. Specifically, the first operation is used to read the input data required by the starting operator in the node. At this time, when the node is not the starting node of the multi-output neural network, the first operation is an operation for reading the input data required by the starting operator from the internal memory. If it is a starting node, it is necessary to perform the fourth operation of reading the required input data from the external memory; and when reading the input data, the input data must first be stored in the internal memory, and then the input data is read from the internal memory.

[0104] In one embodiment, the second operation is used to write the output data of the end operator into the available space. It is understandable that if the node belongs to an end node, the output data generated by the end operator not only needs to be written into the internal memory, but also needs to perform a third operation of writing the output data into the external memory. However, for intermediate nodes (non-starting nodes and end nodes), it is only necessary to perform the second operation of writing the output data generated by the end operator into the available space of the internal memory, and perform the first operation of reading the input data from the available space of the internal memory.

[0105] Among them, refer to Figure 2 , the starting node is Figure 2 The fork node 1 in Figure 2 The nodes in the middle are 3, 5, and 7. Figure 2 Nodes 2, 4, and 6 in .

[0106] It should be noted that when generating a scheduling statement for each operator, it can fuse multiple operators in a node, so that multiple operators in the same node are combined and placed in the same core. In this way, the smart chip can use operator fusion to avoid moving the data of the forked node to the external memory, which can effectively reduce the number of data transfers and save the processing time of the smart chip.

[0107] For example, the post-order access method is used to schedule graphs A, B, and C respectively according to the searched optimal slicing method. Assume that the last operator (compute_op) of each child node is recorded as the end operator (END_OP), and the first operator (compute_op) is recorded as the start operator (START_OP). Figure 2 To explain in detail:

[0108] In Figure A: With the END_OP of the end node 3 as the first root node 1, the split primitive is called to slice the N, C, H, and W axes. The compute_op that moves the output data to the DM (internal memory) and DDR (external memory) is generated through cache_write (storage write operation) END_OP. The compute_op that moves the DM data to the computing unit is generated through cache_read (storage read operation) START_OP. If the compute_op contains parameters, cache_read is also required to generate the compute_op that moves the DDR data to the DM and computing unit, and all compute_ops are moved to the axis corresponding to the root node 1 through compute_at.

[0109] Get the output data of fork node 2, set the END_OP of fork node 2 to the second root node 2, and generate a compute_op to move the output data to DM through cache_write END_OP. Cache_read START_OP generates a compute_op to move DM data to the compute unit. If compute_op contains parameters, cache_read is also required to generate a compute_op to move DDR data to DM and compute unit, and move all compute_ops to the axis corresponding to root node 2 through compute_at.

[0110] Fork node 1 uses a similar method to fork node 2, setting the END_OP of fork node 1 to the second root node 3. Since fork node 1 is the first node of the multi-output neural network, cache_read START_OP needs to generate compute_op to move DDR data to DM and computing unit.

[0111] In Figure B: The END_OP of output node 5 calls the split primitive for slicing the N, C, H, and W axes of the first root node 4. The compute_op that moves the output data to DM and DDR is generated through cache_write END_OP. The compute_op that moves DM data to the compute unit is generated through cache_read START_OP. The parameters required in the compute_op also require cache_read to generate the compute_op that moves DDR data to DM and the compute unit, and all compute_ops are moved to the axis corresponding to the first root node 4 through compute_at.

[0112] Node 4 generates a compute_op to move output data to DM through cache_write END_OP. cache_read START_OP generates a compute_op to move DM data to the compute unit. If the required parameters in compute_op are required, cache_read also generates a compute_op to move DDR data to DM and compute unit, and all compute_ops are moved to the axis corresponding to the first root node 4 through compute_at.

[0113] In Figure C: The END_OP of output node 7 is the first root node 5, and the split primitive is called to slice the N, C, H, and W axes. The compute_op that moves the output data to DM and DDR is generated through cache_write END_OP. The compute_op that moves DM data to the compute unit is generated through cache_readSTART_OP. If the parameters required in the compute_op are required, cache_read is also required to generate the compute_op that moves DDR data to DM and the compute unit, and all compute_ops are moved to the axis corresponding to the first root node 5 through compute_at.

[0114] Node 6 generates compute_op to move output data to DM through cache_write END_OP, and generates compute_op to move DM data to compute unit through cache_read START_OP. If the parameters required in compute_op are required, cache_read is also required to generate compute_op to move DDR data to DM and compute unit, and all compute_ops are moved to the axis corresponding to the first root node 5 through compute_at.

[0115] It should be noted that split, cache_write, cache_read, compute_at, etc. are all scheduling primitives of TVM, and the above steps are mainly steps for improving the processing flow and reading and writing flow of input data and output data. That is, the above method can reduce the number of times the smart chip reads input data from the external memory. However, when each operator is running, it may also be necessary to move other calculation parameters from the external memory to process the input data. However, moving the calculation parameters requires access to the external memory. That is, the slicing method of the multi-output neural network graph described in this application can only reduce the number of times the multi-output neural network graph accesses input data from the external memory.

[0116] In one embodiment, referring to Figure 5 , Figure 5Schematic diagram of a processing scenario for a single-output neural network in a smart chip to process input data. Step 1: The smart chip obtains the input data of the single-output neural network from the external memory and stores it in the internal memory; Step 2: The smart chip reads the input data from the internal memory, and uses the model parameters in the computing unit A to process it to obtain the output data, and then stores the output data in the external memory. Step 3: The smart chip clears the output data and input data of node A; Step 4: Read the input data again from the external memory, and use the model parameters in the computing unit B to process it to obtain the output data; Step 5: Store the output data of node B in the external memory. Figure 6 It can be seen that for a single-output neural network model, when processing the input data in each node, it is necessary to perform an operation of accessing the external memory.

[0117] However, for multi-output neural networks, Figure 6 A processing scenario diagram for a multi-output neural network in a smart chip to process input data. Among them, this example is only explained by the multi-output neural network generated by nodes 1, 2, 3, 4, and 5. Specifically: Step 1: The smart chip obtains the input data of the multi-output neural network from the external memory and stores it in the internal memory. Step 2: For node 2, the smart chip can directly read the input data from the internal memory and delete the output data of node 1 in the internal memory; then, the output data of node 2 is stored in the internal memory; at the same time, based on the segmentation operation of the above network subgraph, it can be seen that even if the output data of node 2 is stored in the internal memory, the sum of the space occupied by the model parameters of the remaining nodes deployed in the internal memory and the space occupied by the generated output data will be less than the available space of the internal memory. Therefore, node 4 and terminal node 3 can directly obtain the output data of node 2 from the internal memory, and then node 4 will also put the generated output data into the internal memory to be read and processed by the terminal node 5; then, the smart chip executes Step 3 and Step 4: the output data generated by the terminal node 3 and the terminal node 5 are stored in the external memory.

[0118] from Figure 6 It can be seen that for a multi-output neural network, each node in each network subgraph realizes data interaction by reading and writing data stored in the internal memory. In this way, only one operation of accessing the external memory is required for the starting node and output node of the multi-output neural network.

[0119] See also Figure 7 , Figure 71 is a block diagram of a multi-output neural network slicing device provided in an embodiment of the present application. The multi-output neural network slicing device in this embodiment includes modules for executing Figure 1 , Figure 3 to Figure 4 For details, please refer to the steps in the corresponding embodiment. Figure 1 , Figure 3 to Figure 4 as well as Figure 1 , Figure 3 to Figure 4 For the convenience of explanation, only the parts related to this embodiment are shown. Figure 7 , the slicing device 700 for a multi-output neural network graph may include: a segmentation module 710, a slicing module 720, a processing time acquisition module 730 and a slicing scheme determination module 740, wherein:

[0120] The segmentation module 710 is used to segment each terminal node in the multi-output neural network from other nodes respectively to generate multiple network subgraphs containing terminal nodes; the multi-output neural network includes at least two terminal nodes and at least one bifurcation node.

[0121] The slicing module 720 is used to slice the output data volume of the output data of the terminal nodes of any network subgraph according to a plurality of preset slicing methods to obtain a plurality of slicing schemes of the network subgraph.

[0122] The processing time acquisition module 730 is used to acquire the processing time of the network subgraph for any slicing scheme of the network subgraph, and determine the target slicing scheme of the network subgraph according to the processing time.

[0123] The slicing scheme determination module 740 is used to determine the slicing scheme of the multi-output neural network according to the target slicing scheme of each network subgraph.

[0124] In one embodiment, the segmentation module 710 is further configured to:

[0125] S1. Take the terminal node as the first current node; S2. If the parent node of the first current node is a forked node, determine whether the forked node has been split by the network subgraphs corresponding to other terminal nodes; S3. If it is determined that the forked node has been split by the network subgraphs corresponding to other terminal nodes, split each node between the first current node and the parent node to generate a network subgraph containing the terminal node; S4. If it is determined that the forked node has not been split by the network subgraphs corresponding to other terminal nodes, or if the parent node is a non-forked node, determine the parent node as the new first current node, and repeat S2-S4.

[0126] In one embodiment, the slicing module 720 is further configured to:

[0127] The minimum dimension of the output data of the terminal node and the maximum dimension of the output data are obtained; between the minimum dimension and the maximum dimension, the output data of any dimension is determined as a slicing method for slicing the output data of the terminal node.

[0128] In one embodiment, the multi-output neural network graph slicing device 700 further includes:

[0129] The judgment module is used to judge whether a slicing scheme is a valid slicing scheme for any slicing scheme of the network subgraph, and if the slicing scheme is a valid slicing scheme, execute the step of obtaining the processing time of the network subgraph.

[0130] In one embodiment, the determination module is further configured to:

[0131] According to the output data volume of the output data of the terminal node after slicing, the input data and output data of each node are reversed respectively; for any node, the target output data of the previous node of the node is determined; according to the target output data, the input data and output data of the node, the occupied space when the node is executed is determined; if the occupied space of any node is less than the available space allocated by the smart chip to the corresponding node, the slicing scheme is determined as a valid slicing scheme.

[0132] In one embodiment, the determination module is further configured to:

[0133] Determine all forked nodes before the node and the output data of each forked node; determine whether the output data of each forked node can be released, and use the output data of all forked nodes that cannot be released as target output data.

[0134] In one embodiment, the determination module is further configured to:

[0135] If the output data of the forked node is also used by other network subgraphs, it is determined that the output data of the forked node cannot be released; otherwise, it is determined that the output data of the forked node can be released.

[0136] When it is understood that Figure 7 In the structural block diagram of the slicing device of the multi-output neural network graph shown in FIG, each module is used to execute Figure 1 , Figure 3 to Figure 4 The steps in the corresponding embodiments, and for Figure 1 , Figure 3 to Figure 4 Each step in the corresponding embodiment has been explained in detail in the above embodiment. Figure 1 , Figure 3 to Figure 4 as well as Figure 1 , Figure 3 to Figure 4 The relevant descriptions in the corresponding embodiments are not repeated here.

[0137] Figure 81 is a block diagram of a smart chip provided by an embodiment of the present application. Figure 8 As shown, the smart chip 800 of this embodiment includes: a processor 810, a memory 820, and a computer program 830 stored in the memory 820 and executable on the processor 810, such as a program for a slicing method for a multi-output neural network. When the processor 810 executes the computer program 830, the steps in each embodiment of the slicing method for a multi-output neural network described above are implemented, such as Figure 1 Alternatively, the processor 810 implements the above when executing the computer program 830 Figure 8 The functions of each module in the corresponding embodiment are, for example, Figure 7 For details on the functions of modules 710 to 740, please refer to Figure 7 Related description in the corresponding embodiment.

[0138] Exemplarily, the computer program 830 can be divided into one or more modules, one or more modules are stored in the memory 820, and are executed by the processor 810 to implement the slicing method of the multi-output neural network provided in the embodiment of the present application. One or more modules can be a series of computer program instruction segments that can perform specific functions, and the instruction segments are used to describe the execution process of the computer program 830 in the smart chip 800. For example, the computer program 830 can implement the slicing method of the multi-output neural network provided in the embodiment of the present application.

[0139] The smart chip 800 may include, but is not limited to, a processor 810 and a memory 820. Those skilled in the art will appreciate that Figure 8 The smart chip 800 is merely an example and does not constitute a limitation of the smart chip 800 , which may include more or less components than those shown in the figure, or combine certain components, or have different components.

[0140] The processor 810 may be a central processing unit, or other general-purpose processors, digital signal processors, application-specific integrated circuits, off-the-shelf programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0141] The memory 820 may be an internal storage unit of the smart chip 800, such as a hard disk or memory of the smart chip 800. The memory 820 may also be an external storage device of the smart chip 800, such as a plug-in hard disk, a smart memory card, a flash memory card, etc. equipped on the smart chip 800. Furthermore, the memory 820 may also include both an internal storage unit of the smart chip 800 and an external storage device.

[0142] An embodiment of the present application provides an intelligent chip, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the slicing method of the multi-output neural network in the above-mentioned embodiments is implemented.

[0143] An embodiment of the present application provides a computer-readable storage medium, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, a slicing method for a multi-output neural network as described in the above-mentioned embodiments is implemented.

[0144] An embodiment of the present application provides a computer program product. When the computer program product is run on a computer, the computer executes the slicing method of the multi-output neural network in the above-mentioned embodiments.

[0145] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A slicing method for a multi-output neural network, characterized in that: Applied to a smart chip, the method comprises: Each terminal node in the multi-output neural network is segmented with other nodes to generate a plurality of network subgraphs including the terminal nodes; the multi-output neural network includes at least two terminal nodes and at least one bifurcation node; For any network subgraph, the output data of the terminal nodes of the network subgraph are sliced ​​according to a plurality of preset slicing methods to obtain a plurality of slicing schemes of the network subgraph; For any slicing scheme of the network subgraph, obtain the processing time of the network subgraph, and determine the target slicing scheme of the network subgraph according to the processing time; Determining a slicing scheme for the multi-output neural network according to a target slicing scheme for each of the network subgraphs; The step of segmenting each terminal node in the multi-output neural network from other nodes to generate a network subgraph containing the terminal node comprises: S1, taking the terminal node as the first current node; S2. If the parent node of the first current node belongs to the forked node, determine whether the forked node has been split by the network subgraphs corresponding to the other terminal nodes; S3, if it is determined that the forked node has been segmented by the network subgraphs corresponding to the other terminal nodes, segment each node between the first current node and the parent node to generate a network subgraph including the terminal node; S4. If it is determined that the bifurcated node is not split by the network subgraphs corresponding to the other terminal nodes, or if the parent node is a non-bifurcated node, the parent node is determined as the new first current node, and S2-S4 are repeated.

2. The method according to claim 1, characterized in that The output data of the terminal nodes of the network subgraph are sliced ​​according to the preset multiple slicing methods to obtain multiple slicing schemes in the network subgraph, including: Obtaining the minimum dimension of the data that can be output by the terminal node and the maximum dimension of the data that can be output; Between the minimum dimension and the maximum dimension, the outputtable data of any dimension is determined as a slicing method for slicing the output data of the terminal node.

3. The method according to any one of claims 1 to 2, characterized in that: Before obtaining the processing time of the network subgraph, the method further includes: For any slicing scheme of the network subgraph, determine whether the slicing scheme is a valid slicing scheme, and if the slicing scheme is a valid slicing scheme, execute the step of obtaining the processing time of the network subgraph.

4. The method according to claim 3, characterized in that: The determining whether the slicing scheme is a valid slicing scheme includes: According to the output data amount of the output data of the terminal node after slicing, respectively inversely infer the input data and output data of each of the nodes; For any node, determine the target output data of the previous node of the node; Determine the occupied space of the node when it is executed according to the target output data, the input data and the output data of the node; If the occupied space of any node is smaller than the available space allocated by the smart chip to the corresponding node, the slicing scheme is determined to be a valid slicing scheme.

5. The method according to claim 4, characterized in that For any node, determine the target output data of the previous node of the node, including: Determine all the forked nodes before the node and the output data of each of the forked nodes; It is determined whether the output data of each of the forked nodes is releasable, and the output data of all the forked nodes that are not releasable are used as the target output data.

6. The method according to claim 5, characterized in that The determining whether the output data of each of the forked nodes is releasable includes: For any of the forked nodes, if the output data of the forked node is also used by other network subgraphs, it is determined that the output data of the forked node cannot be released; Otherwise, it is determined that the output data of the fork node can be released.

7. A slicing device for a multi-output neural network, characterized in that: Applied to a smart chip, the device comprises: A segmentation module, used to segment each terminal node in the multi-output neural network from other nodes respectively, to generate a plurality of network subgraphs containing the terminal nodes; the multi-output neural network includes at least two terminal nodes and at least one bifurcation node; A slicing module, for slicing the output data volume of the output data of the terminal nodes of any network subgraph according to a plurality of preset slicing methods, to obtain a plurality of slicing schemes of the network subgraph; A processing time acquisition module, used for acquiring the processing time of the network subgraph for any slicing scheme of the network subgraph, and determining a target slicing scheme of the network subgraph according to the processing time; A slicing scheme determination module, used to determine the slicing scheme of the multi-output neural network according to the target slicing scheme of each of the network subgraphs; The segmentation module is also used for: S1, taking the terminal node as the first current node; S2. If the parent node of the first current node belongs to the forked node, determine whether the forked node has been split by the network subgraphs corresponding to the other terminal nodes; S3, if it is determined that the forked node has been segmented by the network subgraphs corresponding to the other terminal nodes, segment each node between the first current node and the parent node to generate a network subgraph including the terminal node; S4. If it is determined that the bifurcated node is not split by the network subgraphs corresponding to the other terminal nodes, or if the parent node is a non-bifurcated node, the parent node is determined as the new first current node, and S2-S4 are repeated.

8. An intelligent chip, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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