Arithmetic logic unit, instruction processing method and computer equipment

Abstract

The invention provides an arithmetic logic unit, an instruction processing method and computer equipment. The arithmetic logic unit comprises an internal cache space, an address allocation module and an operation module; the internal cache space is used for caching a reusable first source operand; the address allocation module is used for allocating a first cache address of a target operand in a first source operand to the first instruction under the condition that the target operand with the same storage address exists in a second source operand required by the first instruction to be processed and the first source operand; the storage address is an address of the corresponding source operand in an external storage space deployed outside the arithmetic logic unit; the first cache address is a cache address of the target operand in the internal cache space; and the operation module is used for executing an operation corresponding to the first instruction based on the target operand in the first cache address.

Description

Technical Field

[0001] This application relates to computer technology, and more particularly to an arithmetic logic unit and instruction processing method, and a computer device. Background Technology

[0002] The Arithmetic Logic Unit (ALU) is the core component used to perform basic arithmetic and logical operations. During instruction execution, the ALU reads operands from memory and performs operations such as addition and multiplication according to the instruction type, finally writing the result back to the specified location. However, the ALU must wait for all operands to be ready before it can begin calculation, resulting in low utilization of source operands and hardware resources, and long data retrieval times. Summary of the Invention

[0003] This application provides an arithmetic logic unit and instruction processing method, as well as a computer device, which can reuse data in the internal cache space without having to read data from the external storage space again, thereby improving the utilization rate of the internal storage space and the utilization rate of the source operands.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides an arithmetic logic unit including: an internal cache space, an address allocation module, and an operation module; the internal cache space is used to cache reusable first source operands; the address allocation module is used to allocate the first cache address of the target operand in the first source operand to the first instruction when the second source operand required by the first instruction to be processed has a target operand with the same storage address as the first source operand; the storage address is the address of the corresponding source operand in the external storage space deployed outside the arithmetic logic unit; the first cache address is the cache address of the target operand in the internal cache space; the operation module is used to execute the operation corresponding to the first instruction based on the target operand in the first cache address.

[0005] This application provides an instruction processing method for an arithmetic logic unit, comprising: when a target operand with the same storage address exists between a second source operand required by a first instruction to be processed and a first source operand that can be reused in an internal cache space, the first cache address of the target operand in the first source operand is allocated to the first instruction; the storage address is the address of the corresponding source operand in an external storage space deployed outside the arithmetic logic unit; the first cache address is the cache address of the target operand in the internal cache space; and the operation corresponding to the first instruction is executed based on the target operand in the first cache address.

[0006] This application provides a computer device including an arithmetic logic unit, which is used to implement some or all of the steps in the above method.

[0007] The arithmetic logic unit provided in this application embodiment sets up an internal cache space inside the arithmetic logic unit. The internal cache space is used to cache reusable source operands, so that multiple instructions can reuse data in the internal cache space without having to read data from the external storage space again. This reduces the number of accesses to the external storage space, saves the time overhead of data reading, improves the utilization rate of the internal storage space and the utilization rate of the source operands, reduces the overall power consumption, and effectively alleviates the register access conflict problem caused by multiple instruction concurrency. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0009] Figure 1 A schematic diagram of the composition structure of an arithmetic logic unit provided in this application embodiment. Figure 1 ; Figure 2 A schematic diagram illustrating the implementation flow of an instruction processing method for an arithmetic logic unit provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the composition structure of an arithmetic logic unit in the prior art, provided for an embodiment of this application; Figure 4 A schematic diagram of the composition structure of an arithmetic logic unit provided in this application embodiment. Figure 2 ; Figure 5 A schematic diagram illustrating the composition of an internal cache space (internal register) in an arithmetic logic unit provided in this application embodiment; Figure 6 This is a schematic diagram illustrating the implementation process of reading arbitration in an arithmetic logic unit provided in an embodiment of this application. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0011] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0012] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to be limiting of this application.

[0014] In existing technologies, when executing instructions, the ALU usually needs to read the required operands from external memory one by one. Even if multiple instructions use the same source operands, they still need to be read repeatedly, resulting in resource waste and performance bottlenecks.

[0015] To address the aforementioned problems, this application proposes an improved ALU architecture. For example... Figure 1 As shown, the arithmetic logic unit (improved ALU) 10 includes: an internal cache space 11, an address allocation module 12, and an operation module 13; the internal cache space 11 is used to cache reusable first source operands; the address allocation module 12 is used to allocate the first cache address of the target operand in the first source operand to the first instruction when the second source operand required by the first instruction to be processed has a target operand with the same storage address as the first source operand; the storage address is the address of the corresponding source operand in the external storage space deployed outside the arithmetic logic unit; the first cache address is the cache address of the target operand in the internal cache space; the operation module 13 is used to execute the operation corresponding to the first instruction based on the target operand in the first cache address.

[0016] Arithmetic logic units (ALUs) can be deployed on processors or graphics processors and can be implemented through digital integrated circuits to perform arithmetic operations via circuits. These arithmetic operations may include, but are not limited to: arithmetic operations such as addition, subtraction, multiplication, and division; logical operations such as bitwise AND, bitwise OR, and bitwise XOR; and comparison and judgment operations.

[0017] The address allocation module, also known as the address allocation logic, is the control unit that manages address allocation in the internal cache space. Based on the needs of the current instruction, the address allocation module decides whether to use an existing cache address or allocate a new cache address for the new operand. The design goal of the address allocation module is to optimize cache utilization, reduce conflicts, and improve overall operating efficiency.

[0018] The arithmetic module, also known as the arithmetic unit, is used to perform specific arithmetic operations. In some implementations, if the second source operand required by the first instruction to be processed has an operand with the same storage address as the first source operand, the arithmetic module can execute the arithmetic operation defined by the first instruction based on the operand with the same storage address in the internal cache space (a reusable operand) to obtain the arithmetic result.

[0019] External storage space is a data storage device located outside the arithmetic logic unit (ALU), and can also be referred to as external memory. In some implementations, external storage space includes, but is not limited to, solid-state drives (SSDs), memory cards, network storage devices (NAS), and main memory. Data required by instructions is read from external storage space into an internal cache space so that the operation corresponding to the instruction can be executed by the arithmetic unit. Since external storage space has high access latency, this application reduces the frequency of access to external storage space by reusing data in the internal cache space.

[0020] The internal cache is a data storage device located within the arithmetic logic unit (ALU). In some implementations, the internal cache can be located on the ALU's computation path. The input of the internal cache can be connected to external storage, and the output can be connected to the arithmetic module. The internal cache can be an internal register, including multiple operand registers.

[0021] The first source operand refers to the reusable source operand in the internal cache. The second source operand refers to the source operand required when the first instruction is executed. The first instruction refers to the instruction currently pending processing. The destination operand is the operand with the same storage address as the second and first source operands; it can also be called a reusable operand. The first cache address refers to the cache address of the destination operand in the first source operand within the internal cache, used for quickly locating and accessing data in the internal cache.

[0022] An instruction can correspond to one or more source operands. For example, the ordinary MOV instruction only requires one source operand; the multiply-accumulate instruction requires three source operands. A source operand can be divided into multiple operands; for example, a 32-bit source operand can be divided into four 8-bit operands.

[0023] If the second source operand required by the first instruction contains a target operand in the first source operand, it indicates that the internal cache space caches part or all of the data in the first source operand. In this case, the first cache address of the target operand in the first source operand in the internal cache space is allocated to the first instruction, so that the first instruction can reuse the target operand at the first cache address without having to read this part of the data from the external storage space again. This reduces the number of accesses to the external storage space, saves the time overhead of data reading, and improves the utilization of the internal storage space and the source operand.

[0024] In some implementations, in response to a first instruction, the storage address of the second source operand required by the first instruction is matched one-to-one with the storage address of the first source operand to determine whether the second source operand and the first source operand have a target operand with the same storage address. If the second source operand and the first source operand have a target operand, the first cache address of the target operand in the first source operand in the internal cache space is allocated to the first instruction. Other data is read from the external storage space and cached at the first cache address. The target operand is retrieved from the internal storage space based on the first cache address. The operation corresponding to the first instruction is executed based on the other data read from the external storage space and the target operand read from the internal storage space. The storage address of the first source operand refers to the address of the first source operand in the external storage space, and the storage address of the second source operand refers to the address of the second source operand in the external storage space. The second source operand includes other data and the target operand.

[0025] In some implementations, the internal cache space may include multiple operand registers, each operand register may include multiple cache addresses; each cache address is used to cache a source operand. In this case, allocating the first cache address of the destination operand in the internal cache space to the first instruction means allocating the cache address of the operand register containing the destination operand to the first instruction.

[0026] In some implementations, if the target operand is not present in either the second source operand or the first source operand required by the first instruction to be processed, a new cache address is allocated to the first instruction. In this case, a target operand register can be selected from multiple operand registers according to the identifier of the second source operand; the cache address of the target operand register is then allocated to the first instruction. The target operand register can be an operand register whose register number matches the identifier of the second source operand. Matching means that the register number is the same as the identifier of the second source operand, or that the register number is a multiple of the identifier of the first source operand. Alternatively, the target operand register can be selected from multiple operand registers based on the number of times and the duration of operand register usage.

[0027] It should be noted that conflicts can occur when multiple parties request data access from external storage. These multiple parties include the ALU currently needing data access and other execution units within the graphics processing unit. This application stores data in the internal cache, eliminating the need to read data from external storage, saving one read operation and reducing external storage read conflicts. Since conflict handling is unnecessary, responding to other parties' read operations is faster, and the saved read operation can be used by other parties, reducing resource consumption and register access conflicts caused by multiple concurrent instructions. Other parties refer to ALUs and / or other execution units besides the current ALU. Furthermore, calculating A+B requires two reads from external storage; if A has already been stored in the internal cache, only one read is needed, improving computational efficiency.

[0028] The arithmetic logic unit provided in this application embodiment sets up an internal cache space inside the arithmetic logic unit. The internal cache space is used to cache reusable source operands, so that multiple instructions can reuse data in the internal cache space without having to read data from the external storage space again. This reduces the number of accesses to the external storage space, saves the time overhead of data reading, improves the utilization rate of hardware resources (internal storage space) and source operands, reduces overall power consumption, and effectively alleviates the register access conflict problem caused by multiple instruction concurrency.

[0029] In some embodiments, the arithmetic logic unit further includes a reuse check module; the reuse check module is configured to determine, from a plurality of source operands in the internal cache space, a first source operand with a first reusability flag of a first flag value; determine, from the first source operand, a comparison operand with a second reusability flag of a second flag value; compare the second source operand with the comparison operand one by one to determine whether the second source operand and the comparison operand have a target operand; the first flag value is used to characterize that the corresponding source operand has a reusable operand, and the second flag value is used to characterize that the corresponding operand is reusable.

[0030] The reuse check module is a hardware logic component within the arithmetic logic unit (ALU) used to analyze the reusability of source operands. In some implementations, the reuse check module may be constructed from combinational logic circuitry to compare the operand's address, task information, and validity in real time to determine whether reuse is permitted.

[0031] In some implementations, the reuse check logic can be an abstract description of the logic executed within the reuse check module. The reuse check logic encompasses all algorithms and rules used to determine whether operands are reusable. For example, the reuse check logic may include multiple sub-logic blocks such as address comparison, task consistency verification, and data validity detection, which work together to complete the reuse judgment function.

[0032] The internal cache space can store source operands of multiple instructions executed up to the current time. These source operands include reusable and non-reusable source operands. In some implementations, a first reusability flag can be used to distinguish between reusable and non-reusable source operands, and a second reusability flag can be used to distinguish between reusable and non-reusable operands within a source operand.

[0033] The first reusability flag refers to the reusability flag of the source operand, used to indicate whether the corresponding source operand contains reusable operands. A first reusability flag of the first value indicates that the corresponding source operand contains reusable operands; a first reusability flag of the fourth value indicates that the corresponding source operand does not contain reusable operands. The second reusability flag refers to the reusability flag of the operand, used to indicate whether the corresponding operand is reusable. A second reusability flag of the second value indicates that the corresponding operand is reusable; a first reusability flag of the third value indicates that the corresponding operand is not reusable.

[0034] The first reusability flag indicates the reusability of the source operand, and the second reusability flag indicates the reusability of the operand itself. Although the first and second reusability flags indicate different objects, their usage can be the same. In some implementations, both the first and second reusability flags can be a single bit or signal, and can be represented by `reuse`. For example, ... Figure 5 As shown, in the register file, the storage bits for each operand may include one bit, which is a second reusable flag used to indicate whether the corresponding operand is reusable. Each register may contain an additional bit, which is a first reusable flag used to record whether the source operand in the register has a reusable operand. For example, when the first reusable flag is 1 (first flag value), it indicates that the source operand in the register has a reusable operand; when the first reusable flag is 0 (fourth flag value), it indicates that the source operand in the register does not have a reusable operand. When the second reusable flag is 1 (second flag value), it indicates that the corresponding operand is reusable; when the second reusable flag is 0 (third flag value), it indicates that the corresponding operand is not reusable.

[0035] In some implementations, when any operand in a source operand can be reused, the second reusable flag of that operand can be set to 1, and the first reusable flag of the source operand containing that operand can also be set to 1. This allows us to determine not only which source operands can be reused, but also which operand among the reusable source operands can be reused. Thus, by using these two flag values, reusable operands can be quickly identified, improving data matching efficiency.

[0036] In some implementations, the reuse check module can first filter out first source operands whose first reusability flag is a first flag value from the internal cache space based on the first reusability flag of the source operands. Then, based on the second reusability flag of each operand, it can filter out operands to be compared whose second reusability flag is a first flag value from the internal cache space. Then, it can match the storage address of the operand to be compared with the storage address of the second source operand one by one to determine whether the second source operand and the operand to be compared have a target operand with the same storage address. If the second source operand and the operand to be compared have a target operand, it is determined that the first instruction can reuse the data in the internal cache space. If the second source operand and the target source operand do not have a target operand, it is determined that the first instruction cannot reuse the data in the internal cache space.

[0037] In some implementations, the internal cache space can cache multiple operands, each with a corresponding storage address identifier, task identifier, and data validity. Comparisons can be made based on these information. For example, if the storage address identifier of the operand to be compared matches that of the second source operand, and both operands belong to the same task and have valid data, then the operand to be compared is determined to have the same content as the second source operand, and the operand to be compared can be used as the target operand. This comparison process ensures that data reuse is only allowed under specific conditions, thereby guaranteeing data consistency and correctness.

[0038] In this embodiment, the reuse check module enables intelligent reuse management of operands. It can quickly identify reusable operands before executing the current instruction, thereby reducing the number of memory accesses, avoiding unnecessary data read operations, improving the operational efficiency of the arithmetic logic unit, reducing power consumption, and enhancing overall computing performance.

[0039] In some embodiments, the arithmetic logic unit further includes: a reusable data recording module; the reusable data recording module includes multiple recording spaces, the number of recording spaces being the same as the number of cache addresses contained in the internal cache space, each cache address being used to cache one source operand; the reusable data recording module is used to, when there is a first operand in the second source operand that can be reused by the second instruction, set the second reusable flags of the first operand in the first recording space to the second flag value and set the first reusable flag of the second source operand to the first flag value, and record the storage address of the first operand and the task identifier corresponding to the first operand in the first recording space; the first flag value is used to indicate that there is a reusable operand in the corresponding source operand, and the second flag value is used to indicate that the corresponding operand is reusable; the first recording space is the recording space corresponding to the first cache address, and the second instruction is other instructions executed after the first instruction.

[0040] A reusable data logging module is a hardware logic structure used to record data that can be reused by subsequent instructions. The reusable data logging module configures a corresponding logging space for each cache address in the internal cache space. For example, when the internal cache space can store five different source operands, the reusable data logging module will set up five logging spaces for each of these cache addresses.

[0041] Each record space stores metadata for the corresponding cache address, including but not limited to whether the corresponding cache address contains reusable data (indicated by a reusable flag), the task identifier of the operands within the corresponding cache address (used to distinguish data between different tasks), and the validity of each piece of data in the corresponding cache address. This metadata supports subsequent instructions in quickly querying and evaluating the currently cached data.

[0042] In some implementations, upon detecting that an operand within any source operand can be reused, the reusable data recording module sets the second reusable flag of this operand to a second flag value and the first reusable flag of this source operand to a first flag value in the recording space corresponding to the source operand, indicating that the operand is available for subsequent instructions. Simultaneously, the reusable data recording module also records the storage address of the operand detected by the reusable data recording module and the task identifier of the task to which the operand belongs in the target recording space, facilitating subsequent querying and matching of the storage address and task identifier. This mechanism ensures that only operands with reuse potential are marked and retained, thereby preventing resource waste. Furthermore, by recording the task identifier, the reusable data recording module can promptly clean up invalid data during task switching or at the end of the task, ensuring the accuracy and timeliness of cached content.

[0043] In this embodiment, by setting a record space that corresponds one-to-one with the cache address in the internal cache space, when the data in the internal cache address can be reused, the reusability flag, storage address, and task identifier of the reusable data can be recorded in the record space. This allows for quick determination of whether the cached data can be used directly without additional external memory queries, thereby reducing the number of external accesses, lowering data reading power consumption, improving the execution efficiency of the arithmetic logic unit, and ultimately enhancing the overall performance of the arithmetic logic unit.

[0044] In some embodiments, the reusable data recording module is further configured to, when the first operand is not present in the second source operand, set the second reusable flag of the first operand in the first recording space to a third flag value and the first reusable flag of the second source operand to a fourth flag value; the third flag value indicates that the corresponding operand is not reusable, and the fourth flag value indicates that the corresponding source operand does not have a reusable operand.

[0045] Setting the second reusable flag of the first operand in the first record space to the third flag value and setting the first reusable flag of the second source operand to the fourth flag value indicates that the second source operand cannot be reused, i.e., it cannot be used as a data source for subsequent instructions. For example, in a binary implementation, both the third and fourth flag values ​​can be 0, indicating that it is not reusable.

[0046] In this embodiment of the application, by introducing the setting method of the third flag value and the fourth flag value in the reusable data recording module, non-reusable operands can be accurately identified and marked, so as to optimize the management of internal registers, thereby improving the utilization efficiency of data cache, further reducing the number of external memory accesses, reducing power consumption, and improving overall computing performance.

[0047] In some embodiments, the address allocation module is further configured to, in the case where there is no target operand among the second source operand and the first source operand, determine the second cache address based on the previously allocated cache address according to the address allocation logic of the internal cache space, and allocate the second cache address to the first instruction.

[0048] If the target operand is not present in either the second source operand or the first source operand, it means that the data required by the first instruction is not in the internal cache space, and it needs to be read from the external storage space.

[0049] The previously allocated cache address refers to the cache address most recently allocated for a certain source operand. The second cache address is the new cache address allocated for the source operand of the first instruction.

[0050] In some implementations, the previously allocated cache address can be recorded; based on the recorded previously allocated cache address, the second cache address is determined according to address increment logic. Alternatively, the second cache address can be determined according to address round-robin logic. In this way, an available cache location can be quickly located based on the recorded previously allocated cache address, thereby improving the overall efficiency of address allocation.

[0051] In some implementations, the address allocation logic supports address round-robin logic, which automatically wraps back to the starting address when the maximum address is reached. The round-robin mechanism ensures that all cached addresses have a chance to be used.

[0052] In this embodiment of the application, the second cache address to be allocated for the first instruction is determined based on the previously allocated cache address, which can achieve efficient cache address allocation.

[0053] In some embodiments, the arithmetic logic unit further includes: an instruction cache module; the instruction cache module is used to store instruction information of the first instruction, the cache address of the second source operand in the internal cache space, and read indication information; the read indication information is used to indicate whether the corresponding operand needs to be read from the external storage space.

[0054] The instruction cache module is a preprocessing module that stores instruction information, parsed instruction information, the cache address corresponding to the instruction, and read indication information for the arithmetic module to access. Instruction information may include, but is not limited to, instruction length, arithmetic rules, result processing methods, and specific operations. Read indication information indicates whether the current operand can be retrieved from the internal cache space or must be read from external storage. When an operand is marked as not requiring external memory access, it is determined that the operand's data can be directly retrieved from the internal cache space.

[0055] In this embodiment of the application, by introducing an instruction cache module, the instruction information of the first instruction, the cache address of the second source operand in the internal cache space, and the reading indication information can be temporarily stored so that the arithmetic module can call them, thereby improving the instruction execution efficiency.

[0056] In some embodiments, the arithmetic logic unit further includes: a reading arbitration module; the reading arbitration module has a one-to-one correspondence with external storage space; the reading arbitration module is used to obtain the operand to be read from external storage space according to reading indication information when the second source operand contains other data besides the target operand, or when the second source operand and the first source operand do not contain the target operand; the operand to be read is cached in a first cache address; the operand to be read is other data or the second source operand; and an arithmetic module is used to execute the operation corresponding to the first instruction based on the target operand and / or the operand to be read in the first cache address.

[0057] The readout arbitration module coordinates multiple operand requests to read data from different external storage spaces. Its main function is to arbitrate these requests when multiple instructions simultaneously request access to the same external storage space, determining which requests can be processed immediately and which need to wait for the next cycle. Readout indication information is a control signal that guides data reading behavior, containing the address of the data to be read, the data size, and a multiplexing flag. Through this information, the readout arbitration module can accurately identify the data that needs to be read and initiate the corresponding read request.

[0058] There is a one-to-one correspondence between the readout arbitration module and the external storage space; that is, each external storage space is equipped with an independent readout arbitration module. This one-to-one correspondence ensures that data read requests from each external storage space are processed independently and efficiently, avoiding performance bottlenecks caused by shared arbitration resources. Furthermore, the readout arbitration module can make the arbitration process more flexible and precise when multiple instructions simultaneously request to read different operands from the same external storage space.

[0059] When a second source operand of an instruction contains some data that already exists in the first cache address (i.e., the storage address is the same), while another part of the data has not yet been read, the read arbitration module will determine the remaining data that needs to be retrieved from the external storage space based on the read indication information.

[0060] After receiving the reading instruction, the reading arbitration module sends a data read request to the corresponding external storage space and caches the returned data in the first cache address. By caching unread data in the first cache address, it ensures that all required data is ready in subsequent calculations, eliminating the need to access external storage space again, thereby reducing unnecessary read operations and power consumption.

[0061] After data caching is completed, since all data has been preloaded into the first cache address, the arithmetic module can directly extract data from the first cache address for calculation. This can improve calculation efficiency, reduce data access latency, and make the entire instruction execution process smoother and more efficient.

[0062] In this embodiment, by setting a one-to-one correspondence between the reading arbitration module and the external storage space, and by obtaining unread data from the external storage space according to the reading indication information and caching it to the first cache address, more efficient data reading and operand reuse can be achieved, thereby reducing the number of accesses to the external storage space, and thus reducing power consumption and improving the overall performance of the ALU.

[0063] In some embodiments, the read arbitration module is further configured to, when multiple third instructions simultaneously initiate read requests, employ a preset arbitration strategy to arbitrate the operand to be read from the multiple third instructions; the third instructions do not include instructions in which all source operands required for processing are contained in the first source operand; wherein the arbitration strategy includes at least one of the following: when there are second operands with the same storage address among the multiple third instructions, select the second operand with the smallest identifier, and mark the other operands except the second operand with the smallest identifier as not participating in the arbitration; select the third instruction with the longest cache time in the instruction cache module as the read instruction.

[0064] The instruction to be read is the one arbitrated from multiple third-party instructions. The operands to be read by the instruction to be read are the operands to be read. When multiple third-party instructions simultaneously initiate read requests, a read arbitration module is introduced to ensure system efficiency and rational resource utilization. The read arbitration module selects one or more high-priority operands from these concurrent requests for processing according to a preset arbitration strategy. The read arbitration module avoids conflicts and optimizes the data reading order in this way.

[0065] The purpose of arbitration strategies is to ensure that high-priority instructions or instructions that entered the cache queue earlier can obtain resources first. For example, when two instructions access the same memory address simultaneously, the instruction with the smaller operand identifier can be selected as the priority processing object to reduce the possibility of data overwriting and improve system stability.

[0066] When multiple third instructions fail to hit the internal cache, their priority can be determined based on the length of time they have been cached in the instruction cache module. A longer cache time means a longer wait time for that instruction; therefore, instructions with longer cache times can be given higher priority to reduce overall latency and improve processor response speed.

[0067] In this embodiment, a preset arbitration strategy is used to prioritize and select operands for multiple third instructions, which can effectively avoid conflicts when multiple instructions are read concurrently, improve data reading efficiency, and thus enhance the overall computing performance and resource utilization of the arithmetic logic unit (ALU).

[0068] In some embodiments, the readout arbitration module is further configured to, when an operand to be read is arbitrated, mark all operands with the same storage address as the operand to be read as successfully arbitrated, and mark all operands in other instructions (excluding the instruction to be read) with the same identifier as the operand to be read as not participating in arbitration in the current cycle in all readout arbitration modules.

[0069] Arbitration success means that a source operand of an instruction has passed the priority judgment of the read arbitration logic and is allowed to read data from external storage. Since the operand to be read has been selected, in order to avoid resource conflicts and repeated access to the same external storage space, all operands with the same storage address (i.e., data from different instructions but using the same address) are also marked as arbitration successful. This indicates that these operands can share the result obtained by the above read operation without needing to initiate an arbitration process again or send a new read request.

[0070] "Current cycle non-arbitration" means that certain operands will not enter the read arbitration process within the current clock cycle. Since these operands have the same identifier or memory address as the successfully arbitrated operands, they do not need to attempt to acquire memory access again. This mechanism reduces the number of arbitrations and resource contention, improving overall efficiency.

[0071] For example, in a processing queue containing multiple instructions, if the operand to be read for a certain instruction has been successfully read through arbitration, then all subsequent instructions with operands referencing the same address will be marked as successfully arbitrated, and these operands will not enter the arbitration process. Simultaneously, for operands in other instructions that have the same identifier (e.g., task ID + address) as the aforementioned operands, these operands will be marked as not participating in arbitration in the current cycle across all read arbitration modules, thus avoiding duplicate access and conflicts.

[0072] In this embodiment of the application, operands with the same address are uniformly marked as successful arbitration during the arbitration process, while other related operands are marked as not participating in arbitration in the current cycle. This can avoid repeated access to memory and arbitration conflicts, thereby improving system operating efficiency and enhancing overall computing performance.

[0073] In some embodiments, the internal cache space includes multiple operand registers, the number of operand registers matching the number of source operands required during the processing of a single instruction; the operand registers are not interconnected; the input of the operand register is provided with a first selector, and the output of the operand register is provided with a second selector; the first selector is used to select the data to be stored in the operand register from the data returned from multiple external storage spaces according to a first cache address; the second selector is used to select the data required for the processing of the first instruction from the multiple cache addresses in the operand register.

[0074] To accommodate the number of source operands required by the instructions, the internal cache space can include multiple operand registers. These operand registers can communicate with each other or operate independently without communication. Each operand register caches one or more data items and includes address information for fast lookup. This design significantly reduces reliance on external storage, speeds up instruction execution, and conserves system resources.

[0075] Each operand register is independent of the others, meaning that data in one operand register will not affect or overwrite the contents of another operand register. This independence is designed to prevent data contamination between source operands while ensuring the independence and integrity of the data in each source operand. For example, when processing an instruction with three source operands, these three source operands will be allocated to different operand registers, with no data sharing or interaction between them.

[0076] The first selector, located at the input of each operand register, controls which external data will be written to the operand register. In some implementations, when multiple external data sources provide data simultaneously, the first selector can select data based on cache address and priority rules, ensuring that the correct data is written to the corresponding operand register. The first selector allows for more flexible control of the data writing process, ensuring that each operand register only receives data belonging to that operand register, thereby improving the accuracy and efficiency of data caching.

[0077] The second selector, located at the output of each internal cache space, is used to select the data required for processing the first instruction from multiple cache addresses in the operand register. In some implementations, when an instruction requires a source operand, the second selector retrieves the source operand from the internal cache space based on its cache address and provides this data to the arithmetic module for computation. The second selector allows the arithmetic logic unit to directly obtain the required data from the internal cache space, improving computational efficiency.

[0078] In this embodiment, by matching the number of operand registers with the number of source operands required for processing a single instruction, and setting a first selector at the input and a second selector at the output, efficient caching and management of source operand data is achieved. This avoids repeatedly reading the same data from external storage space, thereby reducing power consumption, improving instruction processing efficiency, and ultimately optimizing the overall performance of the computation path of the arithmetic logic unit.

[0079] This application provides an instruction processing method for an arithmetic logic unit, applied to an arithmetic logic unit, such as... Figure 2 As shown, the instruction processing method may include the following steps 201 to 202: Step 201: If the target operand has the same storage address among the second source operand required by the first instruction to be processed and the first source operand that can be reused in the internal cache space, the first cache address of the target operand in the first source operand is assigned to the first instruction; the storage address is the address of the corresponding source operand in the external storage space deployed outside the arithmetic logic unit.

[0080] In some implementations, determining whether the second source operand and the first source operand have a target operand with the same storage address can be achieved by: determining a first source operand with a first reusability flag of a first flag value from multiple source operands in the internal cache space; determining a comparison operand with a second reusability flag of a second flag value from the first source operand; comparing the second source operand with the comparison operand one by one to determine whether the second source operand and the comparison operand have a target operand; the first flag value is used to indicate that the corresponding source operand has a reusable operand, and the second flag value is used to indicate that the corresponding operand is reusable.

[0081] Step 202: Execute the operation corresponding to the first instruction based on the target operand in the first cache address.

[0082] In some implementations, when the second source operand contains data other than the target operand, the operand to be read is obtained from external storage space according to the reading indication information; the operand to be read is cached in a first cache address; the operand to be read is other data or the second source operand; and the operation corresponding to the first instruction is executed based on the target operand and the operand to be read in the first cache address.

[0083] In some embodiments, the instruction processing method provided in this application can assign a first instruction to a cache address through the following step 203: Step 203: If there is no target operand among the second source operand and the first source operand, determine the second cache address based on the previously allocated cache address according to the address allocation logic of the internal cache space, and allocate the second cache address to the first instruction.

[0084] In some embodiments, the instruction processing method provided in this application can mark the second source operand through the following steps 204 to 205: Step 204: If the second source operand has a first operand that can be reused by the second instruction, set the second reusable flag of the first operand in the first record space to the second flag value and set the first reusable flag of the second source operand to the first flag value, and record the storage address of the first operand and the task identifier corresponding to the first operand in the first record space; the first flag value is used to indicate that the corresponding source operand has a reusable operand, and the second flag value is used to indicate that the corresponding operand is reusable; the first record space is the record space corresponding to the first cache address; the second instruction is other instructions executed after the first instruction.

[0085] Step 205: If the first operand is not present in the second source operand, set the second reusable flag of the first operand in the first record space to a third flag value and set the first reusable flag of the second source operand to a fourth flag value; the third flag value indicates that the corresponding operand is not reusable, and the fourth flag value indicates that the corresponding source operand does not have a reusable operand.

[0086] In some embodiments, the arithmetic logic unit further includes an instruction cache module. In this case, the instruction processing method provided in this application embodiment further includes the following step 206: Step 206: Store the instruction information of the first instruction, the cache address of the second source operand in the internal cache space, and the read indication information to the instruction cache module; the read indication information is used to indicate whether the corresponding operand needs to be read from the external storage space.

[0087] In some embodiments, the instruction processing method provided in this application can execute the first instruction through the following steps 207 to 208: Step 207: If the target operand is not present in either the second source operand or the first source operand, the operand to be read is obtained from the external storage space according to the reading indication information; the operand to be read is cached in the first cache address; the operand to be read is other data or the second source operand; Step 208: Based on the operand to be read in the first cache address, execute the operation corresponding to the first instruction.

[0088] In some embodiments, the instruction processing method provided in this application can arbitrate the operands to be read by the instruction to be read through the following steps 209 to 210: Step 209: When multiple third instructions simultaneously initiate a read request, a preset arbitration strategy is adopted to arbitrate the operand to be read from the multiple third instructions; the third instructions do not include instructions in which all source operands required for processing are contained in the first source operand.

[0089] Arbitration strategies include at least one of the following: In the case where there are second operands with the same storage address among multiple third instructions, the second operand with the smallest identifier is selected, and the other operands are marked as not participating in arbitration. The third instruction with the longest cache time in the instruction cache module is selected as the instruction to be read.

[0090] Step 210: If the operand to be read is arbitrated, mark all operands with the same storage address as the operand to be read as successfully arbitrated. Mark all operands with the same identifier as the operand to be read in other instructions (excluding the instruction to be read) as not participating in arbitration in the current cycle in all read arbitration modules.

[0091] The description of the above method embodiments is similar to that of the above arithmetic logic unit embodiments, and has similar beneficial effects. For technical details not disclosed in the method embodiments of this application, please refer to the description of the arithmetic logic unit embodiments of this application for understanding.

[0092] The following describes the application of the arithmetic logic unit provided in the embodiments of this application in a real-world scenario.

[0093] The ALU is a key component in a processor chip, used to execute arithmetic instructions. For example... Figure 3 As shown, the typical ALU processing flow includes: after receiving an instruction, the ALU performs instruction buffering and instruction parsing; the parsed operand address is transmitted to the read memory logic to initiate a read request to the memory; after receiving the operand returned from the memory, the arithmetic unit executes the operation corresponding to the instruction based on the returned operand.

[0094] The conventional ALU processing flow has at least the following problems: 1. The problem of low utilization efficiency of source operands. Experiments have shown that even if multiple consecutive instructions use the same operand, each instruction needs to read the data from the memory space again, resulting in low utilization efficiency of source operands.

[0095] 2. Long data retrieval time. Multiple operands may reside in the same storage space. In such cases, different operands need to be retrieved from that storage space multiple times, resulting in a long retrieval time.

[0096] To this end, this application proposes a hardware implementation scheme for source operand reuse in ALU (corresponding to the arithmetic logic unit 10 mentioned above), which keeps the source operand in the internal cache space of ALU, so that subsequent instructions may obtain the source operand directly without having to read the data from memory again, thereby improving operand utilization efficiency.

[0097] The hardware solution designed in this application requires adding a reuse flag to each operand in the instruction to indicate the reusability of the operand.

[0098] Reuse rules for this application: 1. After the ALU parses the instruction, if it determines that the reuse flag of a certain source operand is valid (corresponding to the first reusable flag value mentioned above), then the data of that operand, as well as the address information (the storage address in external memory, such as the address number; if the address information of two operands is the same, then the operands are the same), and the task information (the reason for introducing task information is that the addresses corresponding to task A and task B can have the same number. By adding the task identifier to the address number, it is possible to distinguish which address of which task it is) are recorded in the corresponding internal register (corresponding to the internal cache space mentioned above). The registers of each source operand are not interconnected.

[0099] 2. While parsing the instruction, the ALU determines which operands to be compared have a valid reuse flag (corresponding to the second reusable flag value mentioned above). It then checks the internal registers corresponding to each operand to be compared to see if they cache reusable data belonging to the same task as the current instruction and having the same address. If the internal registers cache data belonging to the same task as the current instruction and having the same address, then this instruction does not need to read the data from external memory; otherwise, it needs to read the data from external memory.

[0100] 3. A source operand can be divided into multiple operands. For example, a 32-bit source operand can be divided into four 8-bit operands. When the reuse flag is active, only the operands used by the current instruction are stored in the internal register space.

[0101] 4. If the instruction storing data in the internal register has `reuse` set to valid on the source operand, the operand in the internal register will remain in the internal register after use. Otherwise, the `reuse` corresponding to all cached data will be set to invalid immediately after being used once. After invalidation, the cached data cannot be reused and will be directly overwritten by subsequent data. This is equivalent to all cached sub-data being cleared immediately after being used once.

[0102] 5. Because the internal register space is limited, data that has been cached but is not yet used can be cleared from the internal register in advance.

[0103] The hardware logic designed in this application includes an instruction buffer (instr FIFO) that can hold more than one instruction. Each instruction can use multiple source operands (for example, the ordinary MOV instruction uses only one source operand, while the multiply-accumulate instruction requires three source operands). Each operand is provided with an internal register space that can hold more than one data item (assuming that the number of data items that each operand can hold is m).

[0104] After receiving the instruction, the system first checks whether the source operands used by the current instruction have been cached in the internal register space. To determine whether a piece of data stored in an internal register is the same as a source operand of the current instruction, the following conditions must be met: 1. The stored data remains valid.

[0105] 2. The stored data and the current source operand being searched must be the same source operand; that is, you cannot search across operands.

[0106] 3. The address where the data is stored is the same as the address of the current source operand.

[0107] Regardless of whether a usable cached instruction is found in the register space, an internal register address (corresponding to the cache address mentioned above) needs to be allocated to the source operand of the current instruction. If a usable cached data at the same address is found in the internal register for a source operand of the current instruction, the address of this cached data is directly allocated to the source operand. If the cached data at the same address does not cache the data needed by the current instruction, it is still considered that usable cached data has been found. If no cached data is found, an internal register address is allocated to the source operand according to the address allocation rule, which may be to accumulate the previously allocated address before allocation.

[0108] After completing the cache lookup and internal register address allocation, the cache lookup results for all source operands of the instruction, along with the allocated internal register addresses, are temporarily stored in the instruction cache along with the instruction itself. Simultaneously, if the instruction sets a valid `reuse` flag for a source operand, the information regarding the source operand cached in the internal register is recorded. The recorded details include: 1. The address of the source operand.

[0109] 2. A flag indicating that the source operand can be used by subsequent instructions.

[0110] Each cycle retrieves the n (n<=m) instructions from the instruction register in the order they were loaded, and reads their source operands from memory simultaneously. If a source operand is determined to be available from an internal register, it is not read from external memory. Data located in different external memories can be read simultaneously within a single cycle. If multiple data to be read are stored in the same external memory, only one data can be read per cycle, requiring arbitration according to certain rules. The arbitration rules are as follows: 1. The priority of different instructions is determined by the storage time; the longer the storage time, the higher the priority of the instruction.

[0111] 2. The priority of readable source operands within an instruction can be arbitrarily defined, such as a fixed priority based on a certain order or a relatively fair polling arbitration.

[0112] 3. If there are multiple identical operands within the same instruction, a read request will be issued at most once.

[0113] 4. If a high-priority instruction is reading a source operand, other instructions with lower priority cannot read that source operand at the same time; that is, the source operand is unreadable at this time.

[0114] 5. If a source operand of a high-priority instruction has the same address as other source operands of that instruction that have been arbitrated, then other instructions with lower priority cannot read that source operand at the same time, and the source operand is in an unreadable state at this time.

[0115] After receiving a read request, the memory returns the data to the ALU after a fixed number of cycles. The ALU then writes the data into the register pointed to by the pre-allocated internal register address. If multiple source operands of an instruction have the same address, only the data for one source operand will be returned from the register. This returned data needs to be broadcast to the internal registers of all source operands that require this data. When the last source operand is returned from memory, all operands used by the instruction are loaded into the ALU's arithmetic unit for calculation, but the data remains in the register until it is overwritten by new data.

[0116] The hardware circuit implementation scheme of this application is as follows: Figure 4 The diagram shows a complete ALU control logic design. Instructions are written into the ALU by the upstream instruction scheduling module. After receiving the instruction, the ALU performs a series of parsing and processing steps, storing the parsed information and the instruction together in the instruction cache.

[0117] The information that typically needs to be parsed includes: whether each source operand of the instruction can find available cached data in internal memory; whether each source operand of the instruction needs to leave data in internal registers for subsequent instructions to use; and whether the instruction has multiple source operands with the same address. To this end, it is necessary to set up reusable data recording logic to record data information left in internal registers, reusability check logic to check whether the current instruction can use data in the internal register space, and address allocation logic to allocate internal register space addresses for instruction source operands. The specific working method is described below: Reusable data recording logic (corresponding to the reusable data recording module mentioned above): This logic allocates an independent recording space for each operand, and the number of recording spaces for each operand is equal to the number of spaces in each operand register. For example, assuming the first operand register can hold 3 data items, then the reusable data recording logic allocates 3 recording spaces for the first operand. Furthermore, the space addresses in the reusable data recording logic are consistent with the addresses in the operand registers. According to the description in this application, the information recorded in each space of the reusable data recording logic includes at least: 1. Reuse data by validating each sub-data item.

[0118] 2. Address of reusable data.

[0119] 3. Task information, used to clear all data belonging to the task in the record when the task ends.

[0120] The reuse check logic (corresponding to the reuse check module mentioned above) parses the storage address of each source operand, which data from the source operand the current instruction needs to use, and the instruction information after receiving the instruction. Then, it checks the storage record of the corresponding source operand within the reusable logic one by one. If a storage space can be found that stores data at the same address as the source operand used by the current instruction, it is determined that at least one operand of that data exists in the internal cache space; this situation is called a "hash". If all operands of a source operand can be found in the internal storage space, it is determined that the source operand does not need to be reread from external memory; otherwise, it is determined that the data needs to be reread from memory.

[0121] Address allocation logic (corresponding to the address allocation module above): Allocates the address in the operand register for each valid source operand of the current instruction. If the multiplexing check logic determines that an operand can hit cached data in the internal register space, the address of the hit cached data is directly allocated to that operand of the current instruction. Otherwise, the address of the operand previously allocated by the register is incremented by one and used as the address for this allocation. If the previously allocated address has reached the maximum value of allocable addresses, address 0 is used as the address for this allocation.

[0122] After address allocation, if the instruction specifies that an operand can be reused by subsequent instructions (i.e., the `reuse` flag is valid), the record space corresponding to the operand's register address is set to valid within the reusable data recording logic (indicating that the cached data in that space is valid). The operand's address, task information record, and a flag indicating whether each sub-data item is valid are also saved to the corresponding space in the reusable recording logic. If the instruction does not set the `reuse` flag to valid, the record space corresponding to the operand's register address is set to invalid within the reusable data recording logic, indicating that there is no reusable data in the internal register space corresponding to that address.

[0123] like Figure 5 As shown, using a single source operand as an example, this illustrates the internal structure of reusable data recording logic, multiplexing check logic, and address allocation logic. The internal register can include four addresses, each containing 32 bits, with each 8 bits corresponding to a sub-data item. Currently, the data stored is for source operand 1. When a new instruction arrives, a hit check is performed on the new instruction's source operand address and all four addresses (hit checks 0-3 in the diagram), and only one will be hit. After a hit, the address at which the hit occurred is determined (the address identifier in the selector in the diagram), and the hit register address is assigned to the new instruction. The reusability flag also serves to terminate readings of external storage space.

[0124] After the above steps of parsing, the instruction information, the addresses of the internal register spaces allocated to each source operand obtained from the parsing, and the information on whether each source operand needs to be read from memory again are stored together in the instruction cache.

[0125] Several read arbitration logics are set up, each corresponding to a memory location. Each read arbitration logic can handle read memory requests from multiple source operands, but the maximum number of instructions it can handle cannot exceed the internal register space of each source operand. If multiple source operands simultaneously request to read the same memory location, the corresponding read arbitration logic must select the source operand with the highest priority according to priority rules. Other unselected source operands must wait for the next cycle to participate in the arbitration. Source operands that have already been selected will not participate in the next arbitration. The specific processing steps are as follows.

[0126] For each instruction participating in arbitration, source operands that are determined to be able to reuse data cached in the internal register space and do not need to be read from memory again are marked as not participating in arbitration.

[0127] Then, check each remaining source operand of each instruction to see if there is a duplicate address. If so, mark the source operand with the larger number (or select one according to any rule) as not participating in arbitration.

[0128] A priority is set for each instruction participating in arbitration, with the rule that the longer an instruction is stored in the instruction cache, the higher its priority.

[0129] In all read arbitration logics, the highest priority instruction undergoes source operand arbitration, with the arbitration rule being that the smaller the operand number, the higher the priority (or any other arbitrary rule). If, in a read arbitration logic, the source operand of the highest priority instruction successfully issues a read request to memory, then this operand, along with all source operands at the same address in that instruction, are considered successfully arbitrated. All other source operands with the same number as the currently arbitrated source operand are marked as not participating in arbitration in the current cycle within all read arbitration logics.

[0130] like Figure 6 As shown, the arbitration process is illustrated using four instructions, each with four operands. If operand 1 is hit, arbitration is performed on the remaining operands of instruction 1. Since operand 2 has the smallest number, it wins. Because operand 2 of instruction 1 wins, it blocks the arbitration of operand 2 of instructions 2, 3, and 4. Each read arbitration logic serves its corresponding external memory. For example, if only operand 4 of instruction 2 is arbitrated through read arbitration logic 2, then operand 4 of instruction 2 can be read directly.

[0131] An operand register is set up for each source operand, with a selector at both its entry and exit points. The operand register has internal storage space capable of holding multiple data entries (each storage space corresponding to a memory address). Data returned from a memory space is stored in the space corresponding to the address assigned to the operand, and the memory space is not cleared, only overwritten. The selector at the operand register entry point selects the data to be stored in the operand register from the multiple memory return data entries, while the selector at the exit point selects the data required by the current processing instruction from the multiple memory spaces. The read arbitration logic notifies the operand register corresponding to the arbitrated operand when an operand passes arbitration, along with the operand's address within the internal register space. The operand register uses this information to control the selector at the entry point to select its own return data from the memory return data and store it in the designated internal address.

[0132] Once all the data for an instruction has been collected, the instruction information and valid operands are sent to the arithmetic unit for calculation, and the result is finally written back to memory.

[0133] A single processing cycle requires multiple computation cycles, similar to pipelined processing. Between two pipeline stages, a register (which can store four source operands, the number depending on the hardware) is added. This register is a sequential circuit used for one-time data buffering, serving the computational function. During ALU computation, data needs to be read from the processor's registers and temporarily stored in the registers within the pipeline.

[0134] The technical solution of this application has at least the following technical effects: it implements multiple data caches within the ALU, which more effectively improves data utilization efficiency, reduces the number of memory reads, and thus saves power consumption. Furthermore, under certain conditions, it effectively reduces the performance degradation caused by multiple operands needing to queue to read data from the same register.

[0135] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0136] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0137] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0138] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0139] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0140] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0141] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an encoder or a computer device (which may be a personal computer, server, or network device, etc.) equipped with an encoder to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0142] The above are merely embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An arithmetic logic unit, characterized in that, The arithmetic logic unit includes: an internal cache space, an address allocation module, and an arithmetic module; The internal cache space is used to cache reusable first source operands; The address allocation module is used to allocate the first cache address of the target operand in the first source operand to the first instruction when the second source operand required by the first instruction to be processed has the same target operand with the same storage address as the first source operand; the storage address is the address of the corresponding source operand in the external storage space deployed outside the arithmetic logic unit; the first cache address is the cache address of the target operand in the internal cache space; The arithmetic module is used to execute the operation corresponding to the first instruction based on the target operand in the first cache address.

2. The arithmetic logic unit according to claim 1, characterized in that, The arithmetic logic unit also includes a reuse check module; The reuse check module is used to determine, from multiple source operands in the internal cache space, a first source operand with a first reusable flag value. From the first source operands, determine the operand to be compared with the second reusable flag set to the second flag value; compare the second source operand with the operand to be compared one by one to determine whether the second source operand and the operand to be compared have the target operand; The first flag value is used to indicate that the corresponding source operand has reusable operands, and the second flag value is used to indicate that the corresponding operand is reusable.

3. The arithmetic logic unit according to claim 1, characterized in that, The arithmetic logic unit further includes: a reusable data recording module; the reusable data recording module includes multiple recording spaces, the number of which is the same as the number of cache addresses contained in the internal cache space, and each cache address is used to cache one source operand; The reusable data recording module is configured to, when the second source operand has a first operand that can be reused by the second instruction, set the second reusable flag of the first operand in the first recording space to a second flag value and the first reusable flag of the second source operand to a first flag value, and record the storage address of the first operand and the task identifier corresponding to the first operand in the first recording space; the first flag value is used to indicate that the corresponding source operand has a reusable operand, and the second flag value is used to indicate that the corresponding operand is reusable; the first recording space is the recording space corresponding to the first cache address; the second instruction is other instructions executed after the first instruction.

4. The arithmetic logic unit according to claim 3, characterized in that, The reusable data recording module is further configured to, when the first operand is not present in the second source operand, set the second reusable flag of the first operand in the first recording space to a third flag value and the first reusable flag of the second source operand to a fourth flag value; the third flag value indicates that the corresponding operand is not reusable, and the fourth flag value indicates that the corresponding source operand does not have a reusable operand.

5. The arithmetic logic unit according to any one of claims 1 to 4, characterized in that, The address allocation module is further configured to, when neither the second source operand nor the first source operand has the target operand, determine a second cache address based on the previously allocated cache address according to the address allocation logic of the internal cache space, and allocate the second cache address to the first instruction.

6. The arithmetic logic unit according to any one of claims 1 to 4, characterized in that, The arithmetic logic unit further includes: an instruction cache module; The instruction cache module is used to store the instruction information of the first instruction, the cache address of the second source operand in the internal cache space, and the read indication information; the read indication information is used to indicate whether the corresponding operand needs to be read from the external storage space.

7. The arithmetic logic unit according to claim 6, characterized in that, The arithmetic logic unit further includes a reading arbitration module; the reading arbitration module has a one-to-one correspondence with the external storage space. The reading arbitration module is used to retrieve the operand to be read from the external storage space according to the reading indication information when the second source operand contains other data besides the target operand, or when neither the second source operand nor the first source operand contains the target operand; the operand to be read is cached in the first cache address; the operand to be read is the other data or the second source operand; The arithmetic module is used to execute the operation corresponding to the first instruction based on the target operand and / or the operand to be read in the first cache address.

8. The arithmetic logic unit according to claim 7, characterized in that, The reading arbitration module is also used to, when multiple third instructions simultaneously initiate reading requests, adopt a preset arbitration strategy to arbitrate the operand to be read from the multiple third instructions; the third instructions do not include instructions in which all source operands required for processing are contained in the first source operand; The arbitration strategy includes at least one of the following: In the case where there are second operands with the same storage address among multiple third instructions, the second operand with the smallest identifier is selected, and the other operands except the second operand with the smallest identifier are marked as not participating in arbitration; The third instruction, which has the longest cache time in the instruction cache module, is selected as the instruction to be read.

9. The arithmetic logic unit according to claim 8, characterized in that, The reading arbitration module is further configured to, when arbitrating the operand to be read, mark all operands with the same storage address as the operand to be read as successfully arbitrated, and mark all operands with the same identifier as the operand to be read in other instructions (excluding the instruction to be read) in all reading arbitration modules as not participating in arbitration in the current period.

10. The arithmetic logic unit according to any one of claims 1 to 4, characterized in that, The internal cache space includes multiple operand registers, the number of which matches the number of source operands required during the processing of a single instruction; the operand registers are not interconnected. The operand register has a first selector at its input and a second selector at its output. The first selector is used to select, based on the first cache address, the data to be stored in the operand register from the data returned from the plurality of external storage spaces; The second selector is used to select the data required for processing the first instruction from a plurality of cache addresses in the operand register.

11. A method for processing instructions of an arithmetic logic unit, characterized in that, Applied to an arithmetic logic unit, the method includes: If, among the second source operands required by the first instruction to be processed and the first source operands that can be reused in the internal cache space, there is a target operand with the same storage address, the first cache address of the target operand in the first source operand is allocated to the first instruction; the storage address is the address of the corresponding source operand in the external storage space deployed outside the arithmetic logic unit; the first cache address is the cache address of the target operand in the internal cache space; Based on the target operand in the first cache address, execute the operation corresponding to the first instruction.

12. A computer device comprising an arithmetic logic unit, characterized in that, The arithmetic logic unit is used to implement the steps in the method of claim 11.

Images